OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

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    /socgen/trunk/doc
    from Rev 19 to Rev 20
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Rev 19 → Rev 20

/src/guides/guide_names.html
238,7 → 238,7
<br>
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<img style="width: 800px; height: 600px;" alt=""
src="../drawing/sch/naming_guide_1.png"><br>
src="../png/naming_guide_1.png"><br>
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/src/guides/guide_database.html
0,0 → 1,172
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<p><br>
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</div>
<h1><a name="socgen_project"></a>SOCGEN Project</h1>
<h2><a name="manifesto"></a>Database Guidelines</h2>
<p><br>
</p>
<p>Have a backup plan</p>
<p>&nbsp;&nbsp; <br>
<br>
</p>
<p>Plan ahead and allow for the worst case configurations</p>
<p>Design for the lowest common denominator.</p>
<p>Design first for a completely generic target and then retarget for
the correct one.</p>
<p>Store only the seed data needed to generate the database ( keep it
small and easy to manage)</p>
<p>Do not check generated files into the database ( generation must
not change the database)</p>
<p>Do not copy data. Every object has one and one one storage
location</p>
<p>Do not mix unlike objects in the same container. </p>
<p>Store the databases by their source and not by where they are
used. Use links to get them to where they are needed</p>
<p>A full design will consist of several different databases that are
layered. Upper ones may override any content from a lower layer</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><img style="width: 800px; height: 600px;" alt=""
src="../png/data_fig1.png"><br>
<br>
</p>
<p><br>
<br>
</p>
<h2>SYSTEM<br>
</h2>
<p>A system&nbsp; is at least&nbsp; one PCA containing a targeted
component&nbsp; interconnected with&nbsp;
other electronic components and bus functional models. <br>
</p>
<p><br>
</p>
<h2>TARGET</h2>
<p>A target is a specific physical design that can implement a
component. Targets can be asic or fpga and include a Printed circuit
board(PCB) that may include other electronic components. The goal for
all components is to assign them to at least one target and prove that
the work in silicon<br>
</p>
<p>
<br>
<br>
</p>
<h2>PROJECT</h2>
<p>A project is a collection of components. A database must define at
least one project to create an area where components may be stored.
Other projects may be created as needed to group similar components
together and reducing clutter. If any component in a project uses a
component from a child project then that child project must also be
included in the parent project.</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<h2>COMPONENT</h2>
<p>A component is a&nbsp; basic building block that may be used to make
other components.</p>
<br>
<p>
</p>
<br>
<h2>LIB</h2>
<p>A library is a collection of building blocks&nbsp; that may not be
synthesiable in
all target technologies and may require customizations. The use of lib
parts in the rtl code will
facilitate porting a component into different technologies.</p>
<p><br>
</p>
<h2>TOOLS<br>
</h2>
<p>The tools directory contains all of the socgen tools needed to build
, simulate and synthesise all of the systems and components in the
database. Scripts and installation instructions are provided for any
other opensource tools that may be required. There are also
instructions for any propritory tools that are used.<br>
</p>
<br>
<p><br>
<br>
</p>
<h2>BENCH<br>
</h2>
<p>A testbench is used for all simulations and test suites. Any system
or component may be simulated. Components can only do generic rtl sims
while systems may do either generic rtl ,specific rtl or gate sims.
Generic rtl models are included in the socgen library, specific ones
must be obtained from the IC vendor.<br>
</p>
<p><br>
</p>
<br>
<h2>DOC<br>
</h2>
The documentation&nbsp; directory.
<br>
<br>
<br>
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/src/guides/guide_documentation.html
0,0 → 1,138
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<head>
<meta http-equiv="CONTENT-TYPE" content="text/html; charset=UTF-8">
<title>start</title>
<meta name="GENERATOR" content="OpenOffice.org 3.0 (Linux)">
<meta name="CREATED" content="0;0">
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<meta name="KEYWORDS" content="start">
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<p><br>
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</div>
<h1><a name="socgen_project"></a>SOCGEN Project</h1>
<h2><a name="manifesto"></a>Documentation Guidelines</h2>
<p><br>
<br>
</p>
<p>Every component must include a minimum set of documents. This
consists of a ./doc directory that contains a html file named
"index.html".&nbsp; This file is the link that all external users will
use to access each components documents.&nbsp; Those documents consist
of:<br>
</p>
<p><br>
</p>
<ul>
<li>A Socgen datasheet for the component and each of it's variants</li>
<li>Application notes detailing how to use the component.</li>
<li>Any 3rd party produced reference material needed to support the
component</li>
<li>Test plans detailing how the component rtl was simulated and what
was tested.<br>
</li>
<li>Test plans detailing how to synthesis the component and prove
functionality in silicon. <br>
</li>
</ul>
<p><br>
<br>
</p>
<p>All documentation source will be stored as html files. A pdf will be
extractred from each source and also included. <br>
</p>
<p><br>
</p>
<p><br>
<span style="font-weight: bold;"></span></p>
<h2><a name="manifesto"></a>Tool support for documentation creation</h2>
<br>
The Socgen project uses and supports three opensourced tools for
creating and maintaining component documentation. The key to accurate
and timely documents is to automate their creation as part of the IP
build process.<br>
<br>
<br>
<br>
SEAMONKEY<br>
<br>
Seamonkey composer is the main tool used to edit the html files.<br>
<br>
<br>
GSCHEM<br>
<br>
Geda and friends are used to create any and all graphics used in the
html files. Several support tools are provided that can extract
schematic and symbol information directly from the database ensuring
that the database and documents stay in sync <br>
<br>
<br>
OPENOFFICE WORD PROCESSOR<br>
<br>
Is used to create the pdf for each component <br>
<br>
<p><br>
<br>
</p>
<p><br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/doc_fig1.png"><br>
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/src/prj_description.html
1,33 → 1,35
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<META NAME="CREATED" CONTENT="0;0">
<META NAME="CHANGED" CONTENT="20100309;9110600">
<META NAME="CLASSIFICATION" CONTENT="socgen project description">
<META NAME="DESCRIPTION" CONTENT="socgen is a laboratory for the development of a opensource design for reuse toolset">
<META NAME="KEYWORDS" CONTENT="eda design for reuse opensource tools">
<META NAME="Info 3" CONTENT="">
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<DIV ID="toc__header" DIR="LTR">
<P><BR><BR>
</P>
</DIV>
<H1><A NAME="socgen_project"></A>SOCGEN Project</H1>
<H2>Design for Reuse</H2>
<P>The SOCGEN project is a laboratory for developing and
<html>
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content="socgen is a laboratory for the development of a opensource design for reuse toolset">
<meta name="KEYWORDS" content="eda design for reuse opensource tools">
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<meta name="date" content="2010-01-08T12:01:41-0500">
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<p><br>
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</div>
<h1><a name="socgen_project"></a>SOCGEN Project</h1>
<h2>Design for Reuse</h2>
<p>The SOCGEN project is a laboratory for developing and
demonstrating the methods and processes needed to create and reuse
digital components. The goal of the project is to create a open
source set of eda tools that will enable a designer to configure and
assemble a complete System_on_a_chip (SOC) in a quick, easy and error
free manner.</P>
<P>I am hosting this project on Opencores due to the availability of
free manner.</p>
<p>I am hosting this project on Opencores due to the availability of
free opensourced ip modules and a user community that is in dire need
of a good design for reuse solution. I will be taking various
opencores modules and reworking them into the socgen repository.
35,69 → 37,97
you devote enough time and energy to it but paying attention to the
details can make a huge difference in how easy it is to reuse a
module. Any one is welcome to use these versions of the modules and
the scripts that I am creating. Feedback is always welcome.</P>
<P>The entire industry is about to experience a change in the way
that chips are designed that will be as dramatic as it was back in
the early 90's. Before that point the most common tool for design
the scripts that I am creating. Feedback is always welcome.</p>
<p>The entire industry is about to experience a change in the way
that chips are designed that will be as dramatic as it was back in
the early 90's. Before that point the most common tool for design
entry was schematic capture. But designs had grown to the point where
that was far to inefficient and it was replaced with a rtl to
synthesis process.</P>
<P>That happened 20 years ago and chips have continued to grow to the
synthesis process.</p>
<p>That happened 20 years ago and chips have continued to grow to the
point where you can no longer design and verify the rtl code in a
reasonable time.
</P>
<P>My approach to this problem is to introduce modern hi volume
production line theory into the IC design process. The designs are
too complex to simply get a group together and hand craft rtl code.
Socgen will develop the tools and processes needed to assemble cores
together in quick and predictable manner.</P>
<P>
</P>
<P>A good deal of this effort involves understanding database design
and usage. Most designers simply construct their databases based
reasonable time. </p>
<p>My approach to this problem is to introduce modern hi volume
production line theory into the IC design process. The designs are
too complex to simply get a group together and hand craft rtl code.
Socgen will develop the tools and processes needed to assemble cores
together in quick and predictable manner.</p>
<p> </p>
<p>A good deal of this effort involves understanding database design
and usage. Most designers simply construct their databases based
only on their immediate and past needs. Socgen will provide a
repository of various projects that have been converted to show how
small changes in where you store files can make a big difference in
how easily those files can be reused.</P>
<P><BR><BR>
</P>
<P>All socgen tools and components are released under LGPL. Any other
how easily those files can be reused.</p>
<p><br>
<br>
</p>
<p>All socgen tools and components are released under LGPL. Any other
opencores projects used in the repository will retain their original
license.</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
<P>Socgen will provide:</P>
<OL>
<LI><P>Installation instructions for any and all external tools
needed</P>
<LI><P>Proper data base design and management tools and techniques</P>
<LI><P>Proper design verification</P>
<LI><P>All modules will be proven in silicon</P>
</OL>
<P><BR><BR>
</P>
<P>Socgen is a work in process so expect to see frequent changes. All
license.</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<h2>Definitions<br>
</h2>
<p>COMPONENT&nbsp;&nbsp;&nbsp; The basic design building block<br>
</p>
<p>LIBRARY<br>
</p>
<p>TARGET<br>
</p>
<p>COLLECTOR<br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
<p>Socgen will provide:</p>
<ol>
<li>
<p>Installation instructions for any and all external tools needed</p>
</li>
<li>
<p>Proper data base design and management tools and techniques</p>
</li>
<li>
<p>Proper design verification</p>
</li>
<li>
<p>All modules will be proven in silicon</p>
</li>
</ol>
<p><br>
<br>
</p>
<p>Socgen is a work in process so expect to see frequent changes. All
socgen tools are run under Makefiles and I will try to keep the top
level commands constant.</P>
<P><BR><BR>
</P>
<P>Till Later</P>
<P><BR><BR>
</P>
<P>John Eaton</P>
<P><BR><BR>
</P>
<P><BR><BR>
</P>
</BODY>
</HTML>
level commands constant.</p>
<p><br>
<br>
</p>
<p>Till Later</p>
<p><br>
<br>
</p>
<p>John Eaton</p>
<p><br>
<br>
</p>
<p><br>
<br>
</p>
</body>
</html>
/src/png/data_fig1.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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src/png/naming_guide_1.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: src/png/doc_fig1.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: src/png/doc_fig1.png =================================================================== --- src/png/doc_fig1.png (nonexistent) +++ src/png/doc_fig1.png (revision 20)
src/png/doc_fig1.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: src/drawing/sch/doc_fig1.sch =================================================================== --- src/drawing/sch/doc_fig1.sch (nonexistent) +++ src/drawing/sch/doc_fig1.sch (revision 20) @@ -0,0 +1,55 @@ +v 20100214 2 +C 57800 32800 1 0 0 frame_800x600.sym +T 59100 38300 9 10 1 0 0 0 1 +DataBase RTL Code +T 64500 38100 9 10 1 0 0 0 2 +sym/component.sym +sch/component.sch +T 64900 36400 9 10 1 0 0 0 1 +GSCHEM +T 61600 36500 9 10 1 0 0 0 2 +png/component.png +png/figures.png +T 61600 35200 9 10 1 0 0 0 1 +html/component.html +T 59100 36400 9 10 1 0 0 0 1 +SEAMONKEY +T 59100 33400 9 10 1 0 0 0 3 +OPENOFFICE + WORD +PROCESSOR +T 61600 33700 9 10 1 0 0 0 1 + pdf/component.pdf +T 61800 38100 9 10 1 0 0 0 2 +VER2GEDASYM +VER2GEDASCH +V 59700 36500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 59600 33700 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 65300 36500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 62500 38300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 58900 38100 2100 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 64300 37900 2000 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 61500 36100 2000 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 61500 35000 2000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 61500 33500 2000 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 61000 38300 61700 38300 3 0 0 0 -1 -1 +L 63300 38300 64300 38300 3 0 0 0 -1 -1 +L 65300 37000 65300 37900 3 0 0 0 -1 -1 +L 64800 36500 63500 36500 3 0 0 0 -1 -1 +L 62500 36100 62500 35500 3 0 0 0 -1 -1 +L 60400 33700 61500 33700 3 0 0 0 -1 -1 +L 60300 34100 61500 35000 3 0 0 0 -1 -1 +L 60300 36100 61500 35500 3 0 0 0 -1 -1 +L 61700 38300 61600 38400 3 0 0 0 -1 -1 +L 61700 38300 61600 38200 3 0 0 0 -1 -1 +L 64300 38300 64200 38400 3 0 0 0 -1 -1 +L 64300 38300 64200 38200 3 0 0 0 -1 -1 +L 63500 36500 63600 36600 3 0 0 0 -1 -1 +L 63500 36500 63600 36400 3 0 0 0 -1 -1 +L 62500 35500 62400 35600 3 0 0 0 -1 -1 +L 62500 35500 62600 35600 3 0 0 0 -1 -1 +L 61500 33700 61400 33800 3 0 0 0 -1 -1 +L 61500 33700 61400 33600 3 0 0 0 -1 -1 +V 60900 35800 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 60700 34400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 65300 37400 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 Index: src/drawing/sch/data_fig1.sch =================================================================== --- src/drawing/sch/data_fig1.sch (nonexistent) +++ src/drawing/sch/data_fig1.sch (revision 20) @@ -0,0 +1,72 @@ +v 20100214 2 +C 42600 22000 1 0 0 frame_800x600.sym +B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 49500 27300 9 10 1 0 0 0 1 +Serial Uart +T 49500 26700 9 10 1 0 0 0 1 +VGA Display +T 49600 26200 9 10 1 0 0 0 1 +PS2 Mouse +T 49600 25600 9 10 1 0 0 0 1 +Switches +T 49700 25100 9 10 1 0 0 0 1 +Leds +T 49500 24500 9 10 1 0 0 0 1 +Push Buttons +T 49500 23900 9 10 1 0 0 0 1 +7 Seg display +T 49500 23100 9 10 1 0 0 0 1 +I/O connectors +B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 43000 28400 9 10 1 0 0 0 1 +System +T 43100 27600 9 10 1 0 0 0 1 +PCA (Nexys2) +T 43400 26900 9 10 1 0 0 0 1 +Targeted Component (Xilinx Spartan 3E-500 FG320) +B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 43800 26200 9 10 1 0 0 0 1 +Padring +T 44100 25700 9 10 1 0 0 0 1 +Core +T 44300 25200 9 10 1 0 0 0 1 +Component +B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 44500 24800 9 10 1 0 0 0 1 +comp +T 45600 24800 9 10 1 0 0 0 1 +comp +T 46700 24800 9 10 1 0 0 0 1 +comp +B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 44600 27600 9 10 1 0 0 0 1 +IC +T 45600 27600 9 10 1 0 0 0 1 +IC +T 46600 27600 9 10 1 0 0 0 1 +IC +T 47600 27600 9 10 1 0 0 0 1 +IC +L 48900 27400 49500 27400 3 0 0 0 -1 -1 +L 48900 26800 49500 26800 3 0 0 0 -1 -1 +L 48900 26300 49500 26300 3 0 0 0 -1 -1 +L 48900 25700 49500 25700 3 0 0 0 -1 -1 +L 48900 25200 49500 25200 3 0 0 0 -1 -1 +L 48900 24600 49500 24600 3 0 0 0 -1 -1 +L 48900 24000 49500 24000 3 0 0 0 -1 -1 +L 48900 23200 49500 23200 3 0 0 0 -1 -1 Index: template/template.html =================================================================== --- template/template.html (revision 19) +++ template/template.html (revision 20) @@ -13,17 +13,14 @@ -

SOCGEN LIB: COMPONENT

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SOCGEN
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    SOCGEN -LIB:COMPONENT
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    COMPONENT

    • @@ -101,7 +98,7 @@



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      Interface 

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