URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk/tools/bin
- from Rev 99 to Rev 100
- ↔ Reverse comparison
Rev 99 → Rev 100
/Makefile.root
27,7 → 27,7
rm -f TB.v;\ |
chmod 755 filelist.ver ;\ |
./filelist.ver ;\ |
verilator --cc TB.v --exe ../../../../../../../tools/lint/sim_main.cpp -top-module TB -Wno-WIDTH 2> lint.log;\ |
verilator --cc TB.v --exe ../../../../../../../tools/lint/sim_main.cpp -top-module TB -Wno-WIDTH -Wno-CASEX 2> lint.log;\ |
echo "################################################################################"; \ |
|
|
50,7 → 50,7
chmod 755 filelist.ver ;\ |
rm -f TB.v;\ |
./filelist.ver ;\ |
verilator --cc TB.v --exe ../../../../../../../tools/lint/sim_main.cpp -top-module TB -Wno-WIDTH 2> lint.log;\ |
verilator --cc TB.v --exe ../../../../../../../tools/lint/sim_main.cpp -top-module TB -Wno-WIDTH -Wno-CASEX 2> lint.log;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
131,8 → 131,8
.PHONY sim: |
sim: |
(\ |
$(VERILOG_NAME) -f filelist.sim -D VCD ../../../../../../../tools/simulation/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
$(VERILOG_NAME) -f filelist.sim -D VCD ../../../../../../../tools/simulation/TestBench 2> ./${test}_elab.log | tee >> ./${test}_elab.log ;\ |
./a.out 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
rm a.out;\ |
cd ../../cov/${comp};\ |
make score_cov TEST=${test} ;\ |
189,7 → 189,7
netgen -s 5 -pcf $(Design).pcf -sdf_anno true -sdf_path "./gate_sims/par" -insert_glbl true -insert_pp_buffers true -w -dir ./gate_sims/par -ofmt verilog -sim $(Design).ncd $(Design).v >>$(Design).log ;\ |
bitgen -f ./target/cclk.ut $(Design).ncd >>$(Design).log ;\ |
mv $(Design).bit Board_Design_cclk.bit ;\ |
promgen -u 0 Board_Design_cclk >>$(Design).log ; \ |
promgen -w -u 0 Board_Design_cclk >>$(Design).log ; \ |
mv Board_Design_cclk.mcs ./debug ;\ |
bitgen -f ./target/jtag.ut $(Design).ncd >>$(Design).log ;\ |
mv $(Design).bit Board_Design_jtag.bit ;\ |