OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/tools/sys
    from Rev 115 to Rev 116
    ↔ Reverse comparison
  •

Rev 115 → Rev 116

/build_geda
287,8 → 287,8
my $sch_out_pad = ($in_length +$out_length)*10*$sch_size +3500;
 
printf SCH_FILE ("v 20100214 1\n");
printf SCH_FILE ("T 40 40 8 10 1 1 0 0 1 1\n%srefdes=U?\n");
 
 
my $sym_color = 5;
my $sym_size = 10;
my $sym_box_h = ($max_pins * 200) +300;
/build_registers
70,9 → 70,8
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"bigendian",
"word",
"full_word"
"dest_dir=s" => \$dest_dir,
"bus_intf=s" => \$bus_intf
) || die "(use '$program_name -h' for help)";
 
 
81,7 → 80,7
##############################################################################
if ( $opt_h )
{
print "\n build_registers -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -bigendian dest_dir";
print "\n build_registers -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -bus_intf bus_interface -dest_dir dest_dir";
print "\n";
exit 1;
}
95,8 → 94,6
 
$home = cwd();
 
my $dest_dir = $ARGV[0];
 
#############################################################################
##
##
122,24 → 119,42
my $memmap_base;
my $addblk_name;
my $addblk_range;
my $addblk_numrange;
my $addblk_numaddbits;
my $addblk_width;
my $byte_size;
my $byte_size;
my $reg_dim;
my $memMap;
 
if ($opt_full_word)
{
$byte_size = 32;
}
elsif($opt_word)
{
$byte_size = 16;
}
else
{
$byte_size = 8;
}
 
my $memmap_name;
my $memmap_base;
my $memmap_numbase;
my $memmap_size;
my $memmap_type;
my $parmap_name;
 
my $reg_offset;
my $reg_numoffset;
my $reg_dimbits;
my $reg_create;
my $reg_has_read;
my $reg_has_write;
my $opt_bigendian;
 
my $reg_numdim;
 
my $max_dim = 1;
my $max_has_read = 0;
my $max_has_write = 0;
my $max_has_create = 0;
 
my $pad;
my $sys_byte_lanes;
 
 
@registers = ();
 
#/**********************************************************************/
#/* */
#/* Parse register block info from ip-xact file */
161,36 → 176,36
$library = $comp->findnodes('./spirit:library/text()')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:name'))
foreach my $bus_iface ($spirit_component_file->findnodes("//spirit:busInterface[spirit:name/text() = '$bus_intf']/spirit:slave"))
{
$memmap_name = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('../spirit:baseAddress/text()')->to_literal ;
$BI_name = $bus_iface->findnodes('../spirit:name/text()')->to_literal ;
$BI_endian = $bus_iface->findnodes('../spirit:endianness/text()')->to_literal ;
$BI_width = $bus_iface->findnodes('../spirit:bitsInLau/text()')->to_literal ;
$BI_xname = $bus_iface->findnodes('../spirit:abstractionType/@spirit:name')->to_literal ;
$memMap = $bus_iface->findnodes('../spirit:slave/spirit:memoryMapRef/@spirit:memoryMapRef')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:name'))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
}
$addblk_range = hex($addblk_range);
$addblk_range = log($addblk_range)/log(2);
my $sys_byte_lanes = int( $addblk_width) / $byte_size ;
unless($BI_endian) {$BI_endian = "little";}
$byte_size = int($BI_width) ;
 
if ($sys_byte_lanes == 4 ) { $adr_base = 2;}
elsif ($sys_byte_lanes == 2 ) { $adr_base = 1;}
else { $adr_base = 0;}
print "ZZZZZZQ $library $name $version bus_intf:: $bus_intf name:: $BI_name abstract:: $BI_xname endian:: $BI_endian width:: $BI_width | $byte_size | Map:: $BI_mm \n";
 
my $variant;
if($version) {$variant ="${name}_${version}_${memmap_name}";}
else {$variant ="${name}_${memmap_name}";}
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']"))
{
$memmap_name = $comp_view->findnodes('./spirit:bank/spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('./spirit:bank/spirit:baseAddress/text()')->to_literal ;
$memmap_size = $comp_view->findnodes('./spirit:addressUnitBits/text()')->to_literal ;
$memmap_type = $comp_view->findnodes('./spirit:bank/@spirit:bankAlignment')->to_literal ;
$parmap_name = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
print "ZZZZZZR Name: $memmap_name Base: $memmap_base Type: $memmap_type Size: $memmap_size Parent: $parmap_name \n";
 
 
$memmap_numbase = hex($memmap_base);
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
198,42 → 213,204
#/* */
#/**********************************************************************/
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${variant}";
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${name}_${version}_${memmap_name}";
open OUTFILE,">$outfile" or die "unable to open $outfile";
print OUTFILE " /*********************************************/ \n";
print OUTFILE " /* Register module */ \n";
print OUTFILE sprintf(" /* Vendor: %24s */ \n",$vendor);
print OUTFILE sprintf(" /* Library: %24s */ \n",$library);
print OUTFILE sprintf(" /* Component: %24s */ \n",$name);
print OUTFILE sprintf(" /* Version: %24s */ \n",$version);
print OUTFILE sprintf(" /* Module: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* MemMap: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* Base: %24s */ \n",$memmap_base);
print OUTFILE sprintf(" /* Type: %24s */ \n",$memmap_type);
 
 
 
 
if($BI_endian eq "big" )
{
$opt_bigendian = 1;
print OUTFILE " /* Endian: Big */ \n";
}
else
 
{
print OUTFILE " /* Endian: Little */ \n";
$opt_bigendian = 0;
}
 
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock/spirit:name"))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
print "ZZZZZZS addblk Name: $addblk_name Range: $addblk_range Size: $addblk_width \n";
 
 
$addblk_numrange = hex($addblk_range);
$addblk_numaddbits = log($addblk_numrange)/log(2);
$sys_byte_lanes = int( $addblk_width) / $byte_size ;
 
if ($sys_byte_lanes == 4 ) { $adr_base = 2;}
elsif ($sys_byte_lanes == 2 ) { $adr_base = 1;}
else { $adr_base = 0;}
 
 
print OUTFILE sprintf(" /* AddressBlock: %24s */ \n",$addblk_name);
print OUTFILE sprintf(" /* NumBase: %24s */ \n",$memmap_numbase);
print OUTFILE sprintf(" /* Range: %24s */ \n",$addblk_range);
print OUTFILE sprintf(" /* NumRange: %24s */ \n",$addblk_numrange);
print OUTFILE sprintf(" /* NumAddBits: %24s */ \n",$addblk_numaddbits);
print OUTFILE sprintf(" /* Width: %24s */ \n",$addblk_width);
print OUTFILE sprintf(" /* Byte_lanes: %24s */ \n",$sys_byte_lanes);
print OUTFILE sprintf(" /* Byte_size: %24s */ \n",$byte_size);
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
foreach my $reg_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock[spirit:name/text() = '$addblk_name']/spirit:register/spirit:name "))
 
{
$reg_name = $reg_view->findnodes('./text()')->to_literal ;
$reg_offset = $reg_view->findnodes('../spirit:addressOffset/text()')->to_literal ;
$reg_dim = $reg_view->findnodes('../spirit:dim/text()')->to_literal ;
$reg_size = $reg_view->findnodes('../spirit:size/text()')->to_literal ;
$reg_access = $reg_view->findnodes('../spirit:access/text()')->to_literal ;
$reg_numoffset = hex($reg_offset) + $memmap_numbase;
unless($reg_dim) {$reg_dim = "0x1" ;}
$reg_numdim = hex($reg_dim);
 
if($reg_numdim > $max_dim ) {$max_dim = $reg_numdim;}
 
if($reg_numdim)
{
$reg_dimbits = log($reg_numdim)/log(2);
}
else
{
$reg_dimbits = 1;
}
 
if($reg_access eq "read-write")
{
$reg_has_read = 1;
$reg_has_write = 1;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
}
 
 
 
 
 
 
if($reg_access eq "read-only")
{
$reg_has_read = 1;
$reg_has_write = 0;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
 
}
 
 
if($reg_access eq "write-only")
{
$reg_has_read = 0;
$reg_has_write = 1;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
 
}
 
 
if($reg_access eq "write-strobe")
{
$reg_has_read = 0;
$reg_has_write = 1;
$reg_create = 0;
}
if ($opt_bigendian)
{
print OUTFILE " /* Endian: Big */ \n";
}
else
{
print OUTFILE " /* Endian: Little */ \n";
$opt_bigendian = 0;
}
if($reg_has_read){$max_has_read = 1;}
if($reg_has_write){$max_has_write = 1;}
if($reg_create) {$max_has_create = 1;}
 
 
 
 
 
print "ZZZZZZT reg Name: $reg_name Base: hex(${memmap_base}) Offset: hex(${reg_offset}) Dim: $reg_dim Size: $reg_size Depth: 1 $reg_access \n";
print OUTFILE sprintf(" /* Reg Name: %22s */ \n",$reg_name);
print OUTFILE sprintf(" /* Reg Offset: %22s */ \n",$reg_offset);
print OUTFILE sprintf(" /* Reg numOffset: %22s */ \n",$reg_numoffset);
print OUTFILE sprintf(" /* Reg size: %22s */ \n",$reg_size);
print OUTFILE sprintf(" /* Reg Dim: %22s */ \n",$reg_dim);
print OUTFILE sprintf(" /* Reg numDim: %22s */ \n",$reg_numdim);
print OUTFILE sprintf(" /* Reg DimBits: %22s */ \n",$reg_dimbits);
print OUTFILE sprintf(" /* Reg Create: %22s */ \n",$reg_create);
print OUTFILE sprintf(" /* Reg access: %22s */ \n",$reg_access);
print OUTFILE sprintf(" /* Reg has_read: %22s */ \n",$reg_has_read);
print OUTFILE sprintf(" /* Reg has_write: %22s */ \n",$reg_has_write);
print OUTFILE sprintf(" /*********************************************/ \n");
 
push @registers , ":::${reg_name}:::${reg_numoffset}:::${reg_size}:::${reg_numdim}:::${reg_dimbits}:::${reg_create}:::${reg_access}:::${reg_has_read}:::${reg_has_write}:::";
 
}
}
if($memmap_type eq "serial") { $memmap_numbase = $memmap_numbase + $addblk_numrange; }
 
 
 
}
 
 
 
 
$num_add = log($max_dim)/log(2);
print OUTFILE sprintf(" /*********************************************/ \n");
print OUTFILE sprintf(" /* Max_dim: %22s */ \n",$max_dim);
print OUTFILE sprintf(" /* num_add: %22s */ \n",$num_add);
print OUTFILE sprintf(" /* mas_has_read: %22s */ \n",$max_has_read);
print OUTFILE sprintf(" /* mas_has_write: %22s */ \n",$max_has_write);
print OUTFILE sprintf(" /* mas_has_create: %22s */ \n",$max_has_create);
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
 
 
 
 
 
 
 
 
print OUTFILE " /*********************************************/ \n";
print OUTFILE "\n\nmodule `VARIANT`";
print OUTFILE uc(${memmap_name});
240,67 → 417,64
print OUTFILE "\n";
print OUTFILE "#( parameter UNSELECTED = {${addblk_width}{1'b1}},\n";
print OUTFILE " parameter UNMAPPED = {${addblk_width}{1'b0}}";
#/*********************************************************************************/
#/* */
#/* Add parameters for write reset states and fillers for reading short registers */
#/* */
#/* */
#/*********************************************************************************/
my $has_read = 0;
my $has_write = 0;
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
 
 
 
 
 
 
 
foreach $line (@registers)
{
 
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
if( $t_has_write eq "1" and $t_create eq "1")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_RST = ${t_size}'b0";
}
 
$pad = $byte_size -( int(${t_size}) % $byte_size ) ;
if ( $pad == $byte_size ) { $pad = 0;}
if( $register_access eq "read-write" or $register_access eq "write-only")
{
$has_write = 1;
print OUTFILE ",\n parameter ";
print OUTFILE uc(${register_name});
print OUTFILE "_RST = ${register_size}'b0";
}
if( $register_access eq "read-write" or $register_access eq "read-only")
{
$has_read = 1;
}
if($pad)
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_PAD = ${pad}'b0";
}
my $pad = $byte_size -( int(${register_size}) % $byte_size ) ;
if ( $pad == $byte_size ) { $pad = 0;}
if($pad)
{
if( $register_access eq "read-write" or $register_access eq "read-only")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${register_name});
print OUTFILE "_PAD = ${pad}'b0";
}
print "ZZZZZZA :::${t_name}:::${t_numoffset}:::${t_size}:::${t_numdim}:::${t_dimbits}:::${t_create}:::${t_access}:::${t_has_read}:::${t_has_write}::: \n";
}
}
}
}
print OUTFILE ")\n ";
 
 
 
print OUTFILE ")\n ";
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print io ports */
313,155 → 487,130
print OUTFILE " input wire reset,\n";
print OUTFILE " input wire enable,\n";
print OUTFILE " input wire cs,\n";
if($has_write){ print OUTFILE " input wire wr,\n";}
if($has_read) {print OUTFILE " input wire rd,\n";}
if($has_write) {print OUTFILE " input wire [${addblk_width}-1:0] wdata,\n";}
if($has_read) {print OUTFILE " output reg [${addblk_width}-1:0] rdata,\n";}
if($max_has_write){ print OUTFILE " input wire wr,\n";}
if($max_has_read) {print OUTFILE " input wire rd,\n";}
if($max_has_write) {print OUTFILE " input wire [${addblk_width}-1:0] wdata,\n";}
if($max_has_read) {print OUTFILE " output reg [${addblk_width}-1:0] rdata,\n";}
print OUTFILE " input wire [${sys_byte_lanes}-1:0] byte_lanes,\n";
print OUTFILE " input wire [${addblk_range}-1:${adr_base}] addr";
print OUTFILE " input wire [${addblk_numaddbits}-1:${adr_base}] addr";
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
if($max_dim gt "1" )
{
print OUTFILE " ,\n output wire [${num_add}-1:0] addr_out";
}
 
$register_size = int($register_size);
if($register_size == 1)
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg $register_name ";
print OUTFILE ",\n input wire next_${register_name} ";
print OUTFILE ",\n input wire ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg $register_name ";
print OUTFILE ",\n input wire next_${register_name} ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "read-only")
{
print OUTFILE ",\n input wire ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
}
}
else
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg [${register_size}-1:0] $register_name ";
print OUTFILE ",\n input wire [${register_size}-1:0] next_${register_name} ";
print OUTFILE ",\n input wire [${register_size}-1:0] ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
 
}
if( $register_access eq "write-only")
 
 
 
 
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
print OUTFILE ",\n output reg [${register_size}-1:0] $register_name ";
print OUTFILE ",\n input wire [${register_size}-1:0] next_${register_name} ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
print OUTFILE ",\n output wire ${t_name}_cs ";
print OUTFILE ",\n output reg ${t_name}_dec ";
 
}
if($t_size == 1)
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n input wire ${t_name}_rdata ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg [${register_size}-1:0] ${register_name}_wdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
if( $t_create eq "1")
{
print OUTFILE ",\n output reg $t_name ";
print OUTFILE ",\n input wire next_${t_name} ";
}
else
{
print OUTFILE ",\n output reg ${t_name}_wdata ";
}
}
}
else
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n input wire [${t_size}-1:0] ${t_name}_rdata ";
}
if( $register_access eq "read-only")
{
print OUTFILE ",\n input wire [${register_size}-1:0] ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
if( $t_create eq "1")
{
print OUTFILE ",\n output reg [${t_size}-1:0] $t_name ";
print OUTFILE ",\n input wire [${t_size}-1:0] next_${t_name} ";
}
else
{
print OUTFILE ",\n output reg [${t_size}-1:0] ${t_name}_wdata ";
}
}
}
}
 
if($register_size > ${byte_size})
{
if( $register_access eq "read-write")
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
if($t_size > ${byte_size}) { print OUTFILE ",\n output reg ${t_name}_wr_1 "; }
if($t_size > (${byte_size}*2)) { print OUTFILE ",\n output reg ${t_name}_wr_2 "; }
if($t_size > (${byte_size}*3)) { print OUTFILE ",\n output reg ${t_name}_wr_3 "; }
}
}
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
}
print OUTFILE "\n);\n\n\n";
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
}
}
 
 
if($register_size > (${byte_size}*2))
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
}
 
 
 
if($register_size > (${byte_size}*3))
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
}
 
 
 
}
print OUTFILE "\n);\n\n\n";
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print parameters for register addresses */
469,71 → 618,74
#/* */
#/**********************************************************************/
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
print OUTFILE "parameter ";
print OUTFILE uc(${t_name});
print OUTFILE " = ${addblk_numaddbits}'d${t_numoffset};\n";
my $register_addressOffset_end = $t_numoffset + $t_numdim;
print OUTFILE "parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_END = ${addblk_numaddbits}'d${register_addressOffset_end};\n";
 
}
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
print OUTFILE "parameter ";
print OUTFILE uc(${register_name});
print OUTFILE " = ${addblk_range}'d${register_addressOffset};\n";
}
print OUTFILE "\n\n";
print OUTFILE " reg [${addblk_width}-1:0] rdata_i;\n";
}
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* write data register creation */
#/* */
#/* */
#/**********************************************************************/
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
 
print OUTFILE "\n\n";
print OUTFILE " reg [${addblk_width}-1:0] rdata_i;\n";
if($register_size eq 1)
{
if( $register_access eq "read-write")
{
print OUTFILE "reg ${register_name}_wdata;\n";
}
if( $register_access eq "write-only")
{
print OUTFILE "reg ${register_name}_wdata;\n";
}
 
}
else
{
if( $register_access eq "read-write")
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
print OUTFILE "reg [${register_size}-1:0] ${register_name}_wdata;\n";
}
if( $register_access eq "write-only")
{
print OUTFILE "reg [${register_size}-1:0] ${register_name}_wdata;\n ";
}
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
if(( $t_has_write eq "1") and ( $t_create eq "1"))
{
if($t_size eq 1){ print OUTFILE "reg ${t_name}_wdata;\n";}
else { print OUTFILE "reg [${t_size}-1:0] ${t_name}_wdata;\n";}
}
}
}
}
 
 
 
551,6 → 703,7
 
 
 
 
#/**********************************************************************/
#/* */
605,21 → 758,29
print OUTFILE "/*QQQ Reg_Name Reg_Access sys_byte_lanes reg_byte_lanes reg_size reg_add ar_base log_byte_lane phy_byte_lane reg_lane pad_size padding bigend */ \n";
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
627,22 → 788,23
$pad_size = ${byte_size};
}
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
my $strng = sprintf( "/*QQQ %16s %12s %11s %6s %6s %6s %6s %6s %6s %6s %2s %6s %6s */ \n",${t_name},${t_access},${sys_byte_lanes},${reg_byte_lanes},${t_size},${t_numoffset},${adr_base},${log_byte_lane},${phy_byte_lane},${reg_byte_lane},${pad_size},${padding},${opt_bigendian});
my $strng = sprintf( "/*QQQ %16s %12s %11s %6s %6s %6s %6s %6s %6s %6s %2s %6s %6s */ \n",${register_name},${register_access},${sys_byte_lanes},${reg_byte_lanes},${register_size},${register_addressOffset},${adr_base},${log_byte_lane},${phy_byte_lane},${reg_byte_lane},${pad_size},${padding},${opt_bigendian});
print OUTFILE $strng;
 
}
 
 
}
}
print OUTFILE "\n\n\n";
 
#/**********************************************************************/
#/* */
#/* Read Data Muxing */
651,7 → 813,7
#/**********************************************************************/
if($has_read)
if($max_has_read == "1" and $max_has_create == "1")
{
print OUTFILE "always@(*)\n";
print OUTFILE " if(rd && cs)\n";
664,40 → 826,54
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
print OUTFILE "always@(*)\n";
print OUTFILE " case(addr[$addblk_range-1:${adr_base}])\n";
print OUTFILE " case(addr[$addblk_numaddbits-1:${adr_base}])\n";
 
 
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
my $REG_NAME = uc($t_name);
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
my $REG_NAME = uc($register_name);
if(( $register_access eq "read-write") or ( $register_access eq "read-only"))
if( $t_has_read eq "1" )
{
if(( $sys_byte_lanes eq "1" ) and ( $reg_byte_lanes eq "1") )
704,15 → 880,15
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding)
{
if($pad_size eq "1")
{ print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n";}
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else
{ print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n";}
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n";}
}
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
 
 
722,14 → 898,14
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
}
}
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
737,19 → 913,19
if($opt_bigendian)
{
print OUTFILE "{";
print OUTFILE "${REG_NAME}[$addblk_range-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
}
}
757,26 → 933,26
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
}
}
785,27 → 961,27
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*3)] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*2)-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*3)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*2)-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
}
}
815,21 → 991,21
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n"; }
}
else
{
 
 
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
 
unless ($log_byte_lane){
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
}
 
 
841,35 → 1017,35
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$phy_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$phy_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n"; }
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n";}
}
}
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
}
 
 
877,8 → 1053,8
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
}
 
 
885,9 → 1061,9
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
}
 
 
896,29 → 1072,167
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
}
}
 
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " default: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
print OUTFILE " endcase\n\n";
 
 
 
 
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Read Data Muxing */
#/* */
#/* */
#/**********************************************************************/
if($max_has_read == "1" and $max_has_create == "0" )
{
print OUTFILE "always@(*)\n";
print OUTFILE " if(rd && cs)\n";
print OUTFILE " begin\n";
print OUTFILE " if(byte_lanes[ $phy_byte_lane ])\n";
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; \n";
print OUTFILE " else\n";
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
print OUTFILE " end\n";
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
print OUTFILE " rdata_i = UNMAPPED;\n";
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
 
my $REG_NAME = uc($t_name);
 
 
if( $t_has_read eq "1" )
{
print OUTFILE "if( ${t_name}_cs ) rdata_i = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n";}
}
 
 
 
 
print OUTFILE "\n";
 
 
 
}
 
 
}
 
print OUTFILE " end\n\n";
 
 
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Write Data Selection */
#/* */
#/* */
926,47 → 1240,52
if($has_write)
if($max_has_write)
{
 
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
 
my $REG_NAME = uc($t_name);
 
 
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
my $REG_NAME = uc($register_name);
if(( $register_access eq "read-write") or ( $register_access eq "write-only") or ( $register_access eq "write-strobe") )
if( $t_has_write eq "1" )
{
if ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "1"))
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0];// 1\n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0];// 1\n";
}
 
elsif( $sys_byte_lanes eq $reg_byte_lanes )
973,13 → 1292,13
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}];// 2\n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}];// 2\n";
 
}
else
{
 
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 3 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 3 \n";
}
}
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
986,18 → 1305,18
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:0]; // 4 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:0]; // 4 \n";
 
 
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 5 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 5 \n";
 
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 6 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 6 \n";
 
 
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // ${byte_size}-1 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // ${byte_size}-1 \n";
 
}
}
1006,15 → 1325,15
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 8 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 9 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 10 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 8 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 9 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 10 \n";
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 11 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 12 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 13 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 11 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 12 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 13 \n";
}
}
1022,18 → 1341,18
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 14 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 15 \n";
print OUTFILE "${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 16 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 17 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 14 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 15 \n";
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 16 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 17 \n";
 
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 18 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 19 \n";
print OUTFILE "${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 20 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 21 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 18 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 19 \n";
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 20 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 21 \n";
}
}
1041,14 → 1360,14
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 22 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 22 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
if($log_byte_lane == 0)
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
}
}
}
1057,21 → 1376,21
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 24 \n";
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1+$(byte_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 25 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 24 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1+$(byte_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 25 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 26 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 26 \n";
if($log_byte_lane)
{
 
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
}
else
{
 
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
}
}
1079,22 → 1398,22
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 28 \n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 28 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 29 \n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 29 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 30 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 30 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($phy_byte_lane) ne "3" )
1101,16 → 1420,18
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 32 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 32 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 33 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 33 \n";
}
}
 
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " end\n\n";
1119,13 → 1440,6
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Write strobe Creation */
1138,41 → 1452,55
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
my $REG_NAME = uc($t_name);
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
 
 
 
my $REG_NAME = uc($register_name);
 
if(( $register_access eq "read-write") or ( $register_access eq "write-only") or ( $register_access eq "write-strobe") )
if( $t_has_write eq "1" )
{
if ( $sys_byte_lanes eq $reg_byte_lanes )
{
print OUTFILE "${register_name}_wr_${phy_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${phy_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
 
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
1179,14 → 1507,14
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b1} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
 
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
}
}
1194,15 → 1522,15
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
}
}
1210,17 → 1538,17
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
 
}
}
1229,12 → 1557,12
{
if ($log_byte_lane == 0 )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
elsif ($log_byte_lane == 1 )
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
}
}
 
1244,13 → 1572,13
{
if ($log_byte_lane == 0 )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
elsif ($log_byte_lane == 1 )
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
}
 
1261,22 → 1589,22
 
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($log_byte_lane ne "3") )
1283,11 → 1611,11
{
if( ${reg_byte_lanes}-1 == $log_byte_lane )
{
print OUTFILE "${register_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
}
 
1294,15 → 1622,17
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " end\n\n";
 
 
}
 
 
 
 
}
 
 
 
1315,23 → 1645,6
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
1340,36 → 1653,48
#/* */
#/* */
#/**********************************************************************/
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
 
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
 
my $REG_NAME = uc($t_name);
 
 
 
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
 
 
my $REG_NAME = uc($register_name);
 
 
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
1392,111 → 1717,107
}
elsif ( ( $sys_byte_lanes == 2) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 2) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
}
}
 
}
 
}
 
 
 
 
 
}
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
 
 
 
 
 
 
 
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
 
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
my $REG_NAME = uc($t_name);
 
$reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
 
 
my $REG_NAME = uc($register_name);
 
 
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:0]== ${REG_NAME}[$addblk_range-1:0] );// 1\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:0]== ${REG_NAME}[$addblk_numaddbits-1:0] );// 1\n"
}
 
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 2))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:1]== ${REG_NAME}[$addblk_range-1:1] );// 2\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 2\n"
}
 
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 3\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 3\n"
}
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 2))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:1]== ${REG_NAME}[$addblk_range-1:1] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
 
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
 
1504,8 → 1825,15
 
}
 
}
 
print OUTFILE "\n\n always@(*)\n begin\n";
foreach my $add_line (@add_decs)
{
print OUTFILE "${add_line}";
}
 
print OUTFILE "\n end\n\n";
 
 
 
1515,38 → 1843,81
 
 
 
print OUTFILE "\n\n always@(*)\n begin\n";
foreach my $add_line (@add_decs)
{
print OUTFILE "${add_line}";
}
 
print OUTFILE "\n end\n\n";
 
 
#/**********************************************************************/
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Create Chip Selects */
#/* */
#/* */
#/**********************************************************************/
 
print OUTFILE "\n /* verilator lint_off UNSIGNED */ \n";
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $REG_NAME = uc($t_name);
print OUTFILE "assign ${t_name}_cs = cs && ( addr >= ${REG_NAME} ) && ( addr < ${REG_NAME}_END );\n";
}
}
 
 
print OUTFILE "\n /* verilator lint_on UNSIGNED */ \n";
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Create Registers */
#/* */
#/* */
#/**********************************************************************/
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
1554,14 → 1925,13
$pad_size = ${byte_size};
}
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
if(( $register_access eq "read-write") or ( $register_access eq "write-only") )
if(( $t_has_write eq "1") and ( $t_create eq "1") )
{
print OUTFILE " always@(posedge clk)\n if(reset) $register_name <= ";
print OUTFILE uc($register_name);
print OUTFILE " always@(posedge clk)\n if(reset) $t_name <= ";
print OUTFILE uc($t_name);
print OUTFILE "_RST;\n else\n begin\n";
 
if($reg_byte_lanes == 1)
1568,42 → 1938,42
{
if($pad_size ==1)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name} <= ${register_name}_wdata ;\n";
print OUTFILE " else ${register_name} <= next_${register_name};\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name} <= ${t_name}_wdata ;\n";
print OUTFILE " else ${t_name} <= next_${t_name};\n\n";
}
else
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${pad_size}-1:0] <= ${register_name}_wdata[${pad_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${pad_size}-1:0] <= next_${register_name}[${pad_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${pad_size}-1:0] <= ${t_name}_wdata[${pad_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${pad_size}-1:0] <= next_${t_name}[${pad_size}-1:0];\n\n";
}
 
}
elsif($reg_byte_lanes == 2)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[${pad_size}+${byte_size}-1:${byte_size}] <= ${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+${byte_size}-1:${byte_size}] <= next_${register_name}[${pad_size}+${byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= ${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= next_${t_name}[${pad_size}+${byte_size}-1:${byte_size}];\n\n";
}
elsif($reg_byte_lanes == 3)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[$(byte_size}-1:${byte_size}] <= ${register_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[$(byte_size}-1:${byte_size}] <= next_${register_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${register_name}_wr_2) ${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= ${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= next_${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_2) ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= ${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= next_${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)];\n\n";
}
elsif($reg_byte_lanes == 4)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[$(byte_size}-1:${byte_size}] <= ${register_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[$(byte_size}-1:${byte_size}] <= next_${register_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${register_name}_wr_2) ${register_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= ${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${register_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= next_${register_name}[(${byte_size}*3)-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${register_name}_wr_3) ${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= ${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= next_${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_2) ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= ${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= next_${t_name}[(${byte_size}*3)-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${t_name}_wr_3) ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= ${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= next_${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)];\n\n";
}
 
print OUTFILE "\n end\n\n";
1618,6 → 1988,7
 
}
 
}
 
 
 
1625,12 → 1996,29
 
 
 
 
 
 
 
 
 
 
 
 
 
 
print OUTFILE "\nendmodule \n";
 
 
 
 
 
 
 
close OUTFILE ;
close OUTFILE ;
}
1
1
/build_verilog
68,6 → 68,8
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"dest_dir=s" => \$dest_dir,
"destination=s" => \$destination,
"fragment","no_port"
) || die "(use '$program_name -h' for help)";
 
77,7 → 79,7
## Help option
##############################################################################
if ( $opt_h or $opt_help )
{ print "\n build_verilog -view {sim/syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component component_name -comp_xml_sep /rtl/xml/ -variant variant_name -fragment -no_port file_destination ../verilog/";
{ print "\n build_verilog -view {sim/syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component component_name -comp_xml_sep /rtl/xml/ -variant variant_name -fragment -no_port -destination destination -dest_dir ../verilog/";
print "\n";
exit 1;
}
93,9 → 95,8
$home = cwd();
my $parser = XML::LibXML->new();
my $rtl_xml_sep = "/rtl/xml/";
my $destination = $ARGV[0];
my $dest_dir = $ARGV[1];
 
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
/build_header
0,0 → 1,458
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010-2012> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
use Cwd;
use XML::LibXML;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h",
"view=s" => \$view,
"prefix=s" => \$prefix,
"project=s" => \$project,
"lib_comp_sep=s" => \$lib_comp_sep,
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"dest_dir=s" => \$dest_dir,
"inst_path=s" => \$inst_path
) || die "(use '$program_name -h' for help)";
 
 
##############################################################################
## Help option
##############################################################################
if ( $opt_h )
{
print "\n build_header -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -inst_path a.b.c -dest_dir dest_dir \n";
exit 1;
}
 
 
##############################################################################
##
##############################################################################
 
 
 
$home = cwd();
 
 
my $vendor ="opencores.org";
my $rtl_xml_sep = "/rtl/xml/";
 
my $parser = XML::LibXML->new();
 
 
#############################################################################
##
##
#############################################################################
 
print " Building $view Headers for $prefix $project $component $variant in $dest_dir\n" ;
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}";
mkdir $path,0755 unless( -e $path );
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
#/* */
#/* */
#/**********************************************************************/
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}/${variant}_${inst_path}.h";
open OUTFILE,">$outfile" or die "unable to open $outfile";
print OUTFILE " /*********************************************/ \n";
print OUTFILE sprintf(" /* view: %24s */ \n",$view);
print OUTFILE sprintf(" /* project: %24s */ \n",$project);
print OUTFILE sprintf(" /* component: %24s */ \n",$component);
print OUTFILE sprintf(" /* variant: %24s */ \n",$variant);
print OUTFILE sprintf(" /* inst_path: %24s */ \n",$inst_path);
print OUTFILE " /*********************************************/ \n";
 
 
 
my $inst_name;
my $remainder;
 
$_ = $inst_path;
if(/(\w+)\.(\S+)/)
{
$inst_name = $1;
$remainder = $2;
print OUTFILE " /* INST = $inst_name then $remainder */ \n";
}
else
{
print OUTFILE " /* ERROR no inst_path */ \n";
}
 
 
 
 
my $spirit_component_file = $parser->parse_file("${home}/projects/${vendor}/${project}${lib_comp_sep}${component}${comp_xml_sep}${variant}.xml");
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view'))
{
my($view_name) = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
if($view_name eq "Hierarchical")
{
my($hier_ref_vendor) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:vendor')->to_literal ;
my($hier_ref_library) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:library')->to_literal ;
my($hier_ref_component) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:name')->to_literal ;
my($hier_ref_version) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:version')->to_literal ;
my $spirit_designCfg_file
= $parser->parse_file("${home}/projects/${hier_ref_vendor}/${hier_ref_library}${lib_comp_sep}${hier_ref_component}/ip-xact/${hier_ref_component}_${hier_ref_version}.xml");
 
 
foreach my $design_ref_view ($spirit_designCfg_file->findnodes('//spirit:designConfiguration'))
{
my($hier_xref_vendor) = $design_ref_view->findnodes('./spirit:designRef/@spirit:vendor')->to_literal ;
my($hier_xref_library) = $design_ref_view->findnodes('./spirit:designRef/@spirit:library')->to_literal ;
my($hier_xref_component) = $design_ref_view->findnodes('./spirit:designRef/@spirit:name')->to_literal ;
my($hier_xref_version) = $design_ref_view->findnodes('./spirit:designRef/@spirit:version')->to_literal ;
 
 
 
 
 
my $spirit_design_file = $parser->parse_file("${home}/projects/${hier_xref_vendor}/${hier_xref_library}${lib_comp_sep}${hier_xref_component}${comp_xml_sep}${hier_xref_component}_${hier_xref_version}.xml");
 
 
 
 
 
foreach my $x_name ($spirit_design_file->findnodes("//spirit:design/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
#/**********************************************************************/
#/* */
#/* Lookup VLNV for each instantiated component */
#/* */
#/**********************************************************************/
 
my($instance_name) = $x_name ->findnodes('./text()')->to_literal ;
my($vendor_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:vendor')->to_literal ;
my($library_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:library')->to_literal ;
my($component_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:name')->to_literal ;
my($version_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:version')->to_literal ;
 
my $variant = "${component_name}_${version_name}";
 
if($inst_name eq $instance_name){
 
print OUTFILE " /* $instance_name $vendor_name $library_name $component_name $version_name \n";
 
$_ = $remainder;
parse_hier($vendor_name , $library_name , $component_name, $variant, $remainder, $inst_name);
}
 
}
 
}
 
}
 
}
 
 
 
 
 
close OUTFILE ;
 
 
 
 
 
 
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
sub parse_hier
{
my @params = @_;
my $top_name = pop(@params);
my $inst_path = pop(@params);
my $variant = pop(@params);
my $component = pop(@params);
my $project = pop(@params);
my $vendor = pop(@params);
 
$home = cwd();
 
 
 
 
my $spirit_component_file = $parser->parse_file("${home}/projects/${vendor}/${project}${lib_comp_sep}${component}${rtl_xml_sep}${variant}.xml");
 
 
my $inst_name;
my $remainder;
 
$_ = $inst_path;
if(/(\w+)\.(\S+)/)
{
$inst_name = $1;
$remainder = $2;
print OUTFILE " /* INST = $inst_name then $remainder */ \n";
}
else
{
print_map($spirit_component_file, $top_name);
}
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view'))
{
my($view_name) = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
if($view_name eq "Hierarchical")
{
my($hier_ref_vendor) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:vendor')->to_literal ;
my($hier_ref_library) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:library')->to_literal ;
my($hier_ref_component) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:name')->to_literal ;
my($hier_ref_version) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:version')->to_literal ;
my $spirit_designCfg_file
= $parser->parse_file("${home}/projects/${hier_ref_vendor}/${hier_ref_library}${lib_comp_sep}${hier_ref_component}/ip-xact/${hier_ref_component}_${hier_ref_version}.xml");
 
 
foreach my $design_ref_view ($spirit_designCfg_file->findnodes('//spirit:designConfiguration'))
{
my($hier_xref_vendor) = $design_ref_view->findnodes('./spirit:designRef/@spirit:vendor')->to_literal ;
my($hier_xref_library) = $design_ref_view->findnodes('./spirit:designRef/@spirit:library')->to_literal ;
my($hier_xref_component) = $design_ref_view->findnodes('./spirit:designRef/@spirit:name')->to_literal ;
my($hier_xref_version) = $design_ref_view->findnodes('./spirit:designRef/@spirit:version')->to_literal ;
 
my $spirit_design_file = $parser->parse_file("${home}/projects/${hier_xref_vendor}/${hier_xref_library}${lib_comp_sep}${hier_xref_component}${rtl_xml_sep}${hier_xref_component}_${hier_xref_version}.xml");
 
 
foreach my $x_name ($spirit_design_file->findnodes("//spirit:design/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
#/**********************************************************************/
#/* */
#/* Lookup VLNV for each instantiated component */
#/* */
#/**********************************************************************/
 
my($instance_name) = $x_name ->findnodes('./text()')->to_literal ;
my($vendor_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:vendor')->to_literal ;
my($library_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:library')->to_literal ;
my($component_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:name')->to_literal ;
my($version_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:version')->to_literal ;
 
my $variant = "${component_name}_${version_name}";
 
if($inst_name eq $instance_name){
 
print OUTFILE " /* $instance_name $vendor_name $library_name $component_name $version_name \n";
my $spirit_component_file = $parser->parse_file("${home}${prefix}${library_name}${lib_comp_sep}${component_name}${rtl_xml_sep}${variant}.xml");
 
 
$_ = $remainder;
if(/(\w+)\.(\S+)/)
{
parse_hier($vendor_name , $library_name , $component_name, $variant, $remainder, $top_name);
}
else
{
print OUTFILE " /* mem_map $remainder */ \n";
 
 
 
print_map($spirit_component_file,$top_name);
 
 
 
 
 
 
 
 
}
}
}
}
}
}
}
 
 
 
sub print_map
{
my @params = @_;
my $inst_name = pop(@params);
my $spirit_component_file = pop(@params);
 
 
#/**********************************************************************/
#/* */
#/* Parse register block info from ip-xact file */
#/* */
#/* */
#/**********************************************************************/
 
my $byte_size=32;
 
foreach my $comp ($spirit_component_file->findnodes('//spirit:component'))
{
$name = $comp->findnodes('./spirit:name/text()')->to_literal ;
$version = $comp->findnodes('./spirit:version/text()')->to_literal ;
$vendor = $comp->findnodes('./spirit:vendor/text()')->to_literal ;
$library = $comp->findnodes('./spirit:library/text()')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:name'))
{
$memmap_name = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('../spirit:baseAddress/text()')->to_literal ;
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
#/* */
#/* */
#/**********************************************************************/
print OUTFILE " /***********************************************/ \n";
print OUTFILE " /* Register module */ \n";
print OUTFILE sprintf(" /* Vendor: %24s */ \n",$vendor);
print OUTFILE sprintf(" /* Library: %24s */ \n",$library);
print OUTFILE sprintf(" /* Component: %24s */ \n",$name);
print OUTFILE sprintf(" /* Version: %24s */ \n",$version);
print OUTFILE sprintf(" /* Module: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* Base: %24s */ \n",$memmap_base);
 
$memmap_base = hex($memmap_base);
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:name'))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
$addblk_drange = hex($addblk_range);
print OUTFILE sprintf(" /*: %14s %8s %16x */ \n",$addblk_name,$addblk_drange,$memmap_base);
$memmap_base = $memmap_base + $addblk_drange;
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($block_name) = $comp_view->findnodes('../../spirit:name/text()')->to_literal;
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
 
my $full_name = "${inst_name}_${register_name}";
 
 
if($block_name eq $addblk_name)
{
print OUTFILE sprintf("parameter %14s = %14s; /* %14s %14s */ \n",$full_name, $register_addressOffset, $register_size, $register_access );
}
 
 
}
 
 
 
 
 
 
 
 
 
}
}
 
 
 
}
1
build_header Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: build_verilogLibraryFile =================================================================== --- build_verilogLibraryFile (revision 115) +++ build_verilogLibraryFile (revision 116) @@ -70,7 +70,8 @@ "lib_comp_sep=s" => \$lib_comp_sep, "component=s" => \$component, "comp_xml_sep=s" => \$comp_xml_sep, - "variant=s" => \$variant + "variant=s" => \$variant, + "dest_dir=s" => \$dest_dir ) || die "(use '$program_name -h' for help)"; @@ -79,7 +80,7 @@ ############################################################################## if ( $opt_h or ($opt_help) ) { - print "\n build_verilogLibraryFile -view {sim|syn} -prefix path_to_component -project project_name -component component_name -variant variant_name"; + print "\n build_verilogLibraryFile -view {sim|syn} -prefix path_to_component -project project_name -component component_name -variant variant_name -dest_dir dest_dir"; print "\n"; exit 1; } @@ -93,8 +94,8 @@ $home = cwd(); -my $dest_dir = $ARGV[0]; + ############################################################################# ## ## @@ -119,6 +120,8 @@ + + foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view/spirit:fileSetRef')) { my($view_fileset) = $comp_view->findnodes('./spirit:localName/text()')->to_literal ;
/soc_generate
134,10 → 134,10
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "dash") {$cmd = "$cmd -${gen_param}";}
else {$cmd = "$cmd $gen_param";}
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name) {$cmd = "$cmd -${gen_param_name} $gen_param ";}
else {$cmd = "$cmd $gen_param";}
}
$cmd = "${cmd}\n";
my $cpu_load = 180;
148,11 → 148,13
{
if($gen_group eq $view_name )
{
# print "ZZZZZZG $cmd ";
if (system($cmd)) {}
}
}
else
{
# print "ZZZZZZH $cmd ";
if (system($cmd)) {}
}
}

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