OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/tools/sys
    from Rev 131 to Rev 133
    ↔ Reverse comparison
  •

Rev 131 → Rev 133

/build_sw_master
55,7 → 55,9
use lib './tools';
use sys::lib;
use yp::lib;
use Parallel::ForkManager;
 
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
98,6 → 100,8
my $prefix = yp::lib::get_workspace();
$prefix = "/${prefix}";
 
my $number_of_cpus = yp::lib::get_number_of_cpus();
 
my @vendors = yp::lib::find_vendors();
 
foreach my $vendor (@vendors)
151,14 → 155,110
my $codeSet_library = $i_name ->findnodes('../socgen:library/text()')->to_literal ;
my $codeSet_component = $i_name ->findnodes('../socgen:component/text()')->to_literal ;
my $codeSet_version = $i_name ->findnodes('../socgen:version/text()')->to_literal ;
my $codeSet_prefix = "${prefix}/${vendor}__${library}/children";
 
print "$codeSet_name $codeSet_vendor $codeSet_library $codeSet_component $codeSet_version \n ";
 
$cmd ="./tools/sys/build_generate -prefix ${prefix}/${vendor}__${library}/children -vendor ${codeSet_vendor} -library ${codeSet_library} -component ${codeSet_component} -version ${codeSet_version} \n";
if (system($cmd)) {}
}
print "$codeSet_name $codeSet_prefix $codeSet_vendor $codeSet_library $codeSet_component $codeSet_version \n ";
 
 
 
 
 
 
 
 
 
##############################################################################
##
##############################################################################
 
 
 
my @cmd_list = ();
 
 
 
 
my $lib_comp_sep = yp::lib::find_lib_comp_sep($codeSet_vendor,$codeSet_library,$codeSet_component);
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ Create filelists for simulation, synthesis and linting */
#/ */
#/ */
#/*********************************************************************************************/
 
my @filelist = yp::lib::parse_component_brothers("$codeSet_vendor","$codeSet_library","$codeSet_component","$codeSet_version");
 
foreach $line (@filelist)
{
$_ = $line;
if(/::(\S+)::(\S+)::(\S+)::(\S+)::/)
{
$new_library = $2;
$new_component = $3;
$new_vendor = $1;
$new_version = $4;
 
 
my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($new_vendor,$new_library,$new_component,$new_version));
 
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator/spirit:name"))
{
my($gen_name) = $i_name ->findnodes('../spirit:name/text()')->to_literal ;
my($gen_generatorExe) = $i_name ->findnodes('../spirit:generatorExe/text()')->to_literal ;
my($gen_phase) = $i_name ->findnodes('../spirit:phase/text()')->to_literal ;
 
my $cmd;
$cmd = " -prefix $codeSet_prefix -vendor $codeSet_vendor -library $codeSet_library -component $codeSet_component -version $codeSet_version ";
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:parameters/spirit:parameter"))
{
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${codeSet_prefix}/${codeSet_vendor}__${codeSet_library}${lib_comp_sep}${codeSet_component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${codeSet_prefix}/${codeSet_vendor}__${codeSet_library}${lib_comp_sep}${codeSet_component}/${gen_param}";}
elsif($gen_param_name) {$cmd = "$cmd -${gen_param_name} $gen_param ";}
else {$cmd = "$cmd $gen_param";}
}
 
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:vendorExtensions/socgen:envIdentifier"))
{
my($gen_envidentifier) = $i_name ->findnodes('./text()')->to_literal ;
 
my $New_cmd = " ${gen_generatorExe} -envidentifier $gen_envidentifier ${cmd}\n";
if(${gen_generatorExe} )
{
push @cmd_list, "${gen_phase}::$New_cmd";
}
}
}
}
}
 
 
 
my $manager = new Parallel::ForkManager( $number_of_cpus );
@cmd_list = sys::lib::trim_sort(@cmd_list);
my $cmd;
my $phase;
 
foreach my $Cmd_line (@cmd_list)
{
( $phase,$cmd) = split( /\::/ , $Cmd_line);
$manager->start and next;
if (system($cmd)) {}
$manager->finish;
}
 
$manager->wait_all_children;
print "Software COMPLETE \n";
}
 
}
 
}
166,5 → 266,26
 
 
return(0);
}
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/build_hw_master
128,8 → 128,288
my @params = @_;
my $library = pop(@params);
my $vendor = pop(@params);
my $cmd ="./tools/sys/build_hw ${vendor} ${library} \n";
print "$cmd";
if(system($cmd)){}
 
 
 
 
 
 
my $prefix = yp::lib::get_workspace();
$prefix = "/${prefix}";
 
 
 
my @kids = ( );
my @filelist = ( );
my @cmd_list = ( );
 
my @components = yp::lib::find_components($vendor,$library);
 
foreach my $component (@components)
{
 
my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
if($socgen_filename)
{
my $socgen_file = $parser->parse_file($socgen_filename);
 
#/*********************************************************************************************/
#/ files for simulation */
#/ */
#/*********************************************************************************************/
 
foreach my $i_name ($socgen_file->findnodes("//socgen:sim/socgen:testbenches/socgen:testbench/socgen:version"))
{
my $tb_version = $i_name ->findnodes('./text()')->to_literal ;
my $tb_variant = "${component}_${tb_version}";
 
foreach my $i_name ($socgen_file->findnodes("//socgen:testbench[socgen:variant/text() = '$tb_variant']/socgen:tools/socgen:tool"))
{
 
my $tb_tool = $i_name ->findnodes('./text()')->to_literal ;
 
if( ($tb_tool eq "icarus") || ($tb_tool eq "verilator") || ($tb_tool eq "rtl_check"))
 
{
@filelist = ( );
@filelist = yp::lib::parse_component_file("$vendor","$library","$component","$tb_version");
 
foreach $line (@filelist)
{
$_ = $line;
if(/::(\S+)::(\S+)::(\S+)::(\S+)::/)
{
$new_vendor = $1;
$new_proj = $2;
$new_comp = $3;
$new_version = $4;
}
if( ($vendor eq $new_vendor) && ( $library eq $new_proj) && ( $component eq $new_comp ) && ( $tb_version eq $new_version ) )
{
push @kids , "::${prefix}::${library}::${component}::${vendor}::${tb_version}::";
}
else
{
push @kids , "::${prefix}/${vendor}__${library}/children::${new_proj}::${new_comp}::${new_vendor}::${new_version}::";
}
}
}
 
 
if($tb_tool eq "coverage")
{
print " SIM COVERAGE testbench $vendor $library $component $tb_variant \n";
$cmd ="./tools/simulation/build_coverage -work_site $prefix -vendor $vendor -library $library -component $component -version $tb_version \n";
if (system($cmd)) {}
}
elsif($tb_tool eq "icarus")
{
print " SIM ICARUS testbench $vendor $library $component $tb_variant \n";
$cmd ="./tools/simulation/build_icarus_filelists -work_site $prefix -vendor $vendor -library $library -component $component -version $tb_version \n";
if (system($cmd)) {}
}
elsif($tb_tool eq "verilator")
{
print " SIM VERILATOR testbench $vendor $library $component $tb_variant \n";
$cmd ="./tools/simulation/build_verilator_filelists -work_site $prefix -vendor $vendor -library $library -component $component -version $tb_version \n";
if (system($cmd)) {}
}
elsif($tb_tool eq "rtl_check")
{
print " SIM RTL_CHECK testbench $vendor $library $component $tb_variant \n";
$cmd ="./tools/simulation/build_lint_filelists -work_site $prefix -vendor $vendor -library $library -component $component -version $tb_version \n";
if (system($cmd)) {}
}
}
 
}
 
 
#/*********************************************************************************************/
#/ files for synthesys */
#/ */
#/*********************************************************************************************/
 
foreach my $i_name ($socgen_file->findnodes("//socgen:syn/socgen:ise/socgen:chip/socgen:name"))
{
my $ise_name = $i_name ->findnodes('./text()')->to_literal ;
print " SYN ISE $vendor $library $component $ise_name \n";
 
@filelist = ( );
@filelist = yp::lib::parse_component_file("$vendor","$library","$component","$ise_name");
 
foreach $line (@filelist)
{
$_ = $line;
if(/::(\S+)::(\S+)::(\S+)::(\S+)::/)
{
$new_vendor = $1;
$new_proj = $2;
$new_comp = $3;
$new_version = $4;
}
 
if( ($vendor eq $new_vendor) && ( $library eq $new_proj) && ( $component eq $new_comp ) && ( $ise_name eq $new_version ) )
{
push @kids , "::${prefix}::${library}::${component}::${vendor}::${ise_name}::";
}
else
{
push @kids , "::${prefix}/${vendor}__${library}/children::${new_proj}::${new_comp}::${new_vendor}::${new_version}::";
}
}
}
 
}
}
 
 
 
 
#/**********************************************************************/
#/* */
#/* Sort out the duplicate names and then build the rtl for every */
#/* component needed for simulations or synthesys */
#/* */
#/**********************************************************************/
 
 
@kids = sys::lib::trim_sort(@kids);
foreach my $kid (@kids)
{
$_ = $kid;
 
if(/::(\S+)::(\S+)::(\S+)::(\S+)::(\S+)::/)
{
my $kid_prefix = $1;
my $kid_library = $2;
my $kid_component = $3;
my $kid_vendor = $4;
my $kid_version = $5;
 
 
 
 
 
 
 
#############################################################################
##
##
#############################################################################
 
 
 
 
my $lib_comp_sep = yp::lib::find_lib_comp_sep($kid_vendor,$kid_library,$kid_component);
 
 
 
 
 
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ Create filelists for simulation, synthesis and linting */
#/ */
#/ */
#/*********************************************************************************************/
 
my @filelist = yp::lib::parse_component_brothers("$kid_vendor","$kid_library","$kid_component","$kid_version");
 
foreach $line (@filelist)
{
$_ = $line;
if(/::(\S+)::(\S+)::(\S+)::(\S+)::/)
{
$new_library = $2;
$new_component = $3;
$new_vendor = $1;
$new_version = $4;
 
 
my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($new_vendor,$new_library,$new_component,$new_version));
 
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator/spirit:name"))
{
my($gen_name) = $i_name ->findnodes('../spirit:name/text()')->to_literal ;
my($gen_generatorExe) = $i_name ->findnodes('../spirit:generatorExe/text()')->to_literal ;
my($gen_phase) = $i_name ->findnodes('../spirit:phase/text()')->to_literal ;
 
 
my $cmd;
$cmd = " -prefix $kid_prefix -vendor $kid_vendor -library $kid_library -component $kid_component -version $kid_version ";
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:parameters/spirit:parameter"))
{
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${kid_prefix}/${kid_vendor}__${kid_library}${lib_comp_sep}${kid_component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${kid_prefixn}/${kid_vendor}__${kid_library}${lib_comp_sep}${kid_component}/${gen_param}";}
elsif($gen_param_name) {$cmd = "$cmd -${gen_param_name} $gen_param ";}
else {$cmd = "$cmd $gen_param";}
}
 
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:vendorExtensions/socgen:envIdentifier"))
{
my($gen_envidentifier) = $i_name ->findnodes('./text()')->to_literal ;
 
my $New_cmd = " ${gen_generatorExe} -envidentifier $gen_envidentifier ${cmd}\n";
if(${gen_generatorExe} )
{
push @cmd_list, "${gen_phase}::$New_cmd";
}
}
}
}
}
 
 
 
 
 
 
 
 
}
 
}
 
 
 
 
@cmd_list = sys::lib::trim_sort(@cmd_list);
my $cmd;
my $phase;
 
foreach my $Cmd_line (@cmd_list)
{
 
( $phase,$cmd) = split( /\::/ , $Cmd_line);
if (system($cmd)) {}
}
 
 
 
return(0);
}
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/build_generate
92,7 → 92,9
 
my $home = cwd();
 
my @cmd_list = ();
 
 
#############################################################################
##
##
101,9 → 103,7
 
 
 
#print "\n FFFFFFFFFFFF GENERATE $prefix $vendor $library $component $version \n" ;
 
 
my $parser = XML::LibXML->new();
 
my $lib_comp_sep = yp::lib::find_lib_comp_sep($vendor,$library,$component);
134,8 → 134,8
$new_component = $3;
$new_vendor = $1;
$new_version = $4;
# print " FFFFFFFFFFFFFFFF Brother $new_vendor $new_library $new_component $new_version \n" ;
 
 
my $spirit_component_file = $parser->parse_file(yp::lib::find_ipxact_component($new_vendor,$new_library,$new_component,$new_version));
 
foreach my $i_name ($spirit_component_file->findnodes("//spirit:componentGenerator/spirit:name"))
142,7 → 142,7
{
my($gen_name) = $i_name ->findnodes('../spirit:name/text()')->to_literal ;
my($gen_generatorExe) = $i_name ->findnodes('../spirit:generatorExe/text()')->to_literal ;
# print " FFFFFFFFFFFFFFFF $gen_name $gen_generatorExe \n" ;
my($gen_phase) = $i_name ->findnodes('../spirit:phase/text()')->to_literal ;
 
my $cmd;
$cmd = " -prefix $prefix -vendor $vendor -library $library -component $component -version $version ";
165,7 → 165,8
my $New_cmd = " ${gen_generatorExe} -envidentifier $gen_envidentifier ${cmd}\n";
if(${gen_generatorExe} )
{
if (system($New_cmd)) {}
push @cmd_list, "${gen_phase}::$New_cmd";
# if (system($New_cmd)) {}
}
}
}
172,10 → 173,21
}
}
 
@cmd_list = sys::lib::trim_sort(@cmd_list);
my $cmd;
my $phase;
 
foreach my $Cmd_line (@cmd_list)
{
 
( $phase,$cmd) = split( /\::/ , $Cmd_line);
 
if (system($cmd)) {}
}
 
 
 
 
1
 
 
/build_elab_master
55,6 → 55,7
use lib './tools';
use sys::lib;
use yp::lib;
use Parallel::ForkManager;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
73,7 → 74,7
## Help option
##############################################################################
if ( $opt_h or $opt_help )
{ print "\n build_master";
{ print "\n build_elab_master";
print "\n";
exit 1;
}
93,6 → 94,12
#/* */
#/**********************************************************************/
 
my @elab_cmds = ();
my @des_cmds = ();
my @gen_cmds = ();
 
my $number_of_cpus = yp::lib::get_number_of_cpus();
 
my $home = cwd();
 
my $prefix = yp::lib::get_workspace();
113,7 → 120,7
my $library_status = yp::lib::get_library_status($vendor,$library);
if($library_status eq "active")
{
print "$vendor $library \n ";
# print "$vendor $library \n ";
run_vendor_library ( $vendor , $library)
}
}
139,11 → 146,57
{
my $socgen_file = $parser->parse_file($socgen_filename);
 
#print "ELAB_XXXXX build_master $vendor $library \n";
 
#/*********************************************************************************************/
#/ files for simulation */
#/ elaborate each testbench */
#/ */
#/*********************************************************************************************/
 
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
{
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
my $testbench_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
 
 
if(defined $testbench_configuration )
{
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration configuration -env sim -tool testbenches -unit testbench \n";
}
else
{
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool testbenches -unit testbench \n";
}
 
push @elab_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
push @des_cmds, $cmd;
 
if ($testbench_instance)
{
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";
 
push @gen_cmds, $cmd;
}
}
 
 
 
 
 
 
#/*********************************************************************************************/
#/ elaborate for each test */
#/ */
#/*********************************************************************************************/
 
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
{
my $test_name = $i_name ->findnodes('./text()')->to_literal ;
155,9 → 208,9
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
{
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
 
 
if($test_variant eq $testbench_variant )
164,38 → 217,208
{
# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
 
$cmd ="./tools/verilog/elab_verilog -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
print "$cmd";
if (system($cmd)) {}
#print "ELAB_XXXXX test_variant $vendor $library \n";
 
 
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
# print "$cmd";
# if (system($cmd)) {}
push @elab_cmds, $cmd;
 
 
 
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
# print "$cmd";
# if (system($cmd)) {}
push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
# print "$cmd";
# if (system($cmd)) {}
push @des_cmds, $cmd;
 
 
 
 
if ($testbench_instance)
{
 
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
 
if (system($cmd)) {}
push @gen_cmds, $cmd;
}
}
 
}
}
 
}
 
 
 
#/*********************************************************************************************/
#/ elaborate each fpga */
#/ */
#/*********************************************************************************************/
 
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
{
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
my $fpga_configuration = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
 
if(defined $fpga_configuration )
{
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -configuration $fpga_configuration -env syn -tool fpgas -unit fpga \n";
}
else
{
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool fpgas -unit fpga \n";
}
 
# push @elab_cmds, $cmd;
 
 
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
# push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} ";
# push @des_cmds, $cmd;
}
 
 
 
 
#/*********************************************************************************************/
#/ elaborate for each chip */
#/ */
#/*********************************************************************************************/
 
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))
{
my $chip_name = $i_name ->findnodes('./text()')->to_literal ;
my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
 
# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";
 
 
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
{
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
 
 
if($chip_variant eq $fpga_variant )
{
# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";
 
#print "ELAB_XXXXX test_variant $vendor $library \n";
 
 
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";
# print "$cmd";
 
push @elab_cmds, $cmd;
 
 
 
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
# print "$cmd";
 
push @gen_cmds, $cmd;
 
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
# print "$cmd";
 
push @des_cmds, $cmd;
 
 
 
 
 
}
 
}
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
}
 
 
}
 
 
 
return(0);
}
@elab_cmds = sys::lib::trim_sort(@elab_cmds);
@des_cmds = sys::lib::trim_sort(@des_cmds);
@gen_cmds = sys::lib::trim_sort(@gen_cmds);
 
 
 
#my $manager = new Parallel::ForkManager( $number_of_cpus );
 
 
 
foreach $cmd (@elab_cmds)
{
# $manager->start and next;
if (system($cmd)) {}
# $manager->finish;
}
 
#$manager->wait_all_children;
 
 
foreach $cmd (@des_cmds)
{
if (system($cmd)) {}
}
 
 
foreach $cmd (@gen_cmds)
{
# $manager->start and next;
if (system($cmd)) {}
# $manager->finish;
}
 
#$manager->wait_all_children;
 
 
 
 
 
 
return(0);
 
}
 
/workspace
207,18 → 207,18
foreach my $i_name ($socgen_file->findnodes("//socgen:syn/socgen:ise/socgen:chip/socgen:variant"))
{
my($chip_name) = $i_name ->findnodes('./text()')->to_literal ;
my($chip_variant) = $i_name ->findnodes('./text()')->to_literal ;
my($chip_target) = $i_name ->findnodes('../socgen:target/socgen:library/text()')->to_literal ;
my($chip_part) = $i_name ->findnodes('../socgen:target/socgen:part/text()')->to_literal ;
$outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_name}/Makefile";
$outfile ="${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_variant}/Makefile";
open MAKSYNFILE,">$outfile" or die "unable to open $outfile";
print MAKSYNFILE "include ${home}/tools/bin/Makefile.root\n";
print MAKSYNFILE "Part=${chip_part}\n";
print MAKSYNFILE "board=${chip_target}\n";
print MAKSYNFILE "Design=${chip_name}\n";
my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_name}/target";
print MAKSYNFILE "Design=${chip_variant}\n";
my $path = "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_variant}/target";
mkdir $path,0755 unless( -e $path );
&sys::lib::link_dir( "${home}/tools/synthesys/targets/ip/${chip_target}", "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_name}/target" );
&sys::lib::link_dir( "${home}/tools/synthesys/targets/ip/${chip_target}", "${home}${prefix}/${vendor}__${library}${lib_comp_sep}${component}/syn/ise/${chip_variant}/target" );
}
}
 

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