OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk/tools
    from Rev 115 to Rev 116
    ↔ Reverse comparison
  •

Rev 115 → Rev 116

/or32-elf/or32-elf-linux-x86.tar.bz2 Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/or32-elf/or32-elf-linux-x86.tar.bz2
or32-elf/or32-elf-linux-x86.tar.bz2 Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: or32-elf/Readme.txt =================================================================== --- or32-elf/Readme.txt (revision 115) +++ or32-elf/Readme.txt (nonexistent) @@ -1,4 +0,0 @@ -download link - - -ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-1.0rc1-x86.tar.bz2 Index: or32-elf/Makefile =================================================================== --- or32-elf/Makefile (revision 115) +++ or32-elf/Makefile (nonexistent) @@ -1,14 +0,0 @@ -SHELL=/bin/sh -MAKE=make -CUR_DIR=$(shell pwd) - - -all: or32 - - -.PHONY or32: -or32: - tar xf or32-elf-linux-x86.tar.bz2;\ - - - Index: or32-elf/or32-elf-1.0rc1-x86.tar.bz2 =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: or32-elf/or32-elf-1.0rc1-x86.tar.bz2 =================================================================== --- or32-elf/or32-elf-1.0rc1-x86.tar.bz2 (revision 115) +++ or32-elf/or32-elf-1.0rc1-x86.tar.bz2 (nonexistent)
or32-elf/or32-elf-1.0rc1-x86.tar.bz2 Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: utils/bin2abs.c =================================================================== --- utils/bin2abs.c (revision 115) +++ utils/bin2abs.c (revision 116) @@ -60,12 +60,15 @@ FILE *fd; int c; int i = 0; + int j = 1; int line = 0; int filename_index=1; int bytes_per_line=1; int bytes_per_line_index=2; + int min_num_bytes = 0; int min_num_bytes_index=3; - int min_num_bytes = 0; + int byte_lane=0; + int byte_lane_index=4; if(argc < 3) { @@ -77,27 +80,19 @@ } fd = fopen( argv[filename_index], "r" ); - - - - - - - - bytes_per_line = atoi(argv[bytes_per_line_index]); - - - if(argc > 3) { min_num_bytes = atoi(argv[min_num_bytes_index]); } + if(argc > 4) { + byte_lane = atoi(argv[byte_lane_index]); + } - if ((bytes_per_line == 0) || (bytes_per_line > 8)) + if ((bytes_per_line == 0) || (bytes_per_line > 8) || (byte_lane > bytes_per_line ) ) { fprintf(stderr,"bytes per line incorrect or missing: %s\n",argv[bytes_per_line_index]); exit(1); @@ -104,12 +99,6 @@ } - - - - - - if (fd == NULL) { fprintf(stderr,"failed to open input file: %s\n",argv[1]); @@ -119,8 +108,51 @@ i=0; line=0; + if(byte_lane) + { // Now write out the binary data to hex format while ((c = fgetc(fd)) != EOF) { + j=i+1; + if(byte_lane == j) + { printf("%.2x", (unsigned int) c); + + } + if (++i == bytes_per_line) { + printf("\n"); + line++; + i = 0; + } + } + + + while (i) { + j=i+1; + if(byte_lane == j) + { printf("00"); + + } + + + if (++i == bytes_per_line) { + printf("\n"); + line++; + i = 0; + } + } + + + + while (line < min_num_bytes) { + printf("00\n"); + line++; + } + } + else + + { + // no byte lane + // Now write out the binary data to hex format + while ((c = fgetc(fd)) != EOF) { printf("%.2x", (unsigned int) c); if (++i == bytes_per_line) { printf("\n"); @@ -145,10 +177,10 @@ printf("00000000\n"); line++; } + } - return 0; }
/orbuild/orbuild_Scripts_Projects_OpenRISC_makefile
0,0 → 1,1042
 
# Copyright (C) 2011 R. Diez - see the orbuild project for licensing information.
 
.DELETE_ON_ERROR:
 
SHELL := bash # This makefile has only been tested with bash.
 
include $(ORBUILD_SANDBOX)/Scripts/MakeModules/MakeUtils.mk
include $(ORBUILD_SANDBOX)/Scripts/MakeModules/DownloadAndUnpackTemplates.mk
include $(ORBUILD_SANDBOX)/Scripts/MakeModules/RepositoryCheckoutTemplates.mk
include $(ORBUILD_SANDBOX)/Scripts/MakeModules/AutotoolsTemplates.mk
include $(ORBUILD_SANDBOX)/Scripts/MakeModules/RunAndReportTemplates.mk
 
.PHONY: all generate_groups_file all_pgavin
 
 
# ----------- General options -----------
 
# Option --no-builtin-variables implies --no-builtin-rules, which accelerates GNU Make considerably.
FASTER_MAKE := --no-builtin-variables
 
# This flag allows disabling the actual downloading of the source-control repository updates
# so as to prevent overloading the remote servers during development of this makefile.
# It must be set before using any of the repository checkout templates.
# In order for the build to work properly, the repositories must have been checked out at least one.
SKIP_REPOSITORY_UPDATE := 0
 
ONLY_ANONYMOUS_CHECKOUTS := 0
 
 
# ----------- OpenRISC-specific options -----------
 
ENABLE_PGAVIN := 0
ENABLE_TESTS := 0
ENABLE_ICARUS_VERILOG := 0
ENABLE_VERILATOR := 0
ENABLE_OPEN_RISC_TEST_SUITE := 0
ENABLE_ECOS := 0
ENABLE_ECOS_TEST := 0
 
LINUX_ARCH := or32
OPENRISC_BARE_TARGET := $(LINUX_ARCH)-elf
OPENRISC_LINUX_TARGET := $(LINUX_ARCH)-linux
 
PGAVIN_LINUX_ARCH := or1k
PGAVIN_OPENRISC_BARE_TARGET := $(PGAVIN_LINUX_ARCH)-elf
PGAVIN_OPENRISC_LINUX_TARGET := $(PGAVIN_LINUX_ARCH)-linux
 
# In order for the GCC cross-compiler to automatically pick up the right assembler and so on,
# it must be configured to use the same bin directory as Binutils.
BARE_TOOLCHAIN_DIR := $(ORBUILD_BUILD_DIR)/ToolchainOr32Bare
LINUX_TOOLCHAIN_DIR := $(ORBUILD_BUILD_DIR)/ToolchainOr32Linux
 
PGAVIN_BARE_TOOLCHAIN_DIR := $(ORBUILD_BUILD_DIR)/PGavinToolchainOr1kBare
PGAVIN_LINUX_TOOLCHAIN_DIR := $(ORBUILD_BUILD_DIR)/PGavinToolchainOr1kLinux
PGAVIN_LINUX_TOOLCHAIN_PREFIX := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/$(PGAVIN_OPENRISC_LINUX_TARGET)
 
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
all: all_pgavin
endif
 
ifeq "$(strip $(ENABLE_TESTS))" "1"
all: all_tests
endif
 
 
# ----------- Check out a number of OpenCores repositories under http://opencores.org/ocsvn/ -----------
 
# Each repository depends on the previous one, therefore they are checked out sequentially instead of in parallel,
# in order to prevent overloading the OpenCores server.
 
OC_SVN_BASE_URL := http://opencores.org/ocsvn
OC_OR_SVN_BASE_URL := $(OC_SVN_BASE_URL)/openrisc/openrisc/trunk
 
$(eval $(call subversion_checkout_template,OR1KSIM,or1ksim,$(OC_OR_SVN_BASE_URL)/or1ksim))
all: $(OR1KSIM_CHECKOUT_SENTINEL)
 
$(eval $(call subversion_checkout_template,DOCS,OpenRISC docs,$(OC_OR_SVN_BASE_URL)/docs))
all: $(DOCS_CHECKOUT_SENTINEL)
$(DOCS_CHECKOUT_SENTINEL): $(OR1KSIM_CHECKOUT_SENTINEL)
 
$(eval $(call subversion_checkout_template,ORPSOCV2,ORPSoC v2,$(OC_OR_SVN_BASE_URL)/orpsocv2))
all: $(ORPSOCV2_CHECKOUT_SENTINEL)
$(ORPSOCV2_CHECKOUT_SENTINEL): $(DOCS_CHECKOUT_SENTINEL)
 
$(eval $(call subversion_checkout_template,ECOS,eCos realtime operating system,$(OC_OR_SVN_BASE_URL)/rtos/ecos-3.0))
ifeq "$(strip $(ENABLE_ECOS))" "1"
all: $(ECOS_CHECKOUT_SENTINEL)
$(ECOS_CHECKOUT_SENTINEL): $(ORPSOCV2_CHECKOUT_SENTINEL)
PREV_SVN_REPO_SENTINEL := $(ECOS_CHECKOUT_SENTINEL)
else
PREV_SVN_REPO_SENTINEL := $(ORPSOCV2_CHECKOUT_SENTINEL)
endif
 
# This is the biggest repository by far, so it's the last one to be checked out from OpenCores.
# WARNING: The OC_BLD_ALL task cleans the whole repository every time it runs.
$(eval $(call subversion_checkout_template,GNUSRC,GNU sources,$(OC_OR_SVN_BASE_URL)/gnu-src))
all: $(GNUSRC_CHECKOUT_SENTINEL)
$(GNUSRC_CHECKOUT_SENTINEL): $(PREV_SVN_REPO_SENTINEL)
 
 
$(eval $(call subversion_checkout_template,MINSOC,MinSoC,$(OC_SVN_BASE_URL)/minsoc/minsoc/trunk))
$(MINSOC_CHECKOUT_SENTINEL): $(GNUSRC_CHECKOUT_SENTINEL)
ifeq "$(strip $(ONLY_ANONYMOUS_CHECKOUTS))" "0"
# Only download the repository if we are going to use it, and we only use it for testing.
all_tests: $(MINSOC_CHECKOUT_SENTINEL)
endif
 
 
# ----------- Check out a number of Peter Gavin's repositories under https://github.com/pgavin/ -----------
 
# Each repository depends on the previous one, therefore they are checked out sequentially instead of in parallel,
# in order to prevent overloading the Github server.
 
PGAVIN_GIT_BASE_URL := git://github.com/pgavin
 
$(eval $(call git_checkout_template,PGAVIN_LINUX,Peter Gavin's Linux,$(PGAVIN_GIT_BASE_URL)/linux.git))
all_pgavin: $(PGAVIN_LINUX_CHECKOUT_SENTINEL)
 
$(eval $(call git_checkout_template,PGAVIN_OR1KSIM,Peter Gavin's or1ksim,$(PGAVIN_GIT_BASE_URL)/or1ksim.git))
$(eval $(call git_download_serializer_template,PGAVIN_LINUX,PGAVIN_OR1KSIM))
all_pgavin: $(PGAVIN_OR1KSIM_CHECKOUT_SENTINEL)
 
$(eval $(call git_checkout_template,PGAVIN_UCLIBC,Peter Gavin's uClibc,$(PGAVIN_GIT_BASE_URL)/uClibc.git))
$(eval $(call git_download_serializer_template,PGAVIN_OR1KSIM,PGAVIN_UCLIBC))
all_pgavin: $(PGAVIN_UCLIBC_CHECKOUT_SENTINEL)
 
$(eval $(call git_checkout_template,PGAVIN_OR1K_SRC,Peter Gavin's or1k-src,$(PGAVIN_GIT_BASE_URL)/or1k-src.git))
$(eval $(call git_download_serializer_template,PGAVIN_UCLIBC,PGAVIN_OR1K_SRC))
all_pgavin: $(PGAVIN_OR1K_SRC_CHECKOUT_SENTINEL)
 
$(eval $(call git_checkout_template,PGAVIN_OR1K_GCC,Peter Gavin's or1k-gcc,$(PGAVIN_GIT_BASE_URL)/or1k-gcc.git))
$(eval $(call git_download_serializer_template,PGAVIN_OR1K_SRC,PGAVIN_OR1K_GCC))
all_pgavin: $(PGAVIN_OR1K_GCC_CHECKOUT_SENTINEL)
 
 
# ----------- Jonas Bonn's repositories -----------
 
$(eval $(call git_checkout_template,JBONN_LINUX,Jonas Bon's Linux,git://openrisc.net/jonas/linux))
all: $(JBONN_LINUX_CHECKOUT_SENTINEL)
 
$(eval $(call git_checkout_template,JBONN_UCLIBC,Jonas Bon's uClibc,git://openrisc.net/jonas/uClibc))
all: $(JBONN_UCLIBC_CHECKOUT_SENTINEL)
$(eval $(call git_download_serializer_template,JBONN_LINUX,JBONN_UCLIBC))
 
 
# ----------- Icarus Verilog -----------
 
ICARUS_VERILOG_EXTRA_GIT_CHECKOUT_ARGS := v0_9-branch
$(eval $(call git_checkout_template,ICARUS_VERILOG,Icarus Verilog,git://github.com/steveicarus/iverilog.git))
 
# We don't actually need to create a local branch like this, checking out branch origin/v0_9-branch will probably do.
$(eval $(call git_branch_template,ICARUS_VERILOG,--track v0_9-branch origin/v0_9-branch))
 
# Icarus Verilog's "make install" breaks when running in parallel mode. I have reported it,
# so it may well have been fixed by now.
ICARUS_VERILOG_INSTALL_MAKEFLAGS_FILTER := clear
ICARUS_VERILOG_EXTRA_INSTALL_ARGS := -j 1 # Not actually needed if MAKEFLAGS gets cleared.
 
$(eval $(call autotool_project_template,ICARUS_VERILOG,Icarus Verilog,$(ICARUS_VERILOG_CHECKOUT_DIR)))
 
ICARUS_VERILOG_AUTOGEN_CMD = $(SHELL) autoconf.sh
$(eval $(call autogen_project_template,ICARUS_VERILOG,Icarus Verilog))
$(ICARUS_VERILOG_AUTOGEN_SENTINEL): $(ICARUS_VERILOG_CHECKOUT_SENTINEL)
 
ifeq "$(strip $(ENABLE_ICARUS_VERILOG))" "1"
all: $(ICARUS_VERILOG_INSTALL_SENTINEL)
endif
 
 
# ----------- Verilator -----------
 
$(eval $(call git_checkout_template,VERILATOR,Verilator,http://git.veripool.org/git/verilator))
 
# Build Verilator as a standard autoconf project.
VERILATOR_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
$(eval $(call autotool_project_template,VERILATOR,Verilator,$(VERILATOR_CHECKOUT_DIR)))
 
# Before running the standard autoconf project operations, let autoconf generate the necessary files.
VERILATOR_AUTOGEN_CMD = autoconf --warnings=all
$(eval $(call autogen_project_template,VERILATOR,Verilator))
$(VERILATOR_AUTOGEN_SENTINEL): $(VERILATOR_CHECKOUT_SENTINEL)
 
ifeq "$(strip $(ENABLE_VERILATOR))" "1"
all: $(VERILATOR_INSTALL_SENTINEL)
endif
 
ifeq "0" "1" # Run Verilator's install tests, disabled at the moment.
# Verilator's install_test script sets its own -j flag for GNU Make, therefore remove any inherited flags from MAKEFLAGS.
VERILATOR_INSTALL_TEST_CMD := cd $(VERILATOR_CHECKOUT_DIR) && perl nodist/install_test
VERILATOR_INSTALL_TEST_MAKEFLAGS_FILTER := clear
$(eval $(call run_and_report_template,VERILATOR_INSTALL_TEST,Verilator installation test,$(SHELL) -c "$(VERILATOR_INSTALL_TEST_CMD)"))
 
$(VERILATOR_INSTALL_TEST_SENTINEL): $(VERILATOR_INSTALL_SENTINEL)
all: $(VERILATOR_INSTALL_TEST_SENTINEL)
endif
 
 
# ----------- Binutils -----------
 
# Build Binutils as a standard autoconf project.
#
# Note: I am seeing random build failures around chew.exe under Cygwin,
# it looks like some random timing issue in the makefile for parallel builds.
# I also found thees comments about it on the Internet:
# glitch in bfd/doc
# using make -j 4 for example leads to failure in bdf/doc at least for the mingw32
# targets, chew is build 4 times in parallel and the move to chew.exe fails:
#
# Re: Missing dependency on chew.exe somewhere?
# FWIW, I have seen random failures with "make -j 8 check" in bfd
# on Linux/x86-64. It is not very reproducible.
 
LOCAL_BINUTILS_SRC := $(GNUSRC_CHECKOUT_DIR)/binutils-2.20.1
BINUTILS_BIN_DIR := $(BARE_TOOLCHAIN_DIR)
# TODO: I am not sure whether --enable-fast-install=N/A or --disable-libssp are needed in BINUTILS_EXTRA_CONFIG_ARGS.
BINUTILS_EXTRA_CONFIG_ARGS := --target=$(OPENRISC_BARE_TARGET) --enable-werror=no
BINUTILS_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
# TODO: With the following targets, "make install" fails. I'm not sure which targets are the correct ones:
# BINUTILS_MAKE_TARGETS := all-binutils all-gas all-ld all-build
BINUTILS_CHECK_TARGETS := check-binutils check-gas check-ld
$(eval $(call autotool_project_template,BINUTILS,Binutils,$(LOCAL_BINUTILS_SRC)))
 
$(BINUTILS_CONFIGURE_SENTINEL): $(GNUSRC_CHECKOUT_SENTINEL)
 
# TODO: Some checks fail, investigate why.
# all: $(BINUTILS_CHECK_SENTINEL)
 
 
# ----------- GCC cross-compiler for OpenRISC -----------
 
COMMON_GCC_OPTIONS := --disable-shared
COMMON_GCC_OPTIONS += --disable-libssp
 
COMMON_GCC_OPTIONS += --disable-multilib
 
COMMON_GCC_OPTIONS += --disable-lto
 
BARE_COMMON_GCC_OPTIONS += $(COMMON_GCC_OPTIONS) --with-newlib --target=$(OPENRISC_BARE_TARGET)
 
 
# ---------- GCC phase 1 (bootstrap) ----------
 
# In order to build GCC, the OpenRISC binutils binaries are needed.
GCC_SRC_DIR := $(GNUSRC_CHECKOUT_DIR)/gcc-4.5.1
 
GCC_PHASE_1_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
GCC_PHASE_1_BIN_DIR := $(BARE_TOOLCHAIN_DIR)
 
GCC_PHASE_1_EXTRA_CONFIG_ARGS := $(BARE_COMMON_GCC_OPTIONS) --enable-languages=c --without-headers
GCC_PHASE_1_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
GCC_PHASE_1_MAKE_TARGETS := all-gcc
GCC_PHASE_1_INSTALL_TARGETS := install-gcc
 
$(eval $(call autotool_project_template,GCC_PHASE_1,GCC Phase 1,$(GCC_SRC_DIR)))
 
# In order to build GCC, the OpenRISC Binutils binaries are needed.
$(GCC_PHASE_1_CONFIGURE_SENTINEL): $(BINUTILS_INSTALL_SENTINEL)
 
 
# ---------- newlib ----------
 
NEWLIB_SRC_DIR := $(GNUSRC_CHECKOUT_DIR)/newlib-1.18.0
NEWLIB_BIN_DIR := $(BARE_TOOLCHAIN_DIR)
NEWLIB_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
 
NEWLIB_EXTRA_CONFIG_ARGS :=
NEWLIB_EXTRA_CONFIG_ARGS += --target=$(OPENRISC_BARE_TARGET)
NEWLIB_EXTRA_CONFIG_ARGS += --disable-shared
NEWLIB_EXTRA_CONFIG_ARGS += --disable-multilib
 
NEWLIB_CHECK_TARGETS := check-target-newlib check-target-libgloss
 
$(eval $(call autotool_project_template,NEWLIB,Newlib,$(NEWLIB_SRC_DIR)))
 
$(NEWLIB_CONFIGURE_SENTINEL): $(GCC_PHASE_1_INSTALL_SENTINEL)
 
 
# ---------- GCC phase 2 ----------
# Note that this installs the final GCC binaries over the ones from phase 1.
# Although everything should be properly overwritten, this method does not look very clean to me.
 
GCC_PHASE_2_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
GCC_PHASE_2_BIN_DIR := $(BARE_TOOLCHAIN_DIR)
 
GCC_PHASE_2_EXTRA_CONFIG_ARGS := $(BARE_COMMON_GCC_OPTIONS) --enable-languages=c,c++
GCC_PHASE_2_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
GCC_PHASE_2_CHECK_TARGETS := check-gcc check-target-libgcc check-target-libstdc++-v3
 
$(eval $(call autotool_project_template,GCC_PHASE_2,GCC Phase 2,$(GCC_SRC_DIR)))
 
$(GCC_PHASE_2_CONFIGURE_SENTINEL): $(NEWLIB_INSTALL_SENTINEL)
 
all: $(GCC_PHASE_2_INSTALL_SENTINEL)
 
 
# ----------- or1ksim -----------
 
# Build or1ksim as a standard autoconf project.
 
# About the target used here: or32-elf is the default target, and I don't think that or32-linux
# would have any effect for the simulator itself, although the bundled Test Suite can be built for a Linux target.
OR1KSIM_EXTRA_CONFIG_ARGS := --target=$(OPENRISC_BARE_TARGET)
OR1KSIM_EXTRA_CONFIG_ARGS += --enable-eth-phy
# TODO: optimise compilation for the test suite
# Flag --no-builtin-rules makes the build faster. Flag --no-builtin-variables does not work here because at least one makefile uses built-in variable $(RM).
OR1KSIM_EXTRA_GLOBAL_MAKE_ARGS := --no-builtin-rules
 
# The test suite bundled with or1ksim needs the target compiler.
OR1KSIM_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
 
$(eval $(call autotool_project_template,OR1KSIM,or1ksim,$(OR1KSIM_CHECKOUT_DIR)))
all: $(OR1KSIM_INSTALL_SENTINEL)
$(OR1KSIM_CONFIGURE_SENTINEL): $(OR1KSIM_CHECKOUT_SENTINEL) $(GCC_PHASE_2_INSTALL_SENTINEL)
 
# If the normal installation fails, do not attempt to do any checks.
$(OR1KSIM_DISTCHECK_SENTINEL) : $(OR1KSIM_INSTALL_SENTINEL)
$(OR1KSIM_CHECK_SENTINEL) : $(OR1KSIM_INSTALL_SENTINEL)
 
all_tests: $(OR1KSIM_DISTCHECK_SENTINEL)
# all_tests: $(OR1KSIM_CHECK_SENTINEL)
 
 
# ----------- GDB cross-debugger for OpenRISC -----------
 
GDB_SRC_DIR := $(GNUSRC_CHECKOUT_DIR)/gdb-7.2
GDB_BIN_DIR := $(BARE_TOOLCHAIN_DIR)
GDB_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
 
GDB_EXTRA_CONFIG_ARGS :=
GDB_EXTRA_CONFIG_ARGS += --target=$(OPENRISC_BARE_TARGET)
# GDB uses or1ksim as the target simulator.
GDB_EXTRA_CONFIG_ARGS += --with-or1ksim=$(OR1KSIM_BIN_DIR)
 
$(eval $(call autotool_project_template,GDB,GDB,$(GDB_SRC_DIR)))
 
$(GDB_CONFIGURE_SENTINEL): $(GCC_PHASE_2_INSTALL_SENTINEL) $(OR1KSIM_INSTALL_SENTINEL)
all: $(GDB_INSTALL_SENTINEL)
 
 
# ----------- Verilog Tools Path -----------
 
COLON_CHAR := :
EMPTY_VAR_TRICK :=
SPACE_CHAR := $(EMPTY_VAR_TRICK) $(EMPTY_VAR_TRICK)
 
VERILOG_TOOLS_PREPEND_PATH :=
VERILOG_TOOLS_PREREQS :=
 
ifeq "$(strip $(ENABLE_ICARUS_VERILOG))" "1"
VERILOG_TOOLS_PREREQS += $(ICARUS_VERILOG_INSTALL_SENTINEL)
VERILOG_TOOLS_PREPEND_PATH += $(ICARUS_VERILOG_BIN_DIR)/bin
endif
 
ifeq "$(strip $(ENABLE_VERILATOR))" "1"
VERILOG_TOOLS_PREREQS += $(VERILATOR_INSTALL_SENTINEL)
VERILOG_TOOLS_PREPEND_PATH += $(VERILATOR_BIN_DIR)/bin
endif
 
 
# ----------- ORPSoC v2 -----------
 
ORPSOC_NAME := ORPSOCv2
 
# ------- Build the support tools, they are needed when running the Test Suite (see further below).
 
# Note that this step slightly pollutes the source repository it is run upon.
$(ORPSOC_NAME)_SW_UTILS_CMD := cd $(ORPSOCV2_CHECKOUT_DIR)/sw/utils && make $(FASTER_MAKE) all
$(ORPSOC_NAME)_SW_UTILS_CMD_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,$(ORPSOC_NAME)_SW_UTILS_CMD,ORPSoC v2 sw utils,$(SHELL) -c "$(value $(ORPSOC_NAME)_SW_UTILS_CMD)"))
# These tools are not always needed.
# all: $(value $(ORPSOC_NAME)_SW_UTILS_CMD_SENTINEL)
$(value $(ORPSOC_NAME)_SW_UTILS_CMD_SENTINEL): $(ORPSOCV2_CHECKOUT_SENTINEL)
 
 
# ------- Build the documentation.
 
# Note that this step slightly pollutes the source repository it is run upon.
$(ORPSOC_NAME)_DOCUMENTATION_CMD := cd $(ORPSOCV2_CHECKOUT_DIR)/doc && ./configure && make $(FASTER_MAKE) pdf
$(ORPSOC_NAME)_DOCUMENTATION_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,$(ORPSOC_NAME)_DOCUMENTATION,ORPSoC v2 documentation,$(SHELL) -c "$(value $(ORPSOC_NAME)_DOCUMENTATION_CMD)"))
all: $(value $(ORPSOC_NAME)_DOCUMENTATION_SENTINEL)
$(value $(ORPSOC_NAME)_DOCUMENTATION_SENTINEL): $(ORPSOCV2_CHECKOUT_SENTINEL)
 
 
# ------- Lint (parts of the) Verilog code with Verilator and with Icarus Verilog.
 
LINT_TEMP_DIR := $(ORBUILD_BUILD_DIR)/temp/LINT_TEMP
 
$(ORPSOC_NAME)_LINT_PREPEND_PATH := $(subst $(SPACE_CHAR),$(COLON_CHAR),$(strip $(VERILOG_TOOLS_PREPEND_PATH)))
 
$(ORPSOC_NAME)_LINT_OR1200_PREPEND_PATH := $($(ORPSOC_NAME)_LINT_PREPEND_PATH)
$(ORPSOC_NAME)_LINT_ORPSOC_PREPEND_PATH := $($(ORPSOC_NAME)_LINT_PREPEND_PATH)
$(ORPSOC_NAME)_LINT_ORPSOC_ALTCFG_PREPEND_PATH := $($(ORPSOC_NAME)_LINT_PREPEND_PATH)
$(ORPSOC_NAME)_LINT_TESTBENCH_PREPEND_PATH := $($(ORPSOC_NAME)_LINT_PREPEND_PATH)
 
$(ORPSOC_NAME)_LINT_CMD := $(ORBUILD_PROJECT_DIR)/Tools/Orpsocv2Lint.sh \"$(ORPSOCV2_CHECKOUT_DIR)\" \"$(LINT_TEMP_DIR)\"
 
$(eval $(call run_and_report_template,$(ORPSOC_NAME)_LINT_OR1200,ORPSoC v2 lint or1200,$(SHELL) -c "$(value $(ORPSOC_NAME)_LINT_CMD) or1200 minimal-features"))
$(eval $(call run_and_report_template,$(ORPSOC_NAME)_LINT_ORPSOC,ORPSoC v2 lint orpsoc,$(SHELL) -c "$(value $(ORPSOC_NAME)_LINT_CMD) orpsoc maximal-features"))
$(eval $(call run_and_report_template,$(ORPSOC_NAME)_LINT_ORPSOC_ALTCFG,ORPSoC v2 lint orpsoc alt cfg,$(SHELL) -c "$(value $(ORPSOC_NAME)_LINT_CMD) orpsoc maximal-features-alt-cfg"))
$(eval $(call run_and_report_template,$(ORPSOC_NAME)_LINT_TESTBENCH,ORPSoC v2 lint testbench,$(SHELL) -c "$(value $(ORPSOC_NAME)_LINT_CMD) testbench maximal-features"))
 
$(value $(ORPSOC_NAME)_LINT_OR1200_SENTINEL) : $(VERILOG_TOOLS_PREREQS) $(ORPSOCV2_CHECKOUT_SENTINEL)
$(value $(ORPSOC_NAME)_LINT_ORPSOC_SENTINEL) : $(VERILOG_TOOLS_PREREQS) $(ORPSOCV2_CHECKOUT_SENTINEL)
$(value $(ORPSOC_NAME)_LINT_ORPSOC_ALTCFG_SENTINEL): $(VERILOG_TOOLS_PREREQS) $(ORPSOCV2_CHECKOUT_SENTINEL)
$(value $(ORPSOC_NAME)_LINT_TESTBENCH_SENTINEL) : $(VERILOG_TOOLS_PREREQS) $(ORPSOCV2_CHECKOUT_SENTINEL)
 
all: $(value $(ORPSOC_NAME)_LINT_OR1200_SENTINEL)
all: $(value $(ORPSOC_NAME)_LINT_ORPSOC_SENTINEL)
all: $(value $(ORPSOC_NAME)_LINT_ORPSOC_ALTCFG_SENTINEL)
# TODO: not ready yet, must generate test-defines.v properly:
# all: $(value $(ORPSOC_NAME)_LINT_TESTBENCH_SENTINEL)
 
LINT_GROUP := $(ORPSOC_NAME)_LINT_OR1200
LINT_GROUP += $(ORPSOC_NAME)_LINT_ORPSOC
LINT_GROUP += $(ORPSOC_NAME)_LINT_ORPSOC_ALTCFG
LINT_GROUP += $(ORPSOC_NAME)_LINT_TESTBENCH
 
 
# ------- Run some of the self-tests.
 
# Note that this step slightly pollutes the source repository its run upon.
 
$(ORPSOC_NAME)_RTL_TESTS_CMD := cd $(ORPSOCV2_CHECKOUT_DIR)/sim/bin &&
$(ORPSOC_NAME)_RTL_TESTS_CMD += make -j 1 rtl-tests # About the "-j 1": The rtl-tests target breaks when run in parallel mode.
# Not actually needed if MAKEFLAGS gets cleared (see below).
 
# Clear variable MAKEFLAGS, as the rtl-tests target breaks when run in parallel mode.
$(ORPSOC_NAME)_RTL_TESTS_MAKEFLAGS_FILTER := clear
 
$(ORPSOC_NAME)_RTL_TESTS_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
 
ifeq "$(strip $(ENABLE_ICARUS_VERILOG))" "1"
$(ORPSOC_NAME)_RTL_TESTS_PREPEND_PATH := $(ICARUS_VERILOG_BIN_DIR)/bin:$($(ORPSOC_NAME)_RTL_TESTS_PREPEND_PATH)
endif
 
$(eval $(call run_makefile_and_report_template,$(ORPSOC_NAME)_RTL_TESTS,ORPSoC v2 RTL tests,$(SHELL) -c "$(value $(ORPSOC_NAME)_RTL_TESTS_CMD)"))
 
ifeq "$(strip $(ENABLE_ICARUS_VERILOG))" "1"
$(value $(ORPSOC_NAME)_RTL_TESTS_SENTINEL): $(ICARUS_VERILOG_INSTALL_SENTINEL)
endif
 
$(value $(ORPSOC_NAME)_RTL_TESTS_SENTINEL): $(GCC_PHASE_2_INSTALL_SENTINEL)
 
all: $(value $(ORPSOC_NAME)_RTL_TESTS_SENTINEL)
# The rtl-tests target builds some of the sw utils. In order to prevent collisions while building,
# make the tests depend on the full sw utils set.
$(value $(ORPSOC_NAME)_RTL_TESTS_SENTINEL): $(value $(ORPSOC_NAME)_SW_UTILS_CMD_SENTINEL)
 
 
# ----------- MinSoC -----------
 
# Test MinSoC's automatic installation script.
 
MINSOC_INSTALLATION_SCRIPT_DIR := $(ORBUILD_BUILD_DIR)/MINSOC_INSTALLATION_SCRIPT
MINSOC_INSTALLATION_SCRIPT_CMD := $(ORBUILD_PROJECT_DIR)/Tools/MinsocInstallationTest.sh $(MINSOC_CHECKOUT_DIR) $(MINSOC_INSTALLATION_SCRIPT_DIR)
 
MINSOC_INSTALLATION_SCRIPT_MAKEFLAGS_FILTER := clear
 
$(eval $(call run_and_report_template,MINSOC_INSTALLATION_SCRIPT,MinSoC's installation script,$(SHELL) -c "$(MINSOC_INSTALLATION_SCRIPT_CMD)"))
$(MINSOC_INSTALLATION_SCRIPT_SENTINEL): $(MINSOC_CHECKOUT_SENTINEL)
 
ifeq "$(strip $(ONLY_ANONYMOUS_CHECKOUTS))" "0"
# MinSoC's installation script downloads a repository and some files automatically, so skip it if we have globally disabled repository downloading.
ifeq "$(strip $(SKIP_REPOSITORY_UPDATE))" "0"
all_tests: $(MINSOC_INSTALLATION_SCRIPT_SENTINEL)
endif
endif
 
 
# ----------- Test OpenCore's gnu-src bld-all.sh -----------
 
# WARNING: This component waits until all other components have finished with the GNUSRC repository,
# and then it cleans it before starting its own work. This is to prevent the following error:
# configure: error: `CC' has changed since the previous run
# For faster runs during testing of this makefile: OC_BLD_ARGS := --no-or32-linux
OC_BLD_ARGS += --prefix $(ORBUILD_BUILD_DIR)/OC_BLD_ALL/bin
OC_BLD_ARGS += --prefix-tmp $(ORBUILD_BUILD_DIR)/OC_BLD_ALL/tmp
OC_BLD_ARGS += --or1ksim-dir $(OR1KSIM_BIN_DIR)
OC_BLD_ARGS += --uclibc-dir $(JBONN_UCLIBC_CHECKOUT_DIR)
OC_BLD_ARGS += --linux-dir $(JBONN_LINUX_CHECKOUT_DIR)
# Many of the tests are known to fail, so do not enable them for the time being:
# OC_BLD_ARGS += --check
 
OC_BLD_ALL_CMD := echo \"Cleaning repository...\" && $(ORBUILD_TOOLS)/SvnCleanRepo.sh $(GNUSRC_CHECKOUT_DIR) &&
OC_BLD_ALL_CMD += echo \"Running bld-all.sh...\" && cd $(GNUSRC_CHECKOUT_DIR) &&
OC_BLD_ALL_CMD += ./bld-all.sh $(OC_BLD_ARGS)
 
OC_BLD_ALL_MAKEFLAGS_FILTER := clear
 
$(eval $(call run_and_report_template,OC_BLD_ALL,OpenCore's gnu-src bld-all.sh,$(SHELL) -c "$(OC_BLD_ALL_CMD)"))
 
$(OC_BLD_ALL_SENTINEL): $(OR1KSIM_INSTALL_SENTINEL) $(GNUSRC_CHECKOUT_SENTINEL) $(JBONN_LINUX_CHECKOUT_SENTINEL) $(JBONN_UCLIBC_CHECKOUT_SENTINEL)
 
all_tests: $(OC_BLD_ALL_SENTINEL)
 
 
# ----------- Peter Gavin's Binutils and other tools, common settings -----------
 
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS := --target=$(PGAVIN_OPENRISC_BARE_TARGET)
 
# Note about target compilation flags:
# We don't need to specify any flags like -mcompat-delay here, as newlib gets built in all 3 multilib variants
# (with jump delay slot, without jump delay slot and compatible with both).
# If you ever want to specify target compilation flags, use this syntax:
# PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += CFLAGS_FOR_TARGET=\"-some-flag -g -O2\"
# Keep in mind that the default flags get lost, so you would have to specify "-g -O" manually at this point.
# Beware that other components, like libgcc, need to get built with compatible flags,
# as they all get linked together at the end.
 
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-shared
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-itcl
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-tk
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-tcl
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-winsup
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-libgui
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-rda
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-sid
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --with-sysroot
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-gdb
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --disable-readline
PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS += --with-system-readline
# --disable-multilib: Multilibs have a meaning now: 1) with jump delay slot, 2) without jump delay slot, 3) compatibility (l.nop after every jump instruction).
 
 
# ----------- Peter Gavin's Binutils and other tools (bare), phase 1 -----------
 
PGAVIN_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS := $(PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS)
PGAVIN_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-libgloss
PGAVIN_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-newlib
# We could build the CGEN-based simulator in the first phase, but we are using it only after phase 2,
# when the binutils have settled down, so it's not worth building it in phase 1 too.
PGAVIN_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-sim
 
PGAVIN_BINUTILS_PHASE_1_BIN_DIR := $(PGAVIN_BARE_TOOLCHAIN_DIR)
 
PGAVIN_BINUTILS_PHASE_1_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
 
$(eval $(call autotool_project_template,PGAVIN_BINUTILS_PHASE_1,Peter Gavin's Binutils etc. phase 1,$(PGAVIN_OR1K_SRC_CHECKOUT_DIR)))
 
$(PGAVIN_BINUTILS_PHASE_1_CONFIGURE_SENTINEL): $(PGAVIN_OR1K_SRC_CHECKOUT_SENTINEL)
 
 
# ----------- Peter Gavin's GCC cross-compiler for OpenRISC (bare), common settings -----------
 
PGAVIN_COMMON_GCC_OPTIONS := --disable-shared
PGAVIN_COMMON_GCC_OPTIONS += --disable-libssp
PGAVIN_COMMON_GCC_OPTIONS += --disable-lto
PGAVIN_COMMON_GCC_OPTIONS += --disable-libgomp
PGAVIN_COMMON_GCC_OPTIONS += --disable-libmudflap
PGAVIN_COMMON_GCC_OPTIONS += --enable-threads=single
PGAVIN_COMMON_GCC_OPTIONS += --disable-libquadmath
 
PGAVIN_BARE_COMMON_GCC_OPTIONS := $(PGAVIN_COMMON_GCC_OPTIONS) --with-newlib --target=$(PGAVIN_OPENRISC_BARE_TARGET)
 
 
# ---------- Peter Gavin's GCC phase 1 (bootstrap) ----------
 
# In order to build GCC, the OpenRISC Binutils binaries from phase 1 are needed.
PGAVIN_GCC_PHASE_1_AUTOCONF_PREPEND_PATH := $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
PGAVIN_GCC_PHASE_1_BIN_DIR := $(PGAVIN_BARE_TOOLCHAIN_DIR)
 
PGAVIN_GCC_PHASE_1_EXTRA_CONFIG_ARGS := $(PGAVIN_BARE_COMMON_GCC_OPTIONS) --enable-languages=c --without-headers
PGAVIN_GCC_PHASE_1_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
PGAVIN_GCC_PHASE_1_MAKE_TARGETS := all-gcc
PGAVIN_GCC_PHASE_1_INSTALL_TARGETS := install-gcc
 
# I've seen some sporadic error messages like "cannot create regular file '/home/blah blah/bin/or1k-elf-gcc-ar': No such file or directory",
# and that makes me thing that the install phase breaks when run in parallel mode.
PGAVIN_GCC_PHASE_1_INSTALL_MAKEFLAGS_FILTER := clear
 
$(eval $(call autotool_project_template,PGAVIN_GCC_PHASE_1,Peter Gavin's GCC Phase 1,$(PGAVIN_OR1K_GCC_CHECKOUT_DIR)))
 
# In order to build GCC, the OpenRISC Binutils binaries are needed.
$(PGAVIN_GCC_PHASE_1_CONFIGURE_SENTINEL): $(PGAVIN_BINUTILS_PHASE_1_INSTALL_SENTINEL) $(PGAVIN_OR1K_GCC_CHECKOUT_SENTINEL)
 
 
# ----------- Peter Gavin's Binutils and other tools (bare), phase 2 -----------
# Note that this installs the final Binutils binaries over the ones from phase 1.
# Although everything should be properly overwritten, this method does not look very clean to me.
 
# It is rather unfortunate that we have to reconfigure and build all components again.
# Maybe there is a way to build just newlib, libgloss and the simulator.
 
PGAVIN_BINUTILS_PHASE_2_EXTRA_CONFIG_ARGS := $(PGAVIN_BINUTILS_EXTRA_CONFIG_ARGS)
 
PGAVIN_BINUTILS_PHASE_2_EXTRA_CONFIG_ARGS += --enable-sim-debug
PGAVIN_BINUTILS_PHASE_2_EXTRA_CONFIG_ARGS += --disable-sim-cflags
PGAVIN_BINUTILS_PHASE_2_EXTRA_CONFIG_ARGS += --enable-sim-trace
 
PGAVIN_BINUTILS_PHASE_2_BIN_DIR := $(PGAVIN_BARE_TOOLCHAIN_DIR)
 
PGAVIN_BINUTILS_PHASE_2_AUTOCONF_PREPEND_PATH := $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
 
# At least one of the OpenRISC parts is not compatible with flag --no-builtin-variables:
# PGAVIN_BINUTILS_PHASE_2_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
 
# TODO: These checks are not working properly. I'm also not sure which targets, if any, should be specified here.
# PGAVIN_BINUTILS_PHASE_2_CHECK_TARGETS := check-binutils check-gas check-ld
# PGAVIN_BINUTILS_PHASE_2_CHECK_TARGETS += check-target-newlib check-target-libgloss
 
$(eval $(call autotool_project_template,PGAVIN_BINUTILS_PHASE_2,Peter Gavin's Binutils etc. phase 2,$(PGAVIN_OR1K_SRC_CHECKOUT_DIR)))
 
$(PGAVIN_BINUTILS_PHASE_2_CONFIGURE_SENTINEL): $(PGAVIN_GCC_PHASE_1_INSTALL_SENTINEL)
 
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
# Disabled at the moment, see commentabove:
# all_tests: $(PGAVIN_BINUTILS_PHASE_2_CHECK_SENTINEL)
endif
 
 
# ---------- Peter Gavin's GCC phase 2 ----------
# Note that this installs the final GCC binaries over the ones from phase 1.
# Although everything should be properly overwritten, this method does not look very clean to me.
 
PGAVIN_GCC_PHASE_2_AUTOCONF_PREPEND_PATH := $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
PGAVIN_GCC_PHASE_2_BIN_DIR := $(PGAVIN_BARE_TOOLCHAIN_DIR)
 
PGAVIN_GCC_PHASE_2_EXTRA_CONFIG_ARGS := $(PGAVIN_BARE_COMMON_GCC_OPTIONS) --enable-languages=c,c++
PGAVIN_GCC_PHASE_2_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
PGAVIN_GCC_PHASE_2_CHECK_TARGETS := check-gcc check-target-libgcc check-target-libstdc++-v3
 
$(eval $(call autotool_project_template,PGAVIN_GCC_PHASE_2,Peter Gavin's GCC Phase 2,$(PGAVIN_OR1K_GCC_CHECKOUT_DIR)))
 
$(PGAVIN_GCC_PHASE_2_CONFIGURE_SENTINEL): $(PGAVIN_BINUTILS_PHASE_2_INSTALL_SENTINEL)
all_pgavin: $(PGAVIN_GCC_PHASE_2_INSTALL_SENTINEL)
 
 
# ----------- Peter Gavin's or1ksim -----------
 
# Build or1ksim as a standard autoconf project.
 
PGAVIN_OR1KSIM_EXTRA_CONFIG_ARGS := --target=$(PGAVIN_OPENRISC_BARE_TARGET)
PGAVIN_OR1KSIM_EXTRA_CONFIG_ARGS += --enable-eth-phy
# Flag --no-builtin-rules makes the build faster. Flag --no-builtin-variables does not work here because at least one makefile uses built-in variable $(RM).
PGAVIN_OR1KSIM_EXTRA_GLOBAL_MAKE_ARGS := --no-builtin-rules
 
# The test suite bundled with or1ksim needs the target compiler.
PGAVIN_OR1KSIM_AUTOCONF_PREPEND_PATH := $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
 
$(eval $(call autotool_project_template,PGAVIN_OR1KSIM,Peter Gavin's or1ksim,$(PGAVIN_OR1KSIM_CHECKOUT_DIR)))
 
$(PGAVIN_OR1KSIM_CONFIGURE_SENTINEL): $(PGAVIN_OR1KSIM_CHECKOUT_SENTINEL) $(PGAVIN_GCC_PHASE_2_INSTALL_SENTINEL)
all_pgavin: $(PGAVIN_OR1KSIM_INSTALL_SENTINEL)
 
 
# ----------- Peter Gavin's Binutils and other tools for Linux, common settings -----------
 
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS := --target=$(PGAVIN_OPENRISC_LINUX_TARGET)
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-shared
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-itcl
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-tk
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-tcl
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-winsup
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-libgui
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-rda
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-sid
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --with-sysroot
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-gdb
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --disable-readline
PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS += --with-system-readline
 
# ----------- Peter Gavin's Binutils and other tools for Linux, phase 1 -----------
 
PGAVIN_LINUX_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS := $(PGAVIN_LINUX_BINUTILS_EXTRA_CONFIG_ARGS)
 
# TODO: we are using uclibc, right?
PGAVIN_LINUX_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-libgloss
PGAVIN_LINUX_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-newlib
PGAVIN_LINUX_BINUTILS_PHASE_1_EXTRA_CONFIG_ARGS += --disable-sim
 
PGAVIN_LINUX_BINUTILS_PHASE_1_BIN_DIR := $(PGAVIN_LINUX_TOOLCHAIN_DIR)
 
PGAVIN_LINUX_BINUTILS_PHASE_1_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
 
$(eval $(call autotool_project_template,PGAVIN_LINUX_BINUTILS_PHASE_1,Peter Gavin's Linux Binutils etc. phase 1,$(PGAVIN_OR1K_SRC_CHECKOUT_DIR)))
 
$(PGAVIN_LINUX_BINUTILS_PHASE_1_CONFIGURE_SENTINEL): $(PGAVIN_OR1K_SRC_CHECKOUT_SENTINEL)
 
 
# ---------- Peter Gavin's Linux Headers ----------
 
PGAVIN_LINUX_HEADERS_OBJ_DIR := $(ORBUILD_BUILD_DIR)/PGAVIN_LINUX_HEADERS_OBJ
PGAVIN_LINUX_HEADERS_INSTALL_DIR := $(PGAVIN_LINUX_TOOLCHAIN_PREFIX)
 
PGAVIN_LINUX_HEADERS_CMD := if [ -d \"$(PGAVIN_LINUX_HEADERS_OBJ_DIR)\" ]; then echo \"Deleting previous output directory $(PGAVIN_LINUX_HEADERS_OBJ_DIR)...\" && rm -rf \"$(PGAVIN_LINUX_HEADERS_OBJ_DIR)\"; fi &&
PGAVIN_LINUX_HEADERS_CMD += mkdir \"$(PGAVIN_LINUX_HEADERS_OBJ_DIR)\" &&
PGAVIN_LINUX_HEADERS_CMD += echo \"Creating the Linux headers configuration...\" &&
PGAVIN_LINUX_HEADERS_CMD += make -C \"$(PGAVIN_LINUX_CHECKOUT_DIR)\" O=\"$(PGAVIN_LINUX_HEADERS_OBJ_DIR)\" ARCH=$(PGAVIN_LINUX_ARCH) defconfig &&
PGAVIN_LINUX_HEADERS_CMD += echo \"Installing the Linux headers...\" &&
PGAVIN_LINUX_HEADERS_CMD += make -C \"$(PGAVIN_LINUX_HEADERS_OBJ_DIR)\" ARCH=$(PGAVIN_LINUX_ARCH) INSTALL_HDR_PATH=\"$(PGAVIN_LINUX_HEADERS_INSTALL_DIR)\" headers_install
 
PGAVIN_LINUX_HEADERS_MAKEFLAGS_FILTER := clear
 
$(eval $(call run_makefile_and_report_template,PGAVIN_LINUX_HEADERS,Peter Gavin's Linux Headers,$(SHELL) -c "$(PGAVIN_LINUX_HEADERS_CMD)"))
$(PGAVIN_LINUX_HEADERS_SENTINEL): $(PGAVIN_LINUX_CHECKOUT_SENTINEL)
 
 
# ----------- Peter Gavin's Linux GCC cross-compiler for OpenRISC, common settings -----------
 
PGAVIN_LINUX_COMMON_GCC_OPTIONS := --disable-shared
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-libssp
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-multilib # TODO: should we remove this?
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-lto
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-libgomp
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-libmudflap
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --disable-libquadmath
PGAVIN_LINUX_COMMON_GCC_OPTIONS += --target=$(PGAVIN_OPENRISC_LINUX_TARGET)
 
 
# ---------- Peter Gavin's Linux GCC phase 1 (bootstrap) ----------
 
# In order to build GCC, the OpenRISC Binutils binaries are needed.
PGAVIN_LINUX_GCC_PHASE_1_AUTOCONF_PREPEND_PATH := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/bin
PGAVIN_LINUX_GCC_PHASE_1_BIN_DIR := $(PGAVIN_LINUX_TOOLCHAIN_DIR)
PGAVIN_LINUX_GCC_PHASE_1_EXTRA_CONFIG_ARGS := $(PGAVIN_LINUX_COMMON_GCC_OPTIONS) --enable-languages=c --without-headers --enable-threads=single
PGAVIN_LINUX_GCC_PHASE_1_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
PGAVIN_LINUX_GCC_PHASE_1_MAKE_TARGETS := all-gcc
PGAVIN_LINUX_GCC_PHASE_1_INSTALL_TARGETS := install-gcc
 
$(eval $(call autotool_project_template,PGAVIN_LINUX_GCC_PHASE_1,Peter Gavin's Linux GCC Phase 1,$(PGAVIN_OR1K_GCC_CHECKOUT_DIR)))
 
$(PGAVIN_LINUX_GCC_PHASE_1_CONFIGURE_SENTINEL): $(PGAVIN_LINUX_BINUTILS_PHASE_1_INSTALL_SENTINEL) $(PGAVIN_OR1K_GCC_CHECKOUT_SENTINEL)
 
 
# ---------- Peter Gavin's uClibc for Linux ----------
 
# TODO: The config pollutes the source code repository, but uClibc does not seem to support out-of-tree builds yet:
# If I add with O=\"$(PGAVIN_LINUX_UCLIBC_OBJ_DIR)\" , it fails to install file uClibc_config.h .
# PGAVIN_LINUX_UCLIBC_OBJ_DIR := $(ORBUILD_BUILD_DIR)/PGAVIN_LINUX_UCLIBC_OBJ
 
PGAVIN_LINUX_UCLIBC_CMD :=
 
# PGAVIN_LINUX_UCLIBC_CMD += if [ -d \"$(PGAVIN_LINUX_UCLIBC_OBJ_DIR)\" ]; then echo \"Deleting previous output directory $(PGAVIN_LINUX_UCLIBC_OBJ_DIR)...\" && rm -rf \"$(PGAVIN_LINUX_UCLIBC_OBJ_DIR)\"; fi &&
# PGAVIN_LINUX_UCLIBC_CMD += mkdir \"$(PGAVIN_LINUX_UCLIBC_OBJ_DIR)\" &&
 
PGAVIN_LINUX_UCLIBC_CMD += echo \"Cleaning any previous uClibc configuration ...\" &&
PGAVIN_LINUX_UCLIBC_CMD += make -C \"$(PGAVIN_UCLIBC_CHECKOUT_DIR)\" ARCH=$(PGAVIN_LINUX_ARCH) clean &&
 
PGAVIN_LINUX_UCLIBC_CMD += echo \"Generating the uClibc configuration ...\" &&
PGAVIN_LINUX_UCLIBC_CMD += make -C \"$(PGAVIN_UCLIBC_CHECKOUT_DIR)\"
PGAVIN_LINUX_UCLIBC_CMD += ARCH=$(PGAVIN_LINUX_ARCH)
PGAVIN_LINUX_UCLIBC_CMD += defconfig &&
 
PGAVIN_LINUX_UCLIBC_CMD += echo \"Building uClibc ...\" &&
PGAVIN_LINUX_UCLIBC_CMD += make -C \"$(PGAVIN_UCLIBC_CHECKOUT_DIR)\"
PGAVIN_LINUX_UCLIBC_CMD += PREFIX=\"$(PGAVIN_LINUX_TOOLCHAIN_PREFIX)\"
PGAVIN_LINUX_UCLIBC_CMD += KERNEL_HEADERS=\"$(PGAVIN_LINUX_HEADERS_INSTALL_DIR)/include\"
PGAVIN_LINUX_UCLIBC_CMD += DEVEL_PREFIX=/
PGAVIN_LINUX_UCLIBC_CMD += RUNTIME_PREFIX=/
PGAVIN_LINUX_UCLIBC_CMD += install
 
PGAVIN_LINUX_UCLIBC_MAKEFLAGS_FILTER := pass-j
 
PGAVIN_LINUX_UCLIBC_PREPEND_PATH := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/bin
 
$(eval $(call run_makefile_and_report_template,PGAVIN_LINUX_UCLIBC,Peter Gavin's uClibc for Linux,$(SHELL) -c "$(PGAVIN_LINUX_UCLIBC_CMD)"))
$(PGAVIN_LINUX_UCLIBC_SENTINEL): $(PGAVIN_UCLIBC_CHECKOUT_SENTINEL) $(PGAVIN_LINUX_HEADERS_SENTINEL) $(PGAVIN_LINUX_GCC_PHASE_1_INSTALL_SENTINEL)
# TODO: all_pgavin: $(PGAVIN_LINUX_UCLIBC_SENTINEL)
 
 
# ---------- Peter Gavin's Linux GCC phase 2 ----------
 
# Note that this installs the final GCC binaries over the ones from phase 1.
# Although everything should be properly overwritten, this method does not look very clean to me.
 
PGAVIN_LINUX_GCC_PHASE_2_AUTOCONF_PREPEND_PATH := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/bin
PGAVIN_LINUX_GCC_PHASE_2_BIN_DIR := $(PGAVIN_LINUX_TOOLCHAIN_DIR)
 
PGAVIN_LINUX_GCC_PHASE_2_EXTRA_CONFIG_ARGS := $(PGAVIN_LINUX_COMMON_GCC_OPTIONS) --enable-languages=c,c++
PGAVIN_LINUX_GCC_PHASE_2_EXTRA_CONFIG_ARGS += --enable-threads=posix
PGAVIN_LINUX_GCC_PHASE_2_EXTRA_CONFIG_ARGS += --with-headers=$(PGAVIN_LINUX_HEADERS_INSTALL_DIR)/include
 
PGAVIN_LINUX_GCC_PHASE_2_EXTRA_GLOBAL_MAKE_ARGS := $(FASTER_MAKE)
 
$(eval $(call autotool_project_template,PGAVIN_LINUX_GCC_PHASE_2,Peter Gavin's Linux GCC Phase 2,$(PGAVIN_OR1K_GCC_CHECKOUT_DIR)))
 
$(PGAVIN_LINUX_GCC_PHASE_2_CONFIGURE_SENTINEL): $(PGAVIN_LINUX_UCLIBC_SENTINEL)
# TODO: all_pgavin: $(PGAVIN_LINUX_GCC_PHASE_2_INSTALL_SENTINEL)
 
# TODO: The bld-all.sh rebuilds uClibc with the final (phase 2) compiler, maybe we should do the same here.
 
 
# ----------- Linux GDB cross-debugger for OpenRISC -----------
 
# TODO: This is the old 7.2 debugger, we should probably use a newer one.
 
LINUX_GDB_SRC_DIR := $(GNUSRC_CHECKOUT_DIR)/gdb-7.2
LINUX_GDB_BIN_DIR := $(PGAVIN_LINUX_TOOLCHAIN_DIR)
LINUX_GDB_AUTOCONF_PREPEND_PATH := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/bin
 
# Peter Gavin's toolchain uses 'or1k' and this old GDB uses 'or32', therefore we need the CROSS_COMPILE argument here:
LINUX_GDB_EXTRA_CONFIG_ARGS := CROSS_COMPILE=$(OPENRISC_LINUX_TARGET)-
LINUX_GDB_EXTRA_CONFIG_ARGS += --target=$(OPENRISC_LINUX_TARGET)
# GDB uses or1ksim as the target simulator.
LINUX_GDB_EXTRA_CONFIG_ARGS += --with-or1ksim=$(PGAVIN_OR1KSIM_BIN_DIR)
 
$(eval $(call autotool_project_template,LINUX_GDB,GDB 7.2 for Linux with Peter Gavin's toolchain,$(LINUX_GDB_SRC_DIR)))
 
$(LINUX_GDB_CONFIGURE_SENTINEL): $(PGAVIN_LINUX_GCC_PHASE_2_INSTALL_SENTINEL) $(PGAVIN_OR1KSIM_INSTALL_SENTINEL)
# TODO: all_pgavin: $(LINUX_GDB_INSTALL_SENTINEL)
 
 
# ---- Build gdbserver ----
 
GDBSERVER_SRC_DIR := $(LINUX_GDB_SRC_DIR)/gdb/gdbserver
 
GDBSERVER_EXTRA_CONFIG_ARGS := CC=$(PGAVIN_OPENRISC_LINUX_TARGET)-gcc
GDBSERVER_EXTRA_CONFIG_ARGS += --target=$(OPENRISC_LINUX_TARGET)
GDBSERVER_EXTRA_CONFIG_ARGS += --host=$(OPENRISC_LINUX_TARGET)
 
GDBSERVER_AUTOCONF_PREPEND_PATH := $(PGAVIN_LINUX_TOOLCHAIN_DIR)/bin
$(eval $(call autotool_project_template,GDBSERVER,gdbserver,$(GDBSERVER_SRC_DIR)))
 
$(GDBSERVER_CONFIGURE_SENTINEL): $(LINUX_GDB_INSTALL_SENTINEL)
 
# Disabled for the time being, as I have not been able to get this to work yet.
ifeq "1" "0"
all_pgavin: $(GDBSERVER_INSTALL_SENTINEL)
endif
 
 
# ----------- OpenRISC Test Suite -----------
 
# NOTE: If PGAVIN is enabled, the Test Suite uses that toolchain instead of the standard one.
 
# ----- Build the test suite for a generic reference system.
 
ORTS_DIR := $(ORBUILD_PROJECT_DIR)/TestSuite
 
ORTS_EXES_INSTALL_MAKEFLAGS_FILTER := pass-j
 
# Add --enable-debug=yes to ORTS_EXES_EXTRA_CONFIG_ARGS in order to enable debug builds.
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
ORTS_EXES_EXTRA_CONFIG_ARGS := --build=$$$$($(ORTS_DIR)/config.guess) --host=$(PGAVIN_OPENRISC_BARE_TARGET)
# The 3 alternatives are: -mno-delay, -mdelay and -mcompat-delay
ORTS_EXES_EXTRA_CONFIG_ARGS += CFLAGS="-mcompat-delay" CXXFLAGS="-mcompat-delay"
ORTS_EXES_AUTOCONF_PREPEND_PATH := $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
ORTS_EXES_AUTOGEN_PARAM := $(PGAVIN_OPENRISC_BARE_TARGET)
else
ORTS_EXES_EXTRA_CONFIG_ARGS := --build=$$$$($(ORTS_DIR)/config.guess) --host=$(OPENRISC_BARE_TARGET)
ORTS_EXES_AUTOCONF_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
ORTS_EXES_AUTOGEN_PARAM := $(OPENRISC_BARE_TARGET)
endif
 
ORTS_EXES_EXTRA_GLOBAL_MAKE_ARGS := --no-builtin-rules
 
$(eval $(call autotool_project_template,ORTS_EXES,OpenRISC Test Suite executables,$(ORTS_DIR)))
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
$(ORTS_EXES_CONFIGURE_SENTINEL): $(PGAVIN_GCC_PHASE_2_INSTALL_SENTINEL)
else
$(ORTS_EXES_CONFIGURE_SENTINEL): $(GCC_PHASE_2_INSTALL_SENTINEL)
endif
 
ORTS_EXES_AUTOGEN_CMD = $(SHELL) autogen.sh $(ORTS_EXES_AUTOGEN_PARAM)
$(eval $(call autogen_project_template,ORTS_EXES,OpenRISC Test Suite executables))
 
# During development, it's quite convenient to rerun the tests without rebuilding
# all other components. Uncomment one of the following lines to reconfigure, rebuild and rerun just the tests
# on each "./orbuild --resume" run:
# Just rebuild and rerun:
# $(shell rm $(ORBUILD_AUTOCONF_SENTINELS_DIR)/ORTS_EXES.Make.$(ORBUILD_SENTINEL_FILENAME_SUFFIX))
# Reconfigure, rebuild and rerun:
# $(shell rm $(ORBUILD_AUTOCONF_SENTINELS_DIR)/ORTS_EXES.Autogen.$(ORBUILD_SENTINEL_FILENAME_SUFFIX))
 
# ----- Run the test suite against different targets.
 
ORTS_PREPEND_PATH_LIST := $(VERILOG_TOOLS_PREPEND_PATH)
 
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
ORTS_OR1KSIM_PREPEND_PATH := $(PGAVIN_OR1KSIM_BIN_DIR)/bin
ORTS_PREPEND_PATH_LIST += $(PGAVIN_BARE_TOOLCHAIN_DIR)/bin
# The following setting can be set to either 'with-jump-delay-slot' or 'without-jump-delay-slot'.
# The or1ksim simulator is started in the given mode, and one of the assembler test cases
# is chosen based on this setting. The C/C++ test cases are all compiled with -mcompat-delay (see above),
# but they can manually be compiled in other modes by modifying this makefile.
ORTS_OR1KSIM_JUMP_DELAY_SLOT := with-jump-delay-slot
else
ORTS_OR1KSIM_PREPEND_PATH := $(OR1KSIM_BIN_DIR)/bin
ORTS_PREPEND_PATH_LIST += $(BARE_TOOLCHAIN_DIR)/bin
ORTS_OR1KSIM_JUMP_DELAY_SLOT := with-jump-delay-slot
endif
 
ORTS_PREPEND_PATH := $(subst $(SPACE_CHAR),$(COLON_CHAR),$(strip $(ORTS_PREPEND_PATH_LIST)))
 
ORTS_PGAVIN_CGEN_PREPEND_PATH := $(PGAVIN_BINUTILS_PHASE_2_BIN_DIR)/bin
ORTS_ORPSOC_IVERILOG_PREPEND_PATH := $(ORTS_PREPEND_PATH)
ORTS_MINSOC_VERILATOR_PREPEND_PATH := $(ORTS_PREPEND_PATH)
 
ORTS_COMMON_CMD := \"$(ORBUILD_PROJECT_DIR)/Tools/RunTestSuite.sh\"
ORTS_COMMON_CMD += OrtsPublicReports
ORTS_COMMON_CMD += TestReport.html
ORTS_COMMON_CMD += \"$(ORTS_EXES_BIN_DIR)\"
ORTS_COMMON_CMD += \"$(ORTS_EXES_INSTALL_SENTINEL)\"
ORTS_COMMON_CMD += \"$(ORPSOCV2_CHECKOUT_DIR)\"
 
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
ORTS_COMMON_CMD += $(PGAVIN_OPENRISC_BARE_TARGET)
else
ORTS_COMMON_CMD += $(OPENRISC_BARE_TARGET)
endif
 
ORTS_OR1KSIM_OBJ_DIR := $(ORBUILD_BUILD_DIR)/temp/ORTS_OR1KSIM
ORTS_OR1KSIM_CMD := $(ORTS_COMMON_CMD) \"$(ORTS_OR1KSIM_OBJ_DIR)\" ORTS_OR1KSIM $(ORTS_OR1KSIM_JUMP_DELAY_SLOT)
ORTS_OR1KSIM_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ORTS_OR1KSIM,Test Suite against or1ksim,$(SHELL) -c "$(ORTS_OR1KSIM_CMD)"))
 
ORTS_PGAVIN_CGEN_OBJ_DIR := $(ORBUILD_BUILD_DIR)/temp/ORTS_PGAVIN_CGEN
ORTS_PGAVIN_CGEN_CMD := $(ORTS_COMMON_CMD) \"$(ORTS_PGAVIN_CGEN_OBJ_DIR)\" ORTS_PGAVIN_CGEN with-jump-delay-slot
ORTS_PGAVIN_CGEN_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ORTS_PGAVIN_CGEN,Test Suite against Peter Gavin's CGEN simulator,$(SHELL) -c "$(ORTS_PGAVIN_CGEN_CMD)"))
 
ORTS_ORPSOC_IVERILOG_OBJ_DIR := $(ORBUILD_BUILD_DIR)/temp/ORTS_ORPSOC_IVERILOG
ORTS_ORPSOC_IVERILOG_CMD := $(ORTS_COMMON_CMD) \"$(ORTS_ORPSOC_IVERILOG_OBJ_DIR)\" ORTS_ORPSOC_IVERILOG with-jump-delay-slot
ORTS_ORPSOC_IVERILOG_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ORTS_ORPSOC_IVERILOG,Test Suite against ORPSoC V2 with Icarus Verilog,$(SHELL) -c "$(ORTS_ORPSOC_IVERILOG_CMD)"))
 
ORTS_MINSOC_VERILATOR_OBJ_DIR := $(ORBUILD_BUILD_DIR)/temp/ORTS_MINSOC_VERILATOR
ORTS_MINSOC_VERILATOR_CMD := $(ORTS_COMMON_CMD) \"$(ORTS_MINSOC_VERILATOR_OBJ_DIR)\" ORTS_MINSOC_VERILATOR with-jump-delay-slot
ORTS_MINSOC_VERILATOR_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ORTS_MINSOC_VERILATOR,Test Suite against MINSoC with Verilator,$(SHELL) -c "$(ORTS_MINSOC_VERILATOR_CMD)"))
 
orts_subproject_files:
echo "OpenRISC Test Suite = $(ORTS_EXES_AUTOTOOLS_GROUP) ORTS_OR1KSIM ORTS_PGAVIN_CGEN ORTS_ORPSOC_IVERILOG ORTS_MINSOC_VERILATOR " >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "ORTS_OR1KSIM = $(ORTS_OR1KSIM_OBJ_DIR)/OrtsPublicReports/TestReport.html" >>$(ORBUILD_SUBPROJECTS_FILENAME)
echo "ORTS_PGAVIN_CGEN = $(ORTS_PGAVIN_CGEN_OBJ_DIR)/OrtsPublicReports/TestReport.html" >>$(ORBUILD_SUBPROJECTS_FILENAME)
echo "ORTS_ORPSOC_IVERILOG = $(ORTS_ORPSOC_IVERILOG_OBJ_DIR)/OrtsPublicReports/TestReport.html" >>$(ORBUILD_SUBPROJECTS_FILENAME)
echo "ORTS_MINSOC_VERILATOR = $(ORTS_MINSOC_VERILATOR_OBJ_DIR)/OrtsPublicReports/TestReport.html" >>$(ORBUILD_SUBPROJECTS_FILENAME)
 
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
$(ORTS_OR1KSIM_SENTINEL) : $(ORTS_EXES_INSTALL_SENTINEL) $(PGAVIN_OR1KSIM_INSTALL_SENTINEL)
else
$(ORTS_OR1KSIM_SENTINEL) : $(ORTS_EXES_INSTALL_SENTINEL) $(OR1KSIM_INSTALL_SENTINEL)
endif
$(ORTS_PGAVIN_CGEN_SENTINEL) : $(ORTS_EXES_INSTALL_SENTINEL) $(PGAVIN_BINUTILS_PHASE_2_INSTALL_SENTINEL)
$(ORTS_ORPSOC_IVERILOG_SENTINEL) : $(ORTS_EXES_INSTALL_SENTINEL) $(VERILOG_TOOLS_PREREQS) $(value $(ORPSOC_NAME)_SW_UTILS_CMD_SENTINEL)
$(ORTS_MINSOC_VERILATOR_SENTINEL): $(ORTS_EXES_INSTALL_SENTINEL) $(VERILOG_TOOLS_PREREQS) $(value $(ORPSOC_NAME)_SW_UTILS_CMD_SENTINEL)
 
ifeq "$(strip $(ENABLE_OPEN_RISC_TEST_SUITE))" "1"
all: $(ORTS_OR1KSIM_SENTINEL)
all: $(ORTS_ORPSOC_IVERILOG_SENTINEL)
# TODO: The Verilator support is not ready yet:
# all: $(ORTS_MINSOC_VERILATOR_SENTINEL)
ifeq "$(strip $(ENABLE_PGAVIN))" "1"
all: $(ORTS_PGAVIN_CGEN_SENTINEL)
endif
all: orts_subproject_files
endif
 
 
# -------------- eCos realtime operating system --------------
 
# I'm getting sporadic errors like this:
# mkdir: cannot create directory `cyg': File exists
# I suspect the config tool's makefile breaks in the 'make' phase when running in parallel mode.
ECOS_CONFIG_TOOL_MAKE_MAKEFLAGS_FILTER := clear
ECOS_CONFIG_TOOL_INSTALL_MAKEFLAGS_FILTER := clear
$(eval $(call autotool_project_template,ECOS_CONFIG_TOOL,eCos config tool,$(ECOS_CHECKOUT_DIR)/host))
$(ECOS_CONFIG_TOOL_CONFIGURE_SENTINEL): $(ECOS_CHECKOUT_SENTINEL)
 
ECOS_OBJ_DIR := $(ORBUILD_BUILD_DIR)/bin/ECOS
ECOS_BUILD_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin
ECOS_BUILD_CMD := $(ORBUILD_PROJECT_DIR)/Tools/BuildEcos.sh \"$(ECOS_CHECKOUT_DIR)\" \"$(ECOS_CONFIG_TOOL_BIN_DIR)\" \"$(ECOS_OBJ_DIR)\"
ECOS_BUILD_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ECOS_BUILD,eCos build,$(SHELL) -c "$(ECOS_BUILD_CMD)"))
$(ECOS_BUILD_SENTINEL): $(ECOS_CONFIG_TOOL_INSTALL_SENTINEL) $(GCC_PHASE_2_INSTALL_SENTINEL)
 
ifeq "$(strip $(ENABLE_ECOS))" "1"
all: $(ECOS_BUILD_SENTINEL)
endif
 
ECOS_TEST_OBJ_DIR := $(ORBUILD_BUILD_DIR)/bin/ECOS_TEST
ECOS_TEST_PREPEND_PATH := $(BARE_TOOLCHAIN_DIR)/bin:$(OR1KSIM_BIN_DIR)/bin
ECOS_TEST_CMD := $(ORBUILD_PROJECT_DIR)/Tools/TestEcos.sh \"$(ECOS_OBJ_DIR)\" \"$(ECOS_TEST_OBJ_DIR)\"
ECOS_TEST_MAKEFLAGS_FILTER := pass-j
$(eval $(call run_makefile_and_report_template,ECOS_TEST,eCos simple test,$(SHELL) -c "$(ECOS_TEST_CMD)"))
 
ifeq "$(strip $(ENABLE_ECOS_TEST))" "1"
$(ECOS_TEST_SENTINEL): $(ECOS_BUILD_SENTINEL) $(OR1KSIM_INSTALL_SENTINEL)
all: $(ECOS_TEST_SENTINEL)
endif
 
 
# -------------- Report grouping --------------
 
SVN_CHECKOUT_GROUP := OR1KSIM_SVN_CHECKOUT
SVN_CHECKOUT_GROUP += DOCS_SVN_CHECKOUT
SVN_CHECKOUT_GROUP += ORPSOCV2_SVN_CHECKOUT
SVN_CHECKOUT_GROUP += GNUSRC_SVN_CHECKOUT
SVN_CHECKOUT_GROUP += MINSOC_SVN_CHECKOUT
SVN_CHECKOUT_GROUP += ECOS_SVN_CHECKOUT
 
BARE_TOOLCHAIN_GROUP := $(BINUTILS_AUTOTOOLS_GROUP)
BARE_TOOLCHAIN_GROUP += $(GCC_PHASE_1_AUTOTOOLS_GROUP)
BARE_TOOLCHAIN_GROUP += $(NEWLIB_AUTOTOOLS_GROUP)
BARE_TOOLCHAIN_GROUP += $(GCC_PHASE_2_AUTOTOOLS_GROUP)
BARE_TOOLCHAIN_GROUP += $(OR1KSIM_AUTOTOOLS_GROUP)
BARE_TOOLCHAIN_GROUP += $(GDB_AUTOTOOLS_GROUP)
 
VERILOG_TOOLS_GROUP := $(ICARUS_VERILOG_AUTOTOOLS_GROUP)
VERILOG_TOOLS_GROUP += $(VERILATOR_AUTOTOOLS_GROUP)
 
PGAVIN_TOOLCHAIN_GROUP := PGAVIN_LINUX_HEADERS
PGAVIN_TOOLCHAIN_GROUP += PGAVIN_LINUX_UCLIBC
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_BINUTILS_PHASE_1_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_BINUTILS_PHASE_2_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_GCC_PHASE_1_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_GCC_PHASE_2_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_OR1KSIM_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_LINUX_BINUTILS_PHASE_1_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_LINUX_GCC_PHASE_1_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(PGAVIN_LINUX_GCC_PHASE_2_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(LINUX_GDB_AUTOTOOLS_GROUP)
PGAVIN_TOOLCHAIN_GROUP += $(GDBSERVER_AUTOTOOLS_GROUP)
 
PGAVIN_GIT_GROUP := $(PGAVIN_LINUX_GIT_GROUP)
PGAVIN_GIT_GROUP += $(PGAVIN_OR1KSIM_GIT_GROUP)
PGAVIN_GIT_GROUP += $(PGAVIN_UCLIBC_GIT_GROUP)
PGAVIN_GIT_GROUP += $(PGAVIN_OR1K_SRC_GIT_GROUP)
PGAVIN_GIT_GROUP += $(PGAVIN_OR1K_GCC_GIT_GROUP)
 
ECOS_GROUP := $(ECOS_CONFIG_TOOL_AUTOTOOLS_GROUP)
ECOS_GROUP += ECOS_BUILD
ECOS_GROUP += ECOS_TEST
 
GIT_GROUP := $(JBONN_LINUX_GIT_GROUP)
GIT_GROUP += $(JBONN_UCLIBC_GIT_GROUP)
GIT_GROUP += $(ICARUS_VERILOG_GIT_GROUP)
GIT_GROUP += $(VERILATOR_GIT_GROUP)
 
generate_groups_file:
echo "Subversion Repositories = $(SVN_CHECKOUT_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Bare Toolchain = $(BARE_TOOLCHAIN_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Verilog Tools = $(VERILOG_TOOLS_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Peter Gavin's Toolchain = $(PGAVIN_TOOLCHAIN_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Peter Gavin's Repositories = $(PGAVIN_GIT_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Lint results = $(LINT_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "eCos realtime operating system = $(ECOS_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
echo "Git Repositories = $(GIT_GROUP)" >>$(ORBUILD_COMPONENT_GROUPS_FILENAME)
 
all: generate_groups_file
/orbuild/orbuild.conf
0,0 → 1,69
 
# Configuration file for the orbuild system.
 
RotateSlotCount = 2
 
# The orbuild framework is generic enough to be repurposed for projects other than OpenRISC.
# With this setting you can specify your own project makefile.
#
# Note that the project's top-level path is deduced from this filename,
# so the makefile specified here should live at the top of the project's directory structure.
#
# You probably want to edit the project's makefile in order to choose which components get built.
# In the case of OpenRISC, look at the ENABLE_xxx variables at the top.
#
# Makefile = Scripts/Projects/ExampleSimple/Makefile
# Makefile = Scripts/Projects/ExampleGroups/Makefile
Makefile = Scripts/Projects/OpenRISC/Makefile
 
# Building in parallel can dramatically reduce the build time. However,
# if your build process requires human interaction (for example, when Subversion prompts for a login and password),
# then you should disable the parallel build, otherwise the output will be interleaved
# and you may not see the interactive prompts clearly.
# This setting can be overridden with command-line switch --interactive .
ParallelBuild = no
 
# Set to 'yes' if your build requires interaction (for example, when Subversion prompts for a login and password).
# This setting is incompatible with ParallelBuild, not because it's strictly illegal, but
# because it does not normally make sense. See ParallelBuild for more information.
# This setting can be overridden with command-line switch --interactive .
InteractiveBuild = yes
 
# You normally want to build as many components as possible, instead of stopping on the first error.
StopOnFirstError = no
 
# The PostBuildAction runs only when the build is successful.
PostBuildAction =
 
# The VisualNotification action runs when the build finishes, whether successful or not.
# Use option --test-visual-notification in order to test this setting without building anything.
#
# Example 1, notify with gxmessage under Linux, wait for the user to close the notification window.
# gxmessage has the shortcoming that closing the window without pressing a button
# generates the same exit code as any other error. The "; true" here
# ignores any non-zero exit code.
#
# VisualNotification = gxmessage -title "Build finished" "Build finished"; true
#
# Example 2, open the generated HTML report with Firefox under Linux, but do not wait for the user to close it (leave it running in the background):
# The "</dev/null" suffix prevents file "nohup.out" from being created every time.
#
# VisualNotification = nohup firefox -new-window "$ORBUILD_FINAL_REPORT_FILENAME" 2>/dev/null >/dev/null
#
# Example 3, open the generated HTML report with Firefox under Windows:
#
# VisualNotification = cygstart "$ORBUILD_FINAL_REPORT_FILENAME"
#
# Example 4, leave this setting empty to disable the visual notification, suitable when running on a server:
#
# VisualNotification =
#
# Example 5 (the default). orbuild comes with a script which tries to guess the best way to open the HTML report.
#
# VisualNotification = "$ORBUILD_TOOLS/VisualNotification.sh" "$ORBUILD_FINAL_REPORT_FILENAME"
#
VisualNotification = "$ORBUILD_TOOLS/VisualNotification.sh" "$ORBUILD_FINAL_REPORT_FILENAME"
 
DownloadCacheDir = DownloadCache/
RepositoriesDir = Repositories/
BuildsDir = Builds/
/orbuild/README
0,0 → 1,2
http://www.rte.se/blog/blogg-modesty-corex/using-orbuild
 
/orbuild/Makefile
0,0 → 1,16
SHELL=/bin/sh
MAKE=make
CUR_DIR=$(shell pwd)
home=$(CUR_DIR)/..
 
 
 
.PHONY download:
download:
git clone https://github.com/rdiez/orbuild orbuild;\
)
 
 
 
 
 
/install/Ubuntu_12.04/README.txt
0,0 → 1,36
===================================================
Installation steps to run socgen on Ubuntu 10.10
===================================================
 
Install ubuntu 10.10
 
sudo apt-get install -y subversion;
 
svn co --username <<>> --password <<>> http://opencores.org/ocsvn/socgen/socgen/trunk socgen;\
 
cd socgen/tools/install/Ubuntu_10.10
 
make install ( adds ~/bin into your $PATH)
 
 
cd socgen/tools/JtagProgrammer
 
make install ( adds urjtag tools)
 
reboot
 
cd socgen
 
make build_soc
 
make run_sims
 
make build_fpgas (if you have xilinx webpack 12.4 installed)
 
---------------------------
 
Enable HW drivers
update
Install make composite
Install_cmp make crasm, or-32 msp430
install fpga
/install/Ubuntu_12.04/Makefile
0,0 → 1,68
SHELL=/bin/sh
MAKE=make
CUR_DIR=$(shell pwd)
home=$(CUR_DIR)/..
 
all: install
 
 
.PHONY install:
install:
(\
sudo apt-get install -y emacs23;\
sudo apt-get install -y subversion;\
sudo apt-get install -y git;\
sudo apt-get install -y iverilog;\
sudo apt-get install -y verilator;\
sudo apt-get install -y gcc g++ libmpfr-dev libgmp3-dev libmpc-dev libzip-dev texlive flex bison texinfo libncurses-dev gperf dejagnu;\
sudo apt-get install -y libxml-libxml-perl;\
chmod 755 ../../bin/* ;\
chmod 755 ../../sys/* ;\
sudo apt-get install -y asciidoc;\
sudo apt-get install -y perl-tk;\
sudo apt-get install -y perl-doc;\
sudo apt-get install -y libverilog-perl;\
sudo apt-get install -y cvs;\
sudo apt-get install -y k3b;\
sudo apt-get install -y geda;\
sudo apt-get install -y seamonkey;\
sudo apt-get install -y covered;\
sudo apt-get install -y xutils-dev;\
sudo apt-get install -y gputils;\
sudo apt-get install -y gtkterm;\
sudo apt-get install -y gtkwave;\
sudo apt-get install -y libncurses5-dev;\
sudo apt-get install -y build-essential;\
sudo apt-get install -y tkdiff;\
sudo apt-get install -y librxtx-java;\
sudo apt-get install -y libmpc2;\
sudo apt-get install -y crasm;\
sudo apt-get install -y xa65;\
sudo apt-get install -y sdcc;\
sudo apt-get install -y ghdl;\
sudo apt-get install -y csh;\
sudo apt-get install -y zlibc;\
sudo apt-get install -y zlib1g-dev;\
sudo apt-get install -y libx11-dev;\
sudo apt-get install -y gitk;\
sudo apt-get install -y git-gui;\
sudo apt-get install -y git-doc;\
sudo apt-get install -y git-core;\
sudo apt-get install -y gcc-4.4;\
sudo apt-get install -y patch;\
sudo apt-get install -y libncurses5-dev;\
sudo apt-get install -y libusb-dev;\
sudo apt-get install -y libreadline6-dev;\
sudo apt-get install -y tex-info;\
sudo apt-get install -y texlive;\
sudo apt-get install -y libxml-simple-perl;\
sudo apt-get install -y autoconf;\
sudo apt-get install -y autopoint;\
sudo apt-get install -y libtool;\
sudo apt-get install -y qt4-qmake;\
sudo apt-get install -y qt4-designer;\
sudo apt-get install -y virtualbox-qt;\
sudo apt-get install -y quilt;\
)
 
 
/sys/build_geda
287,8 → 287,8
my $sch_out_pad = ($in_length +$out_length)*10*$sch_size +3500;
 
printf SCH_FILE ("v 20100214 1\n");
printf SCH_FILE ("T 40 40 8 10 1 1 0 0 1 1\n%srefdes=U?\n");
 
 
my $sym_color = 5;
my $sym_size = 10;
my $sym_box_h = ($max_pins * 200) +300;
/sys/build_registers
70,9 → 70,8
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"bigendian",
"word",
"full_word"
"dest_dir=s" => \$dest_dir,
"bus_intf=s" => \$bus_intf
) || die "(use '$program_name -h' for help)";
 
 
81,7 → 80,7
##############################################################################
if ( $opt_h )
{
print "\n build_registers -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -bigendian dest_dir";
print "\n build_registers -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -bus_intf bus_interface -dest_dir dest_dir";
print "\n";
exit 1;
}
95,8 → 94,6
 
$home = cwd();
 
my $dest_dir = $ARGV[0];
 
#############################################################################
##
##
122,24 → 119,42
my $memmap_base;
my $addblk_name;
my $addblk_range;
my $addblk_numrange;
my $addblk_numaddbits;
my $addblk_width;
my $byte_size;
my $byte_size;
my $reg_dim;
my $memMap;
 
if ($opt_full_word)
{
$byte_size = 32;
}
elsif($opt_word)
{
$byte_size = 16;
}
else
{
$byte_size = 8;
}
 
my $memmap_name;
my $memmap_base;
my $memmap_numbase;
my $memmap_size;
my $memmap_type;
my $parmap_name;
 
my $reg_offset;
my $reg_numoffset;
my $reg_dimbits;
my $reg_create;
my $reg_has_read;
my $reg_has_write;
my $opt_bigendian;
 
my $reg_numdim;
 
my $max_dim = 1;
my $max_has_read = 0;
my $max_has_write = 0;
my $max_has_create = 0;
 
my $pad;
my $sys_byte_lanes;
 
 
@registers = ();
 
#/**********************************************************************/
#/* */
#/* Parse register block info from ip-xact file */
161,36 → 176,36
$library = $comp->findnodes('./spirit:library/text()')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:name'))
foreach my $bus_iface ($spirit_component_file->findnodes("//spirit:busInterface[spirit:name/text() = '$bus_intf']/spirit:slave"))
{
$memmap_name = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('../spirit:baseAddress/text()')->to_literal ;
$BI_name = $bus_iface->findnodes('../spirit:name/text()')->to_literal ;
$BI_endian = $bus_iface->findnodes('../spirit:endianness/text()')->to_literal ;
$BI_width = $bus_iface->findnodes('../spirit:bitsInLau/text()')->to_literal ;
$BI_xname = $bus_iface->findnodes('../spirit:abstractionType/@spirit:name')->to_literal ;
$memMap = $bus_iface->findnodes('../spirit:slave/spirit:memoryMapRef/@spirit:memoryMapRef')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:name'))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
}
$addblk_range = hex($addblk_range);
$addblk_range = log($addblk_range)/log(2);
my $sys_byte_lanes = int( $addblk_width) / $byte_size ;
unless($BI_endian) {$BI_endian = "little";}
$byte_size = int($BI_width) ;
 
if ($sys_byte_lanes == 4 ) { $adr_base = 2;}
elsif ($sys_byte_lanes == 2 ) { $adr_base = 1;}
else { $adr_base = 0;}
print "ZZZZZZQ $library $name $version bus_intf:: $bus_intf name:: $BI_name abstract:: $BI_xname endian:: $BI_endian width:: $BI_width | $byte_size | Map:: $BI_mm \n";
 
my $variant;
if($version) {$variant ="${name}_${version}_${memmap_name}";}
else {$variant ="${name}_${memmap_name}";}
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']"))
{
$memmap_name = $comp_view->findnodes('./spirit:bank/spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('./spirit:bank/spirit:baseAddress/text()')->to_literal ;
$memmap_size = $comp_view->findnodes('./spirit:addressUnitBits/text()')->to_literal ;
$memmap_type = $comp_view->findnodes('./spirit:bank/@spirit:bankAlignment')->to_literal ;
$parmap_name = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
print "ZZZZZZR Name: $memmap_name Base: $memmap_base Type: $memmap_type Size: $memmap_size Parent: $parmap_name \n";
 
 
$memmap_numbase = hex($memmap_base);
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
198,42 → 213,204
#/* */
#/**********************************************************************/
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${variant}";
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${name}_${version}_${memmap_name}";
open OUTFILE,">$outfile" or die "unable to open $outfile";
print OUTFILE " /*********************************************/ \n";
print OUTFILE " /* Register module */ \n";
print OUTFILE sprintf(" /* Vendor: %24s */ \n",$vendor);
print OUTFILE sprintf(" /* Library: %24s */ \n",$library);
print OUTFILE sprintf(" /* Component: %24s */ \n",$name);
print OUTFILE sprintf(" /* Version: %24s */ \n",$version);
print OUTFILE sprintf(" /* Module: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* MemMap: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* Base: %24s */ \n",$memmap_base);
print OUTFILE sprintf(" /* Type: %24s */ \n",$memmap_type);
 
 
 
 
if($BI_endian eq "big" )
{
$opt_bigendian = 1;
print OUTFILE " /* Endian: Big */ \n";
}
else
 
{
print OUTFILE " /* Endian: Little */ \n";
$opt_bigendian = 0;
}
 
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
foreach my $comp_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock/spirit:name"))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
print "ZZZZZZS addblk Name: $addblk_name Range: $addblk_range Size: $addblk_width \n";
 
 
$addblk_numrange = hex($addblk_range);
$addblk_numaddbits = log($addblk_numrange)/log(2);
$sys_byte_lanes = int( $addblk_width) / $byte_size ;
 
if ($sys_byte_lanes == 4 ) { $adr_base = 2;}
elsif ($sys_byte_lanes == 2 ) { $adr_base = 1;}
else { $adr_base = 0;}
 
 
print OUTFILE sprintf(" /* AddressBlock: %24s */ \n",$addblk_name);
print OUTFILE sprintf(" /* NumBase: %24s */ \n",$memmap_numbase);
print OUTFILE sprintf(" /* Range: %24s */ \n",$addblk_range);
print OUTFILE sprintf(" /* NumRange: %24s */ \n",$addblk_numrange);
print OUTFILE sprintf(" /* NumAddBits: %24s */ \n",$addblk_numaddbits);
print OUTFILE sprintf(" /* Width: %24s */ \n",$addblk_width);
print OUTFILE sprintf(" /* Byte_lanes: %24s */ \n",$sys_byte_lanes);
print OUTFILE sprintf(" /* Byte_size: %24s */ \n",$byte_size);
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
foreach my $reg_view ($spirit_component_file->findnodes("//spirit:memoryMap[spirit:name/text() = '$memMap']/spirit:bank/spirit:addressBlock[spirit:name/text() = '$addblk_name']/spirit:register/spirit:name "))
 
{
$reg_name = $reg_view->findnodes('./text()')->to_literal ;
$reg_offset = $reg_view->findnodes('../spirit:addressOffset/text()')->to_literal ;
$reg_dim = $reg_view->findnodes('../spirit:dim/text()')->to_literal ;
$reg_size = $reg_view->findnodes('../spirit:size/text()')->to_literal ;
$reg_access = $reg_view->findnodes('../spirit:access/text()')->to_literal ;
$reg_numoffset = hex($reg_offset) + $memmap_numbase;
unless($reg_dim) {$reg_dim = "0x1" ;}
$reg_numdim = hex($reg_dim);
 
if($reg_numdim > $max_dim ) {$max_dim = $reg_numdim;}
 
if($reg_numdim)
{
$reg_dimbits = log($reg_numdim)/log(2);
}
else
{
$reg_dimbits = 1;
}
 
if($reg_access eq "read-write")
{
$reg_has_read = 1;
$reg_has_write = 1;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
}
 
 
 
 
 
 
if($reg_access eq "read-only")
{
$reg_has_read = 1;
$reg_has_write = 0;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
 
}
 
 
if($reg_access eq "write-only")
{
$reg_has_read = 0;
$reg_has_write = 1;
if($reg_numdim)
{
if($reg_dimbits) {$reg_create = 0;}
else {$reg_create = 1;}
}
else
{
$reg_create = 0;
}
 
}
 
 
if($reg_access eq "write-strobe")
{
$reg_has_read = 0;
$reg_has_write = 1;
$reg_create = 0;
}
if ($opt_bigendian)
{
print OUTFILE " /* Endian: Big */ \n";
}
else
{
print OUTFILE " /* Endian: Little */ \n";
$opt_bigendian = 0;
}
if($reg_has_read){$max_has_read = 1;}
if($reg_has_write){$max_has_write = 1;}
if($reg_create) {$max_has_create = 1;}
 
 
 
 
 
print "ZZZZZZT reg Name: $reg_name Base: hex(${memmap_base}) Offset: hex(${reg_offset}) Dim: $reg_dim Size: $reg_size Depth: 1 $reg_access \n";
print OUTFILE sprintf(" /* Reg Name: %22s */ \n",$reg_name);
print OUTFILE sprintf(" /* Reg Offset: %22s */ \n",$reg_offset);
print OUTFILE sprintf(" /* Reg numOffset: %22s */ \n",$reg_numoffset);
print OUTFILE sprintf(" /* Reg size: %22s */ \n",$reg_size);
print OUTFILE sprintf(" /* Reg Dim: %22s */ \n",$reg_dim);
print OUTFILE sprintf(" /* Reg numDim: %22s */ \n",$reg_numdim);
print OUTFILE sprintf(" /* Reg DimBits: %22s */ \n",$reg_dimbits);
print OUTFILE sprintf(" /* Reg Create: %22s */ \n",$reg_create);
print OUTFILE sprintf(" /* Reg access: %22s */ \n",$reg_access);
print OUTFILE sprintf(" /* Reg has_read: %22s */ \n",$reg_has_read);
print OUTFILE sprintf(" /* Reg has_write: %22s */ \n",$reg_has_write);
print OUTFILE sprintf(" /*********************************************/ \n");
 
push @registers , ":::${reg_name}:::${reg_numoffset}:::${reg_size}:::${reg_numdim}:::${reg_dimbits}:::${reg_create}:::${reg_access}:::${reg_has_read}:::${reg_has_write}:::";
 
}
}
if($memmap_type eq "serial") { $memmap_numbase = $memmap_numbase + $addblk_numrange; }
 
 
 
}
 
 
 
 
$num_add = log($max_dim)/log(2);
print OUTFILE sprintf(" /*********************************************/ \n");
print OUTFILE sprintf(" /* Max_dim: %22s */ \n",$max_dim);
print OUTFILE sprintf(" /* num_add: %22s */ \n",$num_add);
print OUTFILE sprintf(" /* mas_has_read: %22s */ \n",$max_has_read);
print OUTFILE sprintf(" /* mas_has_write: %22s */ \n",$max_has_write);
print OUTFILE sprintf(" /* mas_has_create: %22s */ \n",$max_has_create);
print OUTFILE sprintf(" /*********************************************/ \n");
 
 
 
 
 
 
 
 
 
 
print OUTFILE " /*********************************************/ \n";
print OUTFILE "\n\nmodule `VARIANT`";
print OUTFILE uc(${memmap_name});
240,67 → 417,64
print OUTFILE "\n";
print OUTFILE "#( parameter UNSELECTED = {${addblk_width}{1'b1}},\n";
print OUTFILE " parameter UNMAPPED = {${addblk_width}{1'b0}}";
#/*********************************************************************************/
#/* */
#/* Add parameters for write reset states and fillers for reading short registers */
#/* */
#/* */
#/*********************************************************************************/
my $has_read = 0;
my $has_write = 0;
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
 
 
 
 
 
 
 
foreach $line (@registers)
{
 
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
if( $t_has_write eq "1" and $t_create eq "1")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_RST = ${t_size}'b0";
}
 
$pad = $byte_size -( int(${t_size}) % $byte_size ) ;
if ( $pad == $byte_size ) { $pad = 0;}
if( $register_access eq "read-write" or $register_access eq "write-only")
{
$has_write = 1;
print OUTFILE ",\n parameter ";
print OUTFILE uc(${register_name});
print OUTFILE "_RST = ${register_size}'b0";
}
if( $register_access eq "read-write" or $register_access eq "read-only")
{
$has_read = 1;
}
if($pad)
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_PAD = ${pad}'b0";
}
my $pad = $byte_size -( int(${register_size}) % $byte_size ) ;
if ( $pad == $byte_size ) { $pad = 0;}
if($pad)
{
if( $register_access eq "read-write" or $register_access eq "read-only")
{
print OUTFILE ",\n parameter ";
print OUTFILE uc(${register_name});
print OUTFILE "_PAD = ${pad}'b0";
}
print "ZZZZZZA :::${t_name}:::${t_numoffset}:::${t_size}:::${t_numdim}:::${t_dimbits}:::${t_create}:::${t_access}:::${t_has_read}:::${t_has_write}::: \n";
}
}
}
}
print OUTFILE ")\n ";
 
 
 
print OUTFILE ")\n ";
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print io ports */
313,155 → 487,130
print OUTFILE " input wire reset,\n";
print OUTFILE " input wire enable,\n";
print OUTFILE " input wire cs,\n";
if($has_write){ print OUTFILE " input wire wr,\n";}
if($has_read) {print OUTFILE " input wire rd,\n";}
if($has_write) {print OUTFILE " input wire [${addblk_width}-1:0] wdata,\n";}
if($has_read) {print OUTFILE " output reg [${addblk_width}-1:0] rdata,\n";}
if($max_has_write){ print OUTFILE " input wire wr,\n";}
if($max_has_read) {print OUTFILE " input wire rd,\n";}
if($max_has_write) {print OUTFILE " input wire [${addblk_width}-1:0] wdata,\n";}
if($max_has_read) {print OUTFILE " output reg [${addblk_width}-1:0] rdata,\n";}
print OUTFILE " input wire [${sys_byte_lanes}-1:0] byte_lanes,\n";
print OUTFILE " input wire [${addblk_range}-1:${adr_base}] addr";
print OUTFILE " input wire [${addblk_numaddbits}-1:${adr_base}] addr";
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
if($max_dim gt "1" )
{
print OUTFILE " ,\n output wire [${num_add}-1:0] addr_out";
}
 
$register_size = int($register_size);
if($register_size == 1)
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg $register_name ";
print OUTFILE ",\n input wire next_${register_name} ";
print OUTFILE ",\n input wire ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg $register_name ";
print OUTFILE ",\n input wire next_${register_name} ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
}
if( $register_access eq "read-only")
{
print OUTFILE ",\n input wire ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
}
}
else
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg [${register_size}-1:0] $register_name ";
print OUTFILE ",\n input wire [${register_size}-1:0] next_${register_name} ";
print OUTFILE ",\n input wire [${register_size}-1:0] ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
 
}
if( $register_access eq "write-only")
 
 
 
 
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
print OUTFILE ",\n output reg [${register_size}-1:0] $register_name ";
print OUTFILE ",\n input wire [${register_size}-1:0] next_${register_name} ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
print OUTFILE ",\n output wire ${t_name}_cs ";
print OUTFILE ",\n output reg ${t_name}_dec ";
 
}
if($t_size == 1)
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n input wire ${t_name}_rdata ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg [${register_size}-1:0] ${register_name}_wdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
print OUTFILE ",\n output reg ${register_name}_wr_0 ";
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
if( $t_create eq "1")
{
print OUTFILE ",\n output reg $t_name ";
print OUTFILE ",\n input wire next_${t_name} ";
}
else
{
print OUTFILE ",\n output reg ${t_name}_wdata ";
}
}
}
else
{
if( $t_has_read eq "1")
{
print OUTFILE ",\n input wire [${t_size}-1:0] ${t_name}_rdata ";
}
if( $register_access eq "read-only")
{
print OUTFILE ",\n input wire [${register_size}-1:0] ${register_name}_rdata ";
print OUTFILE ",\n output reg ${register_name}_dec ";
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${t_name}_wr_0 ";
if( $t_create eq "1")
{
print OUTFILE ",\n output reg [${t_size}-1:0] $t_name ";
print OUTFILE ",\n input wire [${t_size}-1:0] next_${t_name} ";
}
else
{
print OUTFILE ",\n output reg [${t_size}-1:0] ${t_name}_wdata ";
}
}
}
}
 
if($register_size > ${byte_size})
{
if( $register_access eq "read-write")
if( $t_has_write eq "1")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
if($t_size > ${byte_size}) { print OUTFILE ",\n output reg ${t_name}_wr_1 "; }
if($t_size > (${byte_size}*2)) { print OUTFILE ",\n output reg ${t_name}_wr_2 "; }
if($t_size > (${byte_size}*3)) { print OUTFILE ",\n output reg ${t_name}_wr_3 "; }
}
}
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
}
print OUTFILE "\n);\n\n\n";
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_1 ";
}
}
 
 
if($register_size > (${byte_size}*2))
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_2 ";
}
}
 
 
 
if($register_size > (${byte_size}*3))
{
if( $register_access eq "read-write")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
if( $register_access eq "write-only")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
if( $register_access eq "write-strobe")
{
print OUTFILE ",\n output reg ${register_name}_wr_3 ";
}
}
 
 
 
}
print OUTFILE "\n);\n\n\n";
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print parameters for register addresses */
469,71 → 618,74
#/* */
#/**********************************************************************/
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
print OUTFILE "parameter ";
print OUTFILE uc(${t_name});
print OUTFILE " = ${addblk_numaddbits}'d${t_numoffset};\n";
my $register_addressOffset_end = $t_numoffset + $t_numdim;
print OUTFILE "parameter ";
print OUTFILE uc(${t_name});
print OUTFILE "_END = ${addblk_numaddbits}'d${register_addressOffset_end};\n";
 
}
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
print OUTFILE "parameter ";
print OUTFILE uc(${register_name});
print OUTFILE " = ${addblk_range}'d${register_addressOffset};\n";
}
print OUTFILE "\n\n";
print OUTFILE " reg [${addblk_width}-1:0] rdata_i;\n";
}
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* write data register creation */
#/* */
#/* */
#/**********************************************************************/
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
 
print OUTFILE "\n\n";
print OUTFILE " reg [${addblk_width}-1:0] rdata_i;\n";
if($register_size eq 1)
{
if( $register_access eq "read-write")
{
print OUTFILE "reg ${register_name}_wdata;\n";
}
if( $register_access eq "write-only")
{
print OUTFILE "reg ${register_name}_wdata;\n";
}
 
}
else
{
if( $register_access eq "read-write")
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
print OUTFILE "reg [${register_size}-1:0] ${register_name}_wdata;\n";
}
if( $register_access eq "write-only")
{
print OUTFILE "reg [${register_size}-1:0] ${register_name}_wdata;\n ";
}
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
if(( $t_has_write eq "1") and ( $t_create eq "1"))
{
if($t_size eq 1){ print OUTFILE "reg ${t_name}_wdata;\n";}
else { print OUTFILE "reg [${t_size}-1:0] ${t_name}_wdata;\n";}
}
}
}
}
 
 
 
551,6 → 703,7
 
 
 
 
#/**********************************************************************/
#/* */
605,21 → 758,29
print OUTFILE "/*QQQ Reg_Name Reg_Access sys_byte_lanes reg_byte_lanes reg_size reg_add ar_base log_byte_lane phy_byte_lane reg_lane pad_size padding bigend */ \n";
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
627,22 → 788,23
$pad_size = ${byte_size};
}
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
my $strng = sprintf( "/*QQQ %16s %12s %11s %6s %6s %6s %6s %6s %6s %6s %2s %6s %6s */ \n",${t_name},${t_access},${sys_byte_lanes},${reg_byte_lanes},${t_size},${t_numoffset},${adr_base},${log_byte_lane},${phy_byte_lane},${reg_byte_lane},${pad_size},${padding},${opt_bigendian});
my $strng = sprintf( "/*QQQ %16s %12s %11s %6s %6s %6s %6s %6s %6s %6s %2s %6s %6s */ \n",${register_name},${register_access},${sys_byte_lanes},${reg_byte_lanes},${register_size},${register_addressOffset},${adr_base},${log_byte_lane},${phy_byte_lane},${reg_byte_lane},${pad_size},${padding},${opt_bigendian});
print OUTFILE $strng;
 
}
 
 
}
}
print OUTFILE "\n\n\n";
 
#/**********************************************************************/
#/* */
#/* Read Data Muxing */
651,7 → 813,7
#/**********************************************************************/
if($has_read)
if($max_has_read == "1" and $max_has_create == "1")
{
print OUTFILE "always@(*)\n";
print OUTFILE " if(rd && cs)\n";
664,40 → 826,54
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
print OUTFILE "always@(*)\n";
print OUTFILE " case(addr[$addblk_range-1:${adr_base}])\n";
print OUTFILE " case(addr[$addblk_numaddbits-1:${adr_base}])\n";
 
 
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
my $REG_NAME = uc($t_name);
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
my $REG_NAME = uc($register_name);
if(( $register_access eq "read-write") or ( $register_access eq "read-only"))
if( $t_has_read eq "1" )
{
if(( $sys_byte_lanes eq "1" ) and ( $reg_byte_lanes eq "1") )
704,15 → 880,15
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding)
{
if($pad_size eq "1")
{ print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n";}
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else
{ print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n";}
{ print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n";}
}
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
 
 
722,14 → 898,14
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
}
}
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
737,19 → 913,19
if($opt_bigendian)
{
print OUTFILE "{";
print OUTFILE "${REG_NAME}[$addblk_range-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:1],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
}
}
757,26 → 933,26
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${byte_size}'h0 ;//QQQQ\n";
}
}
785,27 → 961,27
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*3)] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*2)-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*3)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b00}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b01}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*2)-1:${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b10}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],2'b11}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*3)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*4)-1:(${byte_size}*3)] ;//QQQQ\n";}
}
}
815,21 → 991,21
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n"; }
}
else
{
 
 
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
 
unless ($log_byte_lane){
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[(${byte_size}*3)-1:(${byte_size}*2)] ;//QQQQ\n";}
}
 
 
841,35 → 1017,35
{
if($opt_bigendian)
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$phy_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n"; }
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$phy_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n"; }
}
else
{
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_range-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n";}
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b0}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "{${REG_NAME}[$addblk_numaddbits-1:2],1'b1}: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] ;//QQQQ\n";}
}
}
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n"; }
}
 
 
877,8 → 1053,8
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[${byte_size}-1:0] ;//QQQQ\n";
}
 
 
885,9 → 1061,9
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${register_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:${byte_size}] };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata[$(byte_size}-1:${byte_size}] ;//QQQQ\n"; }
}
 
 
896,29 → 1072,167
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${register_name}_rdata[${register_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata[${t_size}-1:$phy_byte_lane*${byte_size}] };//QQQQ\n"; }
else { print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";}
}
else
{
print OUTFILE "${REG_NAME}[$addblk_range-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${register_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
print OUTFILE "${REG_NAME}[$addblk_numaddbits-1:${adr_base}]: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = ";
print OUTFILE " ${t_name}_rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] ;//QQQQ\n";
}
}
 
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " default: rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
print OUTFILE " endcase\n\n";
 
 
 
 
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Read Data Muxing */
#/* */
#/* */
#/**********************************************************************/
if($max_has_read == "1" and $max_has_create == "0" )
{
print OUTFILE "always@(*)\n";
print OUTFILE " if(rd && cs)\n";
print OUTFILE " begin\n";
print OUTFILE " if(byte_lanes[ $phy_byte_lane ])\n";
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = rdata_i[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; \n";
print OUTFILE " else\n";
print OUTFILE " rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNMAPPED;\n";
print OUTFILE " end\n";
print OUTFILE " else rdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = UNSELECTED;\n\n\n";
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
print OUTFILE " rdata_i = UNMAPPED;\n";
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
 
my $REG_NAME = uc($t_name);
 
 
if( $t_has_read eq "1" )
{
print OUTFILE "if( ${t_name}_cs ) rdata_i = ";
if($padding) { print OUTFILE "{${REG_NAME}_PAD , ${t_name}_rdata };//QQQQ\n";}
else { print OUTFILE " ${t_name}_rdata ;//QQQQ\n";}
}
 
 
 
 
print OUTFILE "\n";
 
 
 
}
 
 
}
 
print OUTFILE " end\n\n";
 
 
}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Write Data Selection */
#/* */
#/* */
926,47 → 1240,52
if($has_write)
if($max_has_write)
{
 
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
 
my $REG_NAME = uc($t_name);
 
 
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
my $REG_NAME = uc($register_name);
if(( $register_access eq "read-write") or ( $register_access eq "write-only") or ( $register_access eq "write-strobe") )
if( $t_has_write eq "1" )
{
if ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "1"))
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0];// 1\n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0];// 1\n";
}
 
elsif( $sys_byte_lanes eq $reg_byte_lanes )
973,13 → 1292,13
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}];// 2\n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}];// 2\n";
 
}
else
{
 
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 3 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 3 \n";
}
}
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
986,18 → 1305,18
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:0]; // 4 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:0]; // 4 \n";
 
 
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 5 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 5 \n";
 
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 6 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 6 \n";
 
 
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // ${byte_size}-1 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // ${byte_size}-1 \n";
 
}
}
1006,15 → 1325,15
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 8 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 9 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 10 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 8 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 9 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 10 \n";
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 11 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 12 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 13 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 11 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 12 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 13 \n";
}
}
1022,18 → 1341,18
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 14 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 15 \n";
print OUTFILE "${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 16 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 17 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 14 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 15 \n";
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 16 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 17 \n";
 
}
else
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 18 \n";
print OUTFILE "${register_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 19 \n";
print OUTFILE "${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 20 \n";
print OUTFILE "${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 21 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 18 \n";
print OUTFILE "${t_name}_wdata[$(byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 19 \n";
print OUTFILE "${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 20 \n";
print OUTFILE "${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:0]; // 21 \n";
}
}
1041,14 → 1360,14
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 22 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 22 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
if($log_byte_lane == 0)
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // \n";
}
}
}
1057,21 → 1376,21
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 24 \n";
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1+$(byte_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 25 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 24 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1+$(byte_size}-1:$phy_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 25 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 26 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1:$log_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 26 \n";
if($log_byte_lane)
{
 
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${pad_size}+$(byte_size}-1:$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
}
else
{
 
print OUTFILE "${register_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
print OUTFILE "${t_name}_wdata[$log_byte_lane*${byte_size}+${byte_size}-1+(${byte_size}*2):$log_byte_lane*${byte_size}+(${byte_size}*2)] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 27 \n";
}
}
1079,22 → 1398,22
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 28 \n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 28 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 29 \n";
print OUTFILE "${t_name}_wdata = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 29 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 30 \n";
print OUTFILE "${t_name}_wdata[${byte_size}-1:0] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 30 \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // \n";
print OUTFILE "${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // \n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($phy_byte_lane) ne "3" )
1101,16 → 1420,18
{
if( $reg_byte_lanes - 1 eq $phy_byte_lane )
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 32 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${pad_size}-1:$phy_byte_lane*${byte_size}]; // 32 \n";
}
else
{
print OUTFILE "${register_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 33 \n";
print OUTFILE "${t_name}_wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}] = wdata[$phy_byte_lane*${byte_size}+${byte_size}-1:$phy_byte_lane*${byte_size}]; // 33 \n";
}
}
 
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " end\n\n";
1119,13 → 1440,6
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Write strobe Creation */
1138,41 → 1452,55
print OUTFILE "always@(*)\n";
print OUTFILE " begin\n";
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
my $REG_NAME = uc($t_name);
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
 
 
 
my $REG_NAME = uc($register_name);
 
if(( $register_access eq "read-write") or ( $register_access eq "write-only") or ( $register_access eq "write-strobe") )
if( $t_has_write eq "1" )
{
if ( $sys_byte_lanes eq $reg_byte_lanes )
{
print OUTFILE "${register_name}_wr_${phy_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${phy_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
 
elsif ( ($sys_byte_lanes eq "1") and ( $reg_byte_lanes eq "2"))
1179,14 → 1507,14
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b1} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
 
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:1],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:1],1'b1} ); // \n";
}
}
1194,15 → 1522,15
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
}
}
1210,17 → 1538,17
{
if($opt_bigendian)
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b00} ); // \n";
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b01} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b10} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_range-1:0]== {${REG_NAME}[$addblk_range-1:2],2'b11} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b00} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b01} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b10} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ 0 ] && ( addr[$addblk_numaddbits-1:0]== {${REG_NAME}[$addblk_numaddbits-1:2],2'b11} ); // \n";
 
}
}
1229,12 → 1557,12
{
if ($log_byte_lane == 0 )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
elsif ($log_byte_lane == 1 )
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
}
}
 
1244,13 → 1572,13
{
if ($log_byte_lane == 0 )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_2 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
elsif ($log_byte_lane == 1 )
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b0} ); // \n";
print OUTFILE "${register_name}_wr_3 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:1]== {${REG_NAME}[$addblk_range-1:2],1'b1} ); // \n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b0} ); // \n";
print OUTFILE "${t_name}_wr_3 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:1]== {${REG_NAME}[$addblk_numaddbits-1:2],1'b1} ); // \n";
}
}
 
1261,22 → 1589,22
 
elsif(( $sys_byte_lanes eq "2") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "1") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane eq $log_byte_lane) )
{
print OUTFILE "${register_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_0 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "2") and ($reg_byte_lane == ${log_byte_lane}-1 ))
{
print OUTFILE "${register_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );\n";
print OUTFILE "${t_name}_wr_1 = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );\n";
}
 
elsif(( $sys_byte_lanes eq "4") and ( $reg_byte_lanes eq "3") and ($log_byte_lane ne "3") )
1283,11 → 1611,11
{
if( ${reg_byte_lanes}-1 == $log_byte_lane )
{
print OUTFILE "${register_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
else
{
print OUTFILE "${register_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] ); // \n";
print OUTFILE "${t_name}_wr_${log_byte_lane} = cs && wr && enable && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] ); // \n";
}
}
 
1294,15 → 1622,17
}
}
 
}
print OUTFILE "\n\n\n";
print OUTFILE " end\n\n";
 
 
}
 
 
 
 
}
 
 
 
1315,23 → 1645,6
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
#/**********************************************************************/
1340,36 → 1653,48
#/* */
#/* */
#/**********************************************************************/
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
 
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
$reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
 
my $REG_NAME = uc($t_name);
 
 
 
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
 
 
my $REG_NAME = uc($register_name);
 
 
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
1392,111 → 1717,107
}
elsif ( ( $sys_byte_lanes == 2) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 1) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
elsif ( ( $sys_byte_lanes == 4) and ($reg_byte_lanes == 2) and ( $log_byte_lane == $reg_byte_lane) )
{
push @add_decs, " ${register_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_range-1:${adr_base}]== ${REG_NAME}[$addblk_range-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
push @add_decs, " ${t_name}_dec = cs && byte_lanes[ $phy_byte_lane ] && ( addr[$addblk_numaddbits-1:${adr_base}]== ${REG_NAME}[$addblk_numaddbits-1:${adr_base}] );//. $sys_byte_lanes. $reg_byte_lanes. 5\n"
}
}
}
 
}
 
}
 
 
 
 
 
}
 
 
 
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
 
 
 
 
 
 
 
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
 
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
$padding = 0;
$pad_size = ${byte_size};
}
my $REG_NAME = uc($t_name);
 
$reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + int($t_size))/ $byte_size;
 
 
my $REG_NAME = uc($register_name);
 
 
if(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 1))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:0]== ${REG_NAME}[$addblk_range-1:0] );// 1\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:0]== ${REG_NAME}[$addblk_numaddbits-1:0] );// 1\n"
}
 
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 2))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:1]== ${REG_NAME}[$addblk_range-1:1] );// 2\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 2\n"
}
 
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 3\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 3\n"
}
elsif(( $sys_byte_lanes == 1) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 2))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:1]== ${REG_NAME}[$addblk_range-1:1] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:1]== ${REG_NAME}[$addblk_numaddbits-1:1] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 2) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
 
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 3))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
elsif(( $sys_byte_lanes == 4) and ($reg_byte_lanes == 4))
{
push @add_decs, " ${register_name}_dec = cs && ( addr[$addblk_range-1:2]== ${REG_NAME}[$addblk_range-1:2] );// 4\n"
push @add_decs, " ${t_name}_dec = cs && ( addr[$addblk_numaddbits-1:2]== ${REG_NAME}[$addblk_numaddbits-1:2] );// 4\n"
}
 
 
1504,8 → 1825,15
 
}
 
}
 
print OUTFILE "\n\n always@(*)\n begin\n";
foreach my $add_line (@add_decs)
{
print OUTFILE "${add_line}";
}
 
print OUTFILE "\n end\n\n";
 
 
 
1515,38 → 1843,81
 
 
 
print OUTFILE "\n\n always@(*)\n begin\n";
foreach my $add_line (@add_decs)
{
print OUTFILE "${add_line}";
}
 
print OUTFILE "\n end\n\n";
 
 
#/**********************************************************************/
 
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Create Chip Selects */
#/* */
#/* */
#/**********************************************************************/
 
print OUTFILE "\n /* verilator lint_off UNSIGNED */ \n";
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
my $REG_NAME = uc($t_name);
print OUTFILE "assign ${t_name}_cs = cs && ( addr >= ${REG_NAME} ) && ( addr < ${REG_NAME}_END );\n";
}
}
 
 
print OUTFILE "\n /* verilator lint_on UNSIGNED */ \n";
 
 
 
 
 
 
#/**********************************************************************/
#/* */
#/* Create Registers */
#/* */
#/* */
#/**********************************************************************/
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my $register_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my $register_addressOffset = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my $register_size = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my $register_access = $comp_view->findnodes('../spirit:access/text()')->to_literal;
 
foreach $line (@registers)
{
$_ = $line;
if(/:::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::(\S+):::/)
{
my $t_name = $1;
my $t_numoffset = $2;
my $t_size = $3;
my $t_numdim = $4;
my $t_dimbits = $5;
my $t_create = $6;
my $t_access = $7;
my $t_has_read = $8;
my $t_has_write = $9;
 
 
my $reg_byte_lane = $t_numoffset % $sys_byte_lanes ;
my $reg_byte_lanes = $t_size / ${byte_size} ;
my $pad_size = $t_size % $byte_size ;
 
 
$register_addressOffset = hex($register_addressOffset);
$reg_byte_lane = int(${register_addressOffset}) % $sys_byte_lanes ;
my $reg_byte_lanes = int(${register_size}) / ${byte_size} ;
my $pad_size = int(${register_size}) % $byte_size ;
if($pad_size) {$padding = $byte_size - $pad_size;}
else
{
1554,14 → 1925,13
$pad_size = ${byte_size};
}
my $reg_byte_lanes = ($padding + int($register_size))/ $byte_size;
$reg_byte_lanes = ($padding + $t_size)/ $byte_size;
 
 
if(( $register_access eq "read-write") or ( $register_access eq "write-only") )
if(( $t_has_write eq "1") and ( $t_create eq "1") )
{
print OUTFILE " always@(posedge clk)\n if(reset) $register_name <= ";
print OUTFILE uc($register_name);
print OUTFILE " always@(posedge clk)\n if(reset) $t_name <= ";
print OUTFILE uc($t_name);
print OUTFILE "_RST;\n else\n begin\n";
 
if($reg_byte_lanes == 1)
1568,42 → 1938,42
{
if($pad_size ==1)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name} <= ${register_name}_wdata ;\n";
print OUTFILE " else ${register_name} <= next_${register_name};\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name} <= ${t_name}_wdata ;\n";
print OUTFILE " else ${t_name} <= next_${t_name};\n\n";
}
else
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${pad_size}-1:0] <= ${register_name}_wdata[${pad_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${pad_size}-1:0] <= next_${register_name}[${pad_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${pad_size}-1:0] <= ${t_name}_wdata[${pad_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${pad_size}-1:0] <= next_${t_name}[${pad_size}-1:0];\n\n";
}
 
}
elsif($reg_byte_lanes == 2)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[${pad_size}+${byte_size}-1:${byte_size}] <= ${register_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+${byte_size}-1:${byte_size}] <= next_${register_name}[${pad_size}+${byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= ${t_name}_wdata[${pad_size}+${byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+${byte_size}-1:${byte_size}] <= next_${t_name}[${pad_size}+${byte_size}-1:${byte_size}];\n\n";
}
elsif($reg_byte_lanes == 3)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[$(byte_size}-1:${byte_size}] <= ${register_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[$(byte_size}-1:${byte_size}] <= next_${register_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${register_name}_wr_2) ${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= ${register_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= next_${register_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_2) ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= ${t_name}_wdata[${pad_size}+$(byte_size}-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)] <= next_${t_name}[${pad_size}+$(byte_size}-1:(${byte_size}*2)];\n\n";
}
elsif($reg_byte_lanes == 4)
{
print OUTFILE " if(${register_name}_wr_0) ${register_name}[${byte_size}-1:0] <= ${register_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${register_name}[${byte_size}-1:0] <= next_${register_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${register_name}_wr_1) ${register_name}[$(byte_size}-1:${byte_size}] <= ${register_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${register_name}[$(byte_size}-1:${byte_size}] <= next_${register_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${register_name}_wr_2) ${register_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= ${register_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${register_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= next_${register_name}[(${byte_size}*3)-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${register_name}_wr_3) ${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= ${register_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] ;\n";
print OUTFILE " else ${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= next_${register_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)];\n\n";
print OUTFILE " if(${t_name}_wr_0) ${t_name}[${byte_size}-1:0] <= ${t_name}_wdata[${byte_size}-1:0] ;\n";
print OUTFILE " else ${t_name}[${byte_size}-1:0] <= next_${t_name}[${byte_size}-1:0];\n\n";
print OUTFILE " if(${t_name}_wr_1) ${t_name}[$(byte_size}-1:${byte_size}] <= ${t_name}_wdata[$(byte_size}-1:${byte_size}] ;\n";
print OUTFILE " else ${t_name}[$(byte_size}-1:${byte_size}] <= next_${t_name}[$(byte_size}-1:${byte_size}];\n\n";
print OUTFILE " if(${t_name}_wr_2) ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= ${t_name}_wdata[(${byte_size}*3)-1:(${byte_size}*2)] ;\n";
print OUTFILE " else ${t_name}[(${byte_size}*3)-1:(${byte_size}*2)] <= next_${t_name}[(${byte_size}*3)-1:(${byte_size}*2)];\n\n";
print OUTFILE " if(${t_name}_wr_3) ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= ${t_name}_wdata[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] ;\n";
print OUTFILE " else ${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)] <= next_${t_name}[${pad_size}+(${byte_size}*3)-1:(${byte_size}*3)];\n\n";
}
 
print OUTFILE "\n end\n\n";
1618,6 → 1988,7
 
}
 
}
 
 
 
1625,12 → 1996,29
 
 
 
 
 
 
 
 
 
 
 
 
 
 
print OUTFILE "\nendmodule \n";
 
 
 
 
 
 
 
close OUTFILE ;
close OUTFILE ;
}
1
1
/sys/build_verilog
68,6 → 68,8
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"dest_dir=s" => \$dest_dir,
"destination=s" => \$destination,
"fragment","no_port"
) || die "(use '$program_name -h' for help)";
 
77,7 → 79,7
## Help option
##############################################################################
if ( $opt_h or $opt_help )
{ print "\n build_verilog -view {sim/syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component component_name -comp_xml_sep /rtl/xml/ -variant variant_name -fragment -no_port file_destination ../verilog/";
{ print "\n build_verilog -view {sim/syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component component_name -comp_xml_sep /rtl/xml/ -variant variant_name -fragment -no_port -destination destination -dest_dir ../verilog/";
print "\n";
exit 1;
}
93,9 → 95,8
$home = cwd();
my $parser = XML::LibXML->new();
my $rtl_xml_sep = "/rtl/xml/";
my $destination = $ARGV[0];
my $dest_dir = $ARGV[1];
 
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
/sys/build_header
0,0 → 1,458
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010-2012> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
 
 
############################################################################
# General PERL config
############################################################################
use Getopt::Long;
use English;
use File::Basename;
use Cwd;
use XML::LibXML;
 
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
 
 
############################################################################
### Process the options
############################################################################
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h",
"view=s" => \$view,
"prefix=s" => \$prefix,
"project=s" => \$project,
"lib_comp_sep=s" => \$lib_comp_sep,
"component=s" => \$component,
"comp_xml_sep=s" => \$comp_xml_sep,
"variant=s" => \$variant,
"dest_dir=s" => \$dest_dir,
"inst_path=s" => \$inst_path
) || die "(use '$program_name -h' for help)";
 
 
##############################################################################
## Help option
##############################################################################
if ( $opt_h )
{
print "\n build_header -view {sim|syn} -prefix /work/ -project project_name -lib_comp_sep /ip/ -component comp_name -comp_xml_sep /rtl/xml/ -variant variant_name -inst_path a.b.c -dest_dir dest_dir \n";
exit 1;
}
 
 
##############################################################################
##
##############################################################################
 
 
 
$home = cwd();
 
 
my $vendor ="opencores.org";
my $rtl_xml_sep = "/rtl/xml/";
 
my $parser = XML::LibXML->new();
 
 
#############################################################################
##
##
#############################################################################
 
print " Building $view Headers for $prefix $project $component $variant in $dest_dir\n" ;
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}";
mkdir $path,0755 unless( -e $path );
 
 
 
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
#/* */
#/* */
#/**********************************************************************/
my $outfile ="${home}${prefix}${project}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}/${variant}_${inst_path}.h";
open OUTFILE,">$outfile" or die "unable to open $outfile";
print OUTFILE " /*********************************************/ \n";
print OUTFILE sprintf(" /* view: %24s */ \n",$view);
print OUTFILE sprintf(" /* project: %24s */ \n",$project);
print OUTFILE sprintf(" /* component: %24s */ \n",$component);
print OUTFILE sprintf(" /* variant: %24s */ \n",$variant);
print OUTFILE sprintf(" /* inst_path: %24s */ \n",$inst_path);
print OUTFILE " /*********************************************/ \n";
 
 
 
my $inst_name;
my $remainder;
 
$_ = $inst_path;
if(/(\w+)\.(\S+)/)
{
$inst_name = $1;
$remainder = $2;
print OUTFILE " /* INST = $inst_name then $remainder */ \n";
}
else
{
print OUTFILE " /* ERROR no inst_path */ \n";
}
 
 
 
 
my $spirit_component_file = $parser->parse_file("${home}/projects/${vendor}/${project}${lib_comp_sep}${component}${comp_xml_sep}${variant}.xml");
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view'))
{
my($view_name) = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
if($view_name eq "Hierarchical")
{
my($hier_ref_vendor) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:vendor')->to_literal ;
my($hier_ref_library) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:library')->to_literal ;
my($hier_ref_component) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:name')->to_literal ;
my($hier_ref_version) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:version')->to_literal ;
my $spirit_designCfg_file
= $parser->parse_file("${home}/projects/${hier_ref_vendor}/${hier_ref_library}${lib_comp_sep}${hier_ref_component}/ip-xact/${hier_ref_component}_${hier_ref_version}.xml");
 
 
foreach my $design_ref_view ($spirit_designCfg_file->findnodes('//spirit:designConfiguration'))
{
my($hier_xref_vendor) = $design_ref_view->findnodes('./spirit:designRef/@spirit:vendor')->to_literal ;
my($hier_xref_library) = $design_ref_view->findnodes('./spirit:designRef/@spirit:library')->to_literal ;
my($hier_xref_component) = $design_ref_view->findnodes('./spirit:designRef/@spirit:name')->to_literal ;
my($hier_xref_version) = $design_ref_view->findnodes('./spirit:designRef/@spirit:version')->to_literal ;
 
 
 
 
 
my $spirit_design_file = $parser->parse_file("${home}/projects/${hier_xref_vendor}/${hier_xref_library}${lib_comp_sep}${hier_xref_component}${comp_xml_sep}${hier_xref_component}_${hier_xref_version}.xml");
 
 
 
 
 
foreach my $x_name ($spirit_design_file->findnodes("//spirit:design/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
#/**********************************************************************/
#/* */
#/* Lookup VLNV for each instantiated component */
#/* */
#/**********************************************************************/
 
my($instance_name) = $x_name ->findnodes('./text()')->to_literal ;
my($vendor_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:vendor')->to_literal ;
my($library_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:library')->to_literal ;
my($component_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:name')->to_literal ;
my($version_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:version')->to_literal ;
 
my $variant = "${component_name}_${version_name}";
 
if($inst_name eq $instance_name){
 
print OUTFILE " /* $instance_name $vendor_name $library_name $component_name $version_name \n";
 
$_ = $remainder;
parse_hier($vendor_name , $library_name , $component_name, $variant, $remainder, $inst_name);
}
 
}
 
}
 
}
 
}
 
 
 
 
 
close OUTFILE ;
 
 
 
 
 
 
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
sub parse_hier
{
my @params = @_;
my $top_name = pop(@params);
my $inst_path = pop(@params);
my $variant = pop(@params);
my $component = pop(@params);
my $project = pop(@params);
my $vendor = pop(@params);
 
$home = cwd();
 
 
 
 
my $spirit_component_file = $parser->parse_file("${home}/projects/${vendor}/${project}${lib_comp_sep}${component}${rtl_xml_sep}${variant}.xml");
 
 
my $inst_name;
my $remainder;
 
$_ = $inst_path;
if(/(\w+)\.(\S+)/)
{
$inst_name = $1;
$remainder = $2;
print OUTFILE " /* INST = $inst_name then $remainder */ \n";
}
else
{
print_map($spirit_component_file, $top_name);
}
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view'))
{
my($view_name) = $comp_view->findnodes('./spirit:name/text()')->to_literal ;
if($view_name eq "Hierarchical")
{
my($hier_ref_vendor) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:vendor')->to_literal ;
my($hier_ref_library) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:library')->to_literal ;
my($hier_ref_component) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:name')->to_literal ;
my($hier_ref_version) = $comp_view->findnodes('./spirit:hierarchyRef/@spirit:version')->to_literal ;
my $spirit_designCfg_file
= $parser->parse_file("${home}/projects/${hier_ref_vendor}/${hier_ref_library}${lib_comp_sep}${hier_ref_component}/ip-xact/${hier_ref_component}_${hier_ref_version}.xml");
 
 
foreach my $design_ref_view ($spirit_designCfg_file->findnodes('//spirit:designConfiguration'))
{
my($hier_xref_vendor) = $design_ref_view->findnodes('./spirit:designRef/@spirit:vendor')->to_literal ;
my($hier_xref_library) = $design_ref_view->findnodes('./spirit:designRef/@spirit:library')->to_literal ;
my($hier_xref_component) = $design_ref_view->findnodes('./spirit:designRef/@spirit:name')->to_literal ;
my($hier_xref_version) = $design_ref_view->findnodes('./spirit:designRef/@spirit:version')->to_literal ;
 
my $spirit_design_file = $parser->parse_file("${home}/projects/${hier_xref_vendor}/${hier_xref_library}${lib_comp_sep}${hier_xref_component}${rtl_xml_sep}${hier_xref_component}_${hier_xref_version}.xml");
 
 
foreach my $x_name ($spirit_design_file->findnodes("//spirit:design/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
#/**********************************************************************/
#/* */
#/* Lookup VLNV for each instantiated component */
#/* */
#/**********************************************************************/
 
my($instance_name) = $x_name ->findnodes('./text()')->to_literal ;
my($vendor_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:vendor')->to_literal ;
my($library_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:library')->to_literal ;
my($component_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:name')->to_literal ;
my($version_name) = $x_name ->findnodes('../spirit:componentRef/@spirit:version')->to_literal ;
 
my $variant = "${component_name}_${version_name}";
 
if($inst_name eq $instance_name){
 
print OUTFILE " /* $instance_name $vendor_name $library_name $component_name $version_name \n";
my $spirit_component_file = $parser->parse_file("${home}${prefix}${library_name}${lib_comp_sep}${component_name}${rtl_xml_sep}${variant}.xml");
 
 
$_ = $remainder;
if(/(\w+)\.(\S+)/)
{
parse_hier($vendor_name , $library_name , $component_name, $variant, $remainder, $top_name);
}
else
{
print OUTFILE " /* mem_map $remainder */ \n";
 
 
 
print_map($spirit_component_file,$top_name);
 
 
 
 
 
 
 
 
}
}
}
}
}
}
}
 
 
 
sub print_map
{
my @params = @_;
my $inst_name = pop(@params);
my $spirit_component_file = pop(@params);
 
 
#/**********************************************************************/
#/* */
#/* Parse register block info from ip-xact file */
#/* */
#/* */
#/**********************************************************************/
 
my $byte_size=32;
 
foreach my $comp ($spirit_component_file->findnodes('//spirit:component'))
{
$name = $comp->findnodes('./spirit:name/text()')->to_literal ;
$version = $comp->findnodes('./spirit:version/text()')->to_literal ;
$vendor = $comp->findnodes('./spirit:vendor/text()')->to_literal ;
$library = $comp->findnodes('./spirit:library/text()')->to_literal ;
}
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:name'))
{
$memmap_name = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
$memmap_base = $comp_view->findnodes('../spirit:baseAddress/text()')->to_literal ;
 
#/**********************************************************************/
#/* */
#/* Print header, module name and start parameters */
#/* */
#/* */
#/**********************************************************************/
print OUTFILE " /***********************************************/ \n";
print OUTFILE " /* Register module */ \n";
print OUTFILE sprintf(" /* Vendor: %24s */ \n",$vendor);
print OUTFILE sprintf(" /* Library: %24s */ \n",$library);
print OUTFILE sprintf(" /* Component: %24s */ \n",$name);
print OUTFILE sprintf(" /* Version: %24s */ \n",$version);
print OUTFILE sprintf(" /* Module: %24s */ \n",$memmap_name);
print OUTFILE sprintf(" /* Base: %24s */ \n",$memmap_base);
 
$memmap_base = hex($memmap_base);
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:name'))
{
$addblk_name = $comp_view->findnodes('../spirit:name/text()')->to_literal;
$addblk_range = $comp_view->findnodes('../spirit:range/text()')->to_literal;
$addblk_width = $comp_view->findnodes('../spirit:width/text()')->to_literal;
$addblk_drange = hex($addblk_range);
print OUTFILE sprintf(" /*: %14s %8s %16x */ \n",$addblk_name,$addblk_drange,$memmap_base);
$memmap_base = $memmap_base + $addblk_drange;
 
 
 
 
foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:memoryMaps/spirit:memoryMap/spirit:bank/spirit:addressBlock/spirit:register/spirit:name'))
{
my($block_name) = $comp_view->findnodes('../../spirit:name/text()')->to_literal;
my($register_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal;
my($register_addressOffset) = $comp_view->findnodes('../spirit:addressOffset/text()')->to_literal;
my($register_size) = $comp_view->findnodes('../spirit:size/text()')->to_literal;
my($register_access) = $comp_view->findnodes('../spirit:access/text()')->to_literal;
$register_addressOffset = hex($register_addressOffset);
 
my $full_name = "${inst_name}_${register_name}";
 
 
if($block_name eq $addblk_name)
{
print OUTFILE sprintf("parameter %14s = %14s; /* %14s %14s */ \n",$full_name, $register_addressOffset, $register_size, $register_access );
}
 
 
}
 
 
 
 
 
 
 
 
 
}
}
 
 
 
}
1
sys/build_header Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sys/build_verilogLibraryFile =================================================================== --- sys/build_verilogLibraryFile (revision 115) +++ sys/build_verilogLibraryFile (revision 116) @@ -70,7 +70,8 @@ "lib_comp_sep=s" => \$lib_comp_sep, "component=s" => \$component, "comp_xml_sep=s" => \$comp_xml_sep, - "variant=s" => \$variant + "variant=s" => \$variant, + "dest_dir=s" => \$dest_dir ) || die "(use '$program_name -h' for help)"; @@ -79,7 +80,7 @@ ############################################################################## if ( $opt_h or ($opt_help) ) { - print "\n build_verilogLibraryFile -view {sim|syn} -prefix path_to_component -project project_name -component component_name -variant variant_name"; + print "\n build_verilogLibraryFile -view {sim|syn} -prefix path_to_component -project project_name -component component_name -variant variant_name -dest_dir dest_dir"; print "\n"; exit 1; } @@ -93,8 +94,8 @@ $home = cwd(); -my $dest_dir = $ARGV[0]; + ############################################################################# ## ## @@ -119,6 +120,8 @@ + + foreach my $comp_view ($spirit_component_file->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view/spirit:fileSetRef')) { my($view_fileset) = $comp_view->findnodes('./spirit:localName/text()')->to_literal ;
/sys/soc_generate
134,10 → 134,10
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "dash") {$cmd = "$cmd -${gen_param}";}
else {$cmd = "$cmd $gen_param";}
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}${prefix}${project}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name) {$cmd = "$cmd -${gen_param_name} $gen_param ";}
else {$cmd = "$cmd $gen_param";}
}
$cmd = "${cmd}\n";
my $cpu_load = 180;
148,11 → 148,13
{
if($gen_group eq $view_name )
{
# print "ZZZZZZG $cmd ";
if (system($cmd)) {}
}
}
else
{
# print "ZZZZZZH $cmd ";
if (system($cmd)) {}
}
}

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