OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/bench/verilog/TestBench
41,17 → 41,42
/* */
/**********************************************************************/
 
`include "./TB.defs"
 
`ifndef TIMESCALE
`define TIMESCALE 1ns/1ns
`endif
 
 
`ifndef TIMEFORMAT
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`endif
 
`include "./TB.defs"
 
`ifndef PERIOD
`define PERIOD 40.00000
`endif
 
`ifndef TIMEOUT
`define TIMEOUT 200000
`endif
 
 
`timescale `TIMESCALE
 
 
`include "./filelist"
`include "./liblist"
`include "./modellist"
`include "./liblist"
 
 
module TB();
 
initial
begin
`TIMEFORMAT
end
 
wire clk;
wire reset;
 
74,10 → 99,8
);
 
 
`ifndef TIMEOUT
`define TIMEOUT 200000
`endif
 
 
initial
begin
cg.next (`TIMEOUT);
/bin/Makefile.root
2,8 → 2,8
MAKE=make
 
VPP_NAME=vppreproc
VERILOG_NAME=iverilog
 
 
CUR_DIR=$(shell pwd)
VAR_DIR=$(CUR_DIR)/variants
SRC_DIR=$(CUR_DIR)/verilog
19,7 → 19,7
################################################################################
 
prepare_dirs:
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi
 
 
build_fsm: prepare_dirs
38,15 → 38,15
 
build_hw: build_fsm
@echo
@for VARIENT in `ls $(VAR_DIR)`; do \
@for VARIANT in `ls $(VAR_DIR)`; do \
echo "################################################################################"; \
echo; \
echo "Building: $$VARIENT ####"; echo; \
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \
echo "Building: $$VARIANT ####"; echo; \
cp $(VAR_DIR)/$$VARIANT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \
$(VPP_NAME) --noline --noblank $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \
$(VPP_NAME) --noline --noblank -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \
rm $(DEF_FILE); \
done; \
 
94,14 → 94,14
 
.PHONY run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
echo "Simulating: $$VARIENT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\
echo "Simulating: $$VARIANT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\
echo "include ../../../../../bin/Makefile.root" > Makefile;\
echo -n "test=" >> Makefile;\
echo $$VARIENT_PROG >> Makefile;\
echo $$VARIANT_PROG >> Makefile;\
make sim;\
done; \
 
109,7 → 109,7
.PHONY sim:
sim:
(\
iverilog -D VCD ../../bench/verilog/TestBench;\
$(VERILOG_NAME) -D VCD ../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../log;\
mv TestBench.vcd ../../out/${test}.vcd ;\
122,7 → 122,7
.PHONY rtlsim:
rtlsim:
(\
iverilog -D VCD ../../../bench/verilog/TestBench;\
$(VERILOG_NAME) -D VCD ../../../bench/verilog/TestBench;\
./a.out | tee ./${test}_sim.log ;\
mv *.log ../../../log;\
mv TestBench.vcd ../../../out/${test}.vcd ;\
/bin/Makefile.root.x10
38,15 → 38,15
 
build_hw: build_fsm
@echo
@for VARIENT in `ls $(VAR_DIR)`; do \
@for VARIANT in `ls $(VAR_DIR)`; do \
echo "################################################################################"; \
echo; \
echo "Building: $$VARIENT ####"; echo; \
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \
echo "Building: $$VARIANT ####"; echo; \
cp $(VAR_DIR)/$$VARIANT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \
rm $(DEF_FILE); \
done; \
 
94,14 → 94,14
 
.PHONY run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
echo "Simulating: $$VARIENT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\
echo "Simulating: $$VARIANT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\
echo "include ../../../../../bin/Makefile.root" > Makefile;\
echo -n "test=" >> Makefile;\
echo $$VARIENT_PROG >> Makefile;\
echo $$VARIANT_PROG >> Makefile;\
make sim;\
done; \
 
/bin/Makefile.root.x11
38,15 → 38,15
 
build_hw: build_fsm
@echo
@for VARIENT in `ls $(VAR_DIR)`; do \
@for VARIANT in `ls $(VAR_DIR)`; do \
echo "################################################################################"; \
echo; \
echo "Building: $$VARIENT ####"; echo; \
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \
echo "Building: $$VARIANT ####"; echo; \
cp $(VAR_DIR)/$$VARIANT/$(DEF_FILE) $(DEF_FILE); \
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \
rm $(DEF_FILE); \
done; \
 
94,14 → 94,14
 
.PHONY run_sims:
run_sims: clean_sims
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \
echo "################################################################################"; \
echo; \
echo "Simulating: $$VARIENT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\
echo "Simulating: $$VARIANT_PROG ####"; echo; \
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\
echo "include ../../../../../bin/Makefile.root" > Makefile;\
echo -n "test=" >> Makefile;\
echo $$VARIENT_PROG >> Makefile;\
echo $$VARIANT_PROG >> Makefile;\
make sim;\
done; \
 
179,14 → 179,9
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\
promgen -u 0 Board_Design_cclk ; \
mv Board_Design_cclk.mcs ../debug ;\
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\
impact -batch ../debug/impact_bat ;\
mv *.bit ../debug ;\
)
 
 
/bin/ver2gedasym
0,0 → 1,278
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* convert verilog file(s) to a geda symbol */
#/* */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
# ToDo:
# parse reg from output bus name
# parse bus and change pin type to bus
 
use Verilog::Netlist;
 
# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
"-y","verilog",
);
 
 
@files = @ARGV;
 
 
# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
 
foreach $file (@files) {
print "Parsing $file\n";
$nl->read_file (filename=>$file);
}
 
 
 
 
 
 
 
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();
 
 
foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
 
 
 
sub make_sch {
my $mod = shift;
my $mod_name = $mod->name;
 
my $in_count = 0;
my $out_count = 0;
my $in_length = 0;
my $out_length = 0;
 
my $color = 5;
my $size = 10;
 
 
open(FILE,">sym/${mod_name}.sym") or die "No sym directory";
 
foreach my $sig ($mod->ports_sorted) {
 
my $dir = $sig->direction;
my $data_type = $sig->data_type;
my $sig_name = $sig->name;
$data_type =~ s/reg //;
$data_type =~ s/reg//;
 
 
if($data_type)
{
$pin_name = "$sig_name"."$data_type";
if("in" eq $dir)
{
push(@invads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length) { $in_length = length($pin_name)};
}
if("out" eq $dir)
{
push(@outvads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
 
if("inout" eq $dir)
{
push(@inoutvads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
 
 
 
}
else
{
$pin_name = $sig_name;
if("in" eq $dir)
{
push(@inpads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length){ $in_length = length($pin_name) }
}
if("out" eq $dir)
{
push(@outpads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
 
if("inout" eq $dir)
{
push(@inoutpads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
 
};
 
 
}
 
my $max_pins;
 
if($in_count > $out_count) {$max_pins = $in_count ;} else {$max_pins = $out_count ;}
 
my $box_h = ($max_pins * 200) +300;
my $box_w = ($in_length +$out_length)*10*$size +400;
my $out_title = ($in_length +$out_length)*10*$size +600;
my $out_edg = ($in_length +$out_length)*10*$size +700;
my $out_pad = ($in_length +$out_length)*10*$size +1000;
my $title = $box_h +150;
my $ref_des = $box_h +350;
 
printf FILE ("v 20100214 1\n");
printf FILE ("B 300 0 $box_w $box_h 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1\n");
printf FILE ("T 400 $title 5 10 1 1 0 0 1 1\ndevice=%s\n", $mod->name);
printf FILE ("T 400 $ref_des 8 10 1 1 0 0 1 1\n%srefdes=U?\n");
 
printf ("%s\n", $mod->name);
 
 
my $pin_y = 200;
my $pin_seq = 1;
 
while( $name =pop(@invads))
{
printf FILE ("P 300 $pin_y 0 $pin_y 10 1 1 \n");
printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1\npinnumber=%s\n",$name);
printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1\npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
while( $name =pop(@inpads))
{
printf FILE ("P 300 $pin_y 0 $pin_y 4 0 1 \n");
printf FILE ("{\nT 400 $pin_y $color $size 1 1 0 1 1 1 \npinnumber=%s\n",$name);
printf FILE ("T 400 $pin_y $color $size 0 1 0 1 1 1 \npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
 
$pin_y = 200;
 
while( $name =pop(@outvads))
{
printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
printf FILE ("T $out_title $pin_y $color $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
while( $name =pop(@outpads))
{
printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
printf FILE ("T $out_edg $pin_y $color $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
 
 
while( $name =pop(@inoutvads))
{
printf FILE ("P $out_edg $pin_y $out_pad $pin_y 10 1 1\n");
printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1 \npinnumber=%s\n",$name);
printf FILE ("T $out_title $pin_y $color $size 0 1 0 7 1 1 \npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
while( $name =pop(@inoutpads))
{
printf FILE ("P $out_edg $pin_y $out_pad $pin_y 4 0 1\n");
printf FILE ("{\nT $out_title $pin_y $color $size 1 1 0 7 1 1\npinnumber=%s\n",$name);
printf FILE ("T $out_edg $pin_y $color $size 0 1 0 7 1 1\npinseq=%s\n}\n",$pin_seq);
$pin_seq = $pin_seq +1;
$pin_y = $pin_y +200;
}
 
 
 
 
 
 
 
 
foreach my $cell ($mod->cells_sorted) {
close(FILE);
make_sch ($cell->submod, $cell->name) if $cell->submod;
}
}
 
 
 
 
 
 
 
1;
 
 
 
 
 
 
 
/bin/ver2gedasch
0,0 → 1,252
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
#/**********************************************************************/
#/* */
#/* ------- */
#/* / SOC \ */
#/* / GEN \ */
#/* / TOOL \ */
#/* ============== */
#/* | | */
#/* |____________| */
#/* */
#/* convert verilog file(s)ports to a geda schematic */
#/* */
#/* */
#/* Author(s): */
#/* - John Eaton, jt_eaton@opencores.org */
#/* */
#/**********************************************************************/
#/* */
#/* Copyright (C) <2010> <Ouabache Design Works> */
#/* */
#/* This source file may be used and distributed without */
#/* restriction provided that this copyright statement is not */
#/* removed from the file and that any derivative work contains */
#/* the original copyright notice and the associated disclaimer. */
#/* */
#/* This source file is free software; you can redistribute it */
#/* and/or modify it under the terms of the GNU Lesser General */
#/* Public License as published by the Free Software Foundation; */
#/* either version 2.1 of the License, or (at your option) any */
#/* later version. */
#/* */
#/* This source is distributed in the hope that it will be */
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
#/* PURPOSE. See the GNU Lesser General Public License for more */
#/* details. */
#/* */
#/* You should have received a copy of the GNU Lesser General */
#/* Public License along with this source; if not, download it */
#/* from http://www.opencores.org/lgpl.shtml */
#/* */
#/**********************************************************************/
 
# ToDo:
# parse reg from output bus name
# parse bus and change pin type to bus
 
use Verilog::Netlist;
 
# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
"-y","verilog",
);
 
 
@files = @ARGV;
 
 
# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
 
foreach $file (@files) {
print "Parsing $file\n";
$nl->read_file (filename=>$file);
}
 
 
 
 
 
 
 
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();
 
 
foreach my $mod ($nl->top_modules_sorted) {make_sch ($mod);}
 
 
 
sub make_sch {
my $mod = shift;
my $mod_name = $mod->name;
 
my $in_count = 0;
my $out_count = 0;
my $in_length = 0;
my $out_length = 0;
 
my $color = 5;
my $size = 10;
 
 
open(FILE,">sch/${mod_name}.sch") or die "No sch directory";
 
foreach my $sig ($mod->ports_sorted) {
 
my $dir = $sig->direction;
my $data_type = $sig->data_type;
my $sig_name = $sig->name;
$data_type =~ s/reg //;
$data_type =~ s/reg//;
 
 
 
 
 
 
if($data_type)
{
$pin_name = "$sig_name"."$data_type";
if("in" eq $dir)
{
push(@invads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length) { $in_length = length($pin_name)};
}
if("out" eq $dir)
{
push(@outvads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
if("inout" eq $dir)
{
push(@inoutvads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length){ $in_length = length($pin_name) }
}
 
}
else
{
$pin_name = $sig_name;
if("in" eq $dir)
{
push(@inpads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length){ $in_length = length($pin_name) }
}
if("out" eq $dir)
{
push(@outpads,$pin_name);
$out_count = $out_count+1;
if( length($pin_name) > $out_length){ $out_length = length($pin_name) }
}
 
if("inout" eq $dir)
{
push(@inoutpads,$pin_name);
$in_count = $in_count+1;
if( length($pin_name) > $in_length){ $in_length = length($pin_name) }
}
 
 
};
 
 
}
 
my $max_pins;
 
if($in_count > $out_count) {$max_pins = $in_count ;} else {$max_pins = $out_count ;}
 
my $in_edg = ($in_length)*10*$size +200;
my $in_pad = ($in_length)*10*$size +200;
my $out_edg = ($in_length +$out_length)*10*$size +2500;
my $out_pad = ($in_length +$out_length)*10*$size +1500;
 
printf FILE ("v 20100214 1\n");
 
printf ("%s\n", $mod->name);
 
my $pin_y = 300;
 
while( $name =pop(@invads))
{
printf FILE ("C $in_pad $pin_y 1 0 0 ipad_2.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
while( $name =pop(@inpads))
{
printf FILE ("C $in_pad $pin_y 1 0 0 ipad_1.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
 
while( $name =pop(@inoutvads))
{
printf FILE ("C $in_pad $pin_y 1 0 0 iopad_2.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1\nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
while( $name =pop(@inoutpads))
{
printf FILE ("C $in_pad $pin_y 1 0 0 iopad_1.sym \n{\nT $in_edg $pin_y $color $size 1 1 0 6 1 1 \nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
 
 
$pin_y = 300;
 
while( $name =pop(@outvads))
{
printf FILE ("C $out_pad $pin_y 1 0 0 opad_2.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1 \nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
while( $name =pop(@outpads))
{
printf FILE ("C $out_pad $pin_y 1 0 0 opad_1.sym\n{\nT $out_edg $pin_y $color $size 1 1 0 0 1 1\nrefdes=%s\n}\n",$name);
$pin_y = $pin_y +400;
}
 
 
 
 
 
 
foreach my $cell ($mod->cells_sorted) {
close(FILE);
make_sch ($cell->submod, $cell->name) if $cell->submod;
}
}
 
 
 
 
 
 
 
1;
 
 
 
 
 
 
 
/projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse_mrisc/soc_mouse_defines.v
1,3 → 1,3
`define VARIENT soc_mouse_mrisc
`define VARIANT soc_mouse_mrisc
`define CDE cde
 
/projects/pic_micro/ip/soc_mouse/rtl/verilog/soc_mouse.v
3,7 → 3,7
 
 
module
`VARIENT
`VARIANT
 
#(
parameter ROM_FILE = "NONE",
232,6 → 232,7
.wr ( wr ),
.rd ( !wr ),
.addr ( {1'b1,portbout} ),
.waddr ( portbxout ),
.wdata ( portaout ),
.rdata ( portain ),
.ps2_data_in ( ps2_data_pad_in ),
/projects/pic_micro/ip/soc_mouse/doc/geda/drawing/filelist
0,0 → 1,8
`include "../../../rtl/gen/syn/soc_mouse.v"
`include "../../../../pic16c5x/rtl/gen/syn/pic16c5x.v"
`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v"
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
`include "../../lib/cde_sram/cde_sram.v"
`include "../../lib/cde_lifo/cde_lifo.v"
`include "../../lib/cde_sync/cde_sync_with_hysteresis.v"
/projects/pic_micro/ip/soc_mouse/doc/README.txt
0,0 → 1,120
 
This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the
PIC 16C57 from Microchip.
 
 
Legal
=====
 
PIC, Microship, etc. are Trademarks of Microchip Technology Inc.
 
I have no idea if implementing this core will or will not violate
patents, copyrights or cause any other type of lawsuits.
 
I provide this core AS IS, without any warrenties. If you decide to
build this core, you are responsible for any legal resolutions, such
as patents and copyrights, and perhaps others ....
 
This source file(s) may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
 
THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
FITNESS FOR A PARTICULAR PURPOSE.
 
 
Motivation
==========
 
After seeing the "free_risc8" on the free-ip web site, I got excited
and downloaded the core. Pretty soon I found out that it had many
many errors and omissions from the original 16C57. So I started looking
at the code. This is when I realized it was very badly designed and
could not be made run faster. So, I sat down and wrote my own PIC IP
core last night. A lot of work was spend in writing test code to ensure
that it was 100% compatible from the software point of view.
 
- A PIC compatible Microcontroller that runs a lot faster
- Separate (External to the core) Program Memory
- Options to extend the core
 
 
Compatibility
=============
 
This design should be fully software compatible to the Microchip Implementation
of the PIC 16C57, except for the following extensions:
 
- Port A is full 8 bits wide
- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded)
- Executions of instructions that modify the PC has become a lot more expensive
due to the pipeline and execution of instructions on every cycle.
Any instruction that writes to the PC (PC as destination (f), call, goto, retlw)
now takes 4 cycles to execute (instead of 2 in the origianl implementation).
The 4 'skip' instructions, remain as in the original implmentation: 1 cycle
if not skipped, 2 cycles if skipped.
- Sampling of IO ports might be off
- Timer and watchdog might be off a few cycles
 
 
Performance
===========
 
- Single cycle instruction execution, except as noted above.
- Here are results of some sample implementations:
- Xilinx Spartan 2e ((Device: xc2s50e-6): Fmax: 80Mhz, Utilization: 30%
- Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS
- Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS
- Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS
Half of the cycle time is spend in routing delays. My guess is that by placing
proper locatiuon contrains and guiding the back-end tools, a significant
speed improvement can be achieved ....
- I estimat about 25K gates with the xilinx primitives, (excluding Register
File and Programm Memory).
 
Implementing the core
=====================
 
The only file you should edit if you really want to implement this core, is the
'primitives.v' file. It contains all parts that can be optimized, depending on
the technology used. It includes memories, and arithmetic modules.
I added a primitives_xilinx,v file and xilinx_primitives.zip which contain
primitives for xilinx.
'risc_core.v' is the top level without program memory and tristate Io buffers for ports.
This is probably a good starting point if you want to instantiate the core in to a larger
design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written
with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just
replace the memory blocks ...
 
To-Do
=====
 
Things that need to be done
 
1) Write more test/compliance test vectors
- Verify that all instructions after a goto/call/retlw/write to PCL are not executed
- Verify ALU
- Timer and Watchdog tests
- Perhaps some other ereas ?
 
2) Extensions ?
- I guess this is on a "as needed" basis
- A friend suggested to add registers that can be shared by two or more cores in a MP type configuration
 
Author
======
 
I have been doing ASIC design, verification and synthesis for over 15 years.
This core is only a "mid-night hack", and should used with caution.
 
I'd also like to know if anyone will actually use this core. Please send me a
note if you will !
 
Rudolf Usselmann
russelmann@hotmail.com
 
Feel free to send me comments, suggestions and bug reports.
 
/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/TB.defs
1,9 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/test_define
1,6 → 1,5
initial
begin
`TIMEFORMAT
$display(" ");
$display(" ===================================================");
$display(" Test Start");
/projects/pic_micro/ip/mrisc/rtl/variants/mrisc/mrisc_defines.v
1,4 → 1,4
`define VARIENT mrisc
`define VARIANT mrisc
`define ALU _alu
`define PRESCLR_WDT _presclr_wdt
`define REGISTER_FILE _register_file
/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc.v
43,7 → 43,7
 
 
module
`VARIENT
`VARIANT
(
clk,
rst_in,
299,7 → 299,7
 
////////////////////////////////////////////////////////////////////////
// Synchrounous Register File
`VARIENT`REGISTER_FILE reg_file ( .clk( clk ),
`VARIANT`REGISTER_FILE reg_file ( .clk( clk ),
.rst( rst ),
.rf_rd_bnk( rf_rd_bnk ),
.rf_rd_addr( rf_rd_addr ),
604,7 → 604,7
assign src1 = src1_sel ? rf_rd_data : sfr_rd_data;
 
 
`VARIENT`ALU
`VARIANT`ALU
alu(
.s1 ( src1 ),
.s2 ( w ),
704,7 → 704,7
always @(posedge clk)
tmr0 <= #1 tmr0_next;
 
`VARIENT`PRESCLR_WDT
`VARIANT`PRESCLR_WDT
presclr_wdt(
.clk ( clk ),
.rst ( rst ),
770,7 → 770,7
assign bit_sel = src1[ instr_1[7:5] ];
 
 
`VARIENT`FIFO4
`VARIANT`FIFO4
#(.WIDTH(11))
fifo4( .clk (clk),
.push (pc_call),
/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_alu.v
41,7 → 41,7
`include "mrisc_defines.v"
 
module
`VARIENT`ALU
`VARIANT`ALU
(
input wire [7:0] s1,
input wire [7:0] s2,
/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_fifo.v
43,7 → 43,7
`include "mrisc_defines.v"
 
module
`VARIENT`FIFO4
`VARIANT`FIFO4
#(parameter WIDTH=8)
(
/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v
42,7 → 42,7
 
 
 
module `VARIENT`REGISTER_FILE( clk, rst,
module `VARIANT`REGISTER_FILE( clk, rst,
rf_rd_bnk, rf_rd_addr, rf_rd_data,
rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data);
 
/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_presclr_wdt.v
42,7 → 42,7
 
// Prescaler and Wachdog Counter
module
`VARIENT`PRESCLR_WDT
`VARIANT`PRESCLR_WDT
(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to);
 
 
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/cde_sram.sym
0,0 → 1,62
v 20100214 1
B 300 0 4500 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1850 5 10 1 1 0 0 1 1
device=cde_sram
T 400 2050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=Write_Data[WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=WR_Add[ADDR-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=RD_Add[ADDR-1:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=WR
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=RD
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=CS
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 4800 200 5100 200 10 1 1
{
T 4700 200 5 10 1 1 0 7 1 1
pinnumber=Read_Data[WIDTH-1:0]
T 4700 200 5 10 0 1 0 7 1 1
pinseq=8
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/mrisc.sym
0,0 → 1,132
v 20100214 1
B 300 0 3400 2300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2450 5 10 1 1 0 0 1 1
device=mrisc
T 400 2650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=portcin[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=portbin[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=portain[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=inst_data[11:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=wdt_en
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=tcki
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rst_in
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 3700 200 4000 200 10 1 1
{
T 3600 200 5 10 1 1 0 7 1 1
pinnumber=trisc[7:0]
T 3600 200 5 10 0 1 0 7 1 1
pinseq=9
}
P 3700 400 4000 400 10 1 1
{
T 3600 400 5 10 1 1 0 7 1 1
pinnumber=trisb[7:0]
T 3600 400 5 10 0 1 0 7 1 1
pinseq=10
}
P 3700 600 4000 600 10 1 1
{
T 3600 600 5 10 1 1 0 7 1 1
pinnumber=trisa[7:0]
T 3600 600 5 10 0 1 0 7 1 1
pinseq=11
}
P 3700 800 4000 800 10 1 1
{
T 3600 800 5 10 1 1 0 7 1 1
pinnumber=portcout[7:0]
T 3600 800 5 10 0 1 0 7 1 1
pinseq=12
}
P 3700 1000 4000 1000 10 1 1
{
T 3600 1000 5 10 1 1 0 7 1 1
pinnumber=portbout[7:0]
T 3600 1000 5 10 0 1 0 7 1 1
pinseq=13
}
P 3700 1200 4000 1200 10 1 1
{
T 3600 1200 5 10 1 1 0 7 1 1
pinnumber=portaout[7:0]
T 3600 1200 5 10 0 1 0 7 1 1
pinseq=14
}
P 3700 1400 4000 1400 10 1 1
{
T 3600 1400 5 10 1 1 0 7 1 1
pinnumber=inst_addr[10:0]
T 3600 1400 5 10 0 1 0 7 1 1
pinseq=15
}
P 3700 1600 4000 1600 4 0 1
{
T 3600 1600 5 10 1 1 0 7 1 1
pinnumber=portc_we
T 3700 1600 5 10 0 1 0 7 1 1
pinseq=16
}
P 3700 1800 4000 1800 4 0 1
{
T 3600 1800 5 10 1 1 0 7 1 1
pinnumber=portb_we
T 3700 1800 5 10 0 1 0 7 1 1
pinseq=17
}
P 3700 2000 4000 2000 4 0 1
{
T 3600 2000 5 10 1 1 0 7 1 1
pinnumber=porta_we
T 3700 2000 5 10 0 1 0 7 1 1
pinseq=18
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/mrisc_alu.sym
0,0 → 1,69
v 20100214 1
B 300 0 2100 1300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1450 5 10 1 1 0 0 1 1
device=mrisc_alu
T 400 1650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=s2[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=s1[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=op[3:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=mask[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=c_in
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 2400 200 2700 200 10 1 1
{
T 2300 200 5 10 1 1 0 7 1 1
pinnumber=out[7:0]
T 2300 200 5 10 0 1 0 7 1 1
pinseq=6
}
P 2400 400 2700 400 4 0 1
{
T 2300 400 5 10 1 1 0 7 1 1
pinnumber=z
T 2400 400 5 10 0 1 0 7 1 1
pinseq=7
}
P 2400 600 2700 600 4 0 1
{
T 2300 600 5 10 1 1 0 7 1 1
pinnumber=dc
T 2400 600 5 10 0 1 0 7 1 1
pinseq=8
}
P 2400 800 2700 800 4 0 1
{
T 2300 800 5 10 1 1 0 7 1 1
pinnumber=c
T 2400 800 5 10 0 1 0 7 1 1
pinseq=9
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/mrisc_register_file.sym
0,0 → 1,69
v 20100214 1
B 300 0 3400 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
device=mrisc_register_file
T 400 2250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=rf_wr_data[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=rf_wr_bnk[1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=rf_wr_addr[4:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=rf_rd_bnk[1:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=rf_rd_addr[4:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rst
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rf_we
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 3700 200 4000 200 10 1 1
{
T 3600 200 5 10 1 1 0 7 1 1
pinnumber=rf_rd_data[7:0]
T 3600 200 5 10 0 1 0 7 1 1
pinseq=9
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/mrisc_fifo4.sym
0,0 → 1,41
v 20100214 1
B 300 0 3300 1100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1250 5 10 1 1 0 0 1 1
device=mrisc_fifo4
T 400 1450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=din[WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=push
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=pop
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 3600 200 3900 200 10 1 1
{
T 3500 200 5 10 1 1 0 7 1 1
pinnumber=dout[WIDTH-1:0]
T 3500 200 5 10 0 1 0 7 1 1
pinseq=5
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sym/mrisc_presclr_wdt.sym
0,0 → 1,69
v 20100214 1
B 300 0 2600 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1850 5 10 1 1 0 0 1 1
device=mrisc_presclr_wdt
T 400 2050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=option[5:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=wdt_en
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=wdt_clr
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=tmr0_we
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=tcki
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rst
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 2900 200 3200 200 4 0 1
{
T 2800 200 5 10 1 1 0 7 1 1
pinnumber=wdt_to
T 2900 200 5 10 0 1 0 7 1 1
pinseq=8
}
P 2900 400 3200 400 4 0 1
{
T 2800 400 5 10 1 1 0 7 1 1
pinnumber=tmr0_cnt_en
T 2900 400 5 10 0 1 0 7 1 1
pinseq=9
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/filelist
0,0 → 1,4
`include "../../../rtl/gen/syn/mrisc.v"
`include "../../lib/cde_sram/cde_sram.v"
 
 
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/mrisc_fifo4.sch
0,0 → 1,26
v 20100214 1
C 1600 300 1 0 0 ipad_2.sym
{
T 1600 300 5 10 1 1 0 6 1 1
refdes=din[WIDTH-1:0]
}
C 1600 700 1 0 0 ipad_1.sym
{
T 1600 700 5 10 1 1 0 6 1 1
refdes=push
}
C 1600 1100 1 0 0 ipad_1.sym
{
T 1600 1100 5 10 1 1 0 6 1 1
refdes=pop
}
C 1600 1500 1 0 0 ipad_1.sym
{
T 1600 1500 5 10 1 1 0 6 1 1
refdes=clk
}
C 4400 300 1 0 0 opad_2.sym
{
T 5400 300 5 10 1 1 0 0 1 1
refdes=dout[WIDTH-1:0]
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/mrisc_presclr_wdt.sch
0,0 → 1,46
v 20100214 1
C 1300 300 1 0 0 ipad_2.sym
{
T 1300 300 5 10 1 1 0 6 1 1
refdes=option[5:0]
}
C 1300 700 1 0 0 ipad_1.sym
{
T 1300 700 5 10 1 1 0 6 1 1
refdes=wdt_en
}
C 1300 1100 1 0 0 ipad_1.sym
{
T 1300 1100 5 10 1 1 0 6 1 1
refdes=wdt_clr
}
C 1300 1500 1 0 0 ipad_1.sym
{
T 1300 1500 5 10 1 1 0 6 1 1
refdes=tmr0_we
}
C 1300 1900 1 0 0 ipad_1.sym
{
T 1300 1900 5 10 1 1 0 6 1 1
refdes=tcki
}
C 1300 2300 1 0 0 ipad_1.sym
{
T 1300 2300 5 10 1 1 0 6 1 1
refdes=rst
}
C 1300 2700 1 0 0 ipad_1.sym
{
T 1300 2700 5 10 1 1 0 6 1 1
refdes=clk
}
C 3700 300 1 0 0 opad_1.sym
{
T 4700 300 5 10 1 1 0 0 1 1
refdes=wdt_to
}
C 3700 700 1 0 0 opad_1.sym
{
T 4700 700 5 10 1 1 0 0 1 1
refdes=tmr0_cnt_en
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/cde_sram.sch
0,0 → 1,41
v 20100214 1
C 2300 300 1 0 0 ipad_2.sym
{
T 2300 300 5 10 1 1 0 6 1 1
refdes=Write_Data[WIDTH-1:0]
}
C 2300 700 1 0 0 ipad_2.sym
{
T 2300 700 5 10 1 1 0 6 1 1
refdes=WR_Add[ADDR-1:0]
}
C 2300 1100 1 0 0 ipad_2.sym
{
T 2300 1100 5 10 1 1 0 6 1 1
refdes=RD_Add[ADDR-1:0]
}
C 2300 1500 1 0 0 ipad_1.sym
{
T 2300 1500 5 10 1 1 0 6 1 1
refdes=clk
}
C 2300 1900 1 0 0 ipad_1.sym
{
T 2300 1900 5 10 1 1 0 6 1 1
refdes=WR
}
C 2300 2300 1 0 0 ipad_1.sym
{
T 2300 2300 5 10 1 1 0 6 1 1
refdes=RD
}
C 2300 2700 1 0 0 ipad_1.sym
{
T 2300 2700 5 10 1 1 0 6 1 1
refdes=CS
}
C 5600 300 1 0 0 opad_2.sym
{
T 6600 300 5 10 1 1 0 0 1 1
refdes=Read_Data[WIDTH-1:0]
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/mrisc.sch
0,0 → 1,91
v 20100214 1
C 1700 300 1 0 0 ipad_2.sym
{
T 1700 300 5 10 1 1 0 6 1 1
refdes=portcin[7:0]
}
C 1700 700 1 0 0 ipad_2.sym
{
T 1700 700 5 10 1 1 0 6 1 1
refdes=portbin[7:0]
}
C 1700 1100 1 0 0 ipad_2.sym
{
T 1700 1100 5 10 1 1 0 6 1 1
refdes=portain[7:0]
}
C 1700 1500 1 0 0 ipad_2.sym
{
T 1700 1500 5 10 1 1 0 6 1 1
refdes=inst_data[11:0]
}
C 1700 1900 1 0 0 ipad_1.sym
{
T 1700 1900 5 10 1 1 0 6 1 1
refdes=wdt_en
}
C 1700 2300 1 0 0 ipad_1.sym
{
T 1700 2300 5 10 1 1 0 6 1 1
refdes=tcki
}
C 1700 2700 1 0 0 ipad_1.sym
{
T 1700 2700 5 10 1 1 0 6 1 1
refdes=rst_in
}
C 1700 3100 1 0 0 ipad_1.sym
{
T 1700 3100 5 10 1 1 0 6 1 1
refdes=clk
}
C 4500 300 1 0 0 opad_2.sym
{
T 5500 300 5 10 1 1 0 0 1 1
refdes=trisc[7:0]
}
C 4500 700 1 0 0 opad_2.sym
{
T 5500 700 5 10 1 1 0 0 1 1
refdes=trisb[7:0]
}
C 4500 1100 1 0 0 opad_2.sym
{
T 5500 1100 5 10 1 1 0 0 1 1
refdes=trisa[7:0]
}
C 4500 1500 1 0 0 opad_2.sym
{
T 5500 1500 5 10 1 1 0 0 1 1
refdes=portcout[7:0]
}
C 4500 1900 1 0 0 opad_2.sym
{
T 5500 1900 5 10 1 1 0 0 1 1
refdes=portbout[7:0]
}
C 4500 2300 1 0 0 opad_2.sym
{
T 5500 2300 5 10 1 1 0 0 1 1
refdes=portaout[7:0]
}
C 4500 2700 1 0 0 opad_2.sym
{
T 5500 2700 5 10 1 1 0 0 1 1
refdes=inst_addr[10:0]
}
C 4500 3100 1 0 0 opad_1.sym
{
T 5500 3100 5 10 1 1 0 0 1 1
refdes=portc_we
}
C 4500 3500 1 0 0 opad_1.sym
{
T 5500 3500 5 10 1 1 0 0 1 1
refdes=portb_we
}
C 4500 3900 1 0 0 opad_1.sym
{
T 5500 3900 5 10 1 1 0 0 1 1
refdes=porta_we
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/mrisc_alu.sch
0,0 → 1,46
v 20100214 1
C 1100 300 1 0 0 ipad_2.sym
{
T 1100 300 5 10 1 1 0 6 1 1
refdes=s2[7:0]
}
C 1100 700 1 0 0 ipad_2.sym
{
T 1100 700 5 10 1 1 0 6 1 1
refdes=s1[7:0]
}
C 1100 1100 1 0 0 ipad_2.sym
{
T 1100 1100 5 10 1 1 0 6 1 1
refdes=op[3:0]
}
C 1100 1500 1 0 0 ipad_2.sym
{
T 1100 1500 5 10 1 1 0 6 1 1
refdes=mask[7:0]
}
C 1100 1900 1 0 0 ipad_1.sym
{
T 1100 1900 5 10 1 1 0 6 1 1
refdes=c_in
}
C 3200 300 1 0 0 opad_2.sym
{
T 4200 300 5 10 1 1 0 0 1 1
refdes=out[7:0]
}
C 3200 700 1 0 0 opad_1.sym
{
T 4200 700 5 10 1 1 0 0 1 1
refdes=z
}
C 3200 1100 1 0 0 opad_1.sym
{
T 4200 1100 5 10 1 1 0 0 1 1
refdes=dc
}
C 3200 1500 1 0 0 opad_1.sym
{
T 4200 1500 5 10 1 1 0 0 1 1
refdes=c
}
/projects/pic_micro/ip/mrisc/doc/geda/drawing/sch/mrisc_register_file.sch
0,0 → 1,46
v 20100214 1
C 1700 300 1 0 0 ipad_2.sym
{
T 1700 300 5 10 1 1 0 6 1 1
refdes=rf_wr_data[7:0]
}
C 1700 700 1 0 0 ipad_2.sym
{
T 1700 700 5 10 1 1 0 6 1 1
refdes=rf_wr_bnk[1:0]
}
C 1700 1100 1 0 0 ipad_2.sym
{
T 1700 1100 5 10 1 1 0 6 1 1
refdes=rf_wr_addr[4:0]
}
C 1700 1500 1 0 0 ipad_2.sym
{
T 1700 1500 5 10 1 1 0 6 1 1
refdes=rf_rd_bnk[1:0]
}
C 1700 1900 1 0 0 ipad_2.sym
{
T 1700 1900 5 10 1 1 0 6 1 1
refdes=rf_rd_addr[4:0]
}
C 1700 2300 1 0 0 ipad_1.sym
{
T 1700 2300 5 10 1 1 0 6 1 1
refdes=rst
}
C 1700 2700 1 0 0 ipad_1.sym
{
T 1700 2700 5 10 1 1 0 6 1 1
refdes=rf_we
}
C 1700 3100 1 0 0 ipad_1.sym
{
T 1700 3100 5 10 1 1 0 6 1 1
refdes=clk
}
C 4500 300 1 0 0 opad_2.sym
{
T 5500 300 5 10 1 1 0 0 1 1
refdes=rf_rd_data[7:0]
}
/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs
1,8 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define
2,10 → 2,7
initial
begin
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
`TIMEFORMAT
 
$display ("========== Starting Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs
1,9 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define
2,14 → 2,10
 
initial
begin
`TIMEFORMAT
$display ("\n\nMini-RISC. Version 1.0\n\n");
$display ("========== Starting Sanity 1 Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
 
while(inst_addr != `GOOD & inst_addr != `BAD) @(posedge clk);
if(inst_addr == `GOOD)
/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs
1,8 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/loop/test_define
1,12 → 1,8
 
initial
begin
`TIMEFORMAT
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
 
$display ("========== Starting Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs
1,9 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define
2,10 → 2,7
initial
begin
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
`TIMEFORMAT
 
$display ("========== Starting Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs
1,9 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define
1,12 → 1,8
 
initial
begin
`TIMEFORMAT
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
 
$display ("========== Starting Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs
1,8 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
`define ROM_WORDS 2048
`define ROM_ADDR 11
`define ROM_WIDTH 12
/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define
2,10 → 2,7
initial
begin
$display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
`TIMEFORMAT
 
$display ("========== Starting Test ========== \n");
cg.reset_on;
repeat(10) @(posedge clk);
cg.reset_off;
/projects/logic/ip/ps2_interface/rtl/variants/ps2_interface/ps2_interface_defines.v
1,5 → 1,5
 
`define VARIENT ps2_interface
`define VARIANT ps2_interface
`define CDE cde
 
`define FSM _fsm
/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v
39,7 → 39,7
`include "ps2_interface_defines.v"
 
 
module `VARIENT
module `VARIANT
#(parameter FREQ=24, // clk frequency in Mhz
parameter CLK_HOLD_DELAY =100, // number of microsecs to hold clk before host-> device xfer
parameter DATA_SETUP_DELAY =20, // number of microsecs to hold data startbit for host-> device xfer
/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v
2,7 → 2,7
 
`include "ps2_interface_defines.v"
 
module `VARIENT`FSM
module `VARIANT`FSM
#(parameter NUMBITS=11)
 
(
/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/ps2_interface_fsm.sym
0,0 → 1,118
v 20100214 1
B 300 0 3600 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2250 5 10 1 1 0 0 1 1
device=ps2_interface_fsm
T 400 2450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=bit_count[3:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=usec_delay_done
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_idle
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_fall
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=frame0
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=force_startbit
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3900 200 4200 200 4 0 1
{
T 3800 200 5 10 1 1 0 7 1 1
pinnumber=shift_frame
T 3900 200 5 10 0 1 0 7 1 1
pinseq=10
}
P 3900 400 4200 400 4 0 1
{
T 3800 400 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3900 400 5 10 0 1 0 7 1 1
pinseq=11
}
P 3900 600 4200 600 4 0 1
{
T 3800 600 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3900 600 5 10 0 1 0 7 1 1
pinseq=12
}
P 3900 800 4200 800 4 0 1
{
T 3800 800 5 10 1 1 0 7 1 1
pinnumber=load_tx_data
T 3900 800 5 10 0 1 0 7 1 1
pinseq=13
}
P 3900 1000 4200 1000 4 0 1
{
T 3800 1000 5 10 1 1 0 7 1 1
pinnumber=load_rx_data
T 3900 1000 5 10 0 1 0 7 1 1
pinseq=14
}
P 3900 1200 4200 1200 4 0 1
{
T 3800 1200 5 10 1 1 0 7 1 1
pinnumber=enable_usec_delay
T 3900 1200 5 10 0 1 0 7 1 1
pinseq=15
}
P 3900 1400 4200 1400 4 0 1
{
T 3800 1400 5 10 1 1 0 7 1 1
pinnumber=busy
T 3900 1400 5 10 0 1 0 7 1 1
pinseq=16
}
/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/ps2_interface.sym
0,0 → 1,132
v 20100214 1
B 300 0 3100 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650 5 10 1 1 0 0 1 1
device=ps2_interface
T 400 2850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=tx_data[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=ps2_data_in
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_in
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=clr_rx_full
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 3400 200 3700 200 10 1 1
{
T 3300 200 5 10 1 1 0 7 1 1
pinnumber=rx_data[7:0]
T 3300 200 5 10 0 1 0 7 1 1
pinseq=8
}
P 3400 400 3700 400 4 0 1
{
T 3300 400 5 10 1 1 0 7 1 1
pinnumber=tx_ack_error
T 3400 400 5 10 0 1 0 7 1 1
pinseq=9
}
P 3400 600 3700 600 4 0 1
{
T 3300 600 5 10 1 1 0 7 1 1
pinnumber=rx_parity_rcv
T 3400 600 5 10 0 1 0 7 1 1
pinseq=10
}
P 3400 800 3700 800 4 0 1
{
T 3300 800 5 10 1 1 0 7 1 1
pinnumber=rx_parity_error
T 3400 800 5 10 0 1 0 7 1 1
pinseq=11
}
P 3400 1000 3700 1000 4 0 1
{
T 3300 1000 5 10 1 1 0 7 1 1
pinnumber=rx_parity_cal
T 3400 1000 5 10 0 1 0 7 1 1
pinseq=12
}
P 3400 1200 3700 1200 4 0 1
{
T 3300 1200 5 10 1 1 0 7 1 1
pinnumber=rx_full
T 3400 1200 5 10 0 1 0 7 1 1
pinseq=13
}
P 3400 1400 3700 1400 4 0 1
{
T 3300 1400 5 10 1 1 0 7 1 1
pinnumber=rx_frame_error
T 3400 1400 5 10 0 1 0 7 1 1
pinseq=14
}
P 3400 1600 3700 1600 4 0 1
{
T 3300 1600 5 10 1 1 0 7 1 1
pinnumber=read
T 3400 1600 5 10 0 1 0 7 1 1
pinseq=15
}
P 3400 1800 3700 1800 4 0 1
{
T 3300 1800 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3400 1800 5 10 0 1 0 7 1 1
pinseq=16
}
P 3400 2000 3700 2000 4 0 1
{
T 3300 2000 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3400 2000 5 10 0 1 0 7 1 1
pinseq=17
}
P 3400 2200 3700 2200 4 0 1
{
T 3300 2200 5 10 1 1 0 7 1 1
pinnumber=busy
T 3400 2200 5 10 0 1 0 7 1 1
pinseq=18
}
/projects/logic/ip/ps2_interface/doc/geda/drawing/sym/cde_sync_with_hysteresis.sym
0,0 → 1,48
v 20100214 1
B 300 0 4200 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1050 5 10 1 1 0 0 1 1
device=cde_sync_with_hysteresis
T 400 1250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=data_in[WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 4500 200 4800 200 10 1 1
{
T 4400 200 5 10 1 1 0 7 1 1
pinnumber=data_rise[WIDTH-1:0]
T 4400 200 5 10 0 1 0 7 1 1
pinseq=4
}
P 4500 400 4800 400 10 1 1
{
T 4400 400 5 10 1 1 0 7 1 1
pinnumber=data_out[WIDTH-1:0]
T 4400 400 5 10 0 1 0 7 1 1
pinseq=5
}
P 4500 600 4800 600 10 1 1
{
T 4400 600 5 10 1 1 0 7 1 1
pinnumber=data_fall[WIDTH-1:0]
T 4400 600 5 10 0 1 0 7 1 1
pinseq=6
}
/projects/logic/ip/ps2_interface/doc/geda/drawing/filelist
0,0 → 1,2
`include "../../../rtl/gen/syn/ps2_interface.v"
`include "../../lib/cde_sync/cde_sync_with_hysteresis.v"
/projects/logic/ip/ps2_interface/doc/drawing/sym/ps2_interface_fsm.sym
0,0 → 1,118
v 20100214 1
B 300 0 3600 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2250 5 10 1 1 0 0 1 1
device=ps2_interface_fsm
T 400 2450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=bit_count[3:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=usec_delay_done
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_idle
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_fall
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=frame0
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=force_startbit
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3900 200 4200 200 4 0 1
{
T 3800 200 5 10 1 1 0 7 1 1
pinnumber=shift_frame
T 3900 200 5 10 0 1 0 7 1 1
pinseq=10
}
P 3900 400 4200 400 4 0 1
{
T 3800 400 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3900 400 5 10 0 1 0 7 1 1
pinseq=11
}
P 3900 600 4200 600 4 0 1
{
T 3800 600 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3900 600 5 10 0 1 0 7 1 1
pinseq=12
}
P 3900 800 4200 800 4 0 1
{
T 3800 800 5 10 1 1 0 7 1 1
pinnumber=load_tx_data
T 3900 800 5 10 0 1 0 7 1 1
pinseq=13
}
P 3900 1000 4200 1000 4 0 1
{
T 3800 1000 5 10 1 1 0 7 1 1
pinnumber=load_rx_data
T 3900 1000 5 10 0 1 0 7 1 1
pinseq=14
}
P 3900 1200 4200 1200 4 0 1
{
T 3800 1200 5 10 1 1 0 7 1 1
pinnumber=enable_usec_delay
T 3900 1200 5 10 0 1 0 7 1 1
pinseq=15
}
P 3900 1400 4200 1400 4 0 1
{
T 3800 1400 5 10 1 1 0 7 1 1
pinnumber=busy
T 3900 1400 5 10 0 1 0 7 1 1
pinseq=16
}
/projects/logic/ip/ps2_interface/doc/drawing/sym/ps2_interface.sym
0,0 → 1,132
v 20100214 1
B 300 0 3100 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650 5 10 1 1 0 0 1 1
device=ps2_interface
T 400 2850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=tx_data[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=ps2_data_in
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_in
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=clr_rx_full
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 3400 200 3700 200 10 1 1
{
T 3300 200 5 10 1 1 0 7 1 1
pinnumber=rx_data[7:0]
T 3300 200 5 10 0 1 0 7 1 1
pinseq=8
}
P 3400 400 3700 400 4 0 1
{
T 3300 400 5 10 1 1 0 7 1 1
pinnumber=tx_ack_error
T 3400 400 5 10 0 1 0 7 1 1
pinseq=9
}
P 3400 600 3700 600 4 0 1
{
T 3300 600 5 10 1 1 0 7 1 1
pinnumber=rx_parity_rcv
T 3400 600 5 10 0 1 0 7 1 1
pinseq=10
}
P 3400 800 3700 800 4 0 1
{
T 3300 800 5 10 1 1 0 7 1 1
pinnumber=rx_parity_error
T 3400 800 5 10 0 1 0 7 1 1
pinseq=11
}
P 3400 1000 3700 1000 4 0 1
{
T 3300 1000 5 10 1 1 0 7 1 1
pinnumber=rx_parity_cal
T 3400 1000 5 10 0 1 0 7 1 1
pinseq=12
}
P 3400 1200 3700 1200 4 0 1
{
T 3300 1200 5 10 1 1 0 7 1 1
pinnumber=rx_full
T 3400 1200 5 10 0 1 0 7 1 1
pinseq=13
}
P 3400 1400 3700 1400 4 0 1
{
T 3300 1400 5 10 1 1 0 7 1 1
pinnumber=rx_frame_error
T 3400 1400 5 10 0 1 0 7 1 1
pinseq=14
}
P 3400 1600 3700 1600 4 0 1
{
T 3300 1600 5 10 1 1 0 7 1 1
pinnumber=read
T 3400 1600 5 10 0 1 0 7 1 1
pinseq=15
}
P 3400 1800 3700 1800 4 0 1
{
T 3300 1800 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3400 1800 5 10 0 1 0 7 1 1
pinseq=16
}
P 3400 2000 3700 2000 4 0 1
{
T 3300 2000 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3400 2000 5 10 0 1 0 7 1 1
pinseq=17
}
P 3400 2200 3700 2200 4 0 1
{
T 3300 2200 5 10 1 1 0 7 1 1
pinnumber=busy
T 3400 2200 5 10 0 1 0 7 1 1
pinseq=18
}
/projects/logic/ip/ps2_interface/doc/drawing/sym/cde_sync_with_hysteresis.sym
0,0 → 1,48
v 20100214 1
B 300 0 4200 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1050 5 10 1 1 0 0 1 1
device=cde_sync_with_hysteresis
T 400 1250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=data_in[WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 4500 200 4800 200 10 1 1
{
T 4400 200 5 10 1 1 0 7 1 1
pinnumber=data_rise[WIDTH-1:0]
T 4400 200 5 10 0 1 0 7 1 1
pinseq=4
}
P 4500 400 4800 400 10 1 1
{
T 4400 400 5 10 1 1 0 7 1 1
pinnumber=data_out[WIDTH-1:0]
T 4400 400 5 10 0 1 0 7 1 1
pinseq=5
}
P 4500 600 4800 600 10 1 1
{
T 4400 600 5 10 1 1 0 7 1 1
pinnumber=data_fall[WIDTH-1:0]
T 4400 600 5 10 0 1 0 7 1 1
pinseq=6
}
/projects/logic/ip/ps2_interface/doc/drawing/sch/cde_sync_with_hysteresis.sch
0,0 → 1,31
v 20100214 1
C 2000 300 1 0 0 ipad_2.sym
{
T 2000 300 5 10 1 1 0 6 1 1
refdes=data_in[WIDTH-1:0]
}
C 2000 700 1 0 0 ipad_1.sym
{
T 2000 700 5 10 1 1 0 6 1 1
refdes=reset
}
C 2000 1100 1 0 0 ipad_1.sym
{
T 2000 1100 5 10 1 1 0 6 1 1
refdes=clk
}
C 5300 300 1 0 0 opad_2.sym
{
T 6300 300 5 10 1 1 0 0 1 1
refdes=data_rise[WIDTH-1:0]
}
C 5300 700 1 0 0 opad_2.sym
{
T 6300 700 5 10 1 1 0 0 1 1
refdes=data_out[WIDTH-1:0]
}
C 5300 1100 1 0 0 opad_2.sym
{
T 6300 1100 5 10 1 1 0 0 1 1
refdes=data_fall[WIDTH-1:0]
}
/projects/logic/ip/ps2_interface/doc/drawing/sch/ps2_interface.sch
0,0 → 1,91
v 20100214 1
C 1400 300 1 0 0 ipad_2.sym
{
T 1400 300 5 10 1 1 0 6 1 1
refdes=tx_data[7:0]
}
C 1400 700 1 0 0 ipad_1.sym
{
T 1400 700 5 10 1 1 0 6 1 1
refdes=write
}
C 1400 1100 1 0 0 ipad_1.sym
{
T 1400 1100 5 10 1 1 0 6 1 1
refdes=reset
}
C 1400 1500 1 0 0 ipad_1.sym
{
T 1400 1500 5 10 1 1 0 6 1 1
refdes=ps2_data_in
}
C 1400 1900 1 0 0 ipad_1.sym
{
T 1400 1900 5 10 1 1 0 6 1 1
refdes=ps2_clk_in
}
C 1400 2300 1 0 0 ipad_1.sym
{
T 1400 2300 5 10 1 1 0 6 1 1
refdes=clr_rx_full
}
C 1400 2700 1 0 0 ipad_1.sym
{
T 1400 2700 5 10 1 1 0 6 1 1
refdes=clk
}
C 4200 300 1 0 0 opad_2.sym
{
T 5200 300 5 10 1 1 0 0 1 1
refdes=rx_data[7:0]
}
C 4200 700 1 0 0 opad_1.sym
{
T 5200 700 5 10 1 1 0 0 1 1
refdes=tx_ack_error
}
C 4200 1100 1 0 0 opad_1.sym
{
T 5200 1100 5 10 1 1 0 0 1 1
refdes=rx_parity_rcv
}
C 4200 1500 1 0 0 opad_1.sym
{
T 5200 1500 5 10 1 1 0 0 1 1
refdes=rx_parity_error
}
C 4200 1900 1 0 0 opad_1.sym
{
T 5200 1900 5 10 1 1 0 0 1 1
refdes=rx_parity_cal
}
C 4200 2300 1 0 0 opad_1.sym
{
T 5200 2300 5 10 1 1 0 0 1 1
refdes=rx_full
}
C 4200 2700 1 0 0 opad_1.sym
{
T 5200 2700 5 10 1 1 0 0 1 1
refdes=rx_frame_error
}
C 4200 3100 1 0 0 opad_1.sym
{
T 5200 3100 5 10 1 1 0 0 1 1
refdes=read
}
C 4200 3500 1 0 0 opad_1.sym
{
T 5200 3500 5 10 1 1 0 0 1 1
refdes=ps2_data_oe
}
C 4200 3900 1 0 0 opad_1.sym
{
T 5200 3900 5 10 1 1 0 0 1 1
refdes=ps2_clk_oe
}
C 4200 4300 1 0 0 opad_1.sym
{
T 5200 4300 5 10 1 1 0 0 1 1
refdes=busy
}
/projects/logic/ip/ps2_interface/doc/drawing/sch/ps2_interface_fsm.sch
0,0 → 1,81
v 20100214 1
C 1700 300 1 0 0 ipad_2.sym
{
T 1700 300 5 10 1 1 0 6 1 1
refdes=bit_count[3:0]
}
C 1700 700 1 0 0 ipad_1.sym
{
T 1700 700 5 10 1 1 0 6 1 1
refdes=write
}
C 1700 1100 1 0 0 ipad_1.sym
{
T 1700 1100 5 10 1 1 0 6 1 1
refdes=usec_delay_done
}
C 1700 1500 1 0 0 ipad_1.sym
{
T 1700 1500 5 10 1 1 0 6 1 1
refdes=reset
}
C 1700 1900 1 0 0 ipad_1.sym
{
T 1700 1900 5 10 1 1 0 6 1 1
refdes=ps2_idle
}
C 1700 2300 1 0 0 ipad_1.sym
{
T 1700 2300 5 10 1 1 0 6 1 1
refdes=ps2_clk_fall
}
C 1700 2700 1 0 0 ipad_1.sym
{
T 1700 2700 5 10 1 1 0 6 1 1
refdes=frame0
}
C 1700 3100 1 0 0 ipad_1.sym
{
T 1700 3100 5 10 1 1 0 6 1 1
refdes=force_startbit
}
C 1700 3500 1 0 0 ipad_1.sym
{
T 1700 3500 5 10 1 1 0 6 1 1
refdes=clk
}
C 4700 300 1 0 0 opad_1.sym
{
T 5700 300 5 10 1 1 0 0 1 1
refdes=shift_frame
}
C 4700 700 1 0 0 opad_1.sym
{
T 5700 700 5 10 1 1 0 0 1 1
refdes=ps2_data_oe
}
C 4700 1100 1 0 0 opad_1.sym
{
T 5700 1100 5 10 1 1 0 0 1 1
refdes=ps2_clk_oe
}
C 4700 1500 1 0 0 opad_1.sym
{
T 5700 1500 5 10 1 1 0 0 1 1
refdes=load_tx_data
}
C 4700 1900 1 0 0 opad_1.sym
{
T 5700 1900 5 10 1 1 0 0 1 1
refdes=load_rx_data
}
C 4700 2300 1 0 0 opad_1.sym
{
T 5700 2300 5 10 1 1 0 0 1 1
refdes=enable_usec_delay
}
C 4700 2700 1 0 0 opad_1.sym
{
T 5700 2700 5 10 1 1 0 0 1 1
refdes=busy
}
/projects/logic/ip/ps2_interface/doc/copyright.v
9,7 → 9,7
// //
// //
// //
// Copyright (C) <2010> <Ouabache DesignWorks> //
// Copyright (C) <2009> <Ouabache DesignWorks> //
// //
// //
// This source file may be used and distributed without //
/projects/logic/ip/ps2_interface/sim/run/default/TB.defs
1,6 → 1,4
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 40.00000
 
 
 
 
/projects/logic/ip/ps2_interface/sim/run/default/test_define
1,6 → 1,6
initial
begin
`TIMEFORMAT
 
$display(" ");
$display(" ===================================================");
$display("%8d Test Start",$realtime/`PERIOD );
/projects/logic/ip/disp_io/rtl/variants/disp_io/disp_io_defines.v
1,3 → 1,3
 
`define VARIENT disp_io
`define VARIANT disp_io
`define CDE cde
/projects/logic/ip/disp_io/rtl/verilog/disp_io.v
47,7 → 47,7
`include "disp_io_defines.v"
 
module
`VARIENT
`VARIANT
(
input wire clk,
input wire reset,
/projects/logic/ip/disp_io/doc/geda/drawing/sym/disp_io.sym
0,0 → 1,97
v 20100214 1
B 300 0 3500 1700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1850 5 10 1 1 0 0 1 1
device=disp_io
T 400 2050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=sw_pad_in[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=btn_pad_in[3:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=PosL[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=PosD[15:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=one_usec
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 3800 200 4100 200 10 1 1
{
T 3700 200 5 10 1 1 0 7 1 1
pinnumber=seg_pad_out[6:0]
T 3700 200 5 10 0 1 0 7 1 1
pinseq=8
}
P 3800 400 4100 400 10 1 1
{
T 3700 400 5 10 1 1 0 7 1 1
pinnumber=led_pad_out[7:0]
T 3700 400 5 10 0 1 0 7 1 1
pinseq=9
}
P 3800 600 4100 600 10 1 1
{
T 3700 600 5 10 1 1 0 7 1 1
pinnumber=an_pad_out[3:0]
T 3700 600 5 10 0 1 0 7 1 1
pinseq=10
}
P 3800 800 4100 800 10 1 1
{
T 3700 800 5 10 1 1 0 7 1 1
pinnumber=PosS[7:0]
T 3700 800 5 10 0 1 0 7 1 1
pinseq=11
}
P 3800 1000 4100 1000 10 1 1
{
T 3700 1000 5 10 1 1 0 7 1 1
pinnumber=PosB[3:0]
T 3700 1000 5 10 0 1 0 7 1 1
pinseq=12
}
P 3800 1200 4100 1200 4 0 1
{
T 3700 1200 5 10 1 1 0 7 1 1
pinnumber=dp_pad_out
T 3800 1200 5 10 0 1 0 7 1 1
pinseq=13
}
/projects/logic/ip/disp_io/doc/geda/drawing/filelist
0,0 → 1,3
 
`include "../../../rtl/gen/syn/disp_io.v"
 
/projects/logic/ip/disp_io/sim/run/default/TB.defs
1,5 → 1,2
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 20.00000
 
/projects/logic/ip/disp_io/sim/run/default/test_define
1,6 → 1,5
initial
begin
`TIMEFORMAT
$display(" ");
$display(" ===================================================");
$display("%t Test Start",$realtime);
12,8 → 11,6
sw_pad_in = 8'b00000000;
btn_pad_in = 4'b0000;
 
 
 
cg.next(8);
cg.reset_off;
cg.next(88);
/projects/logic/ip/uart/rtl/variants/uart/uart_defines.v
1,5 → 1,5
 
`define VARIENT uart
`define VARIANT uart
`define CDE cde
 
`define BAUDGEN _baudgen
/projects/logic/ip/uart/rtl/verilog/uart.v
34,8 → 34,10
 
 
module
`VARIENT
#(parameter PRESCALE=5'b01100 ,SIZE=8 ,HAS_PARITY=1 )
`VARIANT
#(parameter PRESCALE=5'b01100,
parameter SIZE=8,
parameter HAS_PARITY=1 )
 
 
(
44,24 → 46,24
 
input wire cts_pad_in,
output reg rts_pad_out,
 
output wire txd_pad_out,
input wire rxd_pad_in,
output reg cts_out,
input wire rts_in,
 
input wire parity,
input wire force_parity,
input wire txd_parity,
input wire txd_force_parity,
input wire txd_load,
input wire txd_break,
input wire [SIZE-1:0] txd_data_in,
output wire txd_buffer_empty,
 
output wire txd_pad_out,
 
input wire rxd_pad_in,
input wire rxd_parity,
input wire rxd_force_parity,
output wire [SIZE-1:0] rxd_data_out,
output wire rxd_buffer_full,
output wire rxd_parity,
output wire rxd_parity_error,
output wire rxd_stop_error
);
78,8 → 80,8
begin
 
 
$display("%t %m Received %h parity %b stop error %b parity error %b",
$realtime,rxd_data_out, rxd_parity, rxd_stop_error,rxd_parity_error );
$display("%t %m Received %h stop error %b parity error %b",
$realtime,rxd_data_out, rxd_stop_error,rxd_parity_error );
end
 
always@(negedge txd_load)
88,23 → 90,14
if(!reset)
begin
$display("%t %m Sending %h parity %b ",
$realtime,txd_data_in,parity );
$realtime,txd_data_in,txd_parity );
end
 
end
 
 
 
 
 
`endif
 
 
 
 
 
 
always@(posedge clk)
117,7 → 110,7
 
 
`VARIENT`BAUDGEN
`VARIANT`BAUDGEN
#(.PRESCALE(PRESCALE))
baudgen (
.clk (clk),
126,36 → 119,35
);
 
 
`VARIENT`XMIT
`VARIANT`XMIT
#(.SIZE(SIZE))
uart_xmit (
.clk (clk),
.reset (reset),
.parity (parity),
.force_parity (force_parity),
.baud_clk (baud_clk),
.txd_load (txd_load),
.txd_break (txd_break),
.txd_data_in (txd_data_in),
.txd_buffer_empty (txd_buffer_empty),
.txd_pad_out (txd_pad_out)
.clk ( clk ),
.reset ( reset ),
.baud_clk ( baud_clk ),
.parity ( txd_parity ),
.force_parity ( txd_force_parity ),
.txd_load ( txd_load ),
.txd_break ( txd_break ),
.txd_data_in ( txd_data_in ),
.txd_buffer_empty ( txd_buffer_empty ),
.txd_pad_out ( txd_pad_out )
);
`VARIENT`RCVR
`VARIANT`RCVR
#(.HAS_PARITY(HAS_PARITY),
.SIZE(SIZE))
uart_rcvr (
.clk (clk),
.reset (reset),
.baud_clk (baud_clk),
.parity (parity),
.force_parity (force_parity),
.rxd_pad_in (rxd_pad_in),
.rxd_data_out (rxd_data_out),
.rxd_buffer_full (rxd_buffer_full),
.rxd_parity (rxd_parity),
.rxd_parity_error (rxd_parity_error),
.rxd_stop_error (rxd_stop_error)
.clk ( clk ),
.reset ( reset ),
.baud_clk ( baud_clk ),
.parity ( rxd_parity ),
.force_parity ( rxd_force_parity ),
.rxd_pad_in ( rxd_pad_in ),
.rxd_data_out ( rxd_data_out ),
.rxd_buffer_full ( rxd_buffer_full ),
.rxd_parity_error ( rxd_parity_error ),
.rxd_stop_error ( rxd_stop_error )
);
/projects/logic/ip/uart/rtl/verilog/uart_xmit.v
32,7 → 32,7
//*
//*---------------------------------------------------------------------
module
`VARIENT`XMIT
`VARIANT`XMIT
#(parameter SIZE=8 )
 
 
/projects/logic/ip/uart/rtl/verilog/uart_baudgen.v
32,7 → 32,7
//*
//*---------------------------------------------------------------------
module
`VARIENT`BAUDGEN
`VARIANT`BAUDGEN
#(parameter PRESCALE=5'b01100 )
(
input wire clk,
/projects/logic/ip/uart/rtl/verilog/uart_rcvr.v
32,7 → 32,7
//*
//*---------------------------------------------------------------------
module
`VARIENT`RCVR
`VARIANT`RCVR
#(parameter SIZE=8 ,HAS_PARITY=1 )
(
input wire clk,
45,7 → 45,6
input wire rxd_pad_in,
output reg [SIZE-1:0] rxd_data_out,
output reg rxd_buffer_full,
output reg rxd_parity,
output reg rxd_parity_error,
output reg rxd_stop_error
);
59,7 → 58,8
reg [SIZE-1:0] rxd_shifter;
reg [3:0] rxd_shifter_cnt;
reg rxd_pad_sig;
 
reg rxd_parity_cal;
reg rxd_data_shifting;
150,7 → 150,7
rxd_data_out <= rxd_shifter[8-1:0];
rxd_buffer_full <= 1'b1;
rxd_stop_error <= !rxd_pad_sig;
rxd_parity_error <= rxd_parity;
rxd_parity_error <= rxd_parity_cal;
end
else
begin
166,14 → 166,14
 
 
always@(posedge clk)
if(reset) rxd_parity <= 1'b0;
if(reset) rxd_parity_cal <= 1'b0;
else
if(!rxd_baud_clk) rxd_parity <= rxd_parity;
if(!rxd_baud_clk) rxd_parity_cal <= rxd_parity_cal;
else
if(force_parity ||(rxd_shifter_cnt == 0)) rxd_parity <= parity;
if(force_parity ||(rxd_shifter_cnt == 0)) rxd_parity_cal <= parity;
else
if(rxd_shifter_cnt <= 8+1 ) rxd_parity <= rxd_parity ^ rxd_pad_sig;
else rxd_parity <= rxd_parity;
if(rxd_shifter_cnt <= 8+1 ) rxd_parity_cal <= rxd_parity_cal ^ rxd_pad_sig;
else rxd_parity_cal <= rxd_parity_cal;
 
/projects/logic/ip/uart/doc/geda/drawing/sym/uart.sym
0,0 → 1,146
v 20100214 1
B 300 0 4700 2700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2850 5 10 1 1 0 0 1 1
device=uart
T 400 3050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=txd_data_in[SIZE-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=txd_parity
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=txd_load
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=txd_force_parity
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=txd_break
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rxd_parity
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=rxd_force_parity
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=rts_in
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=cts_pad_in
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
P 5000 200 5300 200 10 1 1
{
T 4900 200 5 10 1 1 0 7 1 1
pinnumber=rxd_data_out[SIZE-1:0]
T 4900 200 5 10 0 1 0 7 1 1
pinseq=13
}
P 5000 400 5300 400 4 0 1
{
T 4900 400 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 5000 400 5 10 0 1 0 7 1 1
pinseq=14
}
P 5000 600 5300 600 4 0 1
{
T 4900 600 5 10 1 1 0 7 1 1
pinnumber=txd_buffer_empty
T 5000 600 5 10 0 1 0 7 1 1
pinseq=15
}
P 5000 800 5300 800 4 0 1
{
T 4900 800 5 10 1 1 0 7 1 1
pinnumber=rxd_stop_error
T 5000 800 5 10 0 1 0 7 1 1
pinseq=16
}
P 5000 1000 5300 1000 4 0 1
{
T 4900 1000 5 10 1 1 0 7 1 1
pinnumber=rxd_parity_error
T 5000 1000 5 10 0 1 0 7 1 1
pinseq=17
}
P 5000 1200 5300 1200 4 0 1
{
T 4900 1200 5 10 1 1 0 7 1 1
pinnumber=rxd_buffer_full
T 5000 1200 5 10 0 1 0 7 1 1
pinseq=18
}
P 5000 1400 5300 1400 4 0 1
{
T 4900 1400 5 10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 5000 1400 5 10 0 1 0 7 1 1
pinseq=19
}
P 5000 1600 5300 1600 4 0 1
{
T 4900 1600 5 10 1 1 0 7 1 1
pinnumber=cts_out
T 5000 1600 5 10 0 1 0 7 1 1
pinseq=20
}
/projects/logic/ip/uart/doc/geda/drawing/sym/uart_xmit.sym
0,0 → 1,76
v 20100214 1
B 300 0 4100 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
device=uart_xmit
T 400 2250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=txd_data_in[SIZE-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=txd_load
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=txd_break
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=parity
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=force_parity
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=baud_clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 4400 200 4700 200 4 0 1
{
T 4300 200 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 4400 200 5 10 0 1 0 7 1 1
pinseq=9
}
P 4400 400 4700 400 4 0 1
{
T 4300 400 5 10 1 1 0 7 1 1
pinnumber=txd_buffer_empty
T 4400 400 5 10 0 1 0 7 1 1
pinseq=10
}
/projects/logic/ip/uart/doc/geda/drawing/sym/uart_baudgen.sym
0,0 → 1,27
v 20100214 1
B 300 0 2100 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 850 5 10 1 1 0 0 1 1
device=uart_baudgen
T 400 1050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 2400 200 2700 200 4 0 1
{
T 2300 200 5 10 1 1 0 7 1 1
pinnumber=baud_clk_out
T 2400 200 5 10 0 1 0 7 1 1
pinseq=3
}
/projects/logic/ip/uart/doc/geda/drawing/sym/uart_rcvr.sym
0,0 → 1,76
v 20100214 1
B 300 0 3800 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1650 5 10 1 1 0 0 1 1
device=uart_rcvr
T 400 1850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=parity
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=force_parity
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=baud_clk
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=rxd_data_out[SIZE-1:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=7
}
P 4100 400 4400 400 4 0 1
{
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=rxd_stop_error
T 4100 400 5 10 0 1 0 7 1 1
pinseq=8
}
P 4100 600 4400 600 4 0 1
{
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=rxd_parity_error
T 4100 600 5 10 0 1 0 7 1 1
pinseq=9
}
P 4100 800 4400 800 4 0 1
{
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=rxd_buffer_full
T 4100 800 5 10 0 1 0 7 1 1
pinseq=10
}
/projects/logic/ip/uart/doc/geda/drawing/filelist
0,0 → 1,3
 
`include "../../../rtl/gen/syn/uart.v"
 
/projects/logic/ip/uart/doc/geda/drawing/sch/uart_rcvr.sch
0,0 → 1,51
v 20100214 1
C 1400 300 1 0 0 ipad_1.sym
{
T 1400 300 5 10 1 1 0 6 1 1
refdes=rxd_pad_in
}
C 1400 700 1 0 0 ipad_1.sym
{
T 1400 700 5 10 1 1 0 6 1 1
refdes=reset
}
C 1400 1100 1 0 0 ipad_1.sym
{
T 1400 1100 5 10 1 1 0 6 1 1
refdes=parity
}
C 1400 1500 1 0 0 ipad_1.sym
{
T 1400 1500 5 10 1 1 0 6 1 1
refdes=force_parity
}
C 1400 1900 1 0 0 ipad_1.sym
{
T 1400 1900 5 10 1 1 0 6 1 1
refdes=clk
}
C 1400 2300 1 0 0 ipad_1.sym
{
T 1400 2300 5 10 1 1 0 6 1 1
refdes=baud_clk
}
C 4900 300 1 0 0 opad_2.sym
{
T 5900 300 5 10 1 1 0 0 1 1
refdes=rxd_data_out[SIZE-1:0]
}
C 4900 700 1 0 0 opad_1.sym
{
T 5900 700 5 10 1 1 0 0 1 1
refdes=rxd_stop_error
}
C 4900 1100 1 0 0 opad_1.sym
{
T 5900 1100 5 10 1 1 0 0 1 1
refdes=rxd_parity_error
}
C 4900 1500 1 0 0 opad_1.sym
{
T 5900 1500 5 10 1 1 0 0 1 1
refdes=rxd_buffer_full
}
/projects/logic/ip/uart/doc/geda/drawing/sch/uart.sch
0,0 → 1,101
v 20100214 1
C 2300 300 1 0 0 ipad_2.sym
{
T 2300 300 5 10 1 1 0 6 1 1
refdes=txd_data_in[SIZE-1:0]
}
C 2300 700 1 0 0 ipad_1.sym
{
T 2300 700 5 10 1 1 0 6 1 1
refdes=txd_parity
}
C 2300 1100 1 0 0 ipad_1.sym
{
T 2300 1100 5 10 1 1 0 6 1 1
refdes=txd_load
}
C 2300 1500 1 0 0 ipad_1.sym
{
T 2300 1500 5 10 1 1 0 6 1 1
refdes=txd_force_parity
}
C 2300 1900 1 0 0 ipad_1.sym
{
T 2300 1900 5 10 1 1 0 6 1 1
refdes=txd_break
}
C 2300 2300 1 0 0 ipad_1.sym
{
T 2300 2300 5 10 1 1 0 6 1 1
refdes=rxd_parity
}
C 2300 2700 1 0 0 ipad_1.sym
{
T 2300 2700 5 10 1 1 0 6 1 1
refdes=rxd_pad_in
}
C 2300 3100 1 0 0 ipad_1.sym
{
T 2300 3100 5 10 1 1 0 6 1 1
refdes=rxd_force_parity
}
C 2300 3500 1 0 0 ipad_1.sym
{
T 2300 3500 5 10 1 1 0 6 1 1
refdes=rts_in
}
C 2300 3900 1 0 0 ipad_1.sym
{
T 2300 3900 5 10 1 1 0 6 1 1
refdes=reset
}
C 2300 4300 1 0 0 ipad_1.sym
{
T 2300 4300 5 10 1 1 0 6 1 1
refdes=cts_pad_in
}
C 2300 4700 1 0 0 ipad_1.sym
{
T 2300 4700 5 10 1 1 0 6 1 1
refdes=clk
}
C 5800 300 1 0 0 opad_2.sym
{
T 6800 300 5 10 1 1 0 0 1 1
refdes=rxd_data_out[SIZE-1:0]
}
C 5800 700 1 0 0 opad_1.sym
{
T 6800 700 5 10 1 1 0 0 1 1
refdes=txd_pad_out
}
C 5800 1100 1 0 0 opad_1.sym
{
T 6800 1100 5 10 1 1 0 0 1 1
refdes=txd_buffer_empty
}
C 5800 1500 1 0 0 opad_1.sym
{
T 6800 1500 5 10 1 1 0 0 1 1
refdes=rxd_stop_error
}
C 5800 1900 1 0 0 opad_1.sym
{
T 6800 1900 5 10 1 1 0 0 1 1
refdes=rxd_parity_error
}
C 5800 2300 1 0 0 opad_1.sym
{
T 6800 2300 5 10 1 1 0 0 1 1
refdes=rxd_buffer_full
}
C 5800 2700 1 0 0 opad_1.sym
{
T 6800 2700 5 10 1 1 0 0 1 1
refdes=rts_pad_out
}
C 5800 3100 1 0 0 opad_1.sym
{
T 6800 3100 5 10 1 1 0 0 1 1
refdes=cts_out
}
/projects/logic/ip/uart/doc/geda/drawing/sch/uart_xmit.sch
0,0 → 1,51
v 20100214 1
C 2300 300 1 0 0 ipad_2.sym
{
T 2300 300 5 10 1 1 0 6 1 1
refdes=txd_data_in[SIZE-1:0]
}
C 2300 700 1 0 0 ipad_1.sym
{
T 2300 700 5 10 1 1 0 6 1 1
refdes=txd_load
}
C 2300 1100 1 0 0 ipad_1.sym
{
T 2300 1100 5 10 1 1 0 6 1 1
refdes=txd_break
}
C 2300 1500 1 0 0 ipad_1.sym
{
T 2300 1500 5 10 1 1 0 6 1 1
refdes=reset
}
C 2300 1900 1 0 0 ipad_1.sym
{
T 2300 1900 5 10 1 1 0 6 1 1
refdes=parity
}
C 2300 2300 1 0 0 ipad_1.sym
{
T 2300 2300 5 10 1 1 0 6 1 1
refdes=force_parity
}
C 2300 2700 1 0 0 ipad_1.sym
{
T 2300 2700 5 10 1 1 0 6 1 1
refdes=clk
}
C 2300 3100 1 0 0 ipad_1.sym
{
T 2300 3100 5 10 1 1 0 6 1 1
refdes=baud_clk
}
C 5200 300 1 0 0 opad_1.sym
{
T 6200 300 5 10 1 1 0 0 1 1
refdes=txd_pad_out
}
C 5200 700 1 0 0 opad_1.sym
{
T 6200 700 5 10 1 1 0 0 1 1
refdes=txd_buffer_empty
}
/projects/logic/ip/uart/doc/geda/drawing/sch/uart_baudgen.sch
0,0 → 1,16
v 20100214 1
C 700 300 1 0 0 ipad_1.sym
{
T 700 300 5 10 1 1 0 6 1 1
refdes=reset
}
C 700 700 1 0 0 ipad_1.sym
{
T 700 700 5 10 1 1 0 6 1 1
refdes=clk
}
C 3200 300 1 0 0 opad_1.sym
{
T 4200 300 5 10 1 1 0 0 1 1
refdes=baud_clk_out
}
/projects/logic/ip/uart/doc/copyright.v
9,7 → 9,7
// //
// //
// //
// Copyright (C) <2010> <Ouabache DesignWorks> //
// Copyright (C) <2009> <Ouabache DesignWorks> //
// //
// //
// This source file may be used and distributed without //
/projects/logic/ip/uart/sim/run/default/TB.defs
1,6 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 41.6666667
 
 
/projects/logic/ip/uart/sim/run/default/test_define
2,7 → 2,6
 
initial
begin
`TIMEFORMAT
$display(" ");
$display(" ===================================================");
$display("%t Start Test ",$realtime );
9,6 → 8,8
$display(" ===================================================");
$display(" ");
 
parity = 1'b0;
force_parity = 1'b0;
false_start = 1'bz;
 
fork
/projects/logic/ip/uart/sim/run/default/dut
17,6 → 17,9
reg now_load;
reg ready_load;
 
reg parity;
reg force_parity;
 
assign txmit_serial = false_start;
 
 
26,8 → 29,8
dut(
.clk (clk),
.reset (reset),
.parity (1'b0),
.force_parity (1'b0),
.txd_parity (parity),
.txd_force_parity (force_parity),
.txd_data_in (txmit_data_in),
.txd_buffer_empty (txmit_buffer_empty),
.txd_load (txmit_load),
34,10 → 37,11
.txd_break (txd_break),
.txd_pad_out (txmit_serial),
.rxd_pad_in (txmit_serial),
.rxd_parity (parity),
.rxd_force_parity (force_parity),
.rxd_data_out (rcv_buffer),
.rxd_buffer_full (rcv_buffer_full),
.rxd_stop_error (rxd_stop_error),
.rxd_parity (rxd_parity),
.rxd_parity_error (rxd_parity_error),
.cts_pad_in (1'b0),
.rts_pad_out (),
78,8 → 82,8
ua2(
.clk (clk),
.reset (reset),
.parity (1'b0),
.force_parity (1'b0),
.txd_parity (1'b0),
.txd_force_parity (1'b0),
.txd_data_in (data),
.txd_buffer_empty (),
.txd_load (now_load),
87,9 → 91,10
.txd_pad_out (serial),
.rxd_pad_in (txmit_serial),
.rxd_data_out (data),
.rxd_parity (1'b0),
.rxd_force_parity (1'b0),
.rxd_buffer_full (load),
.rxd_stop_error (load_error),
.rxd_parity (),
.rxd_parity_error (),
.cts_pad_in (1'b0),
.rts_pad_out (),
/projects/logic/ip/io_module/rtl/variants/io_module_mouse/io_module_defines.v
1,4 → 1,4
`define VARIENT io_module_mouse
`define VARIANT io_module_mouse
 
`define UART _uart
`define PS2 _ps2
/projects/logic/ip/io_module/rtl/variants/io_module/io_module_defines.v
1,5 → 1,5
 
`define VARIENT io_module
`define VARIANT io_module
`define TIMER _timer
`define GPIO _gpio
`define UART _uart
/projects/logic/ip/io_module/rtl/verilog/io_module.v
1,7 → 1,7
`include "io_module_defines"
 
 
module `VARIENT
module `VARIANT
#(
parameter BASE_ADDR = 8'h80,
parameter BASE_WIDTH = 8,
11,27 → 11,30
)
(
 
input wire clk,
input wire reset,
input wire enable,
input wire clk,
input wire reset,
input wire enable,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
input wire [7:0] wdata,
output wire [7:0] rdata
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
 
 
input wire [ADDR_WIDTH-BASE_WIDTH-1:0] waddr,
input wire [7:0] wdata,
output wire [7:0] rdata
 
`ifdef GPIO
,
output wire [7:0] gpio_0_out ,
output wire [7:0] gpio_0_oe ,
output wire [7:0] gpio_0_lat ,
input wire [7:0] gpio_0_in ,
output wire [7:0] gpio_0_out,
output wire [7:0] gpio_0_oe,
output wire [7:0] gpio_0_lat,
input wire [7:0] gpio_0_in,
 
output wire [7:0] gpio_1_out ,
output wire [7:0] gpio_1_oe ,
output wire [7:0] gpio_1_lat ,
input wire [7:0] gpio_1_in
output wire [7:0] gpio_1_out,
output wire [7:0] gpio_1_oe,
output wire [7:0] gpio_1_lat,
input wire [7:0] gpio_1_in
 
`endif // `ifdef GPIO
 
39,7 → 42,7
`ifdef TIMER
,
output wire [1:0] timer_irq
output wire [1:0] timer_irq
 
`endif
50,37 → 53,37
`ifdef PIC
 
,
output wire pic_irq,
output wire pic_nmi,
input wire [7:0] ext_irq_in
output wire pic_irq,
output wire pic_nmi,
input wire [7:0] ext_irq_in
 
`endif
`ifdef UART
,
output wire txd_pad_out,
input wire rxd_pad_in,
input wire cts_pad_in,
output wire rts_pad_out,
output wire rx_irq,
output wire tx_irq
output wire txd_pad_out,
input wire rxd_pad_in,
input wire cts_pad_in,
output wire rts_pad_out,
output wire rx_irq,
output wire tx_irq
`endif
`ifdef PS2
,
output wire ps2_clk_oe,
input wire ps2_clk_in,
output wire ps2_data_oe,
input wire ps2_data_in,
output wire ps2_data_avail,
output wire ps2_clk_oe,
input wire ps2_clk_in,
output wire ps2_data_oe,
input wire ps2_data_in,
output wire ps2_data_avail,
 
 
output wire [9:0] y_pos,
output wire [9:0] x_pos,
output wire new_packet,
output wire ms_mid,
output wire ms_right,
output wire ms_left
output wire [9:0] y_pos,
output wire [9:0] x_pos,
output wire new_packet,
output wire ms_mid,
output wire ms_right,
output wire ms_left
 
 
127,7 → 130,7
 
`ifdef GPIO
 
`VARIENT`GPIO
`VARIANT`GPIO
#(.BASE_ADDR(4'h0),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
139,7 → 142,8
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( gpio_rdata ),
.gpio_0_out ( gpio_0_out ),
162,7 → 166,7
`ifdef TIMER
 
`VARIENT`TIMER
`VARIANT`TIMER
#(.BASE_ADDR(4'h1),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
174,7 → 178,8
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( timer_rdata ),
.irq ( timer_irq )
193,7 → 198,7
 
 
`VARIENT`UART
`VARIANT`UART
#(.BASE_ADDR(4'h2),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
205,7 → 210,8
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( uart_rdata ),
.txd_pad_out ( txd_pad_out ),
230,7 → 236,7
 
 
`VARIENT`PIC
`VARIANT`PIC
#(.BASE_ADDR(4'h3),
.BASE_WIDTH(4),
.ADDR_WIDTH(8),
244,7 → 250,8
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( pic_rdata ),
.int_in ( ext_irq_in ),
264,7 → 271,7
`ifdef PS2
 
`VARIENT`PS2
`VARIANT`PS2
#(.BASE_ADDR(4'h4),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
276,7 → 283,8
.cs ( cs && enable ),
.wr ( wr ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( ps2_rdata ),
.rcv_data_avail ( ps2_data_avail ),
306,7 → 314,7
`ifdef UTIMER
 
 
`VARIENT`UTIMER
`VARIANT`UTIMER
#(.BASE_ADDR(4'h5),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
318,7 → 326,8
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.addr ( addr[7:0] ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( utim_rdata )
 
/projects/logic/ip/io_module/rtl/verilog/io_module_timer.v
3,7 → 3,7
`ifdef TIMER
 
 
module `VARIENT`TIMER
module `VARIANT`TIMER
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8,
15,7 → 15,9
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
output reg [TIMERS-1:0] irq
44,15 → 46,15
 
 
reg as;
reg was;
reg ras;
 
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(addr) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
reg [7:0] count_0;
reg [2:0] state_0;
 
61,9 → 63,9
 
 
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
TIMER_0_START: rdata = {4'h0,irq,state_0[2:0]};
TIMER_0_COUNT: rdata = count_0[7:0];
TIMER_1_START: rdata = {4'h0,irq,state_1[2:0]};
102,7 → 104,7
case (state_0)
(IDLE):
if(wr && as && cs && addr[3:0] == TIMER_0_START)
if(wr && was && cs && waddr[3:0] == TIMER_0_START)
begin
state_0 <= RUNNING;
count_0 <= wdata;
126,7 → 128,7
end
 
(TRIGGERED):
if(wr && as && cs && addr[3:0] == TIMER_0_END)
if(wr && was && cs && waddr[3:0] == TIMER_0_END)
begin
state_0 <= IDLE;
count_0 <= 8'h00;
158,7 → 160,7
case (state_1)
(IDLE):
if(wr && as && cs && addr[3:0] == TIMER_1_START)
if(wr && was && cs && waddr[3:0] == TIMER_1_START)
begin
state_1 <= RUNNING;
count_1 <= wdata;
182,7 → 184,7
end
 
(TRIGGERED):
if(wr && as && cs && addr[3:0] == TIMER_1_END)
if(wr && was && cs && waddr[3:0] == TIMER_1_END)
begin
state_1 <= IDLE;
count_1 <= 8'h00;
/projects/logic/ip/io_module/rtl/verilog/io_module_ps2.v
3,7 → 3,7
`ifdef PS2
 
 
module `VARIENT`PS2
module `VARIANT`PS2
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
15,7 → 15,8
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] addr,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
output wire rcv_data_avail,
45,7 → 46,9
parameter Y_POS = 4'h8;
 
reg as;
reg was;
reg ras;
reg [7:0] cntrl;
reg [7:0] wdata_buf;
wire [7:0] rcv_data;
63,12 → 66,15
 
always@(*) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
PS2_DATA: rdata = rcv_data;
STATUS: rdata = {
1'b0,
98,7 → 104,7
always@(posedge clk)
if(reset) wdata_buf <= 8'h00;
else
if( wr &&as && cs && addr[3:0] == PS2_DATA)
if( wr &&was && cs && waddr[3:0] == PS2_DATA)
wdata_buf <= wdata;
else
wdata_buf <= wdata_buf;
108,7 → 114,7
always@(posedge clk)
if(reset) cntrl <= 8'h00;
else
if( wr &&as && cs && addr[3:0] == CNTRL)
if( wr &&was && cs && waddr[3:0] == CNTRL)
cntrl <= wdata;
else cntrl <= cntrl;
 
144,7 → 150,7
.rx_parity_rcv ( rx_parity_rcv ),
.rx_parity_cal ( rx_parity_cal ),
.rx_frame_error ( rx_frame_error ),
.clr_rx_full ( cntrl[0] ? read :rd && as && cs && (addr[3:0] == PS2_DATA)),
.clr_rx_full ( cntrl[0] ? read :rd && ras && cs && (raddr[3:0] == PS2_DATA)),
.tx_ack_error ( tx_ack_error )
);
 
234,15 → 240,6
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
/projects/logic/ip/io_module/rtl/verilog/io_module_utimer.v
4,7 → 4,7
 
 
 
module `VARIENT`UTIMER
module `VARIANT`UTIMER
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8,
18,7 → 18,9
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata
);
26,26 → 28,26
parameter TIMER_LATCH = 4'h0;
parameter TIMER_COUNT = 4'h2;
 
 
reg ras;
reg was;
reg [7:0] count;
reg [7:0] latch;
reg as;
 
reg [5:0] u_sec;
 
 
always@( posedge clk)
if(reset) u_sec <= FREQ-1;
else
if((u_sec == 0) || (wr && as && cs && addr[3:0] == TIMER_COUNT) ) u_sec <= FREQ-1;
else u_sec <= u_sec-1;
 
always@(waddr) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(raddr) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(addr) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
TIMER_LATCH: rdata = latch[7:0];
TIMER_COUNT: rdata = count[7:0];
default: rdata = 8'h00;
52,29 → 54,40
endcase
end
else rdata = 8'hFF;
 
 
 
always@( posedge clk)
if(reset) u_sec <= FREQ-1;
else
if((u_sec == 0) || (wr && was && cs && waddr[3:0] == TIMER_COUNT) ) u_sec <= FREQ-1;
else u_sec <= u_sec-1;
 
 
 
always@(posedge clk)
if (reset) latch <= 8'h00;
if (reset) latch <= 8'h00;
else
if(wr && as && cs && addr[3:0] == TIMER_LATCH) latch <= wdata;
else latch <= latch;
if(wr && was && cs && waddr[3:0] == TIMER_LATCH) latch <= wdata;
else latch <= latch;
 
 
 
always@(posedge clk)
if (reset) count <= 8'h00;
if (reset) count <= 8'h00;
else
if(wr && as && cs && addr[3:0] == TIMER_COUNT) count <= wdata;
if(wr && was && cs && waddr[3:0] == TIMER_COUNT) count <= wdata;
else
if(u_sec == 0)
begin
if(count == 8'h00) count <= 8'h00;
if(count == 8'h00) count <= 8'h00;
else
if(count == 8'h01) count <= latch;
else count <= count-1;
if(count == 8'h01) count <= latch;
else count <= count-1;
end
else count <= count;
else count <= count;
 
 
 
/projects/logic/ip/io_module/rtl/verilog/io_module_pic.v
2,7 → 2,7
 
`ifdef PIC
 
module `VARIENT`PIC
module `VARIANT`PIC
 
#(
parameter BASE_ADDR = 4'h0,
20,7 → 20,8
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
46,14 → 47,18
parameter NMI_ACT = 4'h4;
 
 
reg as;
reg was;
reg ras;
 
always@(*) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
INT_IN: rdata = int_in;
IRQ_ENABLE: rdata = irq_enable;
NMI_ENABLE: rdata = nmi_enable;
77,12 → 82,12
nmi_out <= 1'b0;
end
else
if(wr &&as && cs && addr[3:0] == IRQ_ENABLE)
if(wr && was && cs && waddr[3:0] == IRQ_ENABLE)
begin
irq_enable <= wdata;
end
else
if(wr &&as && cs && addr[3:0] == NMI_ENABLE)
if(wr && was && cs && waddr[3:0] == NMI_ENABLE)
begin
nmi_enable <= wdata;
end
/projects/logic/ip/io_module/rtl/verilog/io_module_uart.v
2,7 → 2,7
 
`ifdef UART
 
module `VARIENT`UART
module `VARIANT`UART
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
14,7 → 14,8
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] addr,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
output wire txd_pad_out,
34,7 → 35,9
parameter CNTRL = 4'h4;
parameter STATUS = 4'h6;
reg as;
reg was;
reg ras;
wire [7:0] rcv_data;
reg [7:0] cntrl;
reg load;
44,12 → 47,14
 
always@(*) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
RCV_DATA: rdata = rcv_data;
CNTRL: rdata = cntrl;
STATUS: rdata = {status[7:1],rx_data_avail};
66,12 → 71,12
load <= 1'b0;
end
else
if(wr && as && cs && addr[3:0] == CNTRL)
if(wr && was && cs && waddr[3:0] == CNTRL)
begin
cntrl <= wdata;
end
else
if(wr &&as && cs && addr[3:0] == XMIT_DATA)
if(wr && was && cs && waddr[3:0] == XMIT_DATA)
begin
load <= 1'b1;
87,12 → 92,12
 
 
always@(posedge clk)
if (reset) rx_data_avail <= 1'b0;
if (reset) rx_data_avail <= 1'b0;
else
if(rxd_buffer_full) rx_data_avail <= 1'b1;
if(rxd_buffer_full) rx_data_avail <= 1'b1;
else
if(rd && as && cs && (addr[3:0] == RCV_DATA)) rx_data_avail <= 1'b0;
else rx_data_avail <= rx_data_avail;
if(rd && was && cs && (waddr[3:0] == RCV_DATA)) rx_data_avail <= 1'b0;
else rx_data_avail <= rx_data_avail;
 
 
 
107,39 → 112,34
 
 
assign status[2] = 1'b0;
 
 
uart
uart(
.clk (clk),
.reset (reset),
.parity (cntrl[0]),
.force_parity (cntrl[1]),
.txd_break (cntrl[2]),
.rts_in (cntrl[3]),
.txd_data_in (wdata),
.txd_load (load),
.rxd_data_out (rcv_data),
.rxd_buffer_full (rxd_buffer_full),
.rxd_stop_error (status[1]),
.rxd_parity (status[2]),
.rxd_parity_error (status[3]),
.cts_out (status[4]),
.txd_buffer_empty (status[5]),
.txd_pad_out (txd_pad_out),
.rxd_pad_in (rxd_pad_in),
.cts_pad_in (cts_pad_in),
.rts_pad_out (rts_pad_out)
 
.clk ( clk ),
.reset ( reset ),
.txd_parity ( cntrl[0] ),
.txd_force_parity ( cntrl[1] ),
.txd_break ( cntrl[2] ),
.rts_in ( cntrl[3] ),
.txd_data_in ( wdata ),
.txd_load ( load ),
.rxd_data_out ( rcv_data ),
.rxd_parity ( cntrl[0] ),
.rxd_force_parity ( cntrl[1] ),
.rxd_buffer_full ( rxd_buffer_full ),
.rxd_stop_error ( status[1] ),
.rxd_parity_error ( status[3] ),
.cts_out ( status[4] ),
.txd_buffer_empty ( status[5] ),
.txd_pad_out ( txd_pad_out ),
.rxd_pad_in ( rxd_pad_in ),
.cts_pad_in ( cts_pad_in ),
.rts_pad_out ( rts_pad_out )
);
 
 
 
 
 
 
 
endmodule
 
/projects/logic/ip/io_module/rtl/verilog/io_module_gpio.v
3,7 → 3,7
 
`ifdef GPIO
 
module `VARIENT`GPIO
module `VARIANT`GPIO
 
#(
parameter BASE_ADDR = 4'h0,
19,7 → 19,8
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] addr,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
52,14 → 53,18
 
 
reg as;
reg ras;
reg was;
always@(*) as = (addr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
always@(*)
if(rd && cs && as)
if(rd && cs && ras)
begin
case(addr[3:0])
case(raddr[3:0])
GPIO_0_OUT: rdata = gpio_0_out;
GPIO_0_OE: rdata = gpio_0_oe;
GPIO_0_IN: rdata = gpio_0_lat;
81,22 → 86,22
gpio_1_oe <= 8'h00;
end
else
if(wr && as && cs && (addr[3:0] == GPIO_0_OUT))
if(wr && was && cs && (waddr[3:0] == GPIO_0_OUT))
begin
gpio_0_out <= wdata;
end
else
if(wr && as && cs && (addr[3:0] == GPIO_0_OE))
if(wr && was && cs && (waddr[3:0] == GPIO_0_OE))
begin
gpio_0_oe <= wdata;
end
else
if(wr && as && cs && (addr[3:0] == GPIO_1_OUT))
if(wr && was && cs && (waddr[3:0] == GPIO_1_OUT))
begin
gpio_1_out <= wdata;
end
else
if(wr && as && cs && (addr[3:0] == GPIO_1_OE))
if(wr && was && cs && (waddr[3:0] == GPIO_1_OE))
begin
gpio_1_oe <= wdata;
end
/projects/logic/ip/io_module/doc/geda/drawing/sym/ps2_interface_fsm.sym
0,0 → 1,118
v 20100214 1
B 300 0 3600 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2250 5 10 1 1 0 0 1 1
device=ps2_interface_fsm
T 400 2450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=bit_count[3:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=usec_delay_done
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_idle
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_fall
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=frame0
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=force_startbit
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3900 200 4200 200 4 0 1
{
T 3800 200 5 10 1 1 0 7 1 1
pinnumber=shift_frame
T 3900 200 5 10 0 1 0 7 1 1
pinseq=10
}
P 3900 400 4200 400 4 0 1
{
T 3800 400 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3900 400 5 10 0 1 0 7 1 1
pinseq=11
}
P 3900 600 4200 600 4 0 1
{
T 3800 600 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3900 600 5 10 0 1 0 7 1 1
pinseq=12
}
P 3900 800 4200 800 4 0 1
{
T 3800 800 5 10 1 1 0 7 1 1
pinnumber=load_tx_data
T 3900 800 5 10 0 1 0 7 1 1
pinseq=13
}
P 3900 1000 4200 1000 4 0 1
{
T 3800 1000 5 10 1 1 0 7 1 1
pinnumber=load_rx_data
T 3900 1000 5 10 0 1 0 7 1 1
pinseq=14
}
P 3900 1200 4200 1200 4 0 1
{
T 3800 1200 5 10 1 1 0 7 1 1
pinnumber=enable_usec_delay
T 3900 1200 5 10 0 1 0 7 1 1
pinseq=15
}
P 3900 1400 4200 1400 4 0 1
{
T 3800 1400 5 10 1 1 0 7 1 1
pinnumber=busy
T 3900 1400 5 10 0 1 0 7 1 1
pinseq=16
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_gpio.sym
0,0 → 1,125
v 20100214 1
B 300 0 4000 2300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2450 5 10 1 1 0 0 1 1
device=io_module_gpio
T 400 2650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[ADDR_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[ADDR_WIDTH-1:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=gpio_1_in[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=gpio_0_in[7:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 4300 200 4600 200 10 1 1
{
T 4200 200 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 4200 200 5 10 0 1 0 7 1 1
pinseq=11
}
P 4300 400 4600 400 10 1 1
{
T 4200 400 5 10 1 1 0 7 1 1
pinnumber=gpio_1_out[7:0]
T 4200 400 5 10 0 1 0 7 1 1
pinseq=12
}
P 4300 600 4600 600 10 1 1
{
T 4200 600 5 10 1 1 0 7 1 1
pinnumber=gpio_1_oe[7:0]
T 4200 600 5 10 0 1 0 7 1 1
pinseq=13
}
P 4300 800 4600 800 10 1 1
{
T 4200 800 5 10 1 1 0 7 1 1
pinnumber=gpio_1_lat[7:0]
T 4200 800 5 10 0 1 0 7 1 1
pinseq=14
}
P 4300 1000 4600 1000 10 1 1
{
T 4200 1000 5 10 1 1 0 7 1 1
pinnumber=gpio_0_out[7:0]
T 4200 1000 5 10 0 1 0 7 1 1
pinseq=15
}
P 4300 1200 4600 1200 10 1 1
{
T 4200 1200 5 10 1 1 0 7 1 1
pinnumber=gpio_0_oe[7:0]
T 4200 1200 5 10 0 1 0 7 1 1
pinseq=16
}
P 4300 1400 4600 1400 10 1 1
{
T 4200 1400 5 10 1 1 0 7 1 1
pinnumber=gpio_0_lat[7:0]
T 4200 1400 5 10 0 1 0 7 1 1
pinseq=17
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/uart.sym
0,0 → 1,146
v 20100214 1
B 300 0 4700 2700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2850 5 10 1 1 0 0 1 1
device=uart
T 400 3050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=txd_data_in[SIZE-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=txd_parity
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=txd_load
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=txd_force_parity
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=txd_break
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rxd_parity
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=rxd_force_parity
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=rts_in
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=cts_pad_in
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
P 5000 200 5300 200 10 1 1
{
T 4900 200 5 10 1 1 0 7 1 1
pinnumber=rxd_data_out[SIZE-1:0]
T 4900 200 5 10 0 1 0 7 1 1
pinseq=13
}
P 5000 400 5300 400 4 0 1
{
T 4900 400 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 5000 400 5 10 0 1 0 7 1 1
pinseq=14
}
P 5000 600 5300 600 4 0 1
{
T 4900 600 5 10 1 1 0 7 1 1
pinnumber=txd_buffer_empty
T 5000 600 5 10 0 1 0 7 1 1
pinseq=15
}
P 5000 800 5300 800 4 0 1
{
T 4900 800 5 10 1 1 0 7 1 1
pinnumber=rxd_stop_error
T 5000 800 5 10 0 1 0 7 1 1
pinseq=16
}
P 5000 1000 5300 1000 4 0 1
{
T 4900 1000 5 10 1 1 0 7 1 1
pinnumber=rxd_parity_error
T 5000 1000 5 10 0 1 0 7 1 1
pinseq=17
}
P 5000 1200 5300 1200 4 0 1
{
T 4900 1200 5 10 1 1 0 7 1 1
pinnumber=rxd_buffer_full
T 5000 1200 5 10 0 1 0 7 1 1
pinseq=18
}
P 5000 1400 5300 1400 4 0 1
{
T 4900 1400 5 10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 5000 1400 5 10 0 1 0 7 1 1
pinseq=19
}
P 5000 1600 5300 1600 4 0 1
{
T 4900 1600 5 10 1 1 0 7 1 1
pinnumber=cts_out
T 5000 1600 5 10 0 1 0 7 1 1
pinseq=20
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/uart_xmit.sym
0,0 → 1,76
v 20100214 1
B 300 0 4100 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
device=uart_xmit
T 400 2250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=txd_data_in[SIZE-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=txd_load
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=txd_break
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=parity
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=force_parity
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=baud_clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 4400 200 4700 200 4 0 1
{
T 4300 200 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 4400 200 5 10 0 1 0 7 1 1
pinseq=9
}
P 4400 400 4700 400 4 0 1
{
T 4300 400 5 10 1 1 0 7 1 1
pinnumber=txd_buffer_empty
T 4400 400 5 10 0 1 0 7 1 1
pinseq=10
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_timer.sym
0,0 → 1,76
v 20100214 1
B 300 0 4000 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
device=io_module_timer
T 400 2250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[ADDR_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[ADDR_WIDTH-1:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 4300 200 4600 200 10 1 1
{
T 4200 200 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 4200 200 5 10 0 1 0 7 1 1
pinseq=9
}
P 4300 400 4600 400 10 1 1
{
T 4200 400 5 10 1 1 0 7 1 1
pinnumber=irq[TIMERS-1:0]
T 4200 400 5 10 0 1 0 7 1 1
pinseq=10
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module.sym
0,0 → 1,272
v 20100214 1
B 300 0 5100 4900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 5050 5 10 1 1 0 0 1 1
device=io_module
T 400 5250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[ADDR_WIDTH-BASE_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=gpio_1_in[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=gpio_0_in[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 10 1 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ext_irq_in[7:0]
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 10 1 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=addr[ADDR_WIDTH-1:0]
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 300 2200 0 2200 4 0 1
{
T 400 2200 5 10 1 1 0 1 1 1
pinnumber=ps2_data_in
T 400 2200 5 10 0 1 0 1 1 1
pinseq=11
}
P 300 2400 0 2400 4 0 1
{
T 400 2400 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_in
T 400 2400 5 10 0 1 0 1 1 1
pinseq=12
}
P 300 2600 0 2600 4 0 1
{
T 400 2600 5 10 1 1 0 1 1 1
pinnumber=enable
T 400 2600 5 10 0 1 0 1 1 1
pinseq=13
}
P 300 2800 0 2800 4 0 1
{
T 400 2800 5 10 1 1 0 1 1 1
pinnumber=cts_pad_in
T 400 2800 5 10 0 1 0 1 1 1
pinseq=14
}
P 300 3000 0 3000 4 0 1
{
T 400 3000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 3000 5 10 0 1 0 1 1 1
pinseq=15
}
P 5400 200 5700 200 10 1 1
{
T 5300 200 5 10 1 1 0 7 1 1
pinnumber=y_pos[9:0]
T 5300 200 5 10 0 1 0 7 1 1
pinseq=16
}
P 5400 400 5700 400 10 1 1
{
T 5300 400 5 10 1 1 0 7 1 1
pinnumber=x_pos[9:0]
T 5300 400 5 10 0 1 0 7 1 1
pinseq=17
}
P 5400 600 5700 600 10 1 1
{
T 5300 600 5 10 1 1 0 7 1 1
pinnumber=timer_irq[1:0]
T 5300 600 5 10 0 1 0 7 1 1
pinseq=18
}
P 5400 800 5700 800 10 1 1
{
T 5300 800 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 5300 800 5 10 0 1 0 7 1 1
pinseq=19
}
P 5400 1000 5700 1000 10 1 1
{
T 5300 1000 5 10 1 1 0 7 1 1
pinnumber=gpio_1_out[7:0]
T 5300 1000 5 10 0 1 0 7 1 1
pinseq=20
}
P 5400 1200 5700 1200 10 1 1
{
T 5300 1200 5 10 1 1 0 7 1 1
pinnumber=gpio_1_oe[7:0]
T 5300 1200 5 10 0 1 0 7 1 1
pinseq=21
}
P 5400 1400 5700 1400 10 1 1
{
T 5300 1400 5 10 1 1 0 7 1 1
pinnumber=gpio_1_lat[7:0]
T 5300 1400 5 10 0 1 0 7 1 1
pinseq=22
}
P 5400 1600 5700 1600 10 1 1
{
T 5300 1600 5 10 1 1 0 7 1 1
pinnumber=gpio_0_out[7:0]
T 5300 1600 5 10 0 1 0 7 1 1
pinseq=23
}
P 5400 1800 5700 1800 10 1 1
{
T 5300 1800 5 10 1 1 0 7 1 1
pinnumber=gpio_0_oe[7:0]
T 5300 1800 5 10 0 1 0 7 1 1
pinseq=24
}
P 5400 2000 5700 2000 10 1 1
{
T 5300 2000 5 10 1 1 0 7 1 1
pinnumber=gpio_0_lat[7:0]
T 5300 2000 5 10 0 1 0 7 1 1
pinseq=25
}
P 5400 2200 5700 2200 4 0 1
{
T 5300 2200 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 5400 2200 5 10 0 1 0 7 1 1
pinseq=26
}
P 5400 2400 5700 2400 4 0 1
{
T 5300 2400 5 10 1 1 0 7 1 1
pinnumber=tx_irq
T 5400 2400 5 10 0 1 0 7 1 1
pinseq=27
}
P 5400 2600 5700 2600 4 0 1
{
T 5300 2600 5 10 1 1 0 7 1 1
pinnumber=rx_irq
T 5400 2600 5 10 0 1 0 7 1 1
pinseq=28
}
P 5400 2800 5700 2800 4 0 1
{
T 5300 2800 5 10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 5400 2800 5 10 0 1 0 7 1 1
pinseq=29
}
P 5400 3000 5700 3000 4 0 1
{
T 5300 3000 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 5400 3000 5 10 0 1 0 7 1 1
pinseq=30
}
P 5400 3200 5700 3200 4 0 1
{
T 5300 3200 5 10 1 1 0 7 1 1
pinnumber=ps2_data_avail
T 5400 3200 5 10 0 1 0 7 1 1
pinseq=31
}
P 5400 3400 5700 3400 4 0 1
{
T 5300 3400 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 5400 3400 5 10 0 1 0 7 1 1
pinseq=32
}
P 5400 3600 5700 3600 4 0 1
{
T 5300 3600 5 10 1 1 0 7 1 1
pinnumber=pic_nmi
T 5400 3600 5 10 0 1 0 7 1 1
pinseq=33
}
P 5400 3800 5700 3800 4 0 1
{
T 5300 3800 5 10 1 1 0 7 1 1
pinnumber=pic_irq
T 5400 3800 5 10 0 1 0 7 1 1
pinseq=34
}
P 5400 4000 5700 4000 4 0 1
{
T 5300 4000 5 10 1 1 0 7 1 1
pinnumber=new_packet
T 5400 4000 5 10 0 1 0 7 1 1
pinseq=35
}
P 5400 4200 5700 4200 4 0 1
{
T 5300 4200 5 10 1 1 0 7 1 1
pinnumber=ms_right
T 5400 4200 5 10 0 1 0 7 1 1
pinseq=36
}
P 5400 4400 5700 4400 4 0 1
{
T 5300 4400 5 10 1 1 0 7 1 1
pinnumber=ms_mid
T 5400 4400 5 10 0 1 0 7 1 1
pinseq=37
}
P 5400 4600 5700 4600 4 0 1
{
T 5300 4600 5 10 1 1 0 7 1 1
pinnumber=ms_left
T 5400 4600 5 10 0 1 0 7 1 1
pinseq=38
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/uart_baudgen.sym
0,0 → 1,27
v 20100214 1
B 300 0 2100 700 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 850 5 10 1 1 0 0 1 1
device=uart_baudgen
T 400 1050 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 2400 200 2700 200 4 0 1
{
T 2300 200 5 10 1 1 0 7 1 1
pinnumber=baud_clk_out
T 2400 200 5 10 0 1 0 7 1 1
pinseq=3
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_ps2.sym
0,0 → 1,146
v 20100214 1
B 300 0 2900 2300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2450 5 10 1 1 0 0 1 1
device=io_module_ps2
T 400 2650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=ps2_data_in
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_in
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 3200 200 3500 200 10 1 1
{
T 3100 200 5 10 1 1 0 7 1 1
pinnumber=y_pos[9:0]
T 3100 200 5 10 0 1 0 7 1 1
pinseq=11
}
P 3200 400 3500 400 10 1 1
{
T 3100 400 5 10 1 1 0 7 1 1
pinnumber=x_pos[9:0]
T 3100 400 5 10 0 1 0 7 1 1
pinseq=12
}
P 3200 600 3500 600 10 1 1
{
T 3100 600 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 3100 600 5 10 0 1 0 7 1 1
pinseq=13
}
P 3200 800 3500 800 4 0 1
{
T 3100 800 5 10 1 1 0 7 1 1
pinnumber=rcv_data_avail
T 3200 800 5 10 0 1 0 7 1 1
pinseq=14
}
P 3200 1000 3500 1000 4 0 1
{
T 3100 1000 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3200 1000 5 10 0 1 0 7 1 1
pinseq=15
}
P 3200 1200 3500 1200 4 0 1
{
T 3100 1200 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3200 1200 5 10 0 1 0 7 1 1
pinseq=16
}
P 3200 1400 3500 1400 4 0 1
{
T 3100 1400 5 10 1 1 0 7 1 1
pinnumber=new_packet
T 3200 1400 5 10 0 1 0 7 1 1
pinseq=17
}
P 3200 1600 3500 1600 4 0 1
{
T 3100 1600 5 10 1 1 0 7 1 1
pinnumber=ms_right
T 3200 1600 5 10 0 1 0 7 1 1
pinseq=18
}
P 3200 1800 3500 1800 4 0 1
{
T 3100 1800 5 10 1 1 0 7 1 1
pinnumber=ms_mid
T 3200 1800 5 10 0 1 0 7 1 1
pinseq=19
}
P 3200 2000 3500 2000 4 0 1
{
T 3100 2000 5 10 1 1 0 7 1 1
pinnumber=ms_left
T 3200 2000 5 10 0 1 0 7 1 1
pinseq=20
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_utimer.sym
0,0 → 1,69
v 20100214 1
B 300 0 3500 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2050 5 10 1 1 0 0 1 1
device=io_module_utimer
T 400 2250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[ADDR_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[ADDR_WIDTH-1:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 3800 200 4100 200 10 1 1
{
T 3700 200 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 3700 200 5 10 0 1 0 7 1 1
pinseq=9
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/ps2_interface.sym
0,0 → 1,132
v 20100214 1
B 300 0 3100 2500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2650 5 10 1 1 0 0 1 1
device=ps2_interface
T 400 2850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=tx_data[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=write
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=ps2_data_in
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=ps2_clk_in
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=clr_rx_full
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 3400 200 3700 200 10 1 1
{
T 3300 200 5 10 1 1 0 7 1 1
pinnumber=rx_data[7:0]
T 3300 200 5 10 0 1 0 7 1 1
pinseq=8
}
P 3400 400 3700 400 4 0 1
{
T 3300 400 5 10 1 1 0 7 1 1
pinnumber=tx_ack_error
T 3400 400 5 10 0 1 0 7 1 1
pinseq=9
}
P 3400 600 3700 600 4 0 1
{
T 3300 600 5 10 1 1 0 7 1 1
pinnumber=rx_parity_rcv
T 3400 600 5 10 0 1 0 7 1 1
pinseq=10
}
P 3400 800 3700 800 4 0 1
{
T 3300 800 5 10 1 1 0 7 1 1
pinnumber=rx_parity_error
T 3400 800 5 10 0 1 0 7 1 1
pinseq=11
}
P 3400 1000 3700 1000 4 0 1
{
T 3300 1000 5 10 1 1 0 7 1 1
pinnumber=rx_parity_cal
T 3400 1000 5 10 0 1 0 7 1 1
pinseq=12
}
P 3400 1200 3700 1200 4 0 1
{
T 3300 1200 5 10 1 1 0 7 1 1
pinnumber=rx_full
T 3400 1200 5 10 0 1 0 7 1 1
pinseq=13
}
P 3400 1400 3700 1400 4 0 1
{
T 3300 1400 5 10 1 1 0 7 1 1
pinnumber=rx_frame_error
T 3400 1400 5 10 0 1 0 7 1 1
pinseq=14
}
P 3400 1600 3700 1600 4 0 1
{
T 3300 1600 5 10 1 1 0 7 1 1
pinnumber=read
T 3400 1600 5 10 0 1 0 7 1 1
pinseq=15
}
P 3400 1800 3700 1800 4 0 1
{
T 3300 1800 5 10 1 1 0 7 1 1
pinnumber=ps2_data_oe
T 3400 1800 5 10 0 1 0 7 1 1
pinseq=16
}
P 3400 2000 3700 2000 4 0 1
{
T 3300 2000 5 10 1 1 0 7 1 1
pinnumber=ps2_clk_oe
T 3400 2000 5 10 0 1 0 7 1 1
pinseq=17
}
P 3400 2200 3700 2200 4 0 1
{
T 3300 2200 5 10 1 1 0 7 1 1
pinnumber=busy
T 3400 2200 5 10 0 1 0 7 1 1
pinseq=18
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/cde_sync_with_hysteresis.sym
0,0 → 1,48
v 20100214 1
B 300 0 4200 900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1050 5 10 1 1 0 0 1 1
device=cde_sync_with_hysteresis
T 400 1250 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=data_in[WIDTH-1:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 4500 200 4800 200 10 1 1
{
T 4400 200 5 10 1 1 0 7 1 1
pinnumber=data_rise[WIDTH-1:0]
T 4400 200 5 10 0 1 0 7 1 1
pinseq=4
}
P 4500 400 4800 400 10 1 1
{
T 4400 400 5 10 1 1 0 7 1 1
pinnumber=data_out[WIDTH-1:0]
T 4400 400 5 10 0 1 0 7 1 1
pinseq=5
}
P 4500 600 4800 600 10 1 1
{
T 4400 600 5 10 1 1 0 7 1 1
pinnumber=data_fall[WIDTH-1:0]
T 4400 600 5 10 0 1 0 7 1 1
pinseq=6
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_pic.sym
0,0 → 1,90
v 20100214 1
B 300 0 3500 2100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2250 5 10 1 1 0 0 1 1
device=io_module_pic
T 400 2450 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[ADDR_WIDTH-1:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[ADDR_WIDTH-1:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 10 1 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=int_in[7:0]
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 3800 200 4100 200 10 1 1
{
T 3700 200 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 3700 200 5 10 0 1 0 7 1 1
pinseq=10
}
P 3800 400 4100 400 4 0 1
{
T 3700 400 5 10 1 1 0 7 1 1
pinnumber=nmi_out
T 3800 400 5 10 0 1 0 7 1 1
pinseq=11
}
P 3800 600 4100 600 4 0 1
{
T 3700 600 5 10 1 1 0 7 1 1
pinnumber=irq_out
T 3800 600 5 10 0 1 0 7 1 1
pinseq=12
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/io_module_uart.sym
0,0 → 1,111
v 20100214 1
B 300 0 2500 2300 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 2450 5 10 1 1 0 0 1 1
device=io_module_uart
T 400 2650 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 10 1 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=wdata[7:0]
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 10 1 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=waddr[7:0]
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 10 1 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=raddr[7:0]
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=wr
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 300 1400 0 1400 4 0 1
{
T 400 1400 5 10 1 1 0 1 1 1
pinnumber=rd
T 400 1400 5 10 0 1 0 1 1 1
pinseq=7
}
P 300 1600 0 1600 4 0 1
{
T 400 1600 5 10 1 1 0 1 1 1
pinnumber=cts_pad_in
T 400 1600 5 10 0 1 0 1 1 1
pinseq=8
}
P 300 1800 0 1800 4 0 1
{
T 400 1800 5 10 1 1 0 1 1 1
pinnumber=cs
T 400 1800 5 10 0 1 0 1 1 1
pinseq=9
}
P 300 2000 0 2000 4 0 1
{
T 400 2000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 2000 5 10 0 1 0 1 1 1
pinseq=10
}
P 2800 200 3100 200 10 1 1
{
T 2700 200 5 10 1 1 0 7 1 1
pinnumber=rdata[7:0]
T 2700 200 5 10 0 1 0 7 1 1
pinseq=11
}
P 2800 400 3100 400 4 0 1
{
T 2700 400 5 10 1 1 0 7 1 1
pinnumber=txd_pad_out
T 2800 400 5 10 0 1 0 7 1 1
pinseq=12
}
P 2800 600 3100 600 4 0 1
{
T 2700 600 5 10 1 1 0 7 1 1
pinnumber=tx_irq
T 2800 600 5 10 0 1 0 7 1 1
pinseq=13
}
P 2800 800 3100 800 4 0 1
{
T 2700 800 5 10 1 1 0 7 1 1
pinnumber=rx_irq
T 2800 800 5 10 0 1 0 7 1 1
pinseq=14
}
P 2800 1000 3100 1000 4 0 1
{
T 2700 1000 5 10 1 1 0 7 1 1
pinnumber=rts_pad_out
T 2800 1000 5 10 0 1 0 7 1 1
pinseq=15
}
/projects/logic/ip/io_module/doc/geda/drawing/sym/uart_rcvr.sym
0,0 → 1,76
v 20100214 1
B 300 0 3800 1500 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 1650 5 10 1 1 0 0 1 1
device=uart_rcvr
T 400 1850 8 10 1 1 0 0 1 1
refdes=U?
P 300 200 0 200 4 0 1
{
T 400 200 5 10 1 1 0 1 1 1
pinnumber=rxd_pad_in
T 400 200 5 10 0 1 0 1 1 1
pinseq=1
}
P 300 400 0 400 4 0 1
{
T 400 400 5 10 1 1 0 1 1 1
pinnumber=reset
T 400 400 5 10 0 1 0 1 1 1
pinseq=2
}
P 300 600 0 600 4 0 1
{
T 400 600 5 10 1 1 0 1 1 1
pinnumber=parity
T 400 600 5 10 0 1 0 1 1 1
pinseq=3
}
P 300 800 0 800 4 0 1
{
T 400 800 5 10 1 1 0 1 1 1
pinnumber=force_parity
T 400 800 5 10 0 1 0 1 1 1
pinseq=4
}
P 300 1000 0 1000 4 0 1
{
T 400 1000 5 10 1 1 0 1 1 1
pinnumber=clk
T 400 1000 5 10 0 1 0 1 1 1
pinseq=5
}
P 300 1200 0 1200 4 0 1
{
T 400 1200 5 10 1 1 0 1 1 1
pinnumber=baud_clk
T 400 1200 5 10 0 1 0 1 1 1
pinseq=6
}
P 4100 200 4400 200 10 1 1
{
T 4000 200 5 10 1 1 0 7 1 1
pinnumber=rxd_data_out[SIZE-1:0]
T 4000 200 5 10 0 1 0 7 1 1
pinseq=7
}
P 4100 400 4400 400 4 0 1
{
T 4000 400 5 10 1 1 0 7 1 1
pinnumber=rxd_stop_error
T 4100 400 5 10 0 1 0 7 1 1
pinseq=8
}
P 4100 600 4400 600 4 0 1
{
T 4000 600 5 10 1 1 0 7 1 1
pinnumber=rxd_parity_error
T 4100 600 5 10 0 1 0 7 1 1
pinseq=9
}
P 4100 800 4400 800 4 0 1
{
T 4000 800 5 10 1 1 0 7 1 1
pinnumber=rxd_buffer_full
T 4100 800 5 10 0 1 0 7 1 1
pinseq=10
}
/projects/logic/ip/io_module/doc/geda/drawing/filelist
0,0 → 1,8
`include "../../../rtl/gen/syn/io_module.v"
`include "../../../../uart/rtl/gen/syn/uart.v"
`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
`include "../../lib/cde_sync/cde_sync_with_hysteresis.v"
 
 
 
 
/projects/logic/ip/io_module/doc/copyright.v
9,7 → 9,7
// //
// //
// //
// Copyright (C) <2010> <Ouabache DesignWorks> //
// Copyright (C) <2009> <Ouabache DesignWorks> //
// //
// //
// This source file may be used and distributed without //
/projects/logic/ip/io_module/sim/run/default/TB.defs
1,6 → 1,3
`define TIMESCALE 1ns/1ns
`timescale `TIMESCALE
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`define PERIOD 20.00000
 
/projects/logic/ip/io_module/sim/run/default/test_define
1,6 → 1,5
initial
begin
`TIMEFORMAT
$display(" ");
$display(" ===================================================");
$display("%t Test Start",$realtime);
/targets/Basys/Pad_Ring.v
87,10 → 87,13
wire jc_4_pad_out;
 
 
wire rts_pad_out;
wire cts_pad_in;
wire rxd_pad_in;
wire txd_pad_out;
// Pad Ring
cde_pad_se_dig a_clk_pad(
/Makefile
73,9 → 73,9
(\
cd ${home}/${design}_cmp ;\
echo " number of fpgas";\
find . | grep def_file | wc ;\
find . | grep def_file | grep -v children | wc -l ;\
echo " number that finished";\
find . | grep bitstream.svf |wc ;\
find . | grep Board_Design_jtag.bit |wc -l ;\
)
 
 

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