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/projects/Mos6502/ip/T6502/doc/T6502_doc.txt
0,0 → 1,1150
T6502 Embedded Microprocessor
==================================================================================
 
The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructions
and processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.
 
 
It differs from the original Mos6502 in the following ways
 
 
 
1) Changed memory interface from asynchronous to synchronous. This allows for faster pipelined accesses
 
2) Page Zero is fully filled with RAM. Indirect addresses stored in page 00 MUST be aligned on even addresses.
The original 6502 didn't care but this speeds up indirect and indexed instructions.
 
3) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable via
pushes and pulls
 
4) Number of clock cycles to execute instructions has changed
 
5) Binary Coded Decimal mode has been removed. The D bit in the PSR does nothing
 
6) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset
 
7) Added Debugging logic and error checking
 
8) Removed the TSX and TXS commands
 
 
 
 
 
 
 
 
 
 
 
 
 
 
History
=========================================================================================
 
 
 
 
This component is derived from the opencores t6507lp project.
 
The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini
was a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Processor Model
===============================================================================================
 
+----------+
| A | Accumulator (A)
+----------+
| X | X Index Register (X)
+----------+
| Y | Y Index Register (Y)
+----------+----------+
| PCH | PCL | Program Counter (PC)
+----------+----------+
| 00000001 | SP | Stack Pointer (SP)
+----------+----------+
| P | Processor Status Word (P)
+----------+
NV1BDIZC
|||||||+---- Carry Flag 1 = True
||||||+----- Zero Flag 1 = Result == 8'h00
|||||+------ IRQ Disable 1 = Disable
||||+------- Decimal Mode Not used
|||+-------- Break Command 1 = In break routine
||+--------- Run Mode 1 = Processor is running
|+---------- Overflow Flag 1 = True
+----------- Negative 1 = Negative Number
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Memory Model
===============================================================================================
 
0000-00FF | Page Zero RAM
0010-01FF | Stack RAM
0200-FFF9 | Program and Data RAM
FFFA | NMI Vector Low
FFFB | NMI Vector High
FFFC | Boot Vector Low
FFFD | Boot Vector High
FFFE | IRQ/BRK Vector Low
FFFF | IRQ/BRK Vector High
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Instruction Set
===============================================================================================
 
Inst Description Effect on flags
-----------------------------------------------------------------------------------------------
ADC Operand Add Acc to Operand with Carry NZCV
SBC Operand Subract Operand from Acc with Borrow NZXV
AND Operand Logical AND Acc and Operand NZ
CMP Operand Compare Acc with Operand NZC
CPX Operand Compare X_index with Operand NZC
CPY Operand Compare Y_index with Operand NZC
EOR Operand Exclusive Or Acc with Operand NZ
LDA Operand Load Operand into Acc NZ
LDX Operand Load Operand into X_index NZ
LDY Operand Load Operand into Y_index NZ
ORA Operand Logical Or Acc with Operand NZ
BIT Operand Bit Test Acc with operand Z67
STA Address Store Acc @ address NONE
STX Address Store X_Index @ address NONE
STY Address Store Y_Index @ address NONE
ASL Operand Arithmetic Shift Left Operand into Carry NZC
DEC Operand Decrement Operand NZ
INC Operand Incremement Operand NZ
DEX Decrement X Index NZ
INX Incremement X Index NZ
DEY Decrement Y Index NZ
INY Incremement Y Index NZ
LSR Operand Logical Shift Right Operand into Carry NZC
ROL Operand Rotate Left Operand thru Carry NZC
ROR Operand Rotate Right Operand thru Carry NZC
NOP No Operation NONE
SEC Set Carry Flag 1 -> C
SED Set Decimal Flag 1 -> D
SEI Set Interrupt Flag 1 -> I
CLC Clear Carry Flag 0 -> C
CLD Clear Decimal Flag 0 -> D
CLI Clear Interrupt Flag 0 -> I
CLV Clear Overflow Flag 0 -> V
TAX Transfer Acc into X_Index NZ
TAY Transfer Acc into Y_Index NZ
TSX Transfer SP into X_Index NZ ****
TXA Transfer X_Index into Acc NZ
TXS Transfer X_Index into SP NONE ****
TYA Transfer Y_Index into Acc NZ
BCC Offset Branch if C == 0 NONE
BCS Offset Branch if C == 1 NONE
BNE Offset Branch if Z == 0 NONE
BEQ Offset Branch if Z == 1 NONE
BVC Offset Branch if V == 0 NONE
BVS Offset Branch if V == 1 NONE
BPL Offset Branch if N == 0 NONE
BMI Offset Branch if N == 1 NONE
PLA Pull Acc from Stack NZ
PLP Pull PSR from Stack RESTORE
PHA Push Acc onto Stack NONE
PHP Push PSR onto Stack NONE
JMP Address Jump to New Address NONE
JMP (Address) Jump to New Address stored in (Address) NONE
JSR Address Save PC+2 on stack and jump to New Address NONE
BRK Save PC+1 on stack and jump to New Address 1 -> B
RTI Pull PC from stack RESTORED
RTS Pull Acc and PC from stack NONE
HLT Halt Processor Operation NONE ****
 
 
 
 
**** to be removed
 
 
 
 
 
 
 
 
 
 
 
 
Interrupts
===============================================================================================
 
Non-Maskable (NMI)
 
1) Finish current instruction
2) Push Address of next instruction on stack
3) Read Vector Address from FFFA
4) Execute code @ vector address
 
 
 
Maskable (IRQ) ( if I bit is clear)
 
1) Finish current instruction
2) Push Address of next instruction on stack
3) Push PSR on stack
4) Read Vector Address from FFFE
5) Execute code @ vector address
 
 
Reset
 
1) Clear A,X,Y: Set PSR to 20h
2) Wait for Reset to deassert
3) Read Vector Address from FFFC
4) Execute code @ vector address
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Addressing Modes
===============================================================================================
 
 
Immediate Read
-------------------------------------------------------
Operand is located in memory following the opcode
 
 
 
 
 
 
Absolute Read/Write/ReadModifyWrite
-------------------------------------------------------
16 bit address of operand is located in memory following opcode (low byte,high byte)
 
 
 
 
 
Absolute Indexed Read/Write/ReadModifyWrite
-------------------------------------------------------
Operand is found by adding index value to 16 bit address following opcode.(no wraparound)
 
 
 
 
 
Page Zero Read/Write/ReadModifyWrite
-------------------------------------------------------
8 bit page zero address of operand is located in memory following opcode.
 
 
 
 
 
 
Page Zero Indexed Read/Write/ReadModifyWrite
-------------------------------------------------------
Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)
 
 
 
 
 
 
Page Zero Indirect X Read/Write
-------------------------------------------------------
Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
 
 
 
 
 
 
Page Zero Indirect Y Read/Write
-------------------------------------------------------
8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address
(no wraparound). Page zero address MUST be even.
 
 
 
 
 
Implied Read/Write/Read_Modify_WRite
-------------------------------------------------------
Operand is specified by the Opcode
 
 
 
 
Branch Read
-------------------------------------------------------
Opcode is followed by the relative offset for the branch
 
 
 
Stack StackRead/StackWrite
-------------------------------------------------------
Operation uses the Stack
 
 
 
 
 
Jump Absolute Read
-------------------------------------------------------
16 bit destination address follows opcode
 
 
 
 
 
 
Jump Indirect Read
-------------------------------------------------------
16 bit Address following opcode points to destination address
 
 
 
 
Jump Sub Absolute Read_Stackwrite
-------------------------------------------------------
16 bit destination address follows opcode. Return address is pushed on stack
 
 
 
 
Break Read_Stackwrite
-------------------------------------------------------
Return address is pushed on stack and the IRQ vector is taken
 
 
 
 
Return from Interrupt Read_Stackread
-------------------------------------------------------
PSR and Prog_counter are pulled from stack
 
 
 
Return from Subroutine Read_Stackread
-------------------------------------------------------
Prog_counter is pulled from stack
 
 
 
 
 
Halt Read
-------------------------------------------------------
Operations cease
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Instruction Opcodes (hex)
====================================================================================================
 
 
 
ADC abs 6D
ADC abs,X 7D
ADC abs,Y 79
ADC #n 69
ADC zp 65
ADC (zp,X) 61
ADC zp,X 75
ADC (zp),Y 71
 
AND abs 2D
AND abs,X 3D
AND abs,Y 39
AND #n 29
AND zp 25
AND (zp,X) 21
AND zp,X 35
AND (zp),Y 31
 
ASL A 0A
ASL abs 0E
ASL abs,X 1E
ASL zp 06
ASL zp,X 16
 
BCC rel 90
BCS rel B0
BEQ rel F0
 
BIT abs 2C
BIT zp 24
 
BMI rel 30
BNE rel D0
BPL rel 10
 
BRK 00
 
BVC rel 50
BVS rel 70
 
 
CLC 18
CLD D8
CLI 58
CLV B8
 
CMP abs CD
CMP abs,X DD
CMP abs,Y D9
CMP #n C9
CMP zp C5
CMP (zp,X) C1
CMP zp,X D5
CMP (zp),Y D1
 
CPX abs EC
CPX #n E0
CPX zp E4
CPY abs CC
CPY #n C0
CPY zp C4
 
DEC abs CE
DEC abs,X DE
DEC zp C6
DEC zp,X D6
 
DEX CA
DEY 88
 
EOR abs 4D
EOR abs,X 5D
EOR abs,Y 59
EOR #n 49
EOR zp 45
EOR (zp,X) 41
EOR zp,X 55
EOR (zp),Y 51
 
INC abs EE
INC abs,X FE
INC zp E6
INC zp,X F6
INX E8
INY C8
 
JMP abs 4C
JMP (abs) 6C
JSR abs 20
 
LDA abs AD
LDA abs,X BD
LDA abs,Y B9
LDA #n A9
LDA zp A5
LDA (zp,X) A1
LDA zp,X B5
LDA (zp),Y B1
 
LDX abs AE
LDX abs,Y BE
LDX #n A2
LDX zp A6
LDX zp,Y B6
 
LDY abs AC
LDY abs,X BC
LDY #n A0
LDY zp A4
LDY zp,X B4
 
LSR A 4A
LSR abs 4E
LSR abs,X 5E
LSR zp 46
LSR zp,X 56
 
NOP EA
 
ORA abs 0D
ORA abs,X 1D
ORA abs,Y 19
ORA #n 09
ORA zp 05
ORA (zp,X) 01
ORA zp,X 15
ORA (zp),Y 11
 
PHA 48
PHP 08
 
PLA 68
PLP 28
 
ROL A 2A
ROL abs 2E
ROL abs,X 3E
ROL zp 26
ROL zp,X 36
 
ROR A 6A
ROR abs 6E
ROR abs,X 7E
ROR zp 66
ROR zp,X 76
 
RTI 40
 
RTS 60
 
SBC abs ED
SBC abs,X FD
SBC abs,Y F9
SBC #n E9
SBC zp E5
SBC (zp,X) E1
SBC zp,X F5
SBC (zp),Y F1
 
SEC 38
SED F8
SEI 78
 
STA abs 8D
STA abs,X 9D
STA abs,Y 99
STA zp 85
STA (zp,X) 81
STA zp,X 95
STA (zp),Y 91
 
STX abs 8E
STX zp 86
STX zpy 96
 
STY abs 8C
STY zp 84
STY zp,X 94
 
TAX AA
TAY A8
TSX BA
TXA 8A
TXS 9A
TYA 98
 
 
 
 
 
 
 
 
 
Instruction Decodes
======================================================================================================================================================
 
 
Immediate
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC #n | | alu_a alu_status[0] NZCV ADD 0 0 00 00 A
AND #n | | alu_a 0 NZ AND 0 0 00 00 A
CMP #n | | alu_a 1 NZC ADD 1 0 00 00 0
CPX #n | | alu_x 1 NZC ADD 1 0 00 00 0
CPY #n | | alu_y 1 NZC ADD 1 0 00 00 0
EOR #n | | alu_a 0 NZ EOR 0 0 00 00 A
LDA #n | | 00 0 NZ ADD 0 0 00 00 A
LDX #n | | 00 0 NZ ADD 0 0 00 00 X
LDY #n | | 00 0 NZ ADD 0 0 00 00 Y
ORA #n | | alu_a 0 NZ ORR 0 0 00 00 A
SBC #n | | alu_a alu_status[0] NZXV ADD 1 0 00 00 A
 
 
 
 
Absolute
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC abs | | alu_a alu_status[0] NZCV ADD 0 0 00 00 A
AND abs | | alu_a 0 NZ AND 0 0 00 00 A
BIT abs | | alu_a 0 Z67 AND 0 0 00 00 0
CMP abs | | alu_a 1 NZC ADD 1 0 00 00 0
CPX abs | | alu_x 1 NZC ADD 1 0 00 00 0
CPY abs | | alu_y 1 NZC ADD 1 0 00 00 0
EOR abs | | alu_a 0 NZ EOR 0 0 00 00 A
LDA abs | | 00 0 NZ ADD 0 0 00 00 A
LDX abs | | 00 0 NZ ADD 0 0 00 00 X
LDY abs | | 00 0 NZ ADD 0 0 00 00 Y
ORA abs | | alu_a 0 NZ ORR 0 0 00 00 A
SBC abs | | alu_a alu_status[0] NZXV ADD 1 0 00 00 A
 
 
 
 
Absolute
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA abs | | alu_a 0 NONE ADD 0 0 00 00 M
STX abs | | alu_x 0 NONE ADD 0 0 00 00 M
STY abs | | alu_y 0 NONE ADD 0 0 00 00 M
 
 
 
Absolute
read/modify/write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ASL abs | | 00 0 NZC SFL 0 0 00 00 M
DEC abs | | FF 0 NZ ADD 0 0 00 00 M
INC abs | | 00 1 NZ ADD 0 0 00 00 M
LSR abs | | 00 0 NZC SFR 0 0 00 00 M
ROL abs | | 00 alu_status[0] NZC SFL 0 0 00 00 M
ROR abs | | 00 alu_status[0] NZC SFR 0 0 00 00 M
 
 
 
 
 
 
Absolute indexed
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC abs,X | | alu_a alu_status[0] NZCV ADD 0 X 00 00 A
AND abs,X | | alu_a 0 NZ AND 0 X 00 00 A
CMP abs,X | | alu_a 1 NZC ADD 1 X 00 00 0
EOR abs,X | | alu_a 0 NZ EOR 0 X 00 00 A
LDA abs,X | | 00 0 NZ ADD 0 X 00 00 A
LDY abs,X | | 00 0 NZ ADD 0 X 00 00 Y
ORA abs,X | | alu_a 0 NZ ORR 0 X 00 00 A
SBC abs,X | | alu_a alu_status[0] NZXV ADD 1 X 00 00 A
ADC abs,Y | | alu_a alu_status[0] NZCV ADD 0 Y 00 00 A
AND abs,Y | | alu_a 0 NZ AND 0 Y 00 00 A
CMP abs,Y | | alu_a 1 NZC ADD 1 Y 00 00 0
EOR abs,Y | | alu_a 0 NZ EOR 0 Y 00 00 A
LDA abs,Y | | 00 0 NZ ADD 0 Y 00 00 A
LDX abs,Y | | 00 0 NZ ADD 0 Y 00 00 X
ORA abs,Y | | alu_a 0 NZ ORR 0 Y 00 00 A
SBC abs,Y | | alu_a alu_status[0] NZXV ADD 1 Y 00 00 A
 
 
 
Absolute indexed
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA abs,X | | alu_a 0 ADD 0 X 00 00 M
STA abs,Y | | alu_a 0 NONE ADD 0 Y 00 00 M
 
 
Absolute indexed
read/modify/write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ASL abs,X | | 00 0 NZC SFL 0 X 00 00 M
DEC abs,X | | FF 0 NZ ADD 0 X 00 00 M
INC abs,X | | 00 1 NZ ADD 0 X 00 00 M
LSR abs,X | | 00 0 NZC SFR 0 X 00 00 M
ROL abs,X | | 00 alu_status[0] NZC SFL 0 X 00 00 M
ROR abs,X | | 00 alu_status[0] NZC SFR 0 X 00 00 M
 
 
 
 
 
 
Page Zero
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC zp | | alu_a alu_status[0] NZCV ADD 0 0 00 00 A
AND zp | | alu_a 0 NZ AND 0 0 00 00 A
BIT zp | | alu_a 0 Z67 AND 0 0 00 00 0
CMP zp | | alu_a 1 NZC ADD 1 0 00 00 0
CPX zp | | alu_x 1 NZC ADD 1 0 00 00 0
CPY zp | | alu_y 1 NZC ADD 1 0 00 00 0
EOR zp | | alu_a 0 NZ EOR 0 0 00 00 A
LDA zp | | 00 0 NZ ADD 0 0 00 00 A
LDX zp | | 00 0 NZ ADD 0 0 00 00 X
LDY zp | | 00 0 NZ ADD 0 0 00 00 Y
ORA zp | | alu_a 0 NZ ORR 0 0 00 00 A
SBC zp | | alu_a alu_status[0] NZXV ADD 1 0 00 00 A
 
Page Zero
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA zp | | alu_a 0 NONE ADD 0 0 00 00 M
STX zp | | alu_x 0 NONE ADD 0 0 00 00 M
STY zp | | alu_y 0 NONE ADD 0 0 00 00 M
 
 
Page Zero
read/modify/write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ASL zp | | 00 0 NZC SFL 0 0 00 00 M
DEC zp | | FF 0 NZ ADD 0 0 00 00 M
INC zp | | 00 1 NZ ADD 0 0 00 00 M
LSR zp | | 00 0 NZC SFR 0 0 00 00 M
ROL zp | | 00 alu_status[0] NZC SFL 0 0 00 00 M
ROR zp | | 00 alu_status[0] NZC SFR 0 0 00 00 M
 
 
 
Page Zero indexed
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC zp,X | | alu_a alu_status[0] NZCV ADD 0 X 00 00 A
AND zp,X | | alu_a 0 NZ AND 0 X 00 00 A
CMP zp,X | | alu_a 1 NZC ADD 1 X 00 00 0
EOR zp,X | | alu_a 0 NZ EOR 0 X 00 00 A
LDA zp,X | | 00 0 NZ ADD 0 X 00 00 A
LDY zp,X | | 00 0 NZ ADD 0 X 00 00 Y
ORA zp,X | | alu_a 0 NZ ORR 0 X 00 00 A
SBC zp,X | | alu_a alu_status[0] NZXV ADD 1 X 00 00 A
LDX zp,Y | | 00 0 NZ ADD 0 Y 00 00 X
 
 
Page Zero indexed
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA zp,X | | alu_a 0 NONE ADD 0 X 00 00 M
STY zp,X | | alu_y 0 NONE ADD 0 X 00 00 M
STX zp,Y | | alu_x 0 NONE ADD 0 Y 00 00 M
 
 
 
 
Page Zero indexed
read/modify/write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ASL zp,X | | 00 0 NZC SFL 0 X 00 00 M
DEC zp,X | | FF 0 NZ ADD 0 X 00 00 M
INC zp,X | | 00 1 NZ ADD 0 X 00 00 M
LSR zp,X | | 00 0 NZC SFR 0 X 00 00 M
ROR zp,X | | 00 alu_status[0] NZC SFR 0 X 00 00 M
ROL zp,X | | 00 alu_status[0] NZC SFL 0 X 00 00 M
 
 
 
Page Zero indirectX
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC (zp,X) | | alu_a alu_status[0] NZCV ADD 0 X 00 00 A
AND (zp,X) | | alu_a 0 NZ AND 0 X 00 00 A
CMP (zp,X) | | alu_a 1 NZC ADD 1 X 00 00 0
EOR (zp,X) | | alu_a 0 NZ EOR 0 X 00 00 A
LDA (zp,X) | | 00 0 NZ ADD 0 X 00 00 A
ORA (zp,X) | | alu_a 0 NZ ORR 0 X 00 00 A
SBC (zp,X) | | alu_a alu_status[0] NZXV ADD 1 X 00 00 A
 
 
Page Zero indirectX
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA (zp,X) | | alu_a 0 NONE ADD 0 X 00 00 M
 
 
======================================================================================================================================================
 
 
Page Zero IndirectY
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ADC (zp),Y | | alu_a alu_status[0] NZCV ADD 0 Y 00 00 A
AND (zp),Y | | alu_a 0 NZ AND 0 Y 00 00 A
CMP (zp),Y | | alu_a 1 NZC ADD 1 Y 00 00 0
EOR (zp),Y | | alu_a 0 NZ EOR 0 Y 00 00 A
LDA (zp),Y | | 00 0 NZ ADD 0 Y 00 00 A
ORA (zp),Y | | alu_a 0 NZ ORR 0 Y 00 00 A
SBC (zp),Y | | alu_a alu_status[0] NZXV ADD 1 Y 00 00 A
 
 
 
 
 
 
Page Zero IndirectY
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
STA (zp),Y | | alu_a 0 NONE ADD 0 Y 00 00 M
 
 
 
 
 
Implied
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
NOP | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
Implied
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
SEC | | 00 0 WR ADD 0 0 01 01 0
SED | | 00 0 WR ADD 0 0 08 08 0
SEI | | 00 0 WR ADD 0 0 04 04 0
CLC | | 00 0 WR ADD 0 0 00 01 0
CLD | | 00 0 WR ADD 0 0 00 08 0
CLI | | 00 0 WR ADD 0 0 00 04 0
CLV | | 00 0 WR ADD 0 0 00 40 0
 
 
 
Implied
read/modify/write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
ASL A | | alu_a 0 NZC SFL 0 0 00 00 A
DEX | | alu_x 0 NZ ADD 0 0 00 00 X
DEY | | alu_y 0 NZ ADD 0 0 00 00 Y
INX | | alu_x 1 NZ ADD 0 0 00 00 X
INY | | alu_y 1 NZ ADD 0 0 00 00 Y
LSR A | | alu_a 0 NZC SFR 0 0 00 00 A
ROL A | | alu_a alu_status[0] NZC SFL 0 0 00 00 A
ROR A | | alu_a alu_status[0] NZC SFR 0 0 00 00 A
TAX | | alu_a 0 NZ ADD 0 0 00 00 A
TAY | | alu_a 0 NZ ADD 0 0 00 00 X
TSX | | 00 0 NZ ADD 0 0 00 00 Y
TXA | | alu_x 0 NZ ADD 0 0 00 00 A
TXS | | alu_x 0 NONE ADD 0 0 00 00 S
TYA | | alu_y 0 NZ ADD 0 0 00 00 A
 
 
 
Branch
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
BCC rel | | 00 0 NONE ADD 0 B 00 01 0
BCS rel | | 00 0 NONE ADD 0 B 01 01 0
BNE rel | | 00 0 NONE ADD 0 B 00 02 0
BEQ rel | | 00 0 NONE ADD 0 B 02 02 0
BVC rel | | 00 0 NONE ADD 0 B 00 40 0
BVS rel | | 00 0 NONE ADD 0 B 40 40 0
BPL rel | | 00 0 NONE ADD 0 B 00 80 0
BMI rel | | 00 0 NONE ADD 0 B 80 80 0
 
 
 
Stack
read
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
PLA | | 00 0 NZ ADD 0 A 00 00 A
PLP | | 00 0 RESTORE ADD 0 P 00 00 P
 
 
 
 
Stack
write
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
PHA | | alu_a 0 NONE ADD 0 A 00 00 M
PHP | | alu_a 0 NONE ADD 0 P 00 00 M
 
 
 
Jump absolute
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
JMP abs | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
Jump indirect
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
JMP (abs) | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
Jump Sub absolute
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
JSR abs | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
Break
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
BRK | | alu_a 0 B ADD 0 0 00 00 0
 
 
 
Return from
Interrupt
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
RTI | | 00 0 RESTORE ADD 0 0 00 00 P
 
 
 
Return from
Subroutine
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
------------------------------------------------------------------------------------------------------------------------------------------------------
RTS | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
Halt
Instructions alu_op_a alu_op_c stat_update alu_mode alu_op_b_invert index branch_value branch_enable destination
-------------------------------------------------------------------------------------------------------------------------------------------------------
HLT | | 00 0 NONE ADD 0 0 00 00 0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Address Sequence Decodes
=========================================================================
 
 
 
 
 
Immediate Address Mode
 
c e
l n mem mem status
k b addr rd_data state ir operand dest reg
__________________________________________________________________________________________________________
0 0 opc add FETCH_OP
1 1 opc add opcode FETCH_OP
2 0 add+1 opcode FETCH_LOW opcode
3 1 add+1 operand FETCH_LOW
4 0 add+2 operand FETCH_OP operand
5 1 add+2 newop FETCH_OP
6 0 add+3 newop newop updated
7 1
8 0
9 1
A 0
B 1
C 0
D 1
E 0
F 1
 
 
 
 
Absolute Read Address Mode
 
c e
l n mem mem status
k b addr rd_data state ir operand op_addr dest reg
__________________________________________________________________________________________________________
0 0 opc add FETCH_OP
1 1 opc add opcode FETCH_OP
2 0 add+1 opcode FETCH_LOW opcode
3 1 add+1 add_lo FETCH_LOW
4 0 add+2 add_lo FETCH_HIGH 00addr
5 1 add+2 add_hi FETCH_HIGH
6 0 op_addr add_hi MEM_READ
7 1 op_addr operand MEM_READ
8 0 add+3 operand FETCH_OP operand
9 1 add+3 newop FETCH_OP
A 0 newop newop updated
B 1
C 0
D 1
E 0
F 1
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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