URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk
- from Rev 48 to Rev 49
- ↔ Reverse comparison
Rev 48 → Rev 49
/bench/verilog/TestBench.cov
8,7 → 8,7
/* | | */ |
/* |____________| */ |
/* */ |
/* Testbench file used for all simulations */ |
/* Testbench file used for all codecoverage */ |
/* */ |
/* */ |
/* Author(s): */ |
44,21 → 44,10
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`include "./TB.defs" |
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`timescale 1ns/1ns |
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`include "./filelist.cov" |
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`include "./modellist" |
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`include "./filelist" |
`include "./liblist" |
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module TB(); |
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70,18 → 59,9
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clock_gen |
#(.PERIOD(10), |
.TIMEOUT(0)) |
cg |
( .clk (clk), |
.reset (reset) |
); |
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endmodule |
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/tools/install/Ubuntu_10.4/Makefile
19,8 → 19,6
sudo apt-get install -y gputils;\ |
sudo apt-get install -y gtkterm;\ |
sudo apt-get install -y gtkwave;\ |
sudo apt-get install -y covered;\ |
sudo apt-get install -y covered-doc;\ |
sudo apt-get install -y fxload;\ |
sudo apt-get install -y urjtag;\ |
sudo apt-get install -y libftdi-dev;\ |
/tools/bin/Makefile.root
113,8 → 113,47
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################################################################################ |
# set up coverage |
################################################################################ |
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.PHONY build_cov: |
build_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make build_cdd ;\ |
cd $(CUR_DIR) ;\ |
done; \ |
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################################################################################ |
# run coverage report |
################################################################################ |
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.PHONY report_cov: |
report_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Report Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make report_cov;\ |
cd $(CUR_DIR) ;\ |
done; \ |
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################################################################################ |
# run simulation suite |
################################################################################ |
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128,15 → 167,12
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.PHONY run_sims: |
run_sims: clean_sims |
run_sims: clean_sims build_cov |
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Simulating: $$VARIANT_PROG ####"; echo; \ |
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\ |
echo "include ../../../../../bin/Makefile.root" > Makefile;\ |
echo -n "test=" >> Makefile;\ |
echo $$VARIANT_PROG >> Makefile;\ |
make sim;\ |
done; \ |
|
144,13 → 180,13
.PHONY sim: |
sim: |
(\ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > cov.v ;\ |
covered score -t TB -I ./ -v ./cov.v -o ${test}.cdd 2> ${test}_cov.log | tee >> ${test}_cov.log ;\ |
$(VERILOG_NAME) -D VCD ../../bench/verilog/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
mv *.log ../../log;\ |
mv TestBench.vcd ../../out/${test}.vcd ;\ |
rm a.out;\ |
cd ../../cov/${comp};\ |
make score_cov TEST=${test} ;\ |
) |
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304,7 → 340,8
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims;\ |
make run_sims COMP=$$COMP ;\ |
make report_cov ;\ |
done; \ |
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/tools/bin/soc_link
0,0 → 1,272
eval 'exec `which perl` -S $0 ${1+"$@"}' |
if 0; |
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#/**********************************************************************/ |
#/* */ |
#/* ------- */ |
#/* / SOC \ */ |
#/* / GEN \ */ |
#/* / TOOL \ */ |
#/* ============== */ |
#/* | | */ |
#/* |____________| */ |
#/* */ |
#/* Traverse a socgen project and link it */ |
#/* */ |
#/* */ |
#/* Author(s): */ |
#/* - John Eaton, jt_eaton@opencores.org */ |
#/* */ |
#/**********************************************************************/ |
#/* */ |
#/* Copyright (C) <2010> <Ouabache Design Works> */ |
#/* */ |
#/* This source file may be used and distributed without */ |
#/* restriction provided that this copyright statement is not */ |
#/* removed from the file and that any derivative work contains */ |
#/* the original copyright notice and the associated disclaimer. */ |
#/* */ |
#/* This source file is free software; you can redistribute it */ |
#/* and/or modify it under the terms of the GNU Lesser General */ |
#/* Public License as published by the Free Software Foundation; */ |
#/* either version 2.1 of the License, or (at your option) any */ |
#/* later version. */ |
#/* */ |
#/* This source is distributed in the hope that it will be */ |
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */ |
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ |
#/* PURPOSE. See the GNU Lesser General Public License for more */ |
#/* details. */ |
#/* */ |
#/* You should have received a copy of the GNU Lesser General */ |
#/* Public License along with this source; if not, download it */ |
#/* from http://www.opencores.org/lgpl.shtml */ |
#/* */ |
#/**********************************************************************/ |
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$root = "projects"; |
$dest = "work"; |
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use Cwd; |
use XML::LibXML; |
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$home = cwd(); |
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print "Building socgen work area for $home \n" ; |
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&link_sub( $root ); |
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@projects = qx(ls $home/work ); |
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print "Linking testbench \n" ; |
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foreach my $project (@projects) |
{ |
chomp($project); |
my @components = qx(ls ${home}/work/${project}/ip ); |
foreach my $component (@components) |
{ |
chomp($component); |
$root = "bench"; |
$dest = "work/${project}/ip/${component}/sim/bench"; |
# print "$dest \n"; |
&link_sub( $root ); |
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$root = "lib"; |
$dest = "work/${project}/ip/${component}/sim/lib"; |
# print "$dest \n"; |
&link_sub( $root ); |
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} |
} |
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print "Done \n" ; |
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print "Linking children \n" ; |
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foreach my $project (@projects) |
{ |
chomp($project); |
my @components = qx(ls ${home}/work/${project}/ip ); |
foreach my $component (@components) |
{ |
chomp($component); |
my @xml_files = qx(ls ${home}/work/${project}/ip/${component}/rtl/xml ); |
foreach my $xml_file (@xml_files) |
{ |
chomp($xml_file); |
my $filename= "${home}/work/${project}/ip/${component}/rtl/xml/${xml_file}"; |
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my $parser = XML::LibXML->new(); |
my $doc = $parser->parse_file($filename); |
foreach my $comp ($doc->findnodes('/components/component')) { |
my($name) = $comp->findnodes('./name/text()')->to_literal ; |
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print "Variant $project $component $name\n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/children/child/name")) |
{ |
my($fca) = $i_name ->findnodes('./text()')->to_literal ; |
my($fcb) = $i_name ->findnodes('../family/text()')->to_literal ; |
print " work/${project}/children/${fcb}/ip/${fca}\n"; |
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my $path = "work/${project}/children"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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my $path = "work/${project}/children/${fcb}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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my $path = "work/${project}/children/${fcb}/bin"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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$root = "${home}/projects/${fcb}/bin"; |
$dest = "${home}/work/${project}/children/${fcb}/bin"; |
$cmd = "lndir ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "work/${project}/children/${fcb}/sw"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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$root = "${home}/projects/${fcb}/sw"; |
$dest = "${home}/work/${project}/children/${fcb}/sw"; |
$cmd = "lndir ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "work/${project}/children/${fcb}/ip"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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my $path = "work/${project}/children/${fcb}/ip/${fca}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755; |
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$root = "${home}/projects/${fcb}/ip/${fca}"; |
$dest = "${home}/work/${project}/children/${fcb}/ip/${fca}"; |
$cmd = "lndir ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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} |
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} |
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} |
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my @syns = qx(ls ${home}/work/${project}/ip/${component}/syn ); |
foreach my $syn (@syns) |
{ |
chomp($syn); |
print ("SYN $syn \n"); |
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my @targets = qx(ls ${home}/work/${project}/ip/${component}/syn/${syn}/target ); |
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foreach my $target (@targets) |
{ |
chomp($target); |
print ("TARGET $target \n"); |
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$cmd = |
"lndir ${home}/targets/${target} ${home}/work/${project}/ip/${component}/syn/${syn}/target " ; |
if (system($cmd)) {} |
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$cmd = |
"lndir ${home}/lib ${home}/work/${project}/ip/${component}/syn/${syn}/target/lib/syn" ; |
if (system($cmd)) {} |
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$cmd = |
"rmdir ${home}/work/${project}/ip/${component}/syn/${syn}/target/${target}" ; |
if (system($cmd)) {} |
} |
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} |
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} |
} |
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print "Done \n" ; |
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#foreach my $project (@projects) |
# { |
# chomp($project); |
# my @components = qx(ls ${home}/work/${project}/ip ); |
# foreach my $component (@components) |
# { |
# chomp($component); |
# my @variants = qx(ls ${home}/work/${project}/ip/${component}/rtl/variants ); |
# foreach my $variant (@variants) |
# { |
# chomp($variant); |
# print "$project $component $variant \n"; |
# } |
# } |
# } |
# |
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# recursively map directory information into XML |
# |
sub link_sub { |
my $path = shift; |
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return unless( -e $path ); |
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# if this is a directory, create an element and |
# stuff it full of items |
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my $dest_path = $path; |
$dest_path =~ s/$root/$dest/; |
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if( -d $path ) { |
print "Creating $dest_path\n" unless( -e $dest_path ); |
mkdir $dest_path,0755; |
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# Load the names of all things in this |
# directory into an array |
my @contents = ( ); |
opendir( DIR, $path ); |
while( my $item = readdir( DIR )) { |
next if( $item eq '.' or $item eq '..' ); |
push( @contents, $item ); |
} |
closedir( DIR ); |
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# recurse on items in the directory |
foreach my $item ( @contents ) { &link_sub( "$path/$item" );} |
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# We'll lazily call anything that's not a directory a file. |
} else { |
print "Linking $dest_path\n" unless( -e $dest_path ); |
symlink( "${home}/${path}", $dest_path); |
} |
} |
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tools/bin/soc_link
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tools/bin/build_cmp
===================================================================
--- tools/bin/build_cmp (revision 48)
+++ tools/bin/build_cmp (revision 49)
@@ -100,7 +100,6 @@
print " making $home/${design}_cmp\n";
-
$cmd = "mkdir $home/${design}_cmp > /dev/null " ;
if (system($cmd)) {die "Failed $status ";}
@@ -107,14 +106,15 @@
$cmd = "ln -s $home/${design}/Makefile $home/${design}_cmp > /dev/null " ;
if (system($cmd)) {die "Failed $status ";}
-
$cmd = "mkdir $home/${design}_cmp/projects > /dev/null ";
if (system($cmd)) {die "Failed $status ";}
- my @projects = qx(ls $home/${design}/projects );
- foreach my $project (@projects)
+
+ my @projects = qx(ls $home/${design}/projects );
+
+ foreach my $project (@projects)
{
chomp($project);
$cmd = "mkdir ${home}/${design}_cmp/projects/${project} > /dev/null " ;
@@ -121,8 +121,6 @@
if (system($cmd)) {die "Failed ";}
$cmd = "lndir -silent ${home}/${design}/projects/${project} ${home}/${design}_cmp/projects/${project} " ;
if (system($cmd)) {die "Failed ";}
- $cmd = "ln -s ${home}/${design}/tools/bin/Makefile.root ${home}/${design}_cmp/projects/${project}"."/bin " ;
- if (system($cmd)) {die "Failed ";}
my @components = qx(ls ${home}/${design}/projects/${project}/ip );
foreach my $component (@components)
{
@@ -190,10 +188,10 @@
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
if (system($cmd)) {die "Failed ";}
- $cmd = "ln -s ${home}/${design}/tools/bin/Makefile.root ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
- if (system($cmd)) {die "Failed ";}
- $cmd = "ln -s ${home}/${design}/tools/bin/Makefile ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
- if (system($cmd)) {die "Failed ";}
+ $cmd = "lndir -silent ${home}/${design}/projects/${child}/bin ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
+ if (system($cmd)) {}
+
+
$cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
if (system($cmd)) {die "Failed ";}
$cmd = "lndir -silent ${home}/${design}/projects/${child}/sw ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
@@ -200,6 +198,8 @@
if (system($cmd)) {}
+
+
my @grand_children = qx(ls ${home}/${design}/projects/${project}/children/${child}/ip );
foreach my $grand_child (@grand_children)
{
/doc/src/guides/guide_database.html
18,35 → 18,129
<br> |
</p> |
</div> |
<h1><a name="socgen_project"></a>SOCGEN Project</h1> |
<h2><a name="manifesto"></a>Database Guidelines</h2> |
<h1><a name="socgen_project"></a><font size="+3">SOCGEN Project</font></h1> |
<h2><br> |
</h2> |
The mission of the SOCGEN project is to provide a blueprint showing |
digital designers how to create a System_on_chip (SOC) by |
assembling components created by a variety of sources. It will |
show how to create a component that can be reused and provides a |
free opensourced tool set that can be used to assemble and verify |
a design. It employs modern design for reuse techniques to reduce the |
waste and ineffiencies that is inherent in handcrafting a design<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
<br> |
<h2><a name="manifesto"></a><font size="+2">Principles for Reusable |
design</font><br> |
</h2> |
<p><br> |
</p> |
<p>Have a backup plan</p> |
<p> <br> |
<br> |
<h2><font size="+1">Plan ahead<br> |
</font></h2> |
You may start a design with the intent that it is only going to be used |
for one specific purpose only to find out later that other designers |
want to use it. Create all designs with the intent that they will be |
reused in ways that you haven't imagined and you won't have to scramble |
later. <br> |
<br> |
<h2><font><font size="+1">Design for the lowest common demoninator</font></font></h2> |
Everybody loves to use some quirky little feature of the design target |
to squeeze a little extra preformance out of the system. But if you do |
then you are locked into that target and cannot easily reuse the design |
on a different target. Why do you think they put those features in the |
first place? Instead you should survey the field and only use the |
features that all target technologies can match<br> |
<br> |
<br> |
<h2><font><font><font><font size="+1">Design in a completely generic |
technology<br> |
</font></font></font></font></h2> |
Design is a two step process. First the design is created and verified |
in a completely generic behaverioral RTL format and then converted into |
the target technology. It is tempting to try to save time be designing |
in the target technology but this will make it harder to reuse.<br> |
<br> |
<br> |
<h2><font><font><font><font><font><font><font><font size="+1">Automate |
Everything</font></font></font></font></font></font></font></font><br> |
</h2> |
<p> |
Handcrafting a design file is a time consuming and error prone |
operation. Tasks that are preformed on every design should be done by a |
tool. The designers job is to create the configuration files |
needed by the tools and let automation do all the work.<br> |
</p> |
<p>Plan ahead and allow for the worst case configurations</p> |
<p>Design for the lowest common denominator.</p> |
<p>Design first for a completely generic target and then retarget for |
the correct one.</p> |
<p>Store only the seed data needed to generate the database ( keep it |
small and easy to manage)</p> |
<p>Do not check generated files into the database ( generation must |
not change the database)</p> |
<p>Do not copy data. Every object has one and one one storage |
location</p> |
<p>Do not mix unlike objects in the same container. </p> |
<p>Store the databases by their source and not by where they are |
used. Use links to get them to where they are needed</p> |
<p>A full design will consist of several different databases that are |
layered. Upper ones may override any content from a lower layer</p> |
<p><br> |
</p> |
<h2><font><font><font><font><font><font><font><font size="+1">Never |
Check Generated Files into a Database</font></font></font></font></font></font></font></font></h2> |
The Revision Control System (RCS) that contains the design should only |
contain the minimul seed data needed to rebuild the entire design. It |
should never contain any files that were generated by the build |
process. <br> |
<br> |
<h2><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font |
size="+1">Do not keep duplicate copies of a file in the database</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></h2> |
Doing so makes it difficult to ensure that bug fixes and enhancements |
created by one user can be made available to all users. Every file |
should have one and only one location in the database<br> |
<br> |
<h2><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font |
size="+1">Do not build the design inside of an RCS database.</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></h2> |
It is really hard to keep track of all the new files that you have |
added that you need to check into the RCS if they are buried by |
gigabytes of generated files from the build process. Use symbolic links |
to create a work area where generated files are kept outside the |
database.<br> |
<br> |
<p> |
</p> |
<p></p> |
<h2><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font |
size="+1">Store files based on their source and not their use.</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></h2> |
Are you creating a chip using IP from Joe's IP Emporium? Why not create |
a spot inside your chip database for Joes files? Because that is not |
planning ahead. Later if your lab starts another chip that also uses |
Joes IP then they will also need access to those files. Create a spot |
for files where everybody can simply access them by linking the desired |
files into there database<font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font |
size="+1">.</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font> |
<p></p> |
<h2><br> |
</h2> |
<h2><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font |
size="+1">Do not mix unlike objects in the same container.</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></h2> |
<p>"Unlike" is a delibertely nebulious term. It can mean anything and |
everything. If you have a instance of a hard macro that is |
unsynthesizable then do not put it in a file along with synthesisable |
rtl code. If you have code belonging to one designer then do not mix it |
with code belonging to another. If you do then you have to worry about |
file locking. Fragment the design so that each object is in it's own |
container and then use a tool to put them back together.<br> |
</p> |
<br> |
<br> |
<h2><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font><font>Layer |
the |
design.</font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></font></h2> |
<p>A full design will consist of several different databases that are |
layered. Upper ones may override any content from a lower layer<br> |
</p> |
<p><br> |
<br> |
</p> |
<br> |
<br> |
<br> |
<h2><a name="manifesto"></a>Database Guidelines</h2> |
<p></p> |
<p></p> |
<br> |
<p><img style="width: 800px; height: 600px;" alt="" |
src="../png/data_fig1.png"><br> |
<br> |
/doc/src/png/data_fig1.png
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/doc/src/drawing/sch/data_fig1.sch
1,72 → 1,70
v 20100214 2 |
C 42600 22000 1 0 0 frame_800x600.sym |
B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 49500 27300 9 10 1 0 0 0 1 |
Serial Uart |
T 49500 26700 9 10 1 0 0 0 1 |
VGA Display |
T 49600 26200 9 10 1 0 0 0 1 |
PS2 Mouse |
T 49600 25600 9 10 1 0 0 0 1 |
Switches |
T 49700 25100 9 10 1 0 0 0 1 |
Leds |
T 49500 24500 9 10 1 0 0 0 1 |
Push Buttons |
T 49500 23900 9 10 1 0 0 0 1 |
7 Seg display |
T 49500 23100 9 10 1 0 0 0 1 |
I/O connectors |
B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
C 42500 22100 1 0 0 frame_800x600.sym |
B 42900 27700 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 26100 1000 1900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43000 27500 9 10 1 0 0 0 1 |
LIB |
T 43000 27200 9 10 1 0 0 0 1 |
BENCH |
T 43000 27800 9 10 1 0 0 0 1 |
DOC |
T 43000 26900 9 10 1 0 0 0 1 |
TARGETS |
T 43000 26600 9 10 1 0 0 0 1 |
TOOLS |
T 43900 25900 9 10 1 0 0 0 1 |
Proj #1 |
T 44500 25600 9 10 1 0 0 0 1 |
CMP #1 |
B 42900 26800 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 26500 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 27400 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 27100 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 24600 2300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 25500 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43000 28400 9 10 1 0 0 0 1 |
System |
T 43100 27600 9 10 1 0 0 0 1 |
PCA (Nexys2) |
T 43400 26900 9 10 1 0 0 0 1 |
Targeted Component (Xilinx Spartan 3E-500 FG320) |
B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43800 26200 9 10 1 0 0 0 1 |
Padring |
T 44100 25700 9 10 1 0 0 0 1 |
Core |
T 44300 25200 9 10 1 0 0 0 1 |
Component |
B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 24800 9 10 1 0 0 0 1 |
comp |
T 45600 24800 9 10 1 0 0 0 1 |
comp |
T 46700 24800 9 10 1 0 0 0 1 |
comp |
B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44600 27600 9 10 1 0 0 0 1 |
IC |
T 45600 27600 9 10 1 0 0 0 1 |
IC |
T 46600 27600 9 10 1 0 0 0 1 |
IC |
T 47600 27600 9 10 1 0 0 0 1 |
IC |
L 48900 27400 49500 27400 3 0 0 0 -1 -1 |
L 48900 26800 49500 26800 3 0 0 0 -1 -1 |
L 48900 26300 49500 26300 3 0 0 0 -1 -1 |
L 48900 25700 49500 25700 3 0 0 0 -1 -1 |
L 48900 25200 49500 25200 3 0 0 0 -1 -1 |
L 48900 24600 49500 24600 3 0 0 0 -1 -1 |
L 48900 24000 49500 24000 3 0 0 0 -1 -1 |
L 48900 23200 49500 23200 3 0 0 0 -1 -1 |
Socgen Database |
T 42900 26200 9 10 1 0 0 0 1 |
PROJECTS |
B 44400 25200 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 25300 9 10 1 0 0 0 1 |
CMP #2 |
B 44400 24900 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 25000 9 10 1 0 0 0 1 |
CMP #3 |
B 44400 24600 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 24700 9 10 1 0 0 0 1 |
CMP #4 |
B 42900 23400 2300 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 24000 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 23700 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 23400 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43900 24400 9 10 1 0 0 0 1 |
Proj #2 |
T 44500 24100 9 10 1 0 0 0 1 |
CMP #1 |
T 44500 23800 9 10 1 0 0 0 1 |
CMP #2 |
T 44500 23500 9 10 1 0 0 0 1 |
CMP #3 |
B 42900 22500 2300 900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 22800 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 22500 800 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43900 23200 9 10 1 0 0 0 1 |
Proj #3 |
T 44500 22900 9 10 1 0 0 0 1 |
CMP #1 |
T 44500 22600 9 10 1 0 0 0 1 |
CMP #2 |
B 43900 26800 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44000 26900 9 10 1 0 0 0 1 |
TARGET #1 |
B 45200 26800 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 45300 26900 9 10 1 0 0 0 1 |
TARGET #2 |
B 46500 26800 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 46600 26900 9 10 1 0 0 0 1 |
TARGET #3 |
B 47800 26800 1300 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 47900 26900 9 10 1 0 0 0 1 |
TARGET #4 |
/doc/src/drawing/sch/data_fig2.sch
0,0 → 1,72
v 20100214 2 |
C 42600 22000 1 0 0 frame_800x600.sym |
B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 49500 27300 9 10 1 0 0 0 1 |
Serial Uart |
T 49500 26700 9 10 1 0 0 0 1 |
VGA Display |
T 49600 26200 9 10 1 0 0 0 1 |
PS2 Mouse |
T 49600 25600 9 10 1 0 0 0 1 |
Switches |
T 49700 25100 9 10 1 0 0 0 1 |
Leds |
T 49500 24500 9 10 1 0 0 0 1 |
Push Buttons |
T 49500 23900 9 10 1 0 0 0 1 |
7 Seg display |
T 49500 23100 9 10 1 0 0 0 1 |
I/O connectors |
B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43000 28400 9 10 1 0 0 0 1 |
System |
T 43100 27600 9 10 1 0 0 0 1 |
PCA (Nexys2) |
T 43400 26900 9 10 1 0 0 0 1 |
Targeted Component (Xilinx Spartan 3E-500 FG320) |
B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 43800 26200 9 10 1 0 0 0 1 |
Padring |
T 44100 25700 9 10 1 0 0 0 1 |
Core |
T 44300 25200 9 10 1 0 0 0 1 |
Component |
B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44500 24800 9 10 1 0 0 0 1 |
comp |
T 45600 24800 9 10 1 0 0 0 1 |
comp |
T 46700 24800 9 10 1 0 0 0 1 |
comp |
B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 |
T 44600 27600 9 10 1 0 0 0 1 |
IC |
T 45600 27600 9 10 1 0 0 0 1 |
IC |
T 46600 27600 9 10 1 0 0 0 1 |
IC |
T 47600 27600 9 10 1 0 0 0 1 |
IC |
L 48900 27400 49500 27400 3 0 0 0 -1 -1 |
L 48900 26800 49500 26800 3 0 0 0 -1 -1 |
L 48900 26300 49500 26300 3 0 0 0 -1 -1 |
L 48900 25700 49500 25700 3 0 0 0 -1 -1 |
L 48900 25200 49500 25200 3 0 0 0 -1 -1 |
L 48900 24600 49500 24600 3 0 0 0 -1 -1 |
L 48900 24000 49500 24000 3 0 0 0 -1 -1 |
L 48900 23200 49500 23200 3 0 0 0 -1 -1 |
/lib/cde_serial_rcvr/cde_serial_rcvr.v
172,8 → 172,8
else frame_err <= frame_err; |
|
always@(*) |
if( shift_cnt == {SIZE{1'b1}}) stop_cnt <= 1'b1; |
else stop_cnt <= 1'b0; |
if( shift_cnt == {SIZE{1'b1}}) stop_cnt = 1'b1; |
else stop_cnt = 1'b0; |
|
|
endmodule |
/lib/cde_sram/cde_sram.v
74,7 → 74,7
else $readmemh(INIT_FILE, mem); |
end |
|
|
`ifndef SYNTHESIS |
|
// Function to access GPRs (for use by Verilator). No need to hide this one |
// from the simulator, since it has an input (as required by IEEE 1364-2001). |
85,8 → 85,8
|
endfunction // get_gpr |
|
`endif |
|
|
// Write function |
always@(posedge clk) |
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0]; |
/projects/pic_micro/bin/Makefile.root
0,0 → 1,349
SHELL=/bin/sh |
MAKE=make |
|
VPP_NAME=vppreproc |
VERILOG_NAME=iverilog |
|
CUR_DIR=$(shell pwd) |
VAR_DIR=$(CUR_DIR)/variants |
SRC_DIR=$(CUR_DIR)/verilog |
GEN_DIR=$(CUR_DIR)/gen |
|
|
|
|
|
|
################################################################################ |
# Build rtl code |
################################################################################ |
|
prepare_dirs: |
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi |
|
|
build_fsm: prepare_dirs |
@for COMP in `ls $(CUR_DIR)/fzm`; do \ |
echo "################################################"; \ |
echo; \ |
echo "FSM : $$COMP ####"; echo; \ |
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\ |
done; \ |
|
|
|
|
|
|
|
build_hw: build_fsm |
@echo |
@for VARIANT in `ls $(VAR_DIR)`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Building: $$VARIANT ####"; echo; \ |
cp $(VAR_DIR)/$$VARIANT/defines.v defines.v; \ |
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \ |
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \ |
rm defines.v; \ |
done; \ |
|
|
################################################################################ |
# Build software |
################################################################################ |
|
.PHONY asm_6502: |
asm_6502: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
crasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs16 $(code); \ |
hex2abs $(code); \ |
hex2abs_split $(code); \ |
) |
|
|
|
|
|
|
|
.PHONY asm_pic: |
asm_pic: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
gpasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs12 $(code); \ |
) |
|
|
|
|
|
|
|
|
|
.PHONY asm_msp430: |
asm_msp430: |
(\ |
echo "#######################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
cp ../$(io)/template.def ./$(io).def ;\ |
sed -i "s/PMEM_BASE/$(start)/g" $(io).def;\ |
sed -i "s/PMEM_SIZE/$(pmem)/g" $(io).def;\ |
sed -i "s/DMEM_SIZE/$(dmem)/g" $(io).def;\ |
msp430-as -alsm $(code).s43 -o $(io).o > $(io).l43 ;\ |
msp430-objdump -xdsStr $(io).o >> $(io).l43 ;\ |
msp430-ld -T ./$(io).def $(io).o -o $(io).elf ;\ |
msp430-objcopy -O ihex $(io).elf $(io).hex ;\ |
hex2abs_split $(io); \ |
) |
|
|
|
|
|
|
################################################################################ |
# set up coverage |
################################################################################ |
|
|
|
.PHONY build_cov: |
build_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make build_cdd ;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
################################################################################ |
# run coverage report |
################################################################################ |
|
|
|
.PHONY report_cov: |
report_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Report Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make report_cov;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
|
|
|
|
################################################################################ |
# run simulation suite |
################################################################################ |
|
|
.PHONY clean_sims: |
clean_sims: |
(\ |
rm -f $(CUR_DIR)/../out/*;\ |
rm -f $(CUR_DIR)/../log/*;\ |
) |
|
|
.PHONY run_sims: |
run_sims: clean_sims build_cov |
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Simulating: $$VARIANT_PROG ####"; echo; \ |
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\ |
make sim;\ |
done; \ |
|
|
.PHONY sim: |
sim: |
(\ |
$(VERILOG_NAME) -D VCD ../../bench/verilog/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
mv *.log ../../log;\ |
mv TestBench.vcd ../../out/${test}.vcd ;\ |
rm a.out;\ |
cd ../../cov/${comp};\ |
make score_cov TEST=${test} ;\ |
) |
|
|
|
|
.PHONY rtlsim: |
rtlsim: |
(\ |
$(VERILOG_NAME) -D VCD ../../../bench/verilog/TestBench;\ |
./a.out | tee ./${test}_sim.log ;\ |
mv *.log ../../../log;\ |
mv TestBench.vcd ../../../out/${test}.vcd ;\ |
rm a.out;\ |
) |
|
|
|
|
|
|
|
.PHONY group_build_fpgas: |
group_build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make build_fpgas;\ |
done; \ |
|
|
|
|
|
|
|
|
.PHONY build_fpgas: |
build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../syn`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../syn/$$COMP/;\ |
make fpga;\ |
done; \ |
|
|
|
|
|
|
PHONY: fpga |
fpga: |
(\ |
rm -r xilinx;\ |
mkdir xilinx;\ |
cd xilinx;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
xst -ifn ./Xst -ofn $(board)_$(Design).log;\ |
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\ |
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\ |
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\ |
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\ |
netgen -s 5 -pcf $(board)_$(Design).pcf -sdf_anno true -sdf_path "../gate_sims/par" -insert_glbl true -insert_pp_buffers true -w -dir ../gate_sims/par -ofmt verilog -sim $(board)_$(Design).ncd $(board)_$(Design).v;\ |
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\ |
promgen -u 0 Board_Design_cclk ; \ |
mv Board_Design_cclk.mcs ../debug ;\ |
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\ |
impact -batch ../debug/impact_bat ;\ |
mv *.bit ../debug ;\ |
) |
|
|
|
|
|
|
|
|
.PHONY group_composite: |
group_composite: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make comp_lnk;\ |
done; \ |
|
|
|
|
|
.PHONY group_build_hw: |
group_build_hw: group_start_hw |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/rtl;\ |
echo "include ../../../bin/Makefile.root" > Makefile;\ |
make build_hw;\ |
done; \ |
|
|
|
.PHONY group_start_hw: |
group_start_hw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_hw;\ |
done; \ |
|
|
|
|
.PHONY group_build_sw: |
group_build_sw: group_start_sw |
@for COMP in `ls $(CUR_DIR)/../sw`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../sw/$$COMP;\ |
make all;\ |
done; \ |
|
|
.PHONY group_start_sw: |
group_start_sw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_sw;\ |
done; \ |
|
|
|
.PHONY group_run_sims: |
group_run_sims: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims COMP=$$COMP ;\ |
make report_cov ;\ |
done; \ |
|
|
|
|
projects/pic_micro/bin/Makefile.root
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse_mrisc.xml
===================================================================
--- projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse_mrisc.xml (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse_mrisc.xml (revision 49)
@@ -0,0 +1,84 @@
+
+
+ soc_mouse_mrisc
+ pic_micro
+
+
+ ps2_interface
+ ps2_interface
+ logic
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ io_module
+ io_module
+ logic
+
+
+
+ serial_rcvr
+ serial_rcvr
+ logic
+
+
+
+ terminal
+ terminal
+ logic
+
+
+
+ uart
+ uart
+ logic
+
+
+
+ mouse_ctrl
+ mouse_ctrl
+ logic
+
+
+
+ vga_char_ctrl
+ vga_char_ctrl
+ logic
+
+
+
+ vga_interface
+ vga_interface
+ logic
+
+
+
+
+
+
+
+
+
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse.xml
===================================================================
--- projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse.xml (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse.xml (revision 49)
@@ -0,0 +1,85 @@
+
+
+ soc_mouse
+ pic_micro
+
+
+ ps2_interface
+ ps2_interface
+ logic
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+
+ io_module
+ io_module
+ logic
+
+
+
+ serial_rcvr
+ serial_rcvr
+ logic
+
+
+
+ terminal
+ terminal
+ logic
+
+
+
+ uart
+ uart
+ logic
+
+
+
+ mouse_ctrl
+ mouse_ctrl
+ logic
+
+
+
+ vga_char_ctrl
+ vga_char_ctrl
+ logic
+
+
+
+ vga_interface
+ vga_interface
+ logic
+
+
+
+
+
+
+
+
+
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse/defines.v
===================================================================
--- projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse/defines.v (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse/defines.v (revision 49)
@@ -0,0 +1,3 @@
+`define VARIANT soc_mouse
+`define CDE cde
+`define CPU pic16c5x
projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse/defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/Makefile
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/Makefile (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=soc_mouse_mrisc
+test=mouse_mrisc
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/liblist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/liblist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/liblist (revision 49)
@@ -0,0 +1,8 @@
+`include "../../lib/cde_sram/cde_sram.v"
+`include "../../lib/cde_lifo/cde_lifo.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+
projects/pic_micro/ip/soc_mouse/sim/run/mouse/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/TB.defs
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/TB.defs (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/TB.defs (revision 49)
@@ -0,0 +1,11 @@
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/mouse/mouse.abs12"
+`define TIMEOUT 500000
+
+
+
+
+
+
projects/pic_micro/ip/soc_mouse/sim/run/mouse/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/copyright
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/copyright (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/copyright (revision 49)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
projects/pic_micro/ip/soc_mouse/sim/run/mouse/copyright
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/test_define
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/test_define (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/test_define (revision 49)
@@ -0,0 +1,93 @@
+initial
+begin
+$display(" ");
+$display(" ===================================================");
+$display(" Test Start");
+$display(" ===================================================");
+$display(" ");
+cg.next(20);
+cg.reset_off;
+fork
+
+begin
+ps2_model.rcv_byte(8'hff,1'b1);
+cg.next(5000);
+ps2_model.send_byte(8'hfa);
+cg.next(20000);
+ps2_model.send_byte(8'haa);
+cg.next(20000);
+ps2_model.send_byte(8'h00);
+ps2_model.rcv_byte(8'hf3,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hc8,1'b0);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hf3,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'h64,1'b0);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hf3,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'h50,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hf2,1'b0);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+cg.next(20000);
+ps2_model.send_byte(8'h03);
+ps2_model.rcv_byte(8'he8,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'h03,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hf3,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'h28,1'b1);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+ps2_model.rcv_byte(8'hf4,1'b0);
+cg.next(2000);
+ps2_model.send_byte(8'hfa);
+cg.next(20000);
+ps2_model.send_byte(8'h12);
+cg.next(20000);
+ps2_model.send_byte(8'h34);
+cg.next(20000);
+ps2_model.send_byte(8'h56);
+cg.next(20000);
+ps2_model.send_byte(8'h78);
+cg.next(20000);
+ps2_model.send_byte(8'h9a);
+cg.next(20000);
+ps2_model.send_byte(8'hbc);
+cg.next(20000);
+end
+begin
+uart_model.rcv_byte(8'h64);
+
+
+cg.next(20);
+uart_model.send_byte(8'h45);
+uart_model.rcv_byte(8'h46);
+
+uart_model.send_byte(8'h32);
+uart_model.rcv_byte(8'h33);
+
+uart_model.send_byte(8'h39);
+uart_model.rcv_byte(8'h3a);
+
+end
+
+join
+cg.exit;
+end
+
+
+
projects/pic_micro/ip/soc_mouse/sim/run/mouse/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/dmp_define
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/dmp_define (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/dmp_define (revision 49)
@@ -0,0 +1,4 @@
+$dumpfile ("TestBench.vcd");
+$dumpvars (0, TB);
+
+
projects/pic_micro/ip/soc_mouse/sim/run/mouse/dmp_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/filelist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/filelist (revision 49)
@@ -0,0 +1,9 @@
+`include "../../../rtl/gen/sim/soc_mouse.v"
+`include "../../../../pic16c5x/rtl/gen/sim/pic16c5x.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module_mouse.v"
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
+
+
projects/pic_micro/ip/soc_mouse/sim/run/mouse/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/dut
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/dut (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/dut (revision 49)
@@ -0,0 +1,128 @@
+
+
+
+
+
+wire device_rx_read;
+wire [7:0] device_rx_data;
+wire device_rx_parity;
+wire ps2_data_pad_oe;
+wire ps2_data_pad_in;
+wire ps2_data;
+wire ps2_clk_pad_oe;
+wire ps2_clk_pad_in;
+wire ps2_clk;
+
+
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+
+wire [9:0] y_pos;
+wire [9:0] x_pos;
+wire new_packet;
+wire ms_mid;
+wire ms_right;
+wire ms_left;
+
+
+
+wire txd_pad_out;
+wire rxd_pad_in;
+wire cts_pad_in;
+wire rts_pad_out;
+
+
+// Instantiate one CPU to be tested.
+soc_mouse
+#(
+.ROM_WORDS ( `ROM_WORDS ),
+.ROM_ADDR ( `ROM_ADDR ),
+.ROM_WIDTH ( `ROM_WIDTH ),
+.ROM_FILE ( `ROM_FILE )
+)
+dut(
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+
+
+ .portaout ( portaout ),
+ .portbout ( portbout ),
+ .portcout ( portcout ),
+
+
+ .y_pos ( y_pos ),
+ .x_pos ( x_pos ),
+ .new_packet ( new_packet ),
+ .ms_mid ( ms_mid ),
+ .ms_right ( ms_right ),
+ .ms_left ( ms_left ),
+
+
+
+ .txd_pad_out ( serial_txd ),
+ .rxd_pad_in ( serial_rxd ),
+ .cts_pad_in ( loop2 ),
+ .rts_pad_out ( loop2 )
+
+ );
+
+
+
+
+
+
+
+
+iobuftri
+data_tri_buf
+ (
+ .i ( 1'b0 ),
+ .oe ( ps2_data_pad_oe ),
+ .o ( ps2_data_pad_in ),
+ .pad ( ps2_data )
+ );
+
+
+iobuftri
+clk_tri_buf
+ (
+ .i ( 1'b0 ),
+ .oe ( ps2_clk_pad_oe ),
+ .o ( ps2_clk_pad_in ),
+ .pad ( ps2_clk )
+ );
+
+
+
+pullup ua0(ps2_clk);
+pullup ua1(ps2_data);
+
+
+ps2_model
+#(.CLKCNT(10'h177))
+ps2_model
+(
+ .clk ( clk ),
+ .reset ( reset ),
+ .ps2_clk ( ps2_clk ),
+ .ps2_data ( ps2_data )
+
+);
+
+
+ uart_model #(.CLKCNT(4'hc))
+ uart_model (
+ .clk ( clk ),
+ .reset ( reset ),
+ .txd_in ( serial_txd ),
+ .rxd_out ( serial_rxd )
+ );
projects/pic_micro/ip/soc_mouse/sim/run/mouse/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/modellist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/modellist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/modellist (revision 49)
@@ -0,0 +1,5 @@
+`include "../../bench/verilog/models/clock_gen.v"
+`include "../../bench/verilog/models/ps2_model.v"
+`include "../../bench/verilog/models/iobuftri.v"
+`include "../../bench/verilog/models/uart_model.v"
+`include "../../bench/verilog/models/io_probe.v"
projects/pic_micro/ip/soc_mouse/sim/run/mouse/modellist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/run/mouse/Makefile
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/run/mouse/Makefile (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/run/mouse/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=soc_mouse
+test=mouse
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/liblist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/liblist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/liblist (revision 49)
@@ -0,0 +1,6 @@
+`include "../../lib/cde_sram/cde_sram.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/TB.defs
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/TB.defs (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/TB.defs (revision 49)
@@ -0,0 +1,11 @@
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/mouse/mouse.abs12"
+`define TIMEOUT 500000
+
+
+
+
+
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/filelist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/filelist (revision 49)
@@ -0,0 +1,10 @@
+`include "../../../rtl/gen/syn/soc_mouse_mrisc.v"
+`include "../../../../mrisc/rtl/gen/syn/mrisc.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v"
+
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/dut
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/dut (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/dut (revision 49)
@@ -0,0 +1,79 @@
+
+
+
+
+
+wire device_rx_read;
+wire [7:0] device_rx_data;
+wire device_rx_parity;
+wire ps2_data_pad_oe;
+wire ps2_data_pad_in;
+wire ps2_data;
+wire ps2_clk_pad_oe;
+wire ps2_clk_pad_in;
+wire ps2_clk;
+
+
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+
+wire [9:0] y_pos;
+wire [9:0] x_pos;
+wire new_packet;
+wire ms_mid;
+wire ms_right;
+wire ms_left;
+
+
+
+wire txd_pad_out;
+wire rxd_pad_in;
+wire cts_pad_in;
+wire rts_pad_out;
+
+
+// Instantiate one CPU to be tested.
+soc_mouse_mrisc
+#(
+.ROM_WORDS ( `ROM_WORDS ),
+.ROM_ADDR ( `ROM_ADDR ),
+.ROM_WIDTH ( `ROM_WIDTH ),
+.ROM_FILE ( `ROM_FILE )
+)
+dut(
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+
+
+ .portaout ( portaout ),
+ .portbout ( portbout ),
+ .portcout ( portcout ),
+
+
+ .y_pos ( y_pos ),
+ .x_pos ( x_pos ),
+ .new_packet ( new_packet ),
+ .ms_mid ( ms_mid ),
+ .ms_right ( ms_right ),
+ .ms_left ( ms_left ),
+
+
+
+ .txd_pad_out ( loop1 ),
+ .rxd_pad_in ( loop1 ),
+ .cts_pad_in ( loop2 ),
+ .rts_pad_out ( loop2 )
+
+ );
+
+
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/Makefile
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/Makefile (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/Makefile (revision 49)
@@ -0,0 +1,49 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > soc_mouse_mrisc.v ;\
+ covered score -i TB.dut.pic -t mrisc -I ./ -v ./soc_mouse_mrisc.v -o soc_mouse_mrisc_cpu.cdd 2> soc_mouse_mrisc_cpu_cov.log | tee >> soc_mouse_mrisc_cpu_cov.log ;\
+ covered score -i TB.dut.io_module -t io_module_mouse -I ./ -v ./soc_mouse_mrisc.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd soc_mouse_mrisc_cpu.cdd -vcd ../../out/$(TEST).vcd 2>> cpu_sco_cov.log | tee >> cpu_sco_cov.log ;\
+ covered score -cdd io_module.cdd -vcd ../../out/$(TEST).vcd 2>> io_sco_cov.log | tee >> io_sco_cov.log ;\
+
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd soc_mouse_mrisc_cpu.cdd 2> cpu_rep_cov.log | tee >> cpu_rep_cov.log ;\
+ covered report -cdd io_module.cdd 2> io_rep_cov.log | tee >> io_rep_cov.log ;\
\ No newline at end of file
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/liblist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/liblist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/liblist (revision 49)
@@ -0,0 +1,8 @@
+`include "../../lib/cde_sram/cde_sram.v"
+`include "../../lib/cde_lifo/cde_lifo.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/TB.defs
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/TB.defs (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/TB.defs (revision 49)
@@ -0,0 +1,11 @@
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/mouse/mouse.abs12"
+`define TIMEOUT 500000
+
+
+
+
+
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist (revision 49)
@@ -0,0 +1,9 @@
+`include "../../../rtl/gen/syn/soc_mouse.v"
+`include "../../../../pic16c5x/rtl/gen/syn/pic16c5x.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v"
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
+
+
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/dut
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/dut (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/dut (revision 49)
@@ -0,0 +1,128 @@
+
+
+
+
+
+wire device_rx_read;
+wire [7:0] device_rx_data;
+wire device_rx_parity;
+wire ps2_data_pad_oe;
+wire ps2_data_pad_in;
+wire ps2_data;
+wire ps2_clk_pad_oe;
+wire ps2_clk_pad_in;
+wire ps2_clk;
+
+
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+
+wire [9:0] y_pos;
+wire [9:0] x_pos;
+wire new_packet;
+wire ms_mid;
+wire ms_right;
+wire ms_left;
+
+
+
+wire txd_pad_out;
+wire rxd_pad_in;
+wire cts_pad_in;
+wire rts_pad_out;
+
+
+// Instantiate one CPU to be tested.
+soc_mouse
+#(
+.ROM_WORDS ( `ROM_WORDS ),
+.ROM_ADDR ( `ROM_ADDR ),
+.ROM_WIDTH ( `ROM_WIDTH ),
+.ROM_FILE ( `ROM_FILE )
+)
+dut(
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+
+
+ .portaout ( portaout ),
+ .portbout ( portbout ),
+ .portcout ( portcout ),
+
+
+ .y_pos ( y_pos ),
+ .x_pos ( x_pos ),
+ .new_packet ( new_packet ),
+ .ms_mid ( ms_mid ),
+ .ms_right ( ms_right ),
+ .ms_left ( ms_left ),
+
+
+
+ .txd_pad_out ( serial_txd ),
+ .rxd_pad_in ( serial_rxd ),
+ .cts_pad_in ( loop2 ),
+ .rts_pad_out ( loop2 )
+
+ );
+
+
+
+
+
+
+
+
+iobuftri
+data_tri_buf
+ (
+ .i ( 1'b0 ),
+ .oe ( ps2_data_pad_oe ),
+ .o ( ps2_data_pad_in ),
+ .pad ( ps2_data )
+ );
+
+
+iobuftri
+clk_tri_buf
+ (
+ .i ( 1'b0 ),
+ .oe ( ps2_clk_pad_oe ),
+ .o ( ps2_clk_pad_in ),
+ .pad ( ps2_clk )
+ );
+
+
+
+pullup ua0(ps2_clk);
+pullup ua1(ps2_data);
+
+
+ps2_model
+#(.CLKCNT(10'h177))
+ps2_model
+(
+ .clk ( clk ),
+ .reset ( reset ),
+ .ps2_clk ( ps2_clk ),
+ .ps2_data ( ps2_data )
+
+);
+
+
+ uart_model #(.CLKCNT(4'hc))
+ uart_model (
+ .clk ( clk ),
+ .reset ( reset ),
+ .txd_in ( serial_txd ),
+ .rxd_out ( serial_rxd )
+ );
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/Makefile
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/Makefile (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/Makefile (revision 49)
@@ -0,0 +1,49 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > soc_mouse.v ;\
+ covered score -i TB.dut.pic -t pic16c5x -I ./ -v ./soc_mouse.v -o soc_mouse_cpu.cdd 2> soc_mouse_cpu_cov.log | tee >> soc_mouse_cpu_cov.log ;\
+ covered score -i TB.dut.io_module -t io_module_mouse -I ./ -v ./soc_mouse.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd pic16c5x_cpu.cdd -vcd ../../out/$(TEST).vcd 2>> cpu_sco_cov.log | tee >> cpu_sco_cov.log ;\
+ covered score -cdd io_module.cdd -vcd ../../out/$(TEST).vcd 2>> io_sco_cov.log | tee >> io_sco_cov.log ;\
+
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd soc_mouse_cpu.cdd 2> cpu_rep_cov.log | tee >> cpu_rep_cov.log ;\
+ covered report -cdd io_module.cdd 2> io_rep_cov.log | tee >> io_rep_cov.log ;\
\ No newline at end of file
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/bsdl/xc3s1200e_fg320_1532.bsd
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/bsdl/xc3s1200e_fg320_1532.bsd (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/bsdl/xc3s1200e_fg320_1532.bsd (revision 49)
@@ -0,0 +1,1591 @@
+--$ XILINX$RCSfile: xc3s1200e_fg320_1532.bsd,v $
+--$ XILINX$Revision: 1.2.124.1 $
+
+--###################################################################
+-- WARNING !!!! .. This is a 1532 PROTOTYPE BDSL file.
+--###################################################################
+--
+-- It should not be be used in place of, or along side of 1149.1 bsdl files.
+--
+-- This file conforms to the unapproved IEEE Standard 1532 BSDL draft
+-- Standard. It may not function as expected with IEEE 1149.1 BSDL
+-- and is subject to change pending the ratification of the 1532 Standard
+-- by the IEEE. When denoted as FINAL, it has been verified
+-- syntactically, and against hardware.
+--
+-- Prototype 1532 BSDL file for device XC3S1200E, package FG320
+-- Xilinx, Inc. $State: Exp $ $Date: 2008/07/07 22:23:21 $
+--
+-- Generated by BSDLnet bsdlnet Version 1.40
+------------------------------------------------------------------------
+-- Modification History
+-- | Generated on 05/28/08
+-- | CR # 471899
+-- | Details - Initial Release using BSDLnet.
+-- | Added 'attribute COMPLIANCE_PATTERNS' & changed boundary
+-- | register attribute to internal for PROG_B & PUDC_B.
+------------------------------------------------------------------------
+--
+-- createBSDL template $RCSfile: xc3s1200e_fg320_1532.bsd,v $ $Revision: 1.2.124.1 $ $Date: 2008/07/07 22:23:21 $
+--
+--###################################################################
+--
+--
+-- For technical support, contact Xilinx on the web at:
+--
+-- http://support.xilinx.com
+--
+-- Technical support can also take place via email or phone at:
+--
+-- North America 1-800-255-7778 hotline@xilinx.com
+-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
+-- France (33) 1 3463 0100 frhelp@xilinx.com
+-- Germany (49) 89 991 54930 dlhelp@xilinx.com
+-- Japan (81) 3-3297-9163 jhotline@xilinx.com
+--
+--
+-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
+-- the post-configuration JTAG behavior (if any), edit this file as described
+-- below. Many of these changes are demonstrated by commented-out template
+-- lines preceeding the lines they would replace:
+--
+-- 1. Set disable result of all pads as configured.
+-- 2. Set safe state of boundary cells as necessary.
+-- 3. Rename entity if necessary to avoid name collisions.
+-- 4. Modify USERCODE value in USERCODE_REGISTER declaration.
+--
+--###################################################################--
+
+----------------------------------
+
+-- BSDL File for 1532 Standard.
+
+----------------------------------
+
+entity XC3S1200E_FG320 is
+
+-- Generic Parameter
+
+generic (PHYSICAL_PIN_MAP : string := "FG320" );
+
+-- Logical Port Description
+
+port (
+ A10: inout bit; -- PAD40
+ A11: inout bit; -- PAD49
+ A12: inout bit; -- PAD54
+ A13: inout bit; -- PAD59
+ A14: inout bit; -- PAD62
+ A16: inout bit; -- PAD76
+ A4: inout bit; -- PAD5
+ A6: inout bit; -- PAD14
+ A7: inout bit; -- PAD20
+ A8: inout bit; -- PAD28
+ B10: inout bit; -- PAD41
+ B11: inout bit; -- PAD42
+ B13: inout bit; -- PAD58
+ B14: inout bit; -- PAD63
+ B16: inout bit; -- PAD77
+ B4: inout bit; -- PAD4
+ B6: inout bit; -- PAD15
+ C1: inout bit; -- PAD304
+ C11: inout bit; -- PAD48
+ C14: inout bit; -- PAD72
+ C17: inout bit; -- PAD80
+ C18: inout bit; -- PAD81
+ C2: inout bit; -- PAD303
+ C3: inout bit; -- PAD2
+ C4: inout bit; -- PAD6
+ C5: inout bit; -- PAD8
+ C7: inout bit; -- PAD27
+ C9: inout bit; -- PAD37
+ D1: inout bit; -- PAD302
+ D10: inout bit; -- PAD44
+ D11: inout bit; -- PAD47
+ D13: inout bit; -- PAD57
+ D14: inout bit; -- PAD73
+ D16: inout bit; -- PAD82
+ D17: inout bit; -- PAD83
+ D2: inout bit; -- PAD301
+ D4: inout bit; -- PAD298
+ D5: inout bit; -- PAD7
+ D6: inout bit; -- PAD12
+ D7: inout bit; -- PAD26
+ D9: inout bit; -- PAD36
+ DONE: inout bit;
+ E1: inout bit; -- PAD296
+ E10: inout bit; -- PAD43
+ E11: inout bit; -- PAD51
+ E12: inout bit; -- PAD55
+ E13: inout bit; -- PAD71
+ E15: inout bit; -- PAD85
+ E16: inout bit; -- PAD84
+ E2: inout bit; -- PAD297
+ E3: inout bit; -- PAD291
+ E4: inout bit; -- PAD292
+ E6: inout bit; -- PAD11
+ E7: inout bit; -- PAD21
+ E8: inout bit; -- PAD30
+ E9: inout bit; -- PAD34
+ F1: inout bit; -- PAD287
+ F11: inout bit; -- PAD50
+ F12: inout bit; -- PAD56
+ F14: inout bit; -- PAD92
+ F15: inout bit; -- PAD93
+ F17: inout bit; -- PAD99
+ F18: inout bit; -- PAD100
+ F2: inout bit; -- PAD286
+ F7: inout bit; -- PAD22
+ F8: inout bit; -- PAD29
+ F9: inout bit; -- PAD33
+ G13: inout bit; -- PAD97
+ G14: inout bit; -- PAD98
+ G15: inout bit; -- PAD103
+ G16: inout bit; -- PAD102
+ G3: inout bit; -- PAD285
+ G4: inout bit; -- PAD284
+ G5: inout bit; -- PAD281
+ G6: inout bit; -- PAD282
+ G9: inout bit; -- PAD35
+ GND: linkage bit_vector (1 to 28);
+ H1: inout bit; -- PAD274
+ H14: inout bit; -- PAD105
+ H15: inout bit; -- PAD104
+ H16: inout bit; -- PAD108
+ H17: inout bit; -- PAD107
+ H2: inout bit; -- PAD275
+ H3: inout bit; -- PAD276
+ H4: inout bit; -- PAD277
+ H5: inout bit; -- PAD279
+ H6: inout bit; -- PAD280
+ IPAD10: in bit;
+ IPAD101: in bit;
+ IPAD106: in bit;
+ IPAD111: in bit;
+ IPAD116: in bit;
+ IPAD121: in bit;
+ IPAD126: in bit;
+ IPAD131: in bit;
+ IPAD136: in bit;
+ IPAD141: in bit;
+ IPAD148: in bit;
+ IPAD155: in bit;
+ IPAD161: in bit;
+ IPAD162: in bit;
+ IPAD183: in bit;
+ IPAD184: in bit;
+ IPAD190: in bit;
+ IPAD191: in bit;
+ IPAD197: in bit;
+ IPAD198: in bit;
+ IPAD204: in bit;
+ IPAD205: in bit;
+ IPAD226: in bit;
+ IPAD227: in bit;
+ IPAD230: in bit;
+ IPAD231: in bit;
+ IPAD238: in bit;
+ IPAD243: in bit;
+ IPAD248: in bit;
+ IPAD253: in bit;
+ IPAD258: in bit;
+ IPAD263: in bit;
+ IPAD268: in bit;
+ IPAD273: in bit;
+ IPAD278: in bit;
+ IPAD283: in bit;
+ IPAD288: in bit;
+ IPAD293: in bit;
+ IPAD3: in bit;
+ IPAD300: in bit;
+ IPAD31: in bit;
+ IPAD32: in bit;
+ IPAD38: in bit;
+ IPAD39: in bit;
+ IPAD45: in bit;
+ IPAD46: in bit;
+ IPAD52: in bit;
+ IPAD53: in bit;
+ IPAD74: in bit;
+ IPAD75: in bit;
+ IPAD78: in bit;
+ IPAD79: in bit;
+ IPAD86: in bit;
+ IPAD9: in bit;
+ IPAD91: in bit;
+ IPAD96: in bit;
+ J1: inout bit; -- PAD270
+ J12: inout bit; -- PAD110
+ J13: inout bit; -- PAD109
+ J14: inout bit; -- PAD112
+ J15: inout bit; -- PAD113
+ J16: inout bit; -- PAD114
+ J17: inout bit; -- PAD115
+ J2: inout bit; -- PAD269
+ J4: inout bit; -- PAD271
+ J5: inout bit; -- PAD272
+ K12: inout bit; -- PAD119
+ K13: inout bit; -- PAD120
+ K14: inout bit; -- PAD117
+ K15: inout bit; -- PAD118
+ K3: inout bit; -- PAD267
+ K4: inout bit; -- PAD266
+ K5: inout bit; -- PAD264
+ K6: inout bit; -- PAD265
+ L1: inout bit; -- PAD262
+ L15: inout bit; -- PAD124
+ L16: inout bit; -- PAD125
+ L17: inout bit; -- PAD122
+ L18: inout bit; -- PAD123
+ L2: inout bit; -- PAD261
+ L3: inout bit; -- PAD260
+ L4: inout bit; -- PAD259
+ L5: inout bit; -- PAD256
+ L6: inout bit; -- PAD257
+ M10: inout bit; -- PAD186
+ M13: inout bit; -- PAD134
+ M14: inout bit; -- PAD135
+ M15: inout bit; -- PAD130
+ M16: inout bit; -- PAD129
+ M18: inout bit; -- PAD127
+ M3: inout bit; -- PAD254
+ M4: inout bit; -- PAD255
+ M5: inout bit; -- PAD252
+ M6: inout bit; -- PAD251
+ M9: inout bit; -- PAD195
+ N10: inout bit; -- PAD185
+ N11: inout bit; -- PAD181
+ N12: inout bit; -- PAD171
+ N14: inout bit; -- PAD139
+ N15: inout bit; -- PAD140
+ N18: inout bit; -- PAD128
+ N4: inout bit; -- PAD250
+ N5: inout bit; -- PAD249
+ N7: inout bit; -- PAD208
+ N8: inout bit; -- PAD202
+ N9: inout bit; -- PAD196
+ P1: inout bit; -- PAD244
+ P10: inout bit; -- PAD188
+ P11: inout bit; -- PAD182
+ P12: inout bit; -- PAD170
+ P13: inout bit; -- PAD167
+ P16: inout bit; -- PAD142
+ P17: inout bit; -- PAD133
+ P18: inout bit; -- PAD132
+ P2: inout bit; -- PAD245
+ P3: inout bit; -- PAD242
+ P4: inout bit; -- PAD241
+ P6: inout bit; -- PAD214
+ P7: inout bit; -- PAD207
+ P8: inout bit; -- PAD203
+ P9: inout bit; -- PAD201
+ PROG_B: in bit;
+ PUDC_B: in bit; -- PAD1
+ R10: inout bit; -- PAD189
+ R11: inout bit; -- PAD180
+ R12: inout bit; -- PAD173
+ R13: inout bit; -- PAD166
+ R14: inout bit; -- PAD159
+ R15: inout bit; -- PAD147
+ R16: inout bit; -- PAD146
+ R18: inout bit; -- PAD150
+ R2: inout bit; -- PAD234
+ R3: inout bit; -- PAD235
+ R5: inout bit; -- PAD222
+ R6: inout bit; -- PAD215
+ R8: inout bit; -- PAD200
+ R9: inout bit; -- PAD194
+ T1: inout bit; -- PAD232
+ T12: inout bit; -- PAD174
+ T14: inout bit; -- PAD160
+ T15: inout bit; -- PAD158
+ T16: inout bit; -- PAD154
+ T17: inout bit; -- PAD151
+ T18: inout bit; -- PAD149
+ T2: inout bit; -- PAD233
+ T3: inout bit; -- PAD228
+ T4: inout bit; -- PAD224
+ T5: inout bit; -- PAD221
+ T8: inout bit; -- PAD199
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit;
+ U13: inout bit; -- PAD172
+ U15: inout bit; -- PAD156
+ U16: inout bit; -- PAD153
+ U18: inout bit; -- PAD152
+ U3: inout bit; -- PAD229
+ U4: inout bit; -- PAD225
+ U5: inout bit; -- PAD223
+ U6: inout bit; -- PAD209
+ U9: inout bit; -- PAD193
+ V11: inout bit; -- PAD187
+ V12: inout bit; -- PAD179
+ V13: inout bit; -- PAD178
+ V15: inout bit; -- PAD157
+ V5: inout bit; -- PAD211
+ V6: inout bit; -- PAD210
+ V7: inout bit; -- PAD206
+ V9: inout bit; -- PAD192
+ VCCAUX: linkage bit_vector (1 to 8);
+ VCCINT: linkage bit_vector (1 to 8);
+ VCCO_0: linkage bit_vector (1 to 5);
+ VCCO_1: linkage bit_vector (1 to 5);
+ VCCO_2: linkage bit_vector (1 to 5);
+ VCCO_3: linkage bit_vector (1 to 5)
+); --end port list
+
+-- Use Statements
+
+use STD_1149_1_2001.all;
+use STD_1532_2002.all;
+
+-- Component Conformance Statement(s)
+
+attribute COMPONENT_CONFORMANCE of XC3S1200E_FG320 : entity is
+ "STD_1149_1_2001";
+
+-- Device Package Pin Mappings
+
+attribute PIN_MAP of XC3S1200E_FG320 : entity is PHYSICAL_PIN_MAP;
+
+constant FG320: PIN_MAP_STRING:=
+ "A10:A10," &
+ "A11:A11," &
+ "A12:A12," &
+ "A13:A13," &
+ "A14:A14," &
+ "A16:A16," &
+ "A4:A4," &
+ "A6:A6," &
+ "A7:A7," &
+ "A8:A8," &
+ "B10:B10," &
+ "B11:B11," &
+ "B13:B13," &
+ "B14:B14," &
+ "B16:B16," &
+ "B4:B4," &
+ "B6:B6," &
+ "C1:C1," &
+ "C11:C11," &
+ "C14:C14," &
+ "C17:C17," &
+ "C18:C18," &
+ "C2:C2," &
+ "C3:C3," &
+ "C4:C4," &
+ "C5:C5," &
+ "C7:C7," &
+ "C9:C9," &
+ "D1:D1," &
+ "D10:D10," &
+ "D11:D11," &
+ "D13:D13," &
+ "D14:D14," &
+ "D16:D16," &
+ "D17:D17," &
+ "D2:D2," &
+ "D4:D4," &
+ "D5:D5," &
+ "D6:D6," &
+ "D7:D7," &
+ "D9:D9," &
+ "DONE:V17," &
+ "E1:E1," &
+ "E10:E10," &
+ "E11:E11," &
+ "E12:E12," &
+ "E13:E13," &
+ "E15:E15," &
+ "E16:E16," &
+ "E2:E2," &
+ "E3:E3," &
+ "E4:E4," &
+ "E6:E6," &
+ "E7:E7," &
+ "E8:E8," &
+ "E9:E9," &
+ "F1:F1," &
+ "F11:F11," &
+ "F12:F12," &
+ "F14:F14," &
+ "F15:F15," &
+ "F17:F17," &
+ "F18:F18," &
+ "F2:F2," &
+ "F7:F7," &
+ "F8:F8," &
+ "F9:F9," &
+ "G13:G13," &
+ "G14:G14," &
+ "G15:G15," &
+ "G16:G16," &
+ "G3:G3," &
+ "G4:G4," &
+ "G5:G5," &
+ "G6:G6," &
+ "G9:G9," &
+ "GND:(A1,A18,B2,B17,C10,G7,G12,H8,H9,H10," &
+ "H11,J3,J8,J11,K8,K11,K16,L8,L9,L10," &
+ "L11,M7,M12,T9,U2,U17,V1,V18)," &
+ "H1:H1," &
+ "H14:H14," &
+ "H15:H15," &
+ "H16:H16," &
+ "H17:H17," &
+ "H2:H2," &
+ "H3:H3," &
+ "H4:H4," &
+ "H5:H5," &
+ "H6:H6," &
+ "IPAD10:A5," &
+ "IPAD101:H13," &
+ "IPAD106:G18," &
+ "IPAD111:H18," &
+ "IPAD116:K18," &
+ "IPAD121:K17," &
+ "IPAD126:L13," &
+ "IPAD131:L14," &
+ "IPAD136:N17," &
+ "IPAD141:P15," &
+ "IPAD148:R17," &
+ "IPAD155:V16," &
+ "IPAD161:U14," &
+ "IPAD162:V14," &
+ "IPAD183:U11," &
+ "IPAD184:T11," &
+ "IPAD190:T10," &
+ "IPAD191:U10," &
+ "IPAD197:V8," &
+ "IPAD198:U8," &
+ "IPAD204:R7," &
+ "IPAD205:T7," &
+ "IPAD226:V3," &
+ "IPAD227:V4," &
+ "IPAD230:V2," &
+ "IPAD231:U1," &
+ "IPAD238:R1," &
+ "IPAD243:R4," &
+ "IPAD248:N2," &
+ "IPAD253:N1," &
+ "IPAD258:M1," &
+ "IPAD263:K7," &
+ "IPAD268:K2," &
+ "IPAD273:J6," &
+ "IPAD278:J7," &
+ "IPAD283:G1," &
+ "IPAD288:F5," &
+ "IPAD293:F4," &
+ "IPAD3:A3," &
+ "IPAD300:D3," &
+ "IPAD31:D8," &
+ "IPAD32:C8," &
+ "IPAD38:B9," &
+ "IPAD39:B8," &
+ "IPAD45:G10," &
+ "IPAD46:F10," &
+ "IPAD52:D12," &
+ "IPAD53:C12," &
+ "IPAD74:A15," &
+ "IPAD75:B15," &
+ "IPAD78:C15," &
+ "IPAD79:B18," &
+ "IPAD86:D18," &
+ "IPAD9:B5," &
+ "IPAD91:E17," &
+ "IPAD96:E18," &
+ "J1:J1," &
+ "J12:J12," &
+ "J13:J13," &
+ "J14:J14," &
+ "J15:J15," &
+ "J16:J16," &
+ "J17:J17," &
+ "J2:J2," &
+ "J4:J4," &
+ "J5:J5," &
+ "K12:K12," &
+ "K13:K13," &
+ "K14:K14," &
+ "K15:K15," &
+ "K3:K3," &
+ "K4:K4," &
+ "K5:K5," &
+ "K6:K6," &
+ "L1:L1," &
+ "L15:L15," &
+ "L16:L16," &
+ "L17:L17," &
+ "L18:L18," &
+ "L2:L2," &
+ "L3:L3," &
+ "L4:L4," &
+ "L5:L5," &
+ "L6:L6," &
+ "M10:M10," &
+ "M13:M13," &
+ "M14:M14," &
+ "M15:M15," &
+ "M16:M16," &
+ "M18:M18," &
+ "M3:M3," &
+ "M4:M4," &
+ "M5:M5," &
+ "M6:M6," &
+ "M9:M9," &
+ "N10:N10," &
+ "N11:N11," &
+ "N12:N12," &
+ "N14:N14," &
+ "N15:N15," &
+ "N18:N18," &
+ "N4:N4," &
+ "N5:N5," &
+ "N7:N7," &
+ "N8:N8," &
+ "N9:N9," &
+ "P1:P1," &
+ "P10:P10," &
+ "P11:P11," &
+ "P12:P12," &
+ "P13:P13," &
+ "P16:P16," &
+ "P17:P17," &
+ "P18:P18," &
+ "P2:P2," &
+ "P3:P3," &
+ "P4:P4," &
+ "P6:P6," &
+ "P7:P7," &
+ "P8:P8," &
+ "P9:P9," &
+ "PROG_B:B1," &
+ "PUDC_B:B3," &
+ "R10:R10," &
+ "R11:R11," &
+ "R12:R12," &
+ "R13:R13," &
+ "R14:R14," &
+ "R15:R15," &
+ "R16:R16," &
+ "R18:R18," &
+ "R2:R2," &
+ "R3:R3," &
+ "R5:R5," &
+ "R6:R6," &
+ "R8:R8," &
+ "R9:R9," &
+ "T1:T1," &
+ "T12:T12," &
+ "T14:T14," &
+ "T15:T15," &
+ "T16:T16," &
+ "T17:T17," &
+ "T18:T18," &
+ "T2:T2," &
+ "T3:T3," &
+ "T4:T4," &
+ "T5:T5," &
+ "T8:T8," &
+ "TCK:A17," &
+ "TDI:A2," &
+ "TDO:C16," &
+ "TMS:D15," &
+ "U13:U13," &
+ "U15:U15," &
+ "U16:U16," &
+ "U18:U18," &
+ "U3:U3," &
+ "U4:U4," &
+ "U5:U5," &
+ "U6:U6," &
+ "U9:U9," &
+ "V11:V11," &
+ "V12:V12," &
+ "V13:V13," &
+ "V15:V15," &
+ "V5:V5," &
+ "V6:V6," &
+ "V7:V7," &
+ "V9:V9," &
+ "VCCAUX:(B7,B12,G2,G17,M2,M17,U7,U12)," &
+ "VCCINT:(E5,E14,F6,F13,N6,N13,P5,P14)," &
+ "VCCO_0:(A9,C6,C13,G8,G11)," &
+ "VCCO_1:(F16,H12,J18,L12,N16)," &
+ "VCCO_2:(M8,M11,T6,T13,V10)," &
+ "VCCO_3:(F3,H7,K1,L7,N3)";
+
+
+-- Scan Port Identification
+
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both);
+attribute TAP_SCAN_MODE of TMS : signal is true;
+
+-- Compliance-Enable Description
+
+attribute COMPLIANCE_PATTERNS of XC3S1200E_FG320 : entity is
+ "(PROG_B, PUDC_B) (10)";
+
+-- Instruction Register Description
+
+attribute INSTRUCTION_LENGTH of XC3S1200E_FG320 : entity is 6;
+
+attribute INSTRUCTION_OPCODE of XC3S1200E_FG320 : entity is
+
+ "EXTEST (001111)," &
+ "SAMPLE (000001)," &
+ "PRELOAD (000001)," & -- Same as SAMPLE
+ "USER1 (000010)," & -- Not available until after configuration
+ "USER2 (000011)," & -- Not available until after configuration
+ "CFG_OUT (000100)," & -- Not available during configuration with another mode.
+ "CFG_IN (000101)," & -- Not available during configuration with another mode.
+ "INTEST (000111)," &
+ "USERCODE (001000)," &
+ "IDCODE (001001)," &
+ "HIGHZ (001010)," &
+ "JPROGRAM (001011)," & -- Not available during configuration with another mode.
+ "JSTART (001100)," & -- Not available during configuration with another mode.
+ "JSHUTDOWN (001101)," & -- Not available during configuration with another mode.
+ "BYPASS (111111)," &
+ "ISC_ENABLE (010000)," &
+ "ISC_PROGRAM (010001)," &
+ "ISC_NOOP (010100)," &
+ "ISC_READ (010101)," &
+ "ISC_DISABLE (010110)";
+
+attribute INSTRUCTION_CAPTURE of XC3S1200E_FG320 : entity is
+-- Bit 5 is 1 when DONE is released (part of startup sequence)
+-- Bit 4 is 1 if house-cleaning is complete
+-- Bit 3 is ISC_Enabled
+-- Bit 2 is ISC_Done
+ "XXXX01" ;
+
+attribute INSTRUCTION_PRIVATE of XC3S1200E_FG320 : entity is
+ "USER1," &
+ "USER2," &
+ "CFG_OUT," &
+ "CFG_IN," &
+ "JPROGRAM," &
+ "JSTART," &
+ "JSHUTDOWN," &
+ "ISC_ENABLE," &
+ "ISC_PROGRAM," &
+ "ISC_NOOP," &
+ "ISC_READ," &
+ "ISC_DISABLE";
+
+-- Optional Register Description
+
+attribute IDCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXX" & -- version
+ "0001110" & -- family
+ "000101110" & -- array size
+ "00001001001" & -- manufacturer
+ "1"; -- required by 1149.1
+
+
+attribute USERCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+-- Register Access Description
+
+attribute REGISTER_ACCESS of XC3S1200E_FG320 : entity is
+ "TEST1[8] (USER1)," &
+ "TEST2[8] (USER2)," &
+ "DEVICE_ID (USERCODE,IDCODE)," &
+ "BYPASS (BYPASS,HIGHZ,JPROGRAM,JSTART,JSHUTDOWN)," &
+ "CFG_DATA[3838752] (CFG_IN)," &
+ "ISC_PDATA[16] (ISC_PROGRAM),"&
+ "ISC_RDATA[16] (ISC_READ),"&
+ "ISC_DEFAULT[5] (ISC_NOOP)," &
+ "ISC_CONFIG[5] (ISC_ENABLE,ISC_DISABLE)," &
+ "BOUNDARY (EXTEST, SAMPLE, PRELOAD, INTEST)";
+
+-- Boundary-Scan Register Description
+
+attribute BOUNDARY_LENGTH of XC3S1200E_FG320 : entity is 772;
+
+attribute BOUNDARY_REGISTER of XC3S1200E_FG320 : entity is
+-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
+ " 771 (BC_2, IPAD79, input, X)," &
+ " 770 (BC_2, C17, input, X)," & -- PAD80
+ " 769 (BC_2, C17, output3, X, 768, 1, PULL1)," & -- PAD80
+ " 768 (BC_2, *, controlr, 1)," &
+ " 767 (BC_2, C18, input, X)," & -- PAD81
+ " 766 (BC_2, C18, output3, X, 765, 1, PULL1)," & -- PAD81
+ " 765 (BC_2, *, controlr, 1)," &
+ " 764 (BC_2, D16, input, X)," & -- PAD82
+ " 763 (BC_2, D16, output3, X, 762, 1, PULL1)," & -- PAD82
+ " 762 (BC_2, *, controlr, 1)," &
+ " 761 (BC_2, D17, input, X)," & -- PAD83
+ " 760 (BC_2, D17, output3, X, 759, 1, PULL1)," & -- PAD83
+ " 759 (BC_2, *, controlr, 1)," &
+ " 758 (BC_2, E16, input, X)," & -- PAD84
+ " 757 (BC_2, E16, output3, X, 756, 1, PULL1)," & -- PAD84
+ " 756 (BC_2, *, controlr, 1)," &
+ " 755 (BC_2, E15, input, X)," & -- PAD85
+ " 754 (BC_2, E15, output3, X, 753, 1, PULL1)," & -- PAD85
+ " 753 (BC_2, *, controlr, 1)," &
+ " 752 (BC_2, IPAD86, input, X)," &
+ " 751 (BC_2, *, internal, X)," & -- PAD87.I
+ " 750 (BC_2, *, internal, X)," & -- PAD87.O
+ " 749 (BC_2, *, internal, 1)," & -- PAD87.T
+ " 748 (BC_2, *, internal, X)," & -- PAD88.I
+ " 747 (BC_2, *, internal, X)," & -- PAD88.O
+ " 746 (BC_2, *, internal, 1)," & -- PAD88.T
+ " 745 (BC_2, *, internal, X)," & -- PAD89.I
+ " 744 (BC_2, *, internal, X)," & -- PAD89.O
+ " 743 (BC_2, *, internal, 1)," & -- PAD89.T
+ " 742 (BC_2, *, internal, X)," & -- PAD90.I
+ " 741 (BC_2, *, internal, X)," & -- PAD90.O
+ " 740 (BC_2, *, internal, 1)," & -- PAD90.T
+ " 739 (BC_2, IPAD91, input, X)," &
+ " 738 (BC_2, F14, input, X)," & -- PAD92
+ " 737 (BC_2, F14, output3, X, 736, 1, PULL1)," & -- PAD92
+ " 736 (BC_2, *, controlr, 1)," &
+ " 735 (BC_2, F15, input, X)," & -- PAD93
+ " 734 (BC_2, F15, output3, X, 733, 1, PULL1)," & -- PAD93
+ " 733 (BC_2, *, controlr, 1)," &
+ " 732 (BC_2, *, internal, X)," & -- PAD94.I
+ " 731 (BC_2, *, internal, X)," & -- PAD94.O
+ " 730 (BC_2, *, internal, 1)," & -- PAD94.T
+ " 729 (BC_2, *, internal, X)," & -- PAD95.I
+ " 728 (BC_2, *, internal, X)," & -- PAD95.O
+ " 727 (BC_2, *, internal, 1)," & -- PAD95.T
+ " 726 (BC_2, IPAD96, input, X)," &
+ " 725 (BC_2, G13, input, X)," & -- PAD97
+ " 724 (BC_2, G13, output3, X, 723, 1, PULL1)," & -- PAD97
+ " 723 (BC_2, *, controlr, 1)," &
+ " 722 (BC_2, G14, input, X)," & -- PAD98
+ " 721 (BC_2, G14, output3, X, 720, 1, PULL1)," & -- PAD98
+ " 720 (BC_2, *, controlr, 1)," &
+ " 719 (BC_2, F17, input, X)," & -- PAD99
+ " 718 (BC_2, F17, output3, X, 717, 1, PULL1)," & -- PAD99
+ " 717 (BC_2, *, controlr, 1)," &
+ " 716 (BC_2, F18, input, X)," & -- PAD100
+ " 715 (BC_2, F18, output3, X, 714, 1, PULL1)," & -- PAD100
+ " 714 (BC_2, *, controlr, 1)," &
+ " 713 (BC_2, IPAD101, input, X)," &
+ " 712 (BC_2, G16, input, X)," & -- PAD102
+ " 711 (BC_2, G16, output3, X, 710, 1, PULL1)," & -- PAD102
+ " 710 (BC_2, *, controlr, 1)," &
+ " 709 (BC_2, G15, input, X)," & -- PAD103
+ " 708 (BC_2, G15, output3, X, 707, 1, PULL1)," & -- PAD103
+ " 707 (BC_2, *, controlr, 1)," &
+ " 706 (BC_2, H15, input, X)," & -- PAD104
+ " 705 (BC_2, H15, output3, X, 704, 1, PULL1)," & -- PAD104
+ " 704 (BC_2, *, controlr, 1)," &
+ " 703 (BC_2, H14, input, X)," & -- PAD105
+ " 702 (BC_2, H14, output3, X, 701, 1, PULL1)," & -- PAD105
+ " 701 (BC_2, *, controlr, 1)," &
+ " 700 (BC_2, IPAD106, input, X)," &
+ " 699 (BC_2, H17, input, X)," & -- PAD107
+ " 698 (BC_2, H17, output3, X, 697, 1, PULL1)," & -- PAD107
+ " 697 (BC_2, *, controlr, 1)," &
+ " 696 (BC_2, H16, input, X)," & -- PAD108
+ " 695 (BC_2, H16, output3, X, 694, 1, PULL1)," & -- PAD108
+ " 694 (BC_2, *, controlr, 1)," &
+ " 693 (BC_2, J13, input, X)," & -- PAD109
+ " 692 (BC_2, J13, output3, X, 691, 1, PULL1)," & -- PAD109
+ " 691 (BC_2, *, controlr, 1)," &
+ " 690 (BC_2, J12, input, X)," & -- PAD110
+ " 689 (BC_2, J12, output3, X, 688, 1, PULL1)," & -- PAD110
+ " 688 (BC_2, *, controlr, 1)," &
+ " 687 (BC_2, IPAD111, input, X)," &
+ " 686 (BC_2, J14, input, X)," & -- PAD112
+ " 685 (BC_2, J14, output3, X, 684, 1, PULL1)," & -- PAD112
+ " 684 (BC_2, *, controlr, 1)," &
+ " 683 (BC_2, J15, input, X)," & -- PAD113
+ " 682 (BC_2, J15, output3, X, 681, 1, PULL1)," & -- PAD113
+ " 681 (BC_2, *, controlr, 1)," &
+ " 680 (BC_2, J16, input, X)," & -- PAD114
+ " 679 (BC_2, J16, output3, X, 678, 1, PULL1)," & -- PAD114
+ " 678 (BC_2, *, controlr, 1)," &
+ " 677 (BC_2, J17, input, X)," & -- PAD115
+ " 676 (BC_2, J17, output3, X, 675, 1, PULL1)," & -- PAD115
+ " 675 (BC_2, *, controlr, 1)," &
+ " 674 (BC_2, IPAD116, input, X)," &
+ " 673 (BC_2, K14, input, X)," & -- PAD117
+ " 672 (BC_2, K14, output3, X, 671, 1, PULL1)," & -- PAD117
+ " 671 (BC_2, *, controlr, 1)," &
+ " 670 (BC_2, K15, input, X)," & -- PAD118
+ " 669 (BC_2, K15, output3, X, 668, 1, PULL1)," & -- PAD118
+ " 668 (BC_2, *, controlr, 1)," &
+ " 667 (BC_2, K12, input, X)," & -- PAD119
+ " 666 (BC_2, K12, output3, X, 665, 1, PULL1)," & -- PAD119
+ " 665 (BC_2, *, controlr, 1)," &
+ " 664 (BC_2, K13, input, X)," & -- PAD120
+ " 663 (BC_2, K13, output3, X, 662, 1, PULL1)," & -- PAD120
+ " 662 (BC_2, *, controlr, 1)," &
+ " 661 (BC_2, IPAD121, input, X)," &
+ " 660 (BC_2, L17, input, X)," & -- PAD122
+ " 659 (BC_2, L17, output3, X, 658, 1, PULL1)," & -- PAD122
+ " 658 (BC_2, *, controlr, 1)," &
+ " 657 (BC_2, L18, input, X)," & -- PAD123
+ " 656 (BC_2, L18, output3, X, 655, 1, PULL1)," & -- PAD123
+ " 655 (BC_2, *, controlr, 1)," &
+ " 654 (BC_2, L15, input, X)," & -- PAD124
+ " 653 (BC_2, L15, output3, X, 652, 1, PULL1)," & -- PAD124
+ " 652 (BC_2, *, controlr, 1)," &
+ " 651 (BC_2, L16, input, X)," & -- PAD125
+ " 650 (BC_2, L16, output3, X, 649, 1, PULL1)," & -- PAD125
+ " 649 (BC_2, *, controlr, 1)," &
+ " 648 (BC_2, IPAD126, input, X)," &
+ " 647 (BC_2, M18, input, X)," & -- PAD127
+ " 646 (BC_2, M18, output3, X, 645, 1, PULL1)," & -- PAD127
+ " 645 (BC_2, *, controlr, 1)," &
+ " 644 (BC_2, N18, input, X)," & -- PAD128
+ " 643 (BC_2, N18, output3, X, 642, 1, PULL1)," & -- PAD128
+ " 642 (BC_2, *, controlr, 1)," &
+ " 641 (BC_2, M16, input, X)," & -- PAD129
+ " 640 (BC_2, M16, output3, X, 639, 1, PULL1)," & -- PAD129
+ " 639 (BC_2, *, controlr, 1)," &
+ " 638 (BC_2, M15, input, X)," & -- PAD130
+ " 637 (BC_2, M15, output3, X, 636, 1, PULL1)," & -- PAD130
+ " 636 (BC_2, *, controlr, 1)," &
+ " 635 (BC_2, IPAD131, input, X)," &
+ " 634 (BC_2, P18, input, X)," & -- PAD132
+ " 633 (BC_2, P18, output3, X, 632, 1, PULL1)," & -- PAD132
+ " 632 (BC_2, *, controlr, 1)," &
+ " 631 (BC_2, P17, input, X)," & -- PAD133
+ " 630 (BC_2, P17, output3, X, 629, 1, PULL1)," & -- PAD133
+ " 629 (BC_2, *, controlr, 1)," &
+ " 628 (BC_2, M13, input, X)," & -- PAD134
+ " 627 (BC_2, M13, output3, X, 626, 1, PULL1)," & -- PAD134
+ " 626 (BC_2, *, controlr, 1)," &
+ " 625 (BC_2, M14, input, X)," & -- PAD135
+ " 624 (BC_2, M14, output3, X, 623, 1, PULL1)," & -- PAD135
+ " 623 (BC_2, *, controlr, 1)," &
+ " 622 (BC_2, IPAD136, input, X)," &
+ " 621 (BC_2, *, internal, X)," & -- PAD137.I
+ " 620 (BC_2, *, internal, X)," & -- PAD137.O
+ " 619 (BC_2, *, internal, 1)," & -- PAD137.T
+ " 618 (BC_2, *, internal, X)," & -- PAD138.I
+ " 617 (BC_2, *, internal, X)," & -- PAD138.O
+ " 616 (BC_2, *, internal, 1)," & -- PAD138.T
+ " 615 (BC_2, N14, input, X)," & -- PAD139
+ " 614 (BC_2, N14, output3, X, 613, 1, PULL1)," & -- PAD139
+ " 613 (BC_2, *, controlr, 1)," &
+ " 612 (BC_2, N15, input, X)," & -- PAD140
+ " 611 (BC_2, N15, output3, X, 610, 1, PULL1)," & -- PAD140
+ " 610 (BC_2, *, controlr, 1)," &
+ " 609 (BC_2, IPAD141, input, X)," &
+ " 608 (BC_2, P16, input, X)," & -- PAD142
+ " 607 (BC_2, P16, output3, X, 606, 1, PULL1)," & -- PAD142
+ " 606 (BC_2, *, controlr, 1)," &
+ " 605 (BC_2, *, internal, X)," & -- PAD143.I
+ " 604 (BC_2, *, internal, X)," & -- PAD143.O
+ " 603 (BC_2, *, internal, 1)," & -- PAD143.T
+ " 602 (BC_2, *, internal, X)," & -- PAD144.I
+ " 601 (BC_2, *, internal, X)," & -- PAD144.O
+ " 600 (BC_2, *, internal, 1)," & -- PAD144.T
+ " 599 (BC_2, *, internal, X)," & -- PAD145.I
+ " 598 (BC_2, *, internal, X)," & -- PAD145.O
+ " 597 (BC_2, *, internal, 1)," & -- PAD145.T
+ " 596 (BC_2, R16, input, X)," & -- PAD146
+ " 595 (BC_2, R16, output3, X, 594, 1, PULL1)," & -- PAD146
+ " 594 (BC_2, *, controlr, 1)," &
+ " 593 (BC_2, R15, input, X)," & -- PAD147
+ " 592 (BC_2, R15, output3, X, 591, 1, PULL1)," & -- PAD147
+ " 591 (BC_2, *, controlr, 1)," &
+ " 590 (BC_2, IPAD148, input, X)," &
+ " 589 (BC_2, T18, input, X)," & -- PAD149
+ " 588 (BC_2, T18, output3, X, 587, 1, PULL1)," & -- PAD149
+ " 587 (BC_2, *, controlr, 1)," &
+ " 586 (BC_2, R18, input, X)," & -- PAD150
+ " 585 (BC_2, R18, output3, X, 584, 1, PULL1)," & -- PAD150
+ " 584 (BC_2, *, controlr, 1)," &
+ " 583 (BC_2, T17, input, X)," & -- PAD151
+ " 582 (BC_2, T17, output3, X, 581, 1, PULL1)," & -- PAD151
+ " 581 (BC_2, *, controlr, 1)," &
+ " 580 (BC_2, U18, input, X)," & -- PAD152
+ " 579 (BC_2, U18, output3, X, 578, 1, PULL1)," & -- PAD152
+ " 578 (BC_2, *, controlr, 1)," &
+ " 577 (BC_2, DONE, input, X)," &
+ " 576 (BC_2, DONE, output3, X, 575, 1, PULL1)," &
+ " 575 (BC_2, *, controlr, 1)," &
+ " 574 (BC_2, U16, input, X)," & -- PAD153
+ " 573 (BC_2, U16, output3, X, 572, 1, PULL1)," & -- PAD153
+ " 572 (BC_2, *, controlr, 1)," &
+ " 571 (BC_2, T16, input, X)," & -- PAD154
+ " 570 (BC_2, T16, output3, X, 569, 1, PULL1)," & -- PAD154
+ " 569 (BC_2, *, controlr, 1)," &
+ " 568 (BC_2, IPAD155, input, X)," &
+ " 567 (BC_2, U15, input, X)," & -- PAD156
+ " 566 (BC_2, U15, output3, X, 565, 1, PULL1)," & -- PAD156
+ " 565 (BC_2, *, controlr, 1)," &
+ " 564 (BC_2, V15, input, X)," & -- PAD157
+ " 563 (BC_2, V15, output3, X, 562, 1, PULL1)," & -- PAD157
+ " 562 (BC_2, *, controlr, 1)," &
+ " 561 (BC_2, T15, input, X)," & -- PAD158
+ " 560 (BC_2, T15, output3, X, 559, 1, PULL1)," & -- PAD158
+ " 559 (BC_2, *, controlr, 1)," &
+ " 558 (BC_2, R14, input, X)," & -- PAD159
+ " 557 (BC_2, R14, output3, X, 556, 1, PULL1)," & -- PAD159
+ " 556 (BC_2, *, controlr, 1)," &
+ " 555 (BC_2, T14, input, X)," & -- PAD160
+ " 554 (BC_2, T14, output3, X, 553, 1, PULL1)," & -- PAD160
+ " 553 (BC_2, *, controlr, 1)," &
+ " 552 (BC_2, IPAD161, input, X)," &
+ " 551 (BC_2, IPAD162, input, X)," &
+ " 550 (BC_2, *, internal, X)," & -- PAD163.I
+ " 549 (BC_2, *, internal, X)," & -- PAD163.O
+ " 548 (BC_2, *, internal, 1)," & -- PAD163.T
+ " 547 (BC_2, *, internal, X)," & -- PAD164.I
+ " 546 (BC_2, *, internal, X)," & -- PAD164.O
+ " 545 (BC_2, *, internal, 1)," & -- PAD164.T
+ " 544 (BC_2, *, internal, X)," & -- PAD165.I
+ " 543 (BC_2, *, internal, X)," & -- PAD165.O
+ " 542 (BC_2, *, internal, 1)," & -- PAD165.T
+ " 541 (BC_2, R13, input, X)," & -- PAD166
+ " 540 (BC_2, R13, output3, X, 539, 1, PULL1)," & -- PAD166
+ " 539 (BC_2, *, controlr, 1)," &
+ " 538 (BC_2, P13, input, X)," & -- PAD167
+ " 537 (BC_2, P13, output3, X, 536, 1, PULL1)," & -- PAD167
+ " 536 (BC_2, *, controlr, 1)," &
+ " 535 (BC_2, *, internal, X)," & -- IPAD168
+ " 534 (BC_2, *, internal, X)," & -- IPAD169
+ " 533 (BC_2, P12, input, X)," & -- PAD170
+ " 532 (BC_2, P12, output3, X, 531, 1, PULL1)," & -- PAD170
+ " 531 (BC_2, *, controlr, 1)," &
+ " 530 (BC_2, N12, input, X)," & -- PAD171
+ " 529 (BC_2, N12, output3, X, 528, 1, PULL1)," & -- PAD171
+ " 528 (BC_2, *, controlr, 1)," &
+ " 527 (BC_2, U13, input, X)," & -- PAD172
+ " 526 (BC_2, U13, output3, X, 525, 1, PULL1)," & -- PAD172
+ " 525 (BC_2, *, controlr, 1)," &
+ " 524 (BC_2, R12, input, X)," & -- PAD173
+ " 523 (BC_2, R12, output3, X, 522, 1, PULL1)," & -- PAD173
+ " 522 (BC_2, *, controlr, 1)," &
+ " 521 (BC_2, T12, input, X)," & -- PAD174
+ " 520 (BC_2, T12, output3, X, 519, 1, PULL1)," & -- PAD174
+ " 519 (BC_2, *, controlr, 1)," &
+ " 518 (BC_2, *, internal, X)," & -- IPAD175
+ " 517 (BC_2, *, internal, X)," & -- IPAD176
+ " 516 (BC_2, *, internal, X)," & -- PAD177.I
+ " 515 (BC_2, *, internal, X)," & -- PAD177.O
+ " 514 (BC_2, *, internal, 1)," & -- PAD177.T
+ " 513 (BC_2, V13, input, X)," & -- PAD178
+ " 512 (BC_2, V13, output3, X, 511, 1, PULL1)," & -- PAD178
+ " 511 (BC_2, *, controlr, 1)," &
+ " 510 (BC_2, V12, input, X)," & -- PAD179
+ " 509 (BC_2, V12, output3, X, 508, 1, PULL1)," & -- PAD179
+ " 508 (BC_2, *, controlr, 1)," &
+ " 507 (BC_2, R11, input, X)," & -- PAD180
+ " 506 (BC_2, R11, output3, X, 505, 1, PULL1)," & -- PAD180
+ " 505 (BC_2, *, controlr, 1)," &
+ " 504 (BC_2, N11, input, X)," & -- PAD181
+ " 503 (BC_2, N11, output3, X, 502, 1, PULL1)," & -- PAD181
+ " 502 (BC_2, *, controlr, 1)," &
+ " 501 (BC_2, P11, input, X)," & -- PAD182
+ " 500 (BC_2, P11, output3, X, 499, 1, PULL1)," & -- PAD182
+ " 499 (BC_2, *, controlr, 1)," &
+ " 498 (BC_2, IPAD183, input, X)," &
+ " 497 (BC_2, IPAD184, input, X)," &
+ " 496 (BC_2, N10, input, X)," & -- PAD185
+ " 495 (BC_2, N10, output3, X, 494, 1, PULL1)," & -- PAD185
+ " 494 (BC_2, *, controlr, 1)," &
+ " 493 (BC_2, M10, input, X)," & -- PAD186
+ " 492 (BC_2, M10, output3, X, 491, 1, PULL1)," & -- PAD186
+ " 491 (BC_2, *, controlr, 1)," &
+ " 490 (BC_2, V11, input, X)," & -- PAD187
+ " 489 (BC_2, V11, output3, X, 488, 1, PULL1)," & -- PAD187
+ " 488 (BC_2, *, controlr, 1)," &
+ " 487 (BC_2, P10, input, X)," & -- PAD188
+ " 486 (BC_2, P10, output3, X, 485, 1, PULL1)," & -- PAD188
+ " 485 (BC_2, *, controlr, 1)," &
+ " 484 (BC_2, R10, input, X)," & -- PAD189
+ " 483 (BC_2, R10, output3, X, 482, 1, PULL1)," & -- PAD189
+ " 482 (BC_2, *, controlr, 1)," &
+ " 481 (BC_2, IPAD190, input, X)," &
+ " 480 (BC_2, IPAD191, input, X)," &
+ " 479 (BC_2, V9, input, X)," & -- PAD192
+ " 478 (BC_2, V9, output3, X, 477, 1, PULL1)," & -- PAD192
+ " 477 (BC_2, *, controlr, 1)," &
+ " 476 (BC_2, U9, input, X)," & -- PAD193
+ " 475 (BC_2, U9, output3, X, 474, 1, PULL1)," & -- PAD193
+ " 474 (BC_2, *, controlr, 1)," &
+ " 473 (BC_2, R9, input, X)," & -- PAD194
+ " 472 (BC_2, R9, output3, X, 471, 1, PULL1)," & -- PAD194
+ " 471 (BC_2, *, controlr, 1)," &
+ " 470 (BC_2, M9, input, X)," & -- PAD195
+ " 469 (BC_2, M9, output3, X, 468, 1, PULL1)," & -- PAD195
+ " 468 (BC_2, *, controlr, 1)," &
+ " 467 (BC_2, N9, input, X)," & -- PAD196
+ " 466 (BC_2, N9, output3, X, 465, 1, PULL1)," & -- PAD196
+ " 465 (BC_2, *, controlr, 1)," &
+ " 464 (BC_2, IPAD197, input, X)," &
+ " 463 (BC_2, IPAD198, input, X)," &
+ " 462 (BC_2, T8, input, X)," & -- PAD199
+ " 461 (BC_2, T8, output3, X, 460, 1, PULL1)," & -- PAD199
+ " 460 (BC_2, *, controlr, 1)," &
+ " 459 (BC_2, R8, input, X)," & -- PAD200
+ " 458 (BC_2, R8, output3, X, 457, 1, PULL1)," & -- PAD200
+ " 457 (BC_2, *, controlr, 1)," &
+ " 456 (BC_2, P9, input, X)," & -- PAD201
+ " 455 (BC_2, P9, output3, X, 454, 1, PULL1)," & -- PAD201
+ " 454 (BC_2, *, controlr, 1)," &
+ " 453 (BC_2, N8, input, X)," & -- PAD202
+ " 452 (BC_2, N8, output3, X, 451, 1, PULL1)," & -- PAD202
+ " 451 (BC_2, *, controlr, 1)," &
+ " 450 (BC_2, P8, input, X)," & -- PAD203
+ " 449 (BC_2, P8, output3, X, 448, 1, PULL1)," & -- PAD203
+ " 448 (BC_2, *, controlr, 1)," &
+ " 447 (BC_2, IPAD204, input, X)," &
+ " 446 (BC_2, IPAD205, input, X)," &
+ " 445 (BC_2, V7, input, X)," & -- PAD206
+ " 444 (BC_2, V7, output3, X, 443, 1, PULL1)," & -- PAD206
+ " 443 (BC_2, *, controlr, 1)," &
+ " 442 (BC_2, P7, input, X)," & -- PAD207
+ " 441 (BC_2, P7, output3, X, 440, 1, PULL1)," & -- PAD207
+ " 440 (BC_2, *, controlr, 1)," &
+ " 439 (BC_2, N7, input, X)," & -- PAD208
+ " 438 (BC_2, N7, output3, X, 437, 1, PULL1)," & -- PAD208
+ " 437 (BC_2, *, controlr, 1)," &
+ " 436 (BC_2, U6, input, X)," & -- PAD209
+ " 435 (BC_2, U6, output3, X, 434, 1, PULL1)," & -- PAD209
+ " 434 (BC_2, *, controlr, 1)," &
+ " 433 (BC_2, V6, input, X)," & -- PAD210
+ " 432 (BC_2, V6, output3, X, 431, 1, PULL1)," & -- PAD210
+ " 431 (BC_2, *, controlr, 1)," &
+ " 430 (BC_2, V5, input, X)," & -- PAD211
+ " 429 (BC_2, V5, output3, X, 428, 1, PULL1)," & -- PAD211
+ " 428 (BC_2, *, controlr, 1)," &
+ " 427 (BC_2, *, internal, X)," & -- IPAD212
+ " 426 (BC_2, *, internal, X)," & -- IPAD213
+ " 425 (BC_2, P6, input, X)," & -- PAD214
+ " 424 (BC_2, P6, output3, X, 423, 1, PULL1)," & -- PAD214
+ " 423 (BC_2, *, controlr, 1)," &
+ " 422 (BC_2, R6, input, X)," & -- PAD215
+ " 421 (BC_2, R6, output3, X, 420, 1, PULL1)," & -- PAD215
+ " 420 (BC_2, *, controlr, 1)," &
+ " 419 (BC_2, *, internal, X)," & -- PAD216.I
+ " 418 (BC_2, *, internal, X)," & -- PAD216.O
+ " 417 (BC_2, *, internal, 1)," & -- PAD216.T
+ " 416 (BC_2, *, internal, X)," & -- PAD217.I
+ " 415 (BC_2, *, internal, X)," & -- PAD217.O
+ " 414 (BC_2, *, internal, 1)," & -- PAD217.T
+ " 413 (BC_2, *, internal, X)," & -- PAD218.I
+ " 412 (BC_2, *, internal, X)," & -- PAD218.O
+ " 411 (BC_2, *, internal, 1)," & -- PAD218.T
+ " 410 (BC_2, *, internal, X)," & -- IPAD219
+ " 409 (BC_2, *, internal, X)," & -- IPAD220
+ " 408 (BC_2, T5, input, X)," & -- PAD221
+ " 407 (BC_2, T5, output3, X, 406, 1, PULL1)," & -- PAD221
+ " 406 (BC_2, *, controlr, 1)," &
+ " 405 (BC_2, R5, input, X)," & -- PAD222
+ " 404 (BC_2, R5, output3, X, 403, 1, PULL1)," & -- PAD222
+ " 403 (BC_2, *, controlr, 1)," &
+ " 402 (BC_2, U5, input, X)," & -- PAD223
+ " 401 (BC_2, U5, output3, X, 400, 1, PULL1)," & -- PAD223
+ " 400 (BC_2, *, controlr, 1)," &
+ " 399 (BC_2, T4, input, X)," & -- PAD224
+ " 398 (BC_2, T4, output3, X, 397, 1, PULL1)," & -- PAD224
+ " 397 (BC_2, *, controlr, 1)," &
+ " 396 (BC_2, U4, input, X)," & -- PAD225
+ " 395 (BC_2, U4, output3, X, 394, 1, PULL1)," & -- PAD225
+ " 394 (BC_2, *, controlr, 1)," &
+ " 393 (BC_2, IPAD226, input, X)," &
+ " 392 (BC_2, IPAD227, input, X)," &
+ " 391 (BC_2, T3, input, X)," & -- PAD228
+ " 390 (BC_2, T3, output3, X, 389, 1, PULL1)," & -- PAD228
+ " 389 (BC_2, *, controlr, 1)," &
+ " 388 (BC_2, U3, input, X)," & -- PAD229
+ " 387 (BC_2, U3, output3, X, 386, 1, PULL1)," & -- PAD229
+ " 386 (BC_2, *, controlr, 1)," &
+ " 385 (BC_2, IPAD230, input, X)," &
+ " 384 (BC_2, IPAD231, input, X)," &
+ " 383 (BC_2, T1, input, X)," & -- PAD232
+ " 382 (BC_2, T1, output3, X, 381, 1, PULL1)," & -- PAD232
+ " 381 (BC_2, *, controlr, 1)," &
+ " 380 (BC_2, T2, input, X)," & -- PAD233
+ " 379 (BC_2, T2, output3, X, 378, 1, PULL1)," & -- PAD233
+ " 378 (BC_2, *, controlr, 1)," &
+ " 377 (BC_2, R2, input, X)," & -- PAD234
+ " 376 (BC_2, R2, output3, X, 375, 1, PULL1)," & -- PAD234
+ " 375 (BC_2, *, controlr, 1)," &
+ " 374 (BC_2, R3, input, X)," & -- PAD235
+ " 373 (BC_2, R3, output3, X, 372, 1, PULL1)," & -- PAD235
+ " 372 (BC_2, *, controlr, 1)," &
+ " 371 (BC_2, *, internal, X)," & -- PAD236.I
+ " 370 (BC_2, *, internal, X)," & -- PAD236.O
+ " 369 (BC_2, *, internal, 1)," & -- PAD236.T
+ " 368 (BC_2, *, internal, X)," & -- PAD237.I
+ " 367 (BC_2, *, internal, X)," & -- PAD237.O
+ " 366 (BC_2, *, internal, 1)," & -- PAD237.T
+ " 365 (BC_2, IPAD238, input, X)," &
+ " 364 (BC_2, *, internal, X)," & -- PAD239.I
+ " 363 (BC_2, *, internal, X)," & -- PAD239.O
+ " 362 (BC_2, *, internal, 1)," & -- PAD239.T
+ " 361 (BC_2, *, internal, X)," & -- PAD240.I
+ " 360 (BC_2, *, internal, X)," & -- PAD240.O
+ " 359 (BC_2, *, internal, 1)," & -- PAD240.T
+ " 358 (BC_2, P4, input, X)," & -- PAD241
+ " 357 (BC_2, P4, output3, X, 356, 1, PULL1)," & -- PAD241
+ " 356 (BC_2, *, controlr, 1)," &
+ " 355 (BC_2, P3, input, X)," & -- PAD242
+ " 354 (BC_2, P3, output3, X, 353, 1, PULL1)," & -- PAD242
+ " 353 (BC_2, *, controlr, 1)," &
+ " 352 (BC_2, IPAD243, input, X)," &
+ " 351 (BC_2, P1, input, X)," & -- PAD244
+ " 350 (BC_2, P1, output3, X, 349, 1, PULL1)," & -- PAD244
+ " 349 (BC_2, *, controlr, 1)," &
+ " 348 (BC_2, P2, input, X)," & -- PAD245
+ " 347 (BC_2, P2, output3, X, 346, 1, PULL1)," & -- PAD245
+ " 346 (BC_2, *, controlr, 1)," &
+ " 345 (BC_2, *, internal, X)," & -- PAD246.I
+ " 344 (BC_2, *, internal, X)," & -- PAD246.O
+ " 343 (BC_2, *, internal, 1)," & -- PAD246.T
+ " 342 (BC_2, *, internal, X)," & -- PAD247.I
+ " 341 (BC_2, *, internal, X)," & -- PAD247.O
+ " 340 (BC_2, *, internal, 1)," & -- PAD247.T
+ " 339 (BC_2, IPAD248, input, X)," &
+ " 338 (BC_2, N5, input, X)," & -- PAD249
+ " 337 (BC_2, N5, output3, X, 336, 1, PULL1)," & -- PAD249
+ " 336 (BC_2, *, controlr, 1)," &
+ " 335 (BC_2, N4, input, X)," & -- PAD250
+ " 334 (BC_2, N4, output3, X, 333, 1, PULL1)," & -- PAD250
+ " 333 (BC_2, *, controlr, 1)," &
+ " 332 (BC_2, M6, input, X)," & -- PAD251
+ " 331 (BC_2, M6, output3, X, 330, 1, PULL1)," & -- PAD251
+ " 330 (BC_2, *, controlr, 1)," &
+ " 329 (BC_2, M5, input, X)," & -- PAD252
+ " 328 (BC_2, M5, output3, X, 327, 1, PULL1)," & -- PAD252
+ " 327 (BC_2, *, controlr, 1)," &
+ " 326 (BC_2, IPAD253, input, X)," &
+ " 325 (BC_2, M3, input, X)," & -- PAD254
+ " 324 (BC_2, M3, output3, X, 323, 1, PULL1)," & -- PAD254
+ " 323 (BC_2, *, controlr, 1)," &
+ " 322 (BC_2, M4, input, X)," & -- PAD255
+ " 321 (BC_2, M4, output3, X, 320, 1, PULL1)," & -- PAD255
+ " 320 (BC_2, *, controlr, 1)," &
+ " 319 (BC_2, L5, input, X)," & -- PAD256
+ " 318 (BC_2, L5, output3, X, 317, 1, PULL1)," & -- PAD256
+ " 317 (BC_2, *, controlr, 1)," &
+ " 316 (BC_2, L6, input, X)," & -- PAD257
+ " 315 (BC_2, L6, output3, X, 314, 1, PULL1)," & -- PAD257
+ " 314 (BC_2, *, controlr, 1)," &
+ " 313 (BC_2, IPAD258, input, X)," &
+ " 312 (BC_2, L4, input, X)," & -- PAD259
+ " 311 (BC_2, L4, output3, X, 310, 1, PULL1)," & -- PAD259
+ " 310 (BC_2, *, controlr, 1)," &
+ " 309 (BC_2, L3, input, X)," & -- PAD260
+ " 308 (BC_2, L3, output3, X, 307, 1, PULL1)," & -- PAD260
+ " 307 (BC_2, *, controlr, 1)," &
+ " 306 (BC_2, L2, input, X)," & -- PAD261
+ " 305 (BC_2, L2, output3, X, 304, 1, PULL1)," & -- PAD261
+ " 304 (BC_2, *, controlr, 1)," &
+ " 303 (BC_2, L1, input, X)," & -- PAD262
+ " 302 (BC_2, L1, output3, X, 301, 1, PULL1)," & -- PAD262
+ " 301 (BC_2, *, controlr, 1)," &
+ " 300 (BC_2, IPAD263, input, X)," &
+ " 299 (BC_2, K5, input, X)," & -- PAD264
+ " 298 (BC_2, K5, output3, X, 297, 1, PULL1)," & -- PAD264
+ " 297 (BC_2, *, controlr, 1)," &
+ " 296 (BC_2, K6, input, X)," & -- PAD265
+ " 295 (BC_2, K6, output3, X, 294, 1, PULL1)," & -- PAD265
+ " 294 (BC_2, *, controlr, 1)," &
+ " 293 (BC_2, K4, input, X)," & -- PAD266
+ " 292 (BC_2, K4, output3, X, 291, 1, PULL1)," & -- PAD266
+ " 291 (BC_2, *, controlr, 1)," &
+ " 290 (BC_2, K3, input, X)," & -- PAD267
+ " 289 (BC_2, K3, output3, X, 288, 1, PULL1)," & -- PAD267
+ " 288 (BC_2, *, controlr, 1)," &
+ " 287 (BC_2, IPAD268, input, X)," &
+ " 286 (BC_2, J2, input, X)," & -- PAD269
+ " 285 (BC_2, J2, output3, X, 284, 1, PULL1)," & -- PAD269
+ " 284 (BC_2, *, controlr, 1)," &
+ " 283 (BC_2, J1, input, X)," & -- PAD270
+ " 282 (BC_2, J1, output3, X, 281, 1, PULL1)," & -- PAD270
+ " 281 (BC_2, *, controlr, 1)," &
+ " 280 (BC_2, J4, input, X)," & -- PAD271
+ " 279 (BC_2, J4, output3, X, 278, 1, PULL1)," & -- PAD271
+ " 278 (BC_2, *, controlr, 1)," &
+ " 277 (BC_2, J5, input, X)," & -- PAD272
+ " 276 (BC_2, J5, output3, X, 275, 1, PULL1)," & -- PAD272
+ " 275 (BC_2, *, controlr, 1)," &
+ " 274 (BC_2, IPAD273, input, X)," &
+ " 273 (BC_2, H1, input, X)," & -- PAD274
+ " 272 (BC_2, H1, output3, X, 271, 1, PULL1)," & -- PAD274
+ " 271 (BC_2, *, controlr, 1)," &
+ " 270 (BC_2, H2, input, X)," & -- PAD275
+ " 269 (BC_2, H2, output3, X, 268, 1, PULL1)," & -- PAD275
+ " 268 (BC_2, *, controlr, 1)," &
+ " 267 (BC_2, H3, input, X)," & -- PAD276
+ " 266 (BC_2, H3, output3, X, 265, 1, PULL1)," & -- PAD276
+ " 265 (BC_2, *, controlr, 1)," &
+ " 264 (BC_2, H4, input, X)," & -- PAD277
+ " 263 (BC_2, H4, output3, X, 262, 1, PULL1)," & -- PAD277
+ " 262 (BC_2, *, controlr, 1)," &
+ " 261 (BC_2, IPAD278, input, X)," &
+ " 260 (BC_2, H5, input, X)," & -- PAD279
+ " 259 (BC_2, H5, output3, X, 258, 1, PULL1)," & -- PAD279
+ " 258 (BC_2, *, controlr, 1)," &
+ " 257 (BC_2, H6, input, X)," & -- PAD280
+ " 256 (BC_2, H6, output3, X, 255, 1, PULL1)," & -- PAD280
+ " 255 (BC_2, *, controlr, 1)," &
+ " 254 (BC_2, G5, input, X)," & -- PAD281
+ " 253 (BC_2, G5, output3, X, 252, 1, PULL1)," & -- PAD281
+ " 252 (BC_2, *, controlr, 1)," &
+ " 251 (BC_2, G6, input, X)," & -- PAD282
+ " 250 (BC_2, G6, output3, X, 249, 1, PULL1)," & -- PAD282
+ " 249 (BC_2, *, controlr, 1)," &
+ " 248 (BC_2, IPAD283, input, X)," &
+ " 247 (BC_2, G4, input, X)," & -- PAD284
+ " 246 (BC_2, G4, output3, X, 245, 1, PULL1)," & -- PAD284
+ " 245 (BC_2, *, controlr, 1)," &
+ " 244 (BC_2, G3, input, X)," & -- PAD285
+ " 243 (BC_2, G3, output3, X, 242, 1, PULL1)," & -- PAD285
+ " 242 (BC_2, *, controlr, 1)," &
+ " 241 (BC_2, F2, input, X)," & -- PAD286
+ " 240 (BC_2, F2, output3, X, 239, 1, PULL1)," & -- PAD286
+ " 239 (BC_2, *, controlr, 1)," &
+ " 238 (BC_2, F1, input, X)," & -- PAD287
+ " 237 (BC_2, F1, output3, X, 236, 1, PULL1)," & -- PAD287
+ " 236 (BC_2, *, controlr, 1)," &
+ " 235 (BC_2, IPAD288, input, X)," &
+ " 234 (BC_2, *, internal, X)," & -- PAD289.I
+ " 233 (BC_2, *, internal, X)," & -- PAD289.O
+ " 232 (BC_2, *, internal, 1)," & -- PAD289.T
+ " 231 (BC_2, *, internal, X)," & -- PAD290.I
+ " 230 (BC_2, *, internal, X)," & -- PAD290.O
+ " 229 (BC_2, *, internal, 1)," & -- PAD290.T
+ " 228 (BC_2, E3, input, X)," & -- PAD291
+ " 227 (BC_2, E3, output3, X, 226, 1, PULL1)," & -- PAD291
+ " 226 (BC_2, *, controlr, 1)," &
+ " 225 (BC_2, E4, input, X)," & -- PAD292
+ " 224 (BC_2, E4, output3, X, 223, 1, PULL1)," & -- PAD292
+ " 223 (BC_2, *, controlr, 1)," &
+ " 222 (BC_2, IPAD293, input, X)," &
+ " 221 (BC_2, *, internal, X)," & -- PAD294.I
+ " 220 (BC_2, *, internal, X)," & -- PAD294.O
+ " 219 (BC_2, *, internal, 1)," & -- PAD294.T
+ " 218 (BC_2, *, internal, X)," & -- PAD295.I
+ " 217 (BC_2, *, internal, X)," & -- PAD295.O
+ " 216 (BC_2, *, internal, 1)," & -- PAD295.T
+ " 215 (BC_2, E1, input, X)," & -- PAD296
+ " 214 (BC_2, E1, output3, X, 213, 1, PULL1)," & -- PAD296
+ " 213 (BC_2, *, controlr, 1)," &
+ " 212 (BC_2, E2, input, X)," & -- PAD297
+ " 211 (BC_2, E2, output3, X, 210, 1, PULL1)," & -- PAD297
+ " 210 (BC_2, *, controlr, 1)," &
+ " 209 (BC_2, D4, input, X)," & -- PAD298
+ " 208 (BC_2, D4, output3, X, 207, 1, PULL1)," & -- PAD298
+ " 207 (BC_2, *, controlr, 1)," &
+ " 206 (BC_2, *, internal, X)," & -- PAD299.I
+ " 205 (BC_2, *, internal, X)," & -- PAD299.O
+ " 204 (BC_2, *, internal, 1)," & -- PAD299.T
+ " 203 (BC_2, IPAD300, input, X)," &
+ " 202 (BC_2, D2, input, X)," & -- PAD301
+ " 201 (BC_2, D2, output3, X, 200, 1, PULL1)," & -- PAD301
+ " 200 (BC_2, *, controlr, 1)," &
+ " 199 (BC_2, D1, input, X)," & -- PAD302
+ " 198 (BC_2, D1, output3, X, 197, 1, PULL1)," & -- PAD302
+ " 197 (BC_2, *, controlr, 1)," &
+ " 196 (BC_2, C2, input, X)," & -- PAD303
+ " 195 (BC_2, C2, output3, X, 194, 1, PULL1)," & -- PAD303
+ " 194 (BC_2, *, controlr, 1)," &
+ " 193 (BC_2, C1, input, X)," & -- PAD304
+ " 192 (BC_2, C1, output3, X, 191, 1, PULL1)," & -- PAD304
+ " 191 (BC_2, *, controlr, 1)," &
+ " 190 (BC_2, *, internal, 1)," & -- PROG_B
+ " 189 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 188 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 187 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 186 (BC_2, C3, input, X)," & -- PAD2
+ " 185 (BC_2, C3, output3, X, 184, 1, PULL1)," & -- PAD2
+ " 184 (BC_2, *, controlr, 1)," &
+ " 183 (BC_2, IPAD3, input, X)," &
+ " 182 (BC_2, B4, input, X)," & -- PAD4
+ " 181 (BC_2, B4, output3, X, 180, 1, PULL1)," & -- PAD4
+ " 180 (BC_2, *, controlr, 1)," &
+ " 179 (BC_2, A4, input, X)," & -- PAD5
+ " 178 (BC_2, A4, output3, X, 177, 1, PULL1)," & -- PAD5
+ " 177 (BC_2, *, controlr, 1)," &
+ " 176 (BC_2, C4, input, X)," & -- PAD6
+ " 175 (BC_2, C4, output3, X, 174, 1, PULL1)," & -- PAD6
+ " 174 (BC_2, *, controlr, 1)," &
+ " 173 (BC_2, D5, input, X)," & -- PAD7
+ " 172 (BC_2, D5, output3, X, 171, 1, PULL1)," & -- PAD7
+ " 171 (BC_2, *, controlr, 1)," &
+ " 170 (BC_2, C5, input, X)," & -- PAD8
+ " 169 (BC_2, C5, output3, X, 168, 1, PULL1)," & -- PAD8
+ " 168 (BC_2, *, controlr, 1)," &
+ " 167 (BC_2, IPAD9, input, X)," &
+ " 166 (BC_2, IPAD10, input, X)," &
+ " 165 (BC_2, E6, input, X)," & -- PAD11
+ " 164 (BC_2, E6, output3, X, 163, 1, PULL1)," & -- PAD11
+ " 163 (BC_2, *, controlr, 1)," &
+ " 162 (BC_2, D6, input, X)," & -- PAD12
+ " 161 (BC_2, D6, output3, X, 160, 1, PULL1)," & -- PAD12
+ " 160 (BC_2, *, controlr, 1)," &
+ " 159 (BC_2, *, internal, X)," & -- PAD13.I
+ " 158 (BC_2, *, internal, X)," & -- PAD13.O
+ " 157 (BC_2, *, internal, 1)," & -- PAD13.T
+ " 156 (BC_2, A6, input, X)," & -- PAD14
+ " 155 (BC_2, A6, output3, X, 154, 1, PULL1)," & -- PAD14
+ " 154 (BC_2, *, controlr, 1)," &
+ " 153 (BC_2, B6, input, X)," & -- PAD15
+ " 152 (BC_2, B6, output3, X, 151, 1, PULL1)," & -- PAD15
+ " 151 (BC_2, *, controlr, 1)," &
+ " 150 (BC_2, *, internal, X)," & -- IPAD16
+ " 149 (BC_2, *, internal, X)," & -- IPAD17
+ " 148 (BC_2, *, internal, X)," & -- PAD18.I
+ " 147 (BC_2, *, internal, X)," & -- PAD18.O
+ " 146 (BC_2, *, internal, 1)," & -- PAD18.T
+ " 145 (BC_2, *, internal, X)," & -- PAD19.I
+ " 144 (BC_2, *, internal, X)," & -- PAD19.O
+ " 143 (BC_2, *, internal, 1)," & -- PAD19.T
+ " 142 (BC_2, A7, input, X)," & -- PAD20
+ " 141 (BC_2, A7, output3, X, 140, 1, PULL1)," & -- PAD20
+ " 140 (BC_2, *, controlr, 1)," &
+ " 139 (BC_2, E7, input, X)," & -- PAD21
+ " 138 (BC_2, E7, output3, X, 137, 1, PULL1)," & -- PAD21
+ " 137 (BC_2, *, controlr, 1)," &
+ " 136 (BC_2, F7, input, X)," & -- PAD22
+ " 135 (BC_2, F7, output3, X, 134, 1, PULL1)," & -- PAD22
+ " 134 (BC_2, *, controlr, 1)," &
+ " 133 (BC_2, *, internal, X)," & -- IPAD23
+ " 132 (BC_2, *, internal, X)," & -- IPAD24
+ " 131 (BC_2, *, internal, X)," & -- PAD25.I
+ " 130 (BC_2, *, internal, X)," & -- PAD25.O
+ " 129 (BC_2, *, internal, 1)," & -- PAD25.T
+ " 128 (BC_2, D7, input, X)," & -- PAD26
+ " 127 (BC_2, D7, output3, X, 126, 1, PULL1)," & -- PAD26
+ " 126 (BC_2, *, controlr, 1)," &
+ " 125 (BC_2, C7, input, X)," & -- PAD27
+ " 124 (BC_2, C7, output3, X, 123, 1, PULL1)," & -- PAD27
+ " 123 (BC_2, *, controlr, 1)," &
+ " 122 (BC_2, A8, input, X)," & -- PAD28
+ " 121 (BC_2, A8, output3, X, 120, 1, PULL1)," & -- PAD28
+ " 120 (BC_2, *, controlr, 1)," &
+ " 119 (BC_2, F8, input, X)," & -- PAD29
+ " 118 (BC_2, F8, output3, X, 117, 1, PULL1)," & -- PAD29
+ " 117 (BC_2, *, controlr, 1)," &
+ " 116 (BC_2, E8, input, X)," & -- PAD30
+ " 115 (BC_2, E8, output3, X, 114, 1, PULL1)," & -- PAD30
+ " 114 (BC_2, *, controlr, 1)," &
+ " 113 (BC_2, IPAD31, input, X)," &
+ " 112 (BC_2, IPAD32, input, X)," &
+ " 111 (BC_2, F9, input, X)," & -- PAD33
+ " 110 (BC_2, F9, output3, X, 109, 1, PULL1)," & -- PAD33
+ " 109 (BC_2, *, controlr, 1)," &
+ " 108 (BC_2, E9, input, X)," & -- PAD34
+ " 107 (BC_2, E9, output3, X, 106, 1, PULL1)," & -- PAD34
+ " 106 (BC_2, *, controlr, 1)," &
+ " 105 (BC_2, G9, input, X)," & -- PAD35
+ " 104 (BC_2, G9, output3, X, 103, 1, PULL1)," & -- PAD35
+ " 103 (BC_2, *, controlr, 1)," &
+ " 102 (BC_2, D9, input, X)," & -- PAD36
+ " 101 (BC_2, D9, output3, X, 100, 1, PULL1)," & -- PAD36
+ " 100 (BC_2, *, controlr, 1)," &
+ " 99 (BC_2, C9, input, X)," & -- PAD37
+ " 98 (BC_2, C9, output3, X, 97, 1, PULL1)," & -- PAD37
+ " 97 (BC_2, *, controlr, 1)," &
+ " 96 (BC_2, IPAD38, input, X)," &
+ " 95 (BC_2, IPAD39, input, X)," &
+ " 94 (BC_2, A10, input, X)," & -- PAD40
+ " 93 (BC_2, A10, output3, X, 92, 1, PULL1)," & -- PAD40
+ " 92 (BC_2, *, controlr, 1)," &
+ " 91 (BC_2, B10, input, X)," & -- PAD41
+ " 90 (BC_2, B10, output3, X, 89, 1, PULL1)," & -- PAD41
+ " 89 (BC_2, *, controlr, 1)," &
+ " 88 (BC_2, B11, input, X)," & -- PAD42
+ " 87 (BC_2, B11, output3, X, 86, 1, PULL1)," & -- PAD42
+ " 86 (BC_2, *, controlr, 1)," &
+ " 85 (BC_2, E10, input, X)," & -- PAD43
+ " 84 (BC_2, E10, output3, X, 83, 1, PULL1)," & -- PAD43
+ " 83 (BC_2, *, controlr, 1)," &
+ " 82 (BC_2, D10, input, X)," & -- PAD44
+ " 81 (BC_2, D10, output3, X, 80, 1, PULL1)," & -- PAD44
+ " 80 (BC_2, *, controlr, 1)," &
+ " 79 (BC_2, IPAD45, input, X)," &
+ " 78 (BC_2, IPAD46, input, X)," &
+ " 77 (BC_2, D11, input, X)," & -- PAD47
+ " 76 (BC_2, D11, output3, X, 75, 1, PULL1)," & -- PAD47
+ " 75 (BC_2, *, controlr, 1)," &
+ " 74 (BC_2, C11, input, X)," & -- PAD48
+ " 73 (BC_2, C11, output3, X, 72, 1, PULL1)," & -- PAD48
+ " 72 (BC_2, *, controlr, 1)," &
+ " 71 (BC_2, A11, input, X)," & -- PAD49
+ " 70 (BC_2, A11, output3, X, 69, 1, PULL1)," & -- PAD49
+ " 69 (BC_2, *, controlr, 1)," &
+ " 68 (BC_2, F11, input, X)," & -- PAD50
+ " 67 (BC_2, F11, output3, X, 66, 1, PULL1)," & -- PAD50
+ " 66 (BC_2, *, controlr, 1)," &
+ " 65 (BC_2, E11, input, X)," & -- PAD51
+ " 64 (BC_2, E11, output3, X, 63, 1, PULL1)," & -- PAD51
+ " 63 (BC_2, *, controlr, 1)," &
+ " 62 (BC_2, IPAD52, input, X)," &
+ " 61 (BC_2, IPAD53, input, X)," &
+ " 60 (BC_2, A12, input, X)," & -- PAD54
+ " 59 (BC_2, A12, output3, X, 58, 1, PULL1)," & -- PAD54
+ " 58 (BC_2, *, controlr, 1)," &
+ " 57 (BC_2, E12, input, X)," & -- PAD55
+ " 56 (BC_2, E12, output3, X, 55, 1, PULL1)," & -- PAD55
+ " 55 (BC_2, *, controlr, 1)," &
+ " 54 (BC_2, F12, input, X)," & -- PAD56
+ " 53 (BC_2, F12, output3, X, 52, 1, PULL1)," & -- PAD56
+ " 52 (BC_2, *, controlr, 1)," &
+ " 51 (BC_2, D13, input, X)," & -- PAD57
+ " 50 (BC_2, D13, output3, X, 49, 1, PULL1)," & -- PAD57
+ " 49 (BC_2, *, controlr, 1)," &
+ " 48 (BC_2, B13, input, X)," & -- PAD58
+ " 47 (BC_2, B13, output3, X, 46, 1, PULL1)," & -- PAD58
+ " 46 (BC_2, *, controlr, 1)," &
+ " 45 (BC_2, A13, input, X)," & -- PAD59
+ " 44 (BC_2, A13, output3, X, 43, 1, PULL1)," & -- PAD59
+ " 43 (BC_2, *, controlr, 1)," &
+ " 42 (BC_2, *, internal, X)," & -- IPAD60
+ " 41 (BC_2, *, internal, X)," & -- IPAD61
+ " 40 (BC_2, A14, input, X)," & -- PAD62
+ " 39 (BC_2, A14, output3, X, 38, 1, PULL1)," & -- PAD62
+ " 38 (BC_2, *, controlr, 1)," &
+ " 37 (BC_2, B14, input, X)," & -- PAD63
+ " 36 (BC_2, B14, output3, X, 35, 1, PULL1)," & -- PAD63
+ " 35 (BC_2, *, controlr, 1)," &
+ " 34 (BC_2, *, internal, X)," & -- PAD64.I
+ " 33 (BC_2, *, internal, X)," & -- PAD64.O
+ " 32 (BC_2, *, internal, 1)," & -- PAD64.T
+ " 31 (BC_2, *, internal, X)," & -- PAD65.I
+ " 30 (BC_2, *, internal, X)," & -- PAD65.O
+ " 29 (BC_2, *, internal, 1)," & -- PAD65.T
+ " 28 (BC_2, *, internal, X)," & -- PAD66.I
+ " 27 (BC_2, *, internal, X)," & -- PAD66.O
+ " 26 (BC_2, *, internal, 1)," & -- PAD66.T
+ " 25 (BC_2, *, internal, X)," & -- IPAD67
+ " 24 (BC_2, *, internal, X)," & -- IPAD68
+ " 23 (BC_2, *, internal, X)," & -- PAD69.I
+ " 22 (BC_2, *, internal, X)," & -- PAD69.O
+ " 21 (BC_2, *, internal, 1)," & -- PAD69.T
+ " 20 (BC_2, *, internal, X)," & -- PAD70.I
+ " 19 (BC_2, *, internal, X)," & -- PAD70.O
+ " 18 (BC_2, *, internal, 1)," & -- PAD70.T
+ " 17 (BC_2, E13, input, X)," & -- PAD71
+ " 16 (BC_2, E13, output3, X, 15, 1, PULL1)," & -- PAD71
+ " 15 (BC_2, *, controlr, 1)," &
+ " 14 (BC_2, C14, input, X)," & -- PAD72
+ " 13 (BC_2, C14, output3, X, 12, 1, PULL1)," & -- PAD72
+ " 12 (BC_2, *, controlr, 1)," &
+ " 11 (BC_2, D14, input, X)," & -- PAD73
+ " 10 (BC_2, D14, output3, X, 9, 1, PULL1)," & -- PAD73
+ " 9 (BC_2, *, controlr, 1)," &
+ " 8 (BC_2, IPAD74, input, X)," &
+ " 7 (BC_2, IPAD75, input, X)," &
+ " 6 (BC_2, A16, input, X)," & -- PAD76
+ " 5 (BC_2, A16, output3, X, 4, 1, PULL1)," & -- PAD76
+ " 4 (BC_2, *, controlr, 1)," &
+ " 3 (BC_2, B16, input, X)," & -- PAD77
+ " 2 (BC_2, B16, output3, X, 1, 1, PULL1)," & -- PAD77
+ " 1 (BC_2, *, controlr, 1)," &
+ " 0 (BC_2, IPAD78, input, X)";
+
+
+attribute ISC_PIN_BEHAVIOR of XC3S1200E_FG320 : entity is
+ "HIGHZ" ; -- clamp behavior
+ -- no status
+
+attribute ISC_STATUS of XC3S1200E_FG320 : entity is
+ "NOT IMPLEMENTED" ;
+
+attribute ISC_BLANK_USERCODE of XC3S1200E_FG320 : entity is
+ "00000000000000000000000000000000";
+
+attribute ISC_FLOW of XC3S1200E_FG320 : entity is
+ -- Enable program
+ "flow_enable " &
+ "initialize " &
+ " (ISC_ENABLE 5:00 wait TCK 16)," &
+
+ "flow_disable " &
+ "initialize " &
+ " (ISC_DISABLE wait TCK 16)" &
+ " (BYPASS 1:0 wait TCK 1)," &
+
+ "flow_program(array) " &
+ "Repeat 239922 " &
+ " (ISC_PROGRAM 16:? wait TCK 1 )," &
+
+ "flow_program(legacy) " &
+ "Initialize " &
+ " (JSHUTDOWN wait TCK 16)" &
+ " (CFG_IN 3838752:? wait TCK 1)" &
+ " (JSTART wait TCK 32)" &
+ " (BYPASS 1:0 wait TCK 1)," &
+
+ "flow_verify(idcode) " &
+ "initialize " &
+ " (IDCODE wait TCK 1 32:01C2E093*0FFFFFFF)," &
+
+ "flow_read(usercode) " &
+ "initialize " &
+ " (USERCODE wait TCK 1 32:!)," &
+
+ "flow_read(idcode) " &
+ "initialize " &
+ " (IDCODE wait TCK 1 32:!)," &
+
+ "flow_program_done " &
+ "initialize " &
+ " (BYPASS wait TCK 1)," &
+
+ "flow_error_exit " &
+ "initialize " &
+ " (BYPASS wait TCK 1)";
+
+attribute ISC_PROCEDURE of XC3S1200E_FG320 : entity is
+ "proc_enable = (flow_enable)," &
+ "proc_disable = (flow_disable)," &
+ "proc_program = (flow_program(array))," &
+ "proc_program(legacy) = (flow_program(legacy))," &
+ "proc_verify(idcode) = (flow_verify(idcode))," &
+ "proc_read(idcode) = (flow_read(idcode))," &
+ "proc_read(usercode) = (flow_read(usercode))," &
+ "proc_program_done = (flow_program_done)," &
+ "proc_error_exit = (flow_error_exit)";
+
+attribute ISC_ACTION of XC3S1200E_FG320 : entity is
+ "program = (proc_verify(idcode) recommended," &
+ " proc_enable, proc_program," &
+ " proc_disable)," &
+ "program(lgcy) = (proc_verify(idcode) recommended," &
+ " proc_enable, proc_program(legacy)," &
+ " proc_disable)," &
+ "verify(idcode) = (proc_verify(idcode))," &
+ "read(idcode) = (proc_read(idcode))," &
+ "read(usercode) = (proc_read(usercode))";
+
+-- Design Warning Section
+
+attribute DESIGN_WARNING of XC3S1200E_FG320 : entity is
+ "This is a preliminary BSDL file which has not been verified." &
+ "This BSDL file must be modified by the FPGA designer in order to" &
+ "reflect post-configuration behavior (if any)." &
+ "To avoid losing the current configuration, the PROG_B should be" &
+ "kept high. If the PROG_B pin goes low by any means," &
+ "the configuration will be cleared." &
+ "PROG_B can only be captured, not updated." &
+ "The value at the pin is always used by the device." &
+ "PUDC_B can be captured and updated." &
+ "The value at the pin is always used by the device" &
+ "before configuration is done." &
+ "During pre-configuration, the disable result of a 3-stated" &
+ "I/O in this file corresponds to PUDC_B being low" &
+ "or during EXTEST instruction." &
+ "When PUDC_B is high AND during SAMPLE instruction, change" &
+ "all PULL1s to PULL0s." &
+ "After configuration, the disable result only depends on" &
+ "the individual IO configuration setting." &
+ "In EXTEST, output and tristate values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "In INTEST, the pin input values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "The output and tristate capture values are not valid until after" &
+ "the device is configured." &
+ "The tristate control value is not captured properly when" &
+ "GTS is activated.";
+
+end XC3S1200E_FG320;
+
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/bsdl/xc3s1200e_fg320_1532.bsd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/impact_bat
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/impact_bat (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/impact_bat (revision 49)
@@ -0,0 +1,6 @@
+setMode -bs
+setCable -port svf -file ../debug/bitstream.svf
+addDevice -p 1 -file Board_Design_jtag.bit
+program -p 1
+closeCable
+quit
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/impact_bat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/fpga_load
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/fpga_load (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/fpga_load (revision 49)
@@ -0,0 +1,6 @@
+bsdl path ../bsdl;../target/bsdl;
+cable usbblaster
+detect
+part 1
+svf bitstream.svf
+
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/debug/fpga_load
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/filelist (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/filelist (revision 49)
@@ -0,0 +1,23 @@
+verilog work ./target/Pad_Ring.v
+verilog work ../../../rtl/gen/syn/soc_mouse.v
+verilog work ../../../../pic16c5x/rtl/gen/syn/pic16c5x.v
+verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
+verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v
+verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
+verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
+verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
+verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
+verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
+
+verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
+verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
+verilog work ./target/lib/syn/cde_sram/cde_sram.v
+verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
+verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
+verilog work ./target/lib/syn/cde_divider/cde_divider.v
+verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
+verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
+verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
+
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/core.v
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/core.v (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/core.v (revision 49)
@@ -0,0 +1,182 @@
+
+
+assign micro_addr = 16'h0000;
+assign micro_wdata = 16'h0000;
+assign micro_rdata = 16'h0000;
+assign micro_rd = 1'b0;
+assign micro_wr = 1'b0;
+assign micro_ub = 1'b0;
+assign micro_lb = 1'b0;
+
+
+
+
+ // Declare I/O Port connections
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+wire ms_left;
+wire ms_right;
+
+wire clk = ck25MHz;
+
+
+wire read;
+
+wire [9:0] x_pos;
+wire [9:0] y_pos;
+
+
+
+ assign rs_tx_pad_out = rs_rx_pad_in;
+
+
+
+
+assign jtag_user1_cap = jtag_user1_upd;
+assign jtag_user2_cap = PosS;
+
+
+
+
+assign ja_1_pad_out = 1'b0;
+assign ja_2_pad_out = reset;
+assign ja_3_pad_out = one_usec;
+assign ja_4_pad_out = 1'b0 ;
+
+assign ja_7_pad_out = 1'b0;
+assign ja_8_pad_out = 1'b0;
+assign ja_9_pad_out = 1'b0;
+assign ja_10_pad_out = 1'b0;
+
+
+
+assign jb_1_pad_out = 1'b0;
+assign jb_2_pad_out = 1'b0;
+assign jb_3_pad_out = 1'b0;
+assign jb_4_pad_out = 1'b0;
+
+
+assign jb_7_pad_out = 1'b0;
+assign jb_8_pad_out = 1'b0;
+assign jb_9_pad_out = 1'b0;
+assign jb_10_pad_out = 1'b0;
+
+
+assign jc_1_pad_out = 1'b1;
+assign jc_2_pad_out = 1'b0;
+assign jc_3_pad_out = 1'b1;
+assign jc_4_pad_out = 1'b0;
+
+assign jc_7_pad_out = 1'b1;
+assign jc_8_pad_out = 1'b0;
+assign jc_9_pad_out = 1'b1;
+assign jc_10_pad_out = 1'b0;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+soc_mouse
+#(
+ .ROM_FILE (`ROM_FILE),
+ .ROM_WORDS (`ROM_WORDS),
+ .ROM_ADDR (`ROM_ADDR),
+ .ROM_WIDTH (`ROM_WIDTH)
+ )
+
+
+soc(
+ .clk ( clk ),
+ .reset ( reset ),
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+ .portaout ( portaout ),
+ .portbout ( portbout ),
+ .portcout ( portcout ),
+ .x_pos ( x_pos ),
+ .y_pos ( y_pos ),
+ .ms_right ( ms_right ),
+ .ms_left ( ms_left ),
+ .txd_pad_out ( txd_pad_out ),
+ .rxd_pad_in ( rxd_pad_in ),
+ .cts_pad_in ( cts_pad_in ),
+ .rts_pad_out ( rts_pad_out )
+
+ );
+
+
+
+
+
+
+
+
+assign PosD = {y_pos[7:0],x_pos[7:0]};
+assign PosL = {6'b000000,ms_left,ms_right};
+
+
+
+wire VGA_HSYNCH;
+wire VGA_VSYNCH;
+wire VGA_OUT_RED;
+wire VGA_OUT_GREEN;
+wire VGA_OUT_BLUE;
+
+
+vga_char_ctrl
+#(.STARTUP(`STARTUP),
+ .FONT (`FONT)
+)
+vga_interface
+(
+ .clk ( ck25MHz ),
+ .reset ( reset ),
+
+ .ascii_load (1'b0 ),
+ .add_l_load (1'b0 ),
+ .add_h_load (1'b0 ),
+ .wdata (8'h00 ),
+
+ .char_color ( 8'b00011000 ),
+ .back_color ( 8'b00000010 ),
+ .cursor_color ( 8'b10000000 ),
+
+
+
+
+ .vga_red_pad_out ( vgared_pad_out ),
+ .vga_green_pad_out ( vgagreen_pad_out ),
+ .vga_blue_pad_out ( vgablue_pad_out ),
+ .hsync_n_pad_out ( hsync_pad_out ),
+ .vsync_n_pad_out ( vsync_pad_out )
+
+ );
+
+
+disp_io
+disp_io(
+ .clk ( ck25MHz ),
+ .reset ( reset ),
+ .PosD ( PosD ),
+ .PosL ( PosL ),
+ .PosB ( PosB ),
+ .PosS ( PosS ),
+ .btn_pad_in ( btn_pad_in ),
+ .sw_pad_in ( sw_pad_in ),
+ .led_pad_out ( led_pad_out ),
+ .seg_pad_out ( seg_pad_out ),
+ .dp_pad_out ( dp_pad_out ),
+ .an_pad_out ( an_pad_out ));
+
+
+
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/core.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/Makefile
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/Makefile (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/Makefile (revision 49)
@@ -0,0 +1,4 @@
+include ../../../../bin/Makefile.root
+include ./target/Makefile.brd
+Design=mouse
+
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/def_file
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/def_file (nonexistent)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/def_file (revision 49)
@@ -0,0 +1,17 @@
+`define SYNTHESIS
+`define ROM_FILE "../../../../../../pic_micro/sw/mouse/mouse.abs12"
+`include "../../../../../../pic_micro/sw/mouse/ROM_defines.v"
+`define ROM_ADDR 11
+
+`define STARTUP "../../../../../../pic_micro/sw/vga_startup_screen/vga_startup_screen.abs"
+`define FONT "../../../../../../pic_micro/sw/vga_font/vga_font.abs"
+`define MODULE_NAME Nexys2_mouse
+
+
+
+`define JTAG_USER1_WIDTH 8
+`define JTAG_USER1_RESET 8'h12
+`define JTAG_USER1_UPDR 1'b1
+`define JTAG_USER2_WIDTH 8
+`define JTAG_USER2_RESET 8'h34
+`define JTAG_USER2_UPDR 1'b1
\ No newline at end of file
projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse/def_file
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/def_file
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/def_file (revision 48)
+++ projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/def_file (revision 49)
@@ -1,6 +1,6 @@
`define SYNTHESIS
-`define ROM_FILE "../../../../../../../projects/pic_micro/sw/mouse/mouse.abs12"
-`include "../../../../../../../projects/pic_micro/sw/mouse/ROM_defines.v"
+`define ROM_FILE "../../../../../../pic_micro/sw/mouse/mouse.abs12"
+`include "../../../../../../pic_micro/sw/mouse/ROM_defines.v"
`define ROM_ADDR 11
`define MODULE_NAME Basys_mouse_mrisc
/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/def_file
1,6 → 1,6
`define SYNTHESIS |
`define ROM_FILE "../../../../../../../projects/pic_micro/sw/mouse/mouse.abs12" |
`include "../../../../../../../projects/pic_micro/sw/mouse/ROM_defines.v" |
`define ROM_FILE "../../../../../../pic_micro/sw/mouse/mouse.abs12" |
`include "../../../../../../pic_micro/sw/mouse/ROM_defines.v" |
`define ROM_ADDR 11 |
`define MODULE_NAME Nexys2_mouse_mrisc |
|
/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
0,0 → 1,27
<components> |
<component> |
<name>mrisc</name> |
<parent>pic_micro</parent> |
<children> |
<child> |
<name>ps2_interface</name> |
<parent>ps2_interface</parent> |
<family>logic</family> |
</child> |
</children> |
|
<library> |
<child> |
<name>cde_sram</name> |
<parent>cde_sram</parent> |
<family>cde</family> |
</child> |
<child> |
<name>cde_sync_with_hystersis</name> |
<parent>cde_synchronizers</parent> |
<family>cde</family> |
</child> |
|
</library> |
</component> |
</components> |
/projects/pic_micro/ip/mrisc/sim/run/rf1/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/rf1/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=rf1 |
/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/sanity1/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=sanity1 |
/projects/pic_micro/ip/mrisc/sim/run/loop/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/loop/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=loop |
/projects/pic_micro/ip/mrisc/sim/run/rf2/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/rf2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=rf2 |
/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/sanity2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=sanity2 |
/projects/pic_micro/ip/mrisc/sim/run/rf3/dut
28,7 → 28,7
|
|
// Instantiate one CPU to be tested. |
mrisc u0( |
mrisc dut( |
.clk (clk), |
.rst_in (reset), |
.inst_addr (inst_addr), |
/projects/pic_micro/ip/mrisc/sim/run/rf3/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=mrisc |
test=rf3 |
/projects/pic_micro/ip/mrisc/sim/cov/mrisc/liblist
0,0 → 1,3
`include "../../lib/cde_sram/cde_sram.v" |
|
|
projects/pic_micro/ip/mrisc/sim/cov/mrisc/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/TB.defs
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/TB.defs (nonexistent)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/TB.defs (revision 49)
@@ -0,0 +1,7 @@
+`define TIMEOUT 2000000
+
+
+
+
+
+
projects/pic_micro/ip/mrisc/sim/cov/mrisc/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/copyright
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/copyright (nonexistent)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/copyright (revision 49)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
projects/pic_micro/ip/mrisc/sim/cov/mrisc/copyright
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist (nonexistent)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist (revision 49)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/syn/mrisc.v"
+
+
+
projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/dut
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/dut (nonexistent)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/dut (revision 49)
@@ -0,0 +1,92 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc dut(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portaout),
+ .portbin (portbout),
+ .portcin (portcout),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (1'b0),
+ .wdt_en (1'b0)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
projects/pic_micro/ip/mrisc/sim/cov/mrisc/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/Makefile
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/Makefile (nonexistent)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/Makefile (revision 49)
@@ -0,0 +1,47 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > mrisc.v ;\
+ covered score -i TB.dut -t mrisc -I ./ -v ./mrisc.v -o mrisc.cdd 2> mrisc_cov.log | tee >> mrisc_cov.log ;\
+ echo "################################################################################"; \
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd mrisc.cdd -vcd ../../out/$(TEST).vcd 2>> sco_cov.log | tee >> sco_cov.log ;\
+
+
+
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd mrisc.cdd 2> rep_cov.log | tee >> rep_cov.log ;\
Index: projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file
===================================================================
--- projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file (revision 48)
+++ projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file (revision 49)
@@ -1,6 +1,6 @@
`define SYNTHESIS
-`define ROM_FILE "../../../../../../../projects/pic_micro/sw/loop/loop.abs12"
-`include "../../../../../../../projects/pic_micro/sw/loop/ROM_defines.v"
+`define ROM_FILE "../../../../../../pic_micro/sw/loop/loop.abs12"
+`include "../../../../../../pic_micro/sw/loop/ROM_defines.v"
`define ROM_ADDR 11
`define MODULE_NAME Basys_loop
/projects/Mos6502/bin/Makefile.root
0,0 → 1,349
SHELL=/bin/sh |
MAKE=make |
|
VPP_NAME=vppreproc |
VERILOG_NAME=iverilog |
|
CUR_DIR=$(shell pwd) |
VAR_DIR=$(CUR_DIR)/variants |
SRC_DIR=$(CUR_DIR)/verilog |
GEN_DIR=$(CUR_DIR)/gen |
|
|
|
|
|
|
################################################################################ |
# Build rtl code |
################################################################################ |
|
prepare_dirs: |
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi |
|
|
build_fsm: prepare_dirs |
@for COMP in `ls $(CUR_DIR)/fzm`; do \ |
echo "################################################"; \ |
echo; \ |
echo "FSM : $$COMP ####"; echo; \ |
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\ |
done; \ |
|
|
|
|
|
|
|
build_hw: build_fsm |
@echo |
@for VARIANT in `ls $(VAR_DIR)`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Building: $$VARIANT ####"; echo; \ |
cp $(VAR_DIR)/$$VARIANT/defines.v defines.v; \ |
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \ |
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \ |
rm defines.v; \ |
done; \ |
|
|
################################################################################ |
# Build software |
################################################################################ |
|
.PHONY asm_6502: |
asm_6502: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
crasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs16 $(code); \ |
hex2abs $(code); \ |
hex2abs_split $(code); \ |
) |
|
|
|
|
|
|
|
.PHONY asm_pic: |
asm_pic: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
gpasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs12 $(code); \ |
) |
|
|
|
|
|
|
|
|
|
.PHONY asm_msp430: |
asm_msp430: |
(\ |
echo "#######################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
cp ../$(io)/template.def ./$(io).def ;\ |
sed -i "s/PMEM_BASE/$(start)/g" $(io).def;\ |
sed -i "s/PMEM_SIZE/$(pmem)/g" $(io).def;\ |
sed -i "s/DMEM_SIZE/$(dmem)/g" $(io).def;\ |
msp430-as -alsm $(code).s43 -o $(io).o > $(io).l43 ;\ |
msp430-objdump -xdsStr $(io).o >> $(io).l43 ;\ |
msp430-ld -T ./$(io).def $(io).o -o $(io).elf ;\ |
msp430-objcopy -O ihex $(io).elf $(io).hex ;\ |
hex2abs_split $(io); \ |
) |
|
|
|
|
|
|
################################################################################ |
# set up coverage |
################################################################################ |
|
|
|
.PHONY build_cov: |
build_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make build_cdd ;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
################################################################################ |
# run coverage report |
################################################################################ |
|
|
|
.PHONY report_cov: |
report_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Report Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make report_cov;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
|
|
|
|
################################################################################ |
# run simulation suite |
################################################################################ |
|
|
.PHONY clean_sims: |
clean_sims: |
(\ |
rm -f $(CUR_DIR)/../out/*;\ |
rm -f $(CUR_DIR)/../log/*;\ |
) |
|
|
.PHONY run_sims: |
run_sims: clean_sims build_cov |
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Simulating: $$VARIANT_PROG ####"; echo; \ |
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\ |
make sim;\ |
done; \ |
|
|
.PHONY sim: |
sim: |
(\ |
$(VERILOG_NAME) -D VCD ../../bench/verilog/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
mv *.log ../../log;\ |
mv TestBench.vcd ../../out/${test}.vcd ;\ |
rm a.out;\ |
cd ../../cov/${comp};\ |
make score_cov TEST=${test} ;\ |
) |
|
|
|
|
.PHONY rtlsim: |
rtlsim: |
(\ |
$(VERILOG_NAME) -D VCD ../../../bench/verilog/TestBench;\ |
./a.out | tee ./${test}_sim.log ;\ |
mv *.log ../../../log;\ |
mv TestBench.vcd ../../../out/${test}.vcd ;\ |
rm a.out;\ |
) |
|
|
|
|
|
|
|
.PHONY group_build_fpgas: |
group_build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make build_fpgas;\ |
done; \ |
|
|
|
|
|
|
|
|
.PHONY build_fpgas: |
build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../syn`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../syn/$$COMP/;\ |
make fpga;\ |
done; \ |
|
|
|
|
|
|
PHONY: fpga |
fpga: |
(\ |
rm -r xilinx;\ |
mkdir xilinx;\ |
cd xilinx;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
xst -ifn ./Xst -ofn $(board)_$(Design).log;\ |
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\ |
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\ |
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\ |
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\ |
netgen -s 5 -pcf $(board)_$(Design).pcf -sdf_anno true -sdf_path "../gate_sims/par" -insert_glbl true -insert_pp_buffers true -w -dir ../gate_sims/par -ofmt verilog -sim $(board)_$(Design).ncd $(board)_$(Design).v;\ |
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\ |
promgen -u 0 Board_Design_cclk ; \ |
mv Board_Design_cclk.mcs ../debug ;\ |
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\ |
impact -batch ../debug/impact_bat ;\ |
mv *.bit ../debug ;\ |
) |
|
|
|
|
|
|
|
|
.PHONY group_composite: |
group_composite: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make comp_lnk;\ |
done; \ |
|
|
|
|
|
.PHONY group_build_hw: |
group_build_hw: group_start_hw |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/rtl;\ |
echo "include ../../../bin/Makefile.root" > Makefile;\ |
make build_hw;\ |
done; \ |
|
|
|
.PHONY group_start_hw: |
group_start_hw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_hw;\ |
done; \ |
|
|
|
|
.PHONY group_build_sw: |
group_build_sw: group_start_sw |
@for COMP in `ls $(CUR_DIR)/../sw`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../sw/$$COMP;\ |
make all;\ |
done; \ |
|
|
.PHONY group_start_sw: |
group_start_sw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_sw;\ |
done; \ |
|
|
|
.PHONY group_run_sims: |
group_run_sims: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims COMP=$$COMP ;\ |
make report_cov ;\ |
done; \ |
|
|
|
|
projects/Mos6502/bin/Makefile.root
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
===================================================================
--- projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (nonexistent)
+++ projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (revision 49)
@@ -0,0 +1,96 @@
+
+
+ T6502
+ Mos6502
+
+
+ io_module
+ io_module
+ logic
+
+
+
+ uart
+ uart
+ logic
+
+
+
+ serial_rcvr
+ serial_rcvr
+ logic
+
+
+
+ ps2_interface
+ ps2_interface
+ logic
+
+
+
+ vga_char_ctrl
+ vga_char_ctrl
+ logic
+
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+
+ disp_io
+ disp_io
+ logic
+
+
+
+
+
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+
+ cde_divider
+ cde_divider
+ cde
+
+
+
+ cde_fifo
+ cde_fifo
+ cde
+
+
+
+ cde_lifo
+ cde_lifo
+ cde
+
+
+
+ cde_serial_rcvr
+ cde_serial_rcvr
+ cde
+
+
+
+ cde_serial_xmit
+ cde_serial_xmit
+ cde
+
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/Mos6502/ip/T6502/rtl/variants/T6502/defines.v
===================================================================
--- projects/Mos6502/ip/T6502/rtl/variants/T6502/defines.v (revision 48)
+++ projects/Mos6502/ip/T6502/rtl/variants/T6502/defines.v (revision 49)
@@ -1,9 +1,9 @@
`define VARIANT T6502
-`define CORE _core
+`define CPU _cpu
`define CONTROL _control
-`define ALU_CTRL _alu_ctrl
`define ALU _alu
+`define ALU_LOGIC _alu_logic
`define INST_DECODE _inst_decode
`define STATE_FSM _state_fsm
`define SEQUENCER _sequencer
/projects/Mos6502/ip/T6502/rtl/verilog/alu_logic.v
0,0 → 1,73
|
`include "defines.v" |
|
module |
`VARIANT`ALU_LOGIC |
|
( |
|
|
|
input wire [7:0] alu_op_a, |
input wire [7:0] alu_op_b, |
input wire alu_op_c, |
|
input wire alu_op_b_inv, |
|
|
output reg [7:0] result, |
output reg r_result, |
output reg c_result, |
output reg v_result, |
|
output reg [7:0] and_out, |
output reg [7:0] orr_out, |
output reg [7:0] eor_out, |
|
|
output reg [8:0] a_sh_left, |
output reg [8:0] a_sh_right, |
output reg [8:0] b_sh_left, |
output reg [8:0] b_sh_right |
|
|
|
); |
|
|
reg [8:0] alu_op_b_mod; |
|
always@(*) |
begin |
alu_op_b_mod = alu_op_b_inv ? ~alu_op_b : alu_op_b; |
end |
|
|
always@(*) |
begin |
|
c_result = alu_op_b_inv ? !r_result : r_result; |
v_result = ((alu_op_a[7] == alu_op_b[7]) && (alu_op_a[7] != result[7])); |
end |
|
|
|
always @ (*) |
begin |
{r_result,result[7:0]} = alu_op_a + alu_op_b_mod + alu_op_c; |
end |
|
|
always @ (*) |
begin |
a_sh_left = {alu_op_a, alu_op_c}; |
a_sh_right = {alu_op_a[0],alu_op_c, alu_op_a[7:1]}; |
b_sh_left = {alu_op_b, alu_op_c}; |
b_sh_right = {alu_op_b[0],alu_op_c, alu_op_b[7:1]}; |
and_out = alu_op_a & alu_op_b; |
orr_out = alu_op_a | alu_op_b; |
eor_out = alu_op_a ^ alu_op_b; |
end |
|
|
endmodule |
/projects/Mos6502/ip/T6502/rtl/verilog/alu.v
7,67 → 7,524
( |
|
|
|
input wire [7:0] alu_op_a, |
input wire [7:0] alu_op_b, |
input wire alu_op_c, |
input wire clk, |
input wire reset, |
input wire enable, |
|
input wire alu_op_b_inv, |
|
|
output reg [7:0] result, |
output reg r_result, |
output reg c_result, |
output reg v_result, |
input wire alu_enable, |
|
output reg [7:0] and_out, |
output reg [7:0] orr_out, |
output reg [7:0] eor_out, |
input wire [7:0] alu_op_b, |
input wire [7:0] psp_res, |
|
input wire [7:0] brn_value, |
input wire [7:0] brn_enable, |
input wire [2:0] dest, |
input wire relative, |
input wire [2:0] alu_mode, |
input wire [4:0] alu_status_update, |
input wire [2:0] alu_op_a_sel, |
input wire alu_op_b_inv, |
input wire [1:0] alu_op_c_sel, |
|
output reg [8:0] a_sh_left, |
output reg [8:0] a_sh_right, |
output reg [8:0] b_sh_left, |
output reg [8:0] b_sh_right |
|
output reg branch_inst, |
output reg [7:0] alu_result, |
output reg [7:0] alu_status, |
output reg [7:0] alu_x, |
output reg [7:0] alu_y, |
output reg [7:0] alu_a |
|
|
); |
|
reg [7:0] alu_op_a; |
reg alu_op_c; |
|
reg [8:0] alu_op_b_mod; |
|
always@(*) |
begin |
alu_op_b_mod = alu_op_b_inv ? ~alu_op_b : alu_op_b; |
end |
wire v_result; |
reg z_result; |
reg c_result; |
|
wire r_result; |
wire [7:0] result; |
|
always@(*) |
begin |
wire [7:0] and_out; |
wire [7:0] orr_out; |
wire [7:0] eor_out; |
|
c_result = alu_op_b_inv ? !r_result : r_result; |
v_result = ((alu_op_a[7] == alu_op_b[7]) && (alu_op_a[7] != result[7])); |
end |
|
wire [8:0] a_sh_left; |
wire [8:0] a_sh_right; |
wire [8:0] b_sh_left; |
wire [8:0] b_sh_right; |
|
|
always @ (*) begin |
case( alu_op_a_sel) |
`alu_op_a_00: alu_op_a = 8'h00; |
`alu_op_a_acc: alu_op_a = alu_a; |
`alu_op_a_x: alu_op_a = alu_x; |
`alu_op_a_y: alu_op_a = alu_y; |
`alu_op_a_ff: alu_op_a = 8'hff; |
`alu_op_a_psr: alu_op_a = alu_status; |
default: alu_op_a = 8'h00; |
endcase |
end |
|
always @ (*) begin |
case( alu_op_c_sel) |
`alu_op_c_00: alu_op_c = 1'b0; |
`alu_op_c_01: alu_op_c = 1'b1; |
`alu_op_c_cin: alu_op_c = alu_status[`C]; |
`alu_op_c_xx: alu_op_c = 1'b0; |
endcase |
end |
|
|
`VARIANT`ALU_LOGIC |
alu_logic ( |
.alu_op_b_inv ( alu_op_b_inv ), |
.alu_op_a ( alu_op_a ), |
.alu_op_b ( alu_op_b ), |
.alu_op_c ( alu_op_c ), |
.result ( result ), |
.r_result ( ), |
.c_result ( r_result ), |
.v_result ( v_result ), |
.and_out ( and_out ), |
.orr_out ( orr_out ), |
.eor_out ( eor_out ), |
.a_sh_left ( a_sh_left ), |
.a_sh_right ( a_sh_right ), |
.b_sh_left ( b_sh_left ), |
.b_sh_right ( b_sh_right ) |
|
); |
|
|
always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_status[`N] <= 1'b0; |
alu_status[`V] <= 1'b0; |
end |
else |
if (! (enable && alu_enable ) ) |
begin |
alu_status[7:6] <= alu_status[7:6]; |
end |
else |
case (alu_status_update) |
|
`alu_status_update_none: |
begin |
alu_status[7:6] <= alu_status[7:6]; |
end |
|
|
`alu_status_update_wr: |
begin |
alu_status[7] <= brn_enable[7]?brn_value[7]: alu_status[7]; |
alu_status[6] <= brn_enable[6]?brn_value[6]: alu_status[6]; |
end |
|
`alu_status_update_z67: |
begin |
alu_status[`N] <= alu_op_b[`N]; |
alu_status[`V] <= alu_op_b[`V]; |
end |
|
`alu_status_update_nz: |
begin |
alu_status[`N] <= alu_result[7]; |
alu_status[`V] <= alu_status[`V]; |
end |
|
`alu_status_update_nzc: |
begin |
alu_status[`N] <= alu_result[7]; |
alu_status[`V] <= alu_status[`V]; |
end |
|
`alu_status_update_nzcv: |
begin |
alu_status[`N] <= alu_result[7]; |
alu_status[`V] <= v_result; |
end |
|
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`alu_status_update_res: |
begin |
alu_status[7:6] <= psp_res[7:6]; |
end |
|
default: |
begin |
alu_status[`N] <= alu_status[`N]; |
alu_status[`V] <= alu_status[`V]; |
end |
endcase |
|
end |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_status[5] <= 1'b1; |
alu_status[`B] <= 1'b0; |
alu_status[`D] <= 1'b0; |
alu_status[`I] <= 1'b0; |
end |
else |
if (! (enable && alu_enable ) ) |
begin |
alu_status[5:2] <= alu_status[5:2]; |
end |
else |
case (alu_status_update) |
|
`alu_status_update_none: |
begin |
alu_status[5:2] <= alu_status[5:2]; |
end |
|
|
`alu_status_update_wr: |
begin |
alu_status[5] <= brn_enable[5]?brn_value[5]: alu_status[5]; |
alu_status[4] <= brn_enable[4]?brn_value[4]: alu_status[4]; |
alu_status[3] <= brn_enable[3]?brn_value[3]: alu_status[3]; |
alu_status[2] <= brn_enable[2]?brn_value[2]: alu_status[2]; |
end |
|
`alu_status_update_z67: |
begin |
alu_status[5] <= alu_status[5]; |
alu_status[`B] <= alu_status[`B]; |
alu_status[`D] <= alu_status[`D]; |
alu_status[`I] <= alu_status[`I]; |
end |
|
`alu_status_update_nz: |
begin |
alu_status[5] <= alu_status[5]; |
alu_status[`B] <= alu_status[`B]; |
alu_status[`D] <= alu_status[`D]; |
alu_status[`I] <= alu_status[`I]; |
end |
|
`alu_status_update_nzc: |
begin |
alu_status[5] <= alu_status[5]; |
alu_status[`B] <= alu_status[`B]; |
alu_status[`D] <= alu_status[`D]; |
alu_status[`I] <= alu_status[`I]; |
end |
|
`alu_status_update_nzcv: |
begin |
alu_status[5] <= alu_status[5]; |
alu_status[`B] <= alu_status[`B]; |
alu_status[`D] <= alu_status[`D]; |
alu_status[`I] <= alu_status[`I]; |
end |
|
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|
`alu_status_update_res: |
begin |
alu_status[5:2] <= psp_res[5:2]; |
end |
|
default: |
begin |
alu_status[5] <= alu_status[5]; |
alu_status[`B] <= alu_status[`B]; |
alu_status[`D] <= alu_status[`D]; |
alu_status[`I] <= alu_status[`I]; |
end |
endcase |
|
end |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_status[`Z] <= 1'b1; |
end |
else |
if (! (enable && alu_enable ) ) |
begin |
alu_status[1] <= alu_status[1]; |
end |
else |
case (alu_status_update) |
|
`alu_status_update_none: |
begin |
alu_status[1] <= alu_status[1]; |
end |
|
`alu_status_update_wr: |
begin |
alu_status[1] <= brn_enable[1]?brn_value[1]: alu_status[1]; |
end |
|
`alu_status_update_z67: |
begin |
alu_status[`Z] <= z_result; |
end |
|
`alu_status_update_nz: |
begin |
alu_status[`Z] <= z_result; |
end |
|
`alu_status_update_nzc: |
begin |
alu_status[`Z] <= z_result; |
end |
|
`alu_status_update_nzcv: |
begin |
alu_status[`Z] <= z_result; |
end |
|
`alu_status_update_res: |
begin |
alu_status[1] <= psp_res[1]; |
end |
|
default: |
begin |
alu_status[`Z] <= alu_status[`Z]; |
end |
endcase |
|
end |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_status[`C] <= 1'b0; |
end |
else |
if (! (enable && alu_enable ) ) |
begin |
alu_status[0] <= alu_status[0]; |
end |
else |
case (alu_status_update) |
|
`alu_status_update_none: |
begin |
alu_status[0] <= alu_status[0]; |
end |
|
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`alu_status_update_wr: |
begin |
alu_status[0] <= brn_enable[0]?brn_value[0]: alu_status[0]; |
end |
|
`alu_status_update_z67: |
begin |
alu_status[`C] <= alu_status[`C]; |
end |
|
`alu_status_update_nz: |
begin |
alu_status[`C] <= alu_status[`C]; |
end |
|
`alu_status_update_nzc: |
begin |
alu_status[`C] <= c_result; |
end |
|
`alu_status_update_nzcv: |
begin |
alu_status[`C] <= c_result; |
end |
|
|
|
`alu_status_update_res: |
begin |
alu_status[0] <= psp_res[0]; |
end |
|
default: |
begin |
alu_status[`C] <= alu_status[`C]; |
end |
endcase |
|
end |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_a <= 8'd0; |
end |
else |
if ( enable && alu_enable && (dest == `dest_alu_a)) |
begin |
alu_a <= alu_result[7:0]; |
end |
else |
begin |
alu_a <= alu_a; |
end |
|
end |
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always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_x <= 8'd0; |
end |
else |
if (!(enable && alu_enable)) |
begin |
alu_x <= alu_x; |
end |
else |
case (dest) |
`dest_alu_x: alu_x <= alu_result[7:0]; |
|
default : |
begin |
alu_x <= alu_x; |
end |
endcase |
|
end |
|
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|
always @ (posedge clk ) |
begin |
if (reset) |
begin |
alu_y <= 8'd0; |
end |
else |
if (!(enable && alu_enable)) |
begin |
alu_y <= alu_y; |
end |
else |
case (dest) |
`dest_alu_y: alu_y <= alu_result[7:0]; |
|
default : |
begin |
alu_y <= alu_y; |
end |
endcase |
|
end |
|
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|
always @ (*) |
begin |
{r_result,result[7:0]} = alu_op_a + alu_op_b_mod + alu_op_c; |
alu_result = result[7:0]; |
c_result = r_result; |
|
if (dest == `dest_alu_a) |
|
case (alu_mode) |
`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]}; |
`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]}; |
`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]}; |
`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]}; |
`alu_mode_sfl:{c_result,alu_result[7:0]} = a_sh_left; |
`alu_mode_sfr:{c_result,alu_result[7:0]} = a_sh_right; |
default:{c_result,alu_result[7:0]} = 9'b111111111; |
|
endcase |
else |
case (alu_mode) |
`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]}; |
`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]}; |
`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]}; |
`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]}; |
`alu_mode_sfl:{c_result,alu_result[7:0]} = b_sh_left; |
`alu_mode_sfr:{c_result,alu_result[7:0]} = b_sh_right; |
default:{c_result,alu_result[7:0]} = 9'b111111111; |
endcase |
|
end |
|
|
always @ (*) |
begin |
a_sh_left = {alu_op_a, alu_op_c}; |
a_sh_right = {alu_op_a[0],alu_op_c, alu_op_a[7:1]}; |
b_sh_left = {alu_op_b, alu_op_c}; |
b_sh_right = {alu_op_b[0],alu_op_c, alu_op_b[7:1]}; |
and_out = alu_op_a & alu_op_b; |
orr_out = alu_op_a | alu_op_b; |
eor_out = alu_op_a ^ alu_op_b; |
end |
|
always@(*) |
begin |
z_result = ~(|alu_result[7:0]); |
end |
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always@(*) branch_inst = relative &&( | (brn_enable & ( ~ (brn_value ^ alu_status)))); |
|
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|
endmodule |
/projects/Mos6502/ip/T6502/rtl/verilog/top.v
278,9 → 278,9
|
|
|
`VARIANT`CORE |
`VARIANT`CPU |
#(.VEC_TABLE(VEC_TABLE)) |
core ( |
cpu ( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
550,30 → 550,7
|
|
); |
/* |
always@(posedge clk) |
if(reset) |
begin |
ext_add <= 'b0; |
ext_wdata <= 16'b0000000000000; |
ext_rd <= 1'b0; |
ext_wr <= 1'b0; |
ext_cs <= 2'b00; |
ext_ub <= 1'b0; |
ext_lb <= 1'b0; |
end |
else |
begin |
ext_add <= {10'b0000000000, addr_pin[13:1]}; |
ext_wdata <= {write_data,write_data}; |
ext_rd <= CSE && rd_pin; |
ext_wr <= CSE && we_pin; |
ext_cs <= {1'b0,CSE}; |
ext_ub <= CSE && addr_pin[0]; |
ext_lb <= CSE && !addr_pin[0]; |
end |
|
*/ |
|
|
endmodule |
|
/projects/Mos6502/ip/T6502/rtl/verilog/cpu.v
0,0 → 1,1433
|
`include "defines.v" |
|
module `VARIANT`CPU |
#( parameter VEC_TABLE = 8'hff, |
parameter BOOT_VEC = 8'hfc |
) |
|
|
( |
input wire clk, |
input wire reset, |
input wire enable, |
input wire [15:0] mem_rdata, // data that comes from the bus controller |
|
input wire nmi, |
input wire [7:0] vec_int, |
|
input wire [15:0] prog_data, |
input wire [7:0] pg0_data, |
|
|
|
output wire [7:0] alu_status, |
output wire [15:0] prog_counter, // program counter |
|
|
output wire [7:0] pg0_add, |
output wire pg0_rd, |
output wire pg0_wr, |
|
|
output wire [15:0] mem_add, // system bus address |
output wire mem_rd, // read = 1 |
output wire mem_wr, // write = 1 |
output wire [7:0] mem_wdata, // data that will be written somewhere else |
|
output wire stk_push, |
output wire [15:0] stk_push_data , |
output wire stk_pull, |
input wire [15:0] stk_pull_data |
|
|
|
|
|
); |
|
|
|
|
|
wire [7:0] ir; // instruction register |
wire [1:0] length; // instruction length |
|
wire [`STATE_SIZE:0] state; // current and next state registers |
|
wire [2:0] dest; |
wire [2:0] ctrl; |
|
wire [7:0] vector; |
|
wire [7:0] operand ; |
wire [7:0] imm_data; // |
reg [7:0] index; // will be assigned with either X or Y |
wire [15:0] offset; |
|
wire now_fetch_op; |
|
// wiring that simplifies the FSM logic by simplifying the addressing modes |
wire absolute; |
wire immediate; |
wire implied; |
wire indirectx; |
wire indirecty; |
wire relative; |
wire zero_page; |
wire stack; |
|
wire fetch_op; |
|
|
wire [1:0] ins_type; |
|
wire jump; |
wire jump_indirect; |
|
// regs for the special instructions |
wire brk; |
wire rti; |
wire rts; |
wire jsr; |
|
wire invalid; |
wire core_reset; |
|
|
wire branch_inst; // a simple reg that is asserted everytime a branch will be executed. |
wire [7:0] brn_value; |
wire [7:0] brn_enable; |
wire [4:0] alu_status_update; |
|
wire [2:0] alu_op_a_sel; |
wire [1:0] alu_op_b_sel; |
|
wire alu_op_b_inv; |
wire [1:0] alu_op_c_sel; |
wire [2:0] alu_mode; |
|
wire [1:0] idx_sel; |
|
|
wire [7:0] alu_result; // result from alu operation |
|
|
wire [7:0] alu_a; // alu accumulator |
wire [7:0] alu_x; // alu x index register |
wire [7:0] alu_y; // alu y index register |
|
reg [7:0] alu_op_b; |
|
wire alu_enable; // a flag that when high tells the alu when to perform the operations |
wire alu_enable_s; |
wire Error; |
|
wire [1:0] cmd; |
|
assign alu_enable = ((alu_enable_s || implied || stack ) && !((state == `INT_1)|| (state == `INT_2) ) ); |
|
|
|
`VARIANT`CONTROL |
#( .BOOT_VEC (BOOT_VEC)) |
control( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.state ( state ), |
.ir ( ir ), |
.nmi ( nmi ), |
.vec_int ( vec_int ), |
.invalid ( invalid ), |
.run_status ( alu_status[5] ), |
.irq_status ( alu_status[2] ), |
.brk_status ( alu_status[4] ), |
.cmd ( cmd ), |
.ctrl ( ctrl ), |
.address ( mem_add ), |
.branch_inst ( branch_inst ), |
.vector ( vector ), |
.core_reset ( core_reset ) |
); |
|
|
`VARIANT`STATE_FSM |
state_fsm ( |
.clk ( clk ), |
.reset ( core_reset ), |
.enable ( enable ), |
.cmd ( cmd ), |
.now_fetch_op ( now_fetch_op ), |
.run ( alu_status[5] ), |
.length ( length ), |
.immediate ( immediate ), |
.absolute ( absolute ), |
.stack ( stack ), |
.relative ( relative ), |
.implied ( implied ), |
.indirectx ( indirectx ), |
.indirecty ( indirecty ), |
.brk ( brk ), |
.rts ( rts ), |
.jump_indirect ( jump_indirect ), |
.jump ( jump ), |
.jsr ( jsr ), |
.rti ( rti ), |
.branch_inst ( branch_inst ), |
.ins_type ( ins_type ), |
.invalid ( invalid ), |
.state ( state ) |
|
); |
|
`VARIANT`INST_DECODE |
inst_decode ( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.disable_ir ((state == `INT_1) || (state == `INT_2) ), |
.now_fetch_op ( now_fetch_op ), |
.fetch_op ( fetch_op ), |
.state ( state ), |
.prog_data ( prog_counter[0]? prog_data[15:8]:prog_data[7:0]), |
|
.length ( length ), |
.ir ( ir ), |
.absolute ( absolute ), |
.immediate ( immediate ), |
.implied ( implied ), |
.indirectx ( indirectx ), |
.indirecty ( indirecty ), |
.relative ( relative ), |
.zero_page ( zero_page ), |
.stack ( stack ), |
.jump ( jump ), |
.jump_indirect ( jump_indirect ), |
.brk ( brk ), |
.rti ( rti ), |
.rts ( rts ), |
.jsr ( jsr ), |
.ins_type ( ins_type ), |
.alu_mode ( alu_mode ), |
.alu_op_a_sel ( alu_op_a_sel ), |
.alu_op_b_sel ( alu_op_b_sel ), |
.alu_op_b_inv ( alu_op_b_inv ), |
.alu_op_c_sel ( alu_op_c_sel ), |
.idx_sel ( idx_sel ), |
.alu_status_update ( alu_status_update ), |
.brn_value ( brn_value ), |
.brn_enable ( brn_enable ), |
.dest ( dest ), |
.ctrl ( ctrl ), |
.invalid ( invalid ) |
); |
|
|
reg last_prg_cnt_0; |
|
always@(posedge clk ) |
last_prg_cnt_0 <= prog_counter[0]; |
|
`VARIANT`SEQUENCER |
#( .VEC_TABLE (VEC_TABLE)) |
sequencer ( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.now_fetch_op ( now_fetch_op ), |
.cmd ( cmd ), |
.state ( state ), |
.length ( length ), |
.vector ( vector ), |
.alu_result ( alu_result ), |
.alu_a ( alu_a ), |
.alu_status ( alu_status ), |
.alu_enable ( alu_enable_s ), |
.alu_op_a_sel ( alu_op_a_sel ), |
.pg0_data ( pg0_data ), |
.data_in ( mem_add[0]? mem_rdata[15:8]: mem_rdata[7:0]), |
.prog_data16 ( prog_data ), |
.index ( index ), |
.prog_data ( last_prg_cnt_0? prog_data[15:8]:prog_data[7:0]), |
.implied ( implied ), |
.fetch_op ( fetch_op ), |
.immediate ( immediate ), |
.relative ( relative ), |
.absolute ( absolute ), |
.zero_page ( zero_page ), |
.stack ( stack ), |
.indirectx ( indirectx ), |
.indirecty ( indirecty ), |
.jump_indirect ( jump_indirect ), |
.jump ( jump ), |
.jsr ( jsr ), |
.brk ( brk ), |
.rti ( rti ), |
.rts ( rts ), |
.branch_inst ( branch_inst ), |
.ins_type ( ins_type ), |
.prog_counter ( prog_counter ), |
.address ( mem_add ), |
.operand ( operand ), |
.imm_data ( imm_data ), |
|
.pg0_add ( pg0_add ), |
.pg0_rd ( pg0_rd ), |
.pg0_wr ( pg0_wr ), |
|
|
|
.mem_rd ( mem_rd ), |
.mem_wr ( mem_wr ), |
.data_out ( mem_wdata ), |
.offset ( offset ), |
.stk_push ( stk_push ), |
.stk_push_data ( stk_push_data ), |
.stk_pull ( stk_pull ), |
.stk_pull_data ( stk_pull_data ) |
|
|
); |
|
|
always@(*) |
|
case (idx_sel) |
`idx_sel_00: index = 8'h00; |
`idx_sel_x: index = alu_x; |
`idx_sel_y: index = alu_y; |
default: index = 8'bxxxxxxxx; |
endcase |
|
|
reg [7:0] mem_dat; |
|
always@(*) mem_dat = mem_add[0] ? mem_rdata[15:8] : mem_rdata[7:0]; |
|
|
always@(*) |
|
case (alu_op_b_sel) |
`alu_op_b_00: alu_op_b = 8'h00; |
`alu_op_b_imm: alu_op_b = imm_data; |
`alu_op_b_stk: alu_op_b = stk_pull_data[7:0]; |
`alu_op_b_opnd: alu_op_b = mem_dat; |
endcase |
|
|
`VARIANT`ALU |
alu ( |
.clk ( clk ), |
.reset ( reset ), |
.enable ( enable ), |
.alu_enable ( alu_enable ), |
.alu_result ( alu_result ), |
.alu_status ( alu_status ), |
.alu_op_b ( alu_op_b ), |
.psp_res ( stk_pull_data[15:8] ), |
.alu_mode ( alu_mode ), |
.alu_op_a_sel ( alu_op_a_sel ), |
.alu_op_b_inv ( alu_op_b_inv ), |
.alu_op_c_sel ( alu_op_c_sel ), |
.alu_status_update ( alu_status_update ), |
.branch_inst ( branch_inst ), |
.relative ( relative ), |
.dest ( dest ), |
.brn_enable ( brn_enable ), |
.brn_value ( brn_value ), |
.alu_x ( alu_x ), |
.alu_y ( alu_y ), |
.alu_a ( alu_a ) |
); |
|
|
|
`ifndef SYNTHESIS |
|
reg [7*8-1:0] A_instr; |
reg [10*8-1:0] A_state; |
reg [3*8-1:0] A_alu_mode; |
reg [3*8-1:0] A_alu_op_a_sel; |
reg [3*8-1:0] A_alu_op_b_inv; |
reg [3*8-1:0] A_alu_op_b_sel; |
reg [3*8-1:0] A_alu_op_c_sel; |
reg [4*8-1:0] A_alu_status_update; |
reg [3*8-1:0] A_dest; |
reg [7*8-1:0] A_ctrl; |
reg [8*8-1:0] A_cmd; |
reg [5*8-1:0] A_ins_type; |
reg [3*8-1:0] A_idx_sel; |
|
|
always @(*) begin |
case (state) |
|
`FETCH_OP: A_state = "FETCH_OP "; |
`EXECUTE: A_state = "EXECUTE "; |
`EXE_1: A_state = "EXE_1 "; |
`AXE_1: A_state = "AXE_1 "; |
`AXE_2: A_state = "AXE_2 "; |
`IDX_1: A_state = "IDX_1 "; |
`IDX_2: A_state = "IDX_2 "; |
`IDX_3: A_state = "IDX_3 "; |
`IDY_1: A_state = "IDY_1 "; |
`IDY_2: A_state = "IDY_2 "; |
`IDY_3: A_state = "IDY_3 "; |
`RESET: A_state = "RESET "; |
`HALT: A_state = "HALT "; |
`INT_2: A_state = "INT_2 "; |
`INT_1: A_state = "INT_1 "; |
default: A_state = "-XXXXXXXX-"; |
endcase |
end |
|
|
|
|
|
always @(*) begin |
case (ir) |
`ADC_IMM: |
begin |
A_instr = "ADC_IMM"; |
end |
|
`ADC_ZPG: |
begin |
A_instr = "ADC_ZPG"; |
end |
|
`ADC_ZPX: |
begin |
A_instr = "ADC_ZPX"; |
end |
|
`ADC_ABS: |
begin |
A_instr = "ADC_ABS"; |
end |
|
`ADC_ABX: |
begin |
A_instr = "ADC_ABX"; |
end |
|
`ADC_ABY: |
begin |
A_instr = "ADC_ABY"; |
end |
|
`ADC_IDX: |
begin |
A_instr = "ADC_IDX"; |
end |
|
`ADC_IDY: |
begin |
A_instr = "ADC_IDY"; |
end |
|
`AND_IMM: |
begin |
A_instr = "AND_IMM"; |
end |
|
`AND_ZPG: |
begin |
A_instr = "AND_ZPG"; |
end |
|
`AND_ZPX: |
begin |
A_instr = "AND_ZPX"; |
end |
|
`AND_ABS: |
begin |
A_instr = "AND_ABS"; |
end |
|
`AND_ABX: |
begin |
A_instr = "AND_ABX"; |
end |
|
`AND_ABY: |
begin |
A_instr = "AND_ABY"; |
end |
|
`AND_IDX: |
begin |
A_instr = "AND_IDX"; |
end |
|
`AND_IDY: |
begin |
A_instr = "AND_IDY"; |
end |
|
`ASL_ACC: |
begin |
A_instr = "ASL_ACC"; |
end |
|
`ASL_ZPG: |
begin |
A_instr = "ASL_ZPG"; |
end |
|
`ASL_ZPX: |
begin |
A_instr = "ASL_ZPX"; |
end |
|
`ASL_ABS: |
begin |
A_instr = "ASL_ABS"; |
end |
|
`ASL_ABX: |
begin |
A_instr = "ASL_ABX"; |
end |
|
`BCC_REL: |
begin |
A_instr = "BCC_REL"; |
end |
|
`BCS_REL: |
begin |
A_instr = "BCS_REL"; |
end |
|
`BEQ_REL: |
begin |
A_instr = "BEQ_REL"; |
end |
|
`BIT_ZPG: |
begin |
A_instr = "BIT_ZPG"; |
end |
|
`BIT_ABS: |
begin |
A_instr = "BIT_ABS"; |
end |
|
`BMI_REL: |
begin |
A_instr = "BMI_REL"; |
end |
|
`BNE_REL: |
begin |
A_instr = "BNE_REL"; |
end |
|
`BPL_REL: |
begin |
A_instr = "BPL_REL"; |
end |
|
`BRK_IMP: |
begin |
A_instr = "BRK_IMP"; |
end |
|
`BVC_REL: |
begin |
A_instr = "BVC_REL"; |
end |
|
`BVS_REL: |
begin |
A_instr = "BVS_REL"; |
end |
|
`CLC_IMP: |
begin |
A_instr = "CLC_IMP"; |
end |
|
`CLD_IMP: |
begin |
A_instr = "CLD_IMP"; |
end |
|
`CLI_IMP: |
begin |
A_instr = "CLI_IMP"; |
end |
|
`CLV_IMP: |
begin |
A_instr = "CLV_IMP"; |
end |
|
`CMP_IMM: |
begin |
A_instr = "CMP_IMM"; |
end |
|
`CMP_ZPG: |
begin |
A_instr = "CMP_ZPG"; |
end |
|
`CMP_ZPX: |
begin |
A_instr = "CMP_ZPX"; |
end |
|
`CMP_ABS: |
begin |
A_instr = "CMP_ABS"; |
end |
|
`CMP_ABX: |
begin |
A_instr = "CMP_ABX"; |
end |
|
`CMP_ABY: |
begin |
A_instr = "CMP_ABY"; |
end |
|
`CMP_IDX: |
begin |
A_instr = "CMP_IDX"; |
end |
|
`CMP_IDY: |
begin |
A_instr = "CMP_IDY"; |
end |
|
`CPX_IMM: |
begin |
A_instr = "CPX_IMM"; |
end |
|
`CPX_ZPG: |
begin |
A_instr = "CPX_ZPG"; |
end |
|
`CPX_ABS: |
begin |
A_instr = "CPX_ABS"; |
end |
|
`CPY_IMM: |
begin |
A_instr = "CPY_IMM"; |
end |
|
`CPY_ZPG: |
begin |
A_instr = "CPY_ZPG"; |
end |
|
`CPY_ABS: |
begin |
A_instr = "CPY_ABS"; |
end |
|
`DEC_ZPG: |
begin |
A_instr = "DEC_ZPG"; |
end |
|
|
`DEC_ZPX: |
begin |
A_instr = "DEC_ZPX"; |
end |
|
`DEC_ABS: |
begin |
A_instr = "DEC_ABS"; |
end |
|
`DEC_ABX: |
begin |
A_instr = "DEC_ABX"; |
end |
|
`DEX_IMP: |
begin |
A_instr = "DEX_IMP"; |
end |
|
`DEY_IMP: |
begin |
A_instr = "DEY_IMP"; |
end |
|
`EOR_IMM: |
begin |
A_instr = "EOR_IMM"; |
end |
|
`EOR_ZPG: |
begin |
A_instr = "EOR_ZPG"; |
end |
|
`EOR_ZPX: |
begin |
A_instr = "EOR_ZPX"; |
end |
|
`EOR_ABS: |
begin |
A_instr = "EOR_ABS"; |
end |
|
`EOR_ABX: |
begin |
A_instr = "EOR_ABX"; |
end |
|
`EOR_ABY: |
begin |
A_instr = "EOR_ABY"; |
end |
|
`EOR_IDX: |
begin |
A_instr = "EOR_IDX"; |
end |
|
`EOR_IDY: |
begin |
A_instr = "EOR_IDY"; |
end |
|
`INC_ZPG: |
begin |
A_instr = "INC_ZPG"; |
end |
|
`INC_ZPX: |
begin |
A_instr = "INC_ZPX"; |
end |
|
`INC_ABS: |
begin |
A_instr = "INC_ABS"; |
end |
|
`INC_ABX: |
begin |
A_instr = "INC_ABX"; |
end |
|
`INX_IMP: |
begin |
A_instr = "INX_IMP"; |
end |
|
`INY_IMP: |
begin |
A_instr = "INY_IMP"; |
end |
|
`JMP_ABS: |
begin |
A_instr = "JMP_ABS"; |
end |
|
`JMP_IND: |
begin |
A_instr = "JMP_IND"; |
end |
|
`JSR_ABS: |
begin |
A_instr = "JSR_ABS"; |
end |
|
`LDA_IMM: |
begin |
A_instr = "LDA_IMM"; |
end |
|
`LDA_ZPG: |
begin |
A_instr = "LDA_ZPG"; |
end |
|
`LDA_ZPX: |
begin |
A_instr = "LDA_ZPX"; |
end |
|
`LDA_ABS: |
begin |
A_instr = "LDA_ABS"; |
end |
|
`LDA_ABX: |
begin |
A_instr = "LDA_ABX"; |
end |
|
`LDA_ABY: |
begin |
A_instr = "LDA_ABY"; |
end |
|
`LDA_IDX: |
begin |
A_instr = "LDA_IDX"; |
end |
|
`LDA_IDY: |
begin |
A_instr = "LDA_IDY"; |
end |
|
`LDX_IMM: |
begin |
A_instr = "LDX_IMM"; |
end |
|
`LDX_ZPG: |
begin |
A_instr = "LDX_ZPG"; |
end |
|
`LDX_ZPY: |
begin |
A_instr = "LDX_ZPY"; |
end |
|
`LDX_ABS: |
begin |
A_instr = "LDX_ABS"; |
end |
|
`LDX_ABY: |
begin |
A_instr = "LDX_ABY"; |
end |
|
`LDY_IMM: |
begin |
A_instr = "LDY_IMM"; |
end |
|
`LDY_ZPG: |
begin |
A_instr = "LDY_ZPG"; |
end |
|
`LDY_ZPX: |
begin |
A_instr = "LDY_ZPX"; |
end |
|
`LDY_ABS: |
begin |
A_instr = "LDY_ABS"; |
end |
|
`LDY_ABX: |
begin |
A_instr = "LDY_ABX"; |
end |
|
`LSR_ACC: |
begin |
A_instr = "LSR_ACC"; |
end |
|
`LSR_ZPG: |
begin |
A_instr = "LSR_ZPG"; |
end |
|
`LSR_ZPX: |
begin |
A_instr = "LSR_ZPX"; |
end |
|
`LSR_ABS: |
begin |
A_instr = "LSR_ABS"; |
end |
|
`LSR_ABX: |
begin |
A_instr = "LSR_ABX"; |
end |
|
`NOP_IMP: |
begin |
A_instr = "NOP_IMP"; |
end |
|
`ORA_IMM: |
begin |
A_instr = "ORA_IMM"; |
end |
|
`ORA_ZPG: |
begin |
A_instr = "ORA_ZPG"; |
end |
|
`ORA_ZPX: |
begin |
A_instr = "ORA_ZPX"; |
end |
|
`ORA_ABS: |
begin |
A_instr = "ORA_ABS"; |
end |
|
`ORA_ABX: |
begin |
A_instr = "ORA_ABX"; |
end |
|
`ORA_ABY: |
begin |
A_instr = "ORA_ABY"; |
end |
|
`ORA_IDX: |
begin |
A_instr = "ORA_IDX"; |
end |
|
`ORA_IDY: |
begin |
A_instr = "ORA_IDY"; |
end |
|
`PHA_IMP: |
begin |
A_instr = "PHA_IMP"; |
end |
|
`PHP_IMP: |
begin |
A_instr = "PHP_IMP"; |
end |
|
`PLA_IMP: |
begin |
A_instr = "PLA_IMP"; |
end |
|
`PLP_IMP: |
begin |
A_instr = "PLP_IMP"; |
end |
|
`ROL_ACC: |
begin |
A_instr = "ROL_ACC"; |
end |
|
`ROL_ZPG: |
begin |
A_instr = "ROL_ZPG"; |
end |
|
`ROL_ZPX: |
begin |
A_instr = "ROL_ZPX"; |
end |
|
`ROL_ABS: |
begin |
A_instr = "ROL_ABS"; |
end |
|
`ROL_ABX: |
begin |
A_instr = "ROL_ABX"; |
end |
|
`ROR_ACC: |
begin |
A_instr = "ROR_ACC"; |
end |
|
`ROR_ZPG: |
begin |
A_instr = "ROR_ZPG"; |
end |
|
`ROR_ZPX: |
begin |
A_instr = "ROR_ZPX"; |
end |
|
`ROR_ABS: |
begin |
A_instr = "ROR_ABS"; |
end |
|
`ROR_ABX: |
begin |
A_instr = "ROR_ABX"; |
end |
|
`RTI_IMP: |
begin |
A_instr = "RTI_IMP"; |
end |
|
`RTS_IMP: |
begin |
A_instr = "RTS_IMP"; |
end |
|
`SBC_IMM: |
begin |
A_instr = "SBC_IMM"; |
end |
|
`SBC_ZPG: |
begin |
A_instr = "SBC_ZPG"; |
end |
|
`SBC_ZPX: |
begin |
A_instr = "SBC_ZPX"; |
end |
|
`SBC_ABS: |
begin |
A_instr = "SBC_ABS"; |
end |
|
`SBC_ABX: |
begin |
A_instr = "SBC_ABX"; |
end |
|
`SBC_ABY: |
begin |
A_instr = "SBC_ABY"; |
end |
|
`SBC_IDX: |
begin |
A_instr = "SBC_IDX"; |
end |
|
`SBC_IDY: |
begin |
A_instr = "SBC_IDY"; |
end |
|
`SEC_IMP: |
begin |
A_instr = "SEC_IMP"; |
end |
|
`SED_IMP: |
begin |
A_instr = "SED_IMP"; |
end |
|
`SEI_IMP: |
begin |
A_instr = "SEI_IMP"; |
end |
|
`STA_ZPG: |
begin |
A_instr = "STA_ZPG"; |
end |
|
`STA_ZPX: |
begin |
A_instr = "STA_ZPX"; |
end |
|
`STA_ABS: |
begin |
A_instr = "STA_ABS"; |
end |
|
`STA_ABX: |
begin |
A_instr = "STA_ABX"; |
end |
|
`STA_ABY: |
begin |
A_instr = "STA_ABY"; |
end |
|
`STA_IDX: |
begin |
A_instr = "STA_IDX"; |
end |
|
`STA_IDY: |
begin |
A_instr = "STA_IDY"; |
end |
|
`STX_ZPG: |
begin |
A_instr = "STX_ZPG"; |
end |
|
`STX_ZPY: |
begin |
A_instr = "STX_ZPY"; |
end |
|
`STX_ABS: |
begin |
A_instr = "STX_ABS"; |
end |
|
`STY_ZPG: |
begin |
A_instr = "STY_ZPG"; |
end |
|
`STY_ZPX: |
begin |
A_instr = "STY_ZPX"; |
end |
|
`STY_ABS: |
begin |
A_instr = "STY_ABS"; |
end |
|
`TAX_IMP: |
begin |
A_instr = "TAX_IMP"; |
end |
|
`TAY_IMP: |
begin |
A_instr = "TAY_IMP"; |
end |
|
`TXA_IMP: |
begin |
A_instr = "TXA_IMP"; |
end |
|
`TYA_IMP: |
begin |
A_instr = "TYA_IMP"; |
end |
|
default: A_instr = "XXX_XXX"; |
endcase |
|
end |
|
|
|
|
|
|
|
|
always @(*) begin |
case (alu_mode) |
`alu_mode_add: begin |
A_alu_mode = "ADD"; |
end |
`alu_mode_and: begin |
A_alu_mode = "AND"; |
end |
`alu_mode_orr: begin |
A_alu_mode = "OR "; |
end |
`alu_mode_eor: begin |
A_alu_mode = "EOR"; |
end |
`alu_mode_sfl: begin |
A_alu_mode = "SFL"; |
end |
`alu_mode_sfr: begin |
A_alu_mode = "SFR"; |
end |
default: begin |
A_alu_mode = "XXX"; |
end |
endcase |
|
end |
|
|
|
|
|
|
|
|
|
|
|
// alu_op_a_sel |
|
|
|
always @(*) begin |
case (alu_op_a_sel) |
`alu_op_a_00: begin |
A_alu_op_a_sel = "00 "; |
end |
`alu_op_a_acc: begin |
A_alu_op_a_sel = "ACC"; |
end |
`alu_op_a_x : begin |
A_alu_op_a_sel = " X "; |
end |
`alu_op_a_y : begin |
A_alu_op_a_sel = " Y "; |
end |
`alu_op_a_ff : begin |
A_alu_op_a_sel = " FF "; |
end |
`alu_op_a_psr: begin |
A_alu_op_a_sel = "PSR"; |
end |
|
default: begin |
A_alu_op_a_sel = "XXX"; |
end |
endcase |
|
end |
|
|
|
|
|
|
|
|
|
|
// alu_op_b_sel |
|
|
always @(*) begin |
case (alu_op_b_sel) |
`alu_op_b_00: begin |
A_alu_op_b_sel = " 0 "; |
end |
`alu_op_b_opnd: begin |
A_alu_op_b_sel = "OPR"; |
end |
`alu_op_b_stk: begin |
A_alu_op_b_sel = "STK"; |
end |
`alu_op_b_imm: begin |
A_alu_op_b_sel = "IMM"; |
end |
default: begin |
A_alu_op_b_sel = "XXX"; |
end |
endcase |
|
end |
|
|
|
|
// alu_op_b_inv |
|
|
always @(*) begin |
case (alu_op_b_inv) |
1'b1: begin |
A_alu_op_b_inv = "INV"; |
end |
1'b0: begin |
A_alu_op_b_inv = " "; |
end |
|
default: begin |
A_alu_op_b_inv = "XXX"; |
end |
endcase |
|
end |
|
|
|
|
// alu_op_c_sel |
|
|
always @(*) begin |
case (alu_op_c_sel) |
`alu_op_c_00: A_alu_op_c_sel = " 0 "; |
`alu_op_c_01: A_alu_op_c_sel = " 1 "; |
`alu_op_c_cin: A_alu_op_c_sel = "CIN"; |
default: A_alu_op_c_sel = "XXX"; |
|
endcase |
|
end |
|
|
|
// alu_status_update |
|
|
|
always @(*) begin |
case (alu_status_update) |
`alu_status_update_none:begin |
A_alu_status_update = " "; |
end |
`alu_status_update_nz: begin |
A_alu_status_update = "N Z "; |
end |
`alu_status_update_nzc: begin |
A_alu_status_update = "N ZC"; |
end |
`alu_status_update_nzcv:begin |
A_alu_status_update = "NVZC"; |
end |
`alu_status_update_wr: begin |
A_alu_status_update = " WR "; |
end |
`alu_status_update_z67: begin |
A_alu_status_update = "76Z "; |
end |
`alu_status_update_res: begin |
A_alu_status_update = "RES "; |
end |
default: begin |
A_alu_status_update = "XXXX"; |
end |
endcase |
|
end |
|
|
|
|
|
|
|
// dest |
|
|
always @(*) begin |
case (dest) |
`dest_none: A_dest = " "; |
`dest_alu_a: A_dest = " A "; |
`dest_alu_x: A_dest = " X "; |
`dest_alu_y: A_dest = " Y "; |
`dest_mem: A_dest = "MEM"; |
default: A_dest = "XXX"; |
|
endcase |
|
end |
|
|
|
|
// ctrl |
|
|
always @(*) begin |
case (ctrl) |
`ctrl_none: A_ctrl = " "; |
`ctrl_jsr: A_ctrl = "JMP_SUB"; |
`ctrl_jmp: A_ctrl = " JUMP "; |
`ctrl_jmp_ind: A_ctrl = "JMP_IND"; |
`ctrl_brk: A_ctrl = " BREAK "; |
`ctrl_rti: A_ctrl = "RET INT"; |
`ctrl_rts: A_ctrl = "RET SUB"; |
`ctrl_branch: A_ctrl = "BRANCH "; |
default: A_ctrl = " -XXX- "; |
endcase |
|
end |
|
|
|
|
// cmd |
|
|
always @(*) begin |
case (cmd) |
`cmd_none: A_cmd = " "; |
`cmd_run: A_cmd = " RUN "; |
`cmd_load_add: A_cmd = "LOAD ADD"; |
`cmd_load_vec: A_cmd = "LOAD VEC"; |
default: A_cmd = " -XXX- "; |
endcase |
|
end |
|
|
|
|
|
// ins_type |
|
|
always @(*) begin |
case (ins_type) |
`ins_type_none: A_ins_type = " "; |
`ins_type_read: A_ins_type = "READ "; |
`ins_type_write: A_ins_type = "WRITE"; |
`ins_type_rmw: A_ins_type = " RMW "; |
default: A_ins_type = "-XXX-"; |
endcase |
|
end |
|
|
// idx_sel |
|
|
always @(*) begin |
case (idx_sel) |
`idx_sel_00: A_idx_sel = " 0 "; |
`idx_sel_x: A_idx_sel = " X "; |
`idx_sel_y: A_idx_sel = " Y "; |
default: A_idx_sel = "---"; |
endcase |
|
end |
|
|
|
|
|
|
|
`endif // `ifndef SYNTHESIS |
|
|
|
|
|
|
|
|
endmodule |
/projects/Mos6502/ip/T6502/sim/run/kim_2/filelist
4,4 → 4,7
`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" |
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
`include "../../../../../children/logic/ip/flash_memcontrl/rtl/gen/sim/flash_memcontrl.v" |
`include "../../../../../children/logic/ip/flash_memcontrl/rtl/gen/sim/flash_memcontrl.v" |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/kim_2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=kim_2 |
/projects/Mos6502/ip/T6502/sim/run/io_irq_2/filelist
5,3 → 5,5
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/io_irq_2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=io_irq_2 |
/projects/Mos6502/ip/T6502/sim/run/tim_2/filelist
5,3 → 5,5
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/tim_2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=tim_2 |
/projects/Mos6502/ip/T6502/sim/run/irq_2_test/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=irq_2_test |
/projects/Mos6502/ip/T6502/sim/run/inst_2_test/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=inst_2_test |
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/liblist
0,0 → 1,7
`include "../../lib/cde_sram/cde_sram.v" |
`include "../../lib/cde_divider/cde_divider.v" |
`include "../../lib/cde_fifo/cde_fifo.v" |
`include "../../lib/cde_lifo/cde_lifo.v" |
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" |
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" |
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" |
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/TB.defs
0,0 → 1,10
`define TIMEOUT 2000000 |
|
|
|
|
|
|
|
|
|
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/test_define
0,0 → 1,23
initial |
begin |
$display(" "); |
$display(" ==================================================="); |
$display(" Test Start"); |
$display(" ==================================================="); |
$display(" "); |
cg.next(20); |
cg.reset_off; |
|
while (run == 1'b0) |
begin |
|
|
cg.next(1); |
end |
|
|
cg.exit; |
end |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/dmp_define
0,0 → 1,7
$dumpfile ("TestBench.vcd"); |
$dumpvars (0, TB); |
|
|
|
|
|
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/filelist
0,0 → 1,6
`include "../../../rtl/gen/sim/T6502.v" |
`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" |
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" |
`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" |
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/modellist
0,0 → 1,5
`include "../../bench/verilog/models/clock_gen.v" |
`include "../../bench/verilog/models/io_probe.v" |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/dut
0,0 → 1,513
|
|
wire [7:0] alu_op_a; |
wire [7:0] alu_op_b; |
wire alu_op_c; |
wire alu_op_b_inv; |
|
|
reg [7:0] alu_op_a_drv; |
reg [7:0] alu_op_b_drv; |
reg alu_op_c_drv; |
reg alu_op_b_inv_drv; |
|
|
reg [7:0] next_alu_op_a; |
reg [7:0] next_alu_op_b; |
reg next_alu_op_c; |
reg next_alu_op_b_inv; |
|
|
|
|
|
wire [7:0] result; |
wire r_result; |
wire c_result; |
wire v_result; |
|
wire [7:0] and_out; |
wire [7:0] orr_out; |
wire [7:0] eor_out; |
|
|
wire [8:0] a_sh_left; |
wire [8:0] a_sh_right; |
wire [8:0] b_sh_left; |
wire [8:0] b_sh_right; |
|
|
|
reg [7:0] exp_result; |
reg exp_r_result; |
reg exp_c_result; |
reg exp_v_result; |
|
reg [7:0] exp_and_out; |
reg [7:0] exp_orr_out; |
reg [7:0] exp_eor_out; |
|
|
reg [8:0] exp_a_sh_left; |
reg [8:0] exp_a_sh_right; |
reg [8:0] exp_b_sh_left; |
reg [8:0] exp_b_sh_right; |
|
|
|
|
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|
T6502_alu_logic |
dut ( |
.alu_op_a ( alu_op_a ), |
.alu_op_b ( alu_op_b ), |
.alu_op_c ( alu_op_c ), |
.alu_op_b_inv ( alu_op_b_inv ), |
|
.result ( result ), |
.r_result ( r_result ), |
.c_result ( c_result ), |
.v_result ( v_result ), |
|
.and_out ( and_out ), |
.orr_out ( orr_out ), |
.eor_out ( eor_out ), |
|
.a_sh_left ( a_sh_left ), |
.a_sh_right ( a_sh_right ), |
.b_sh_left ( b_sh_left ), |
.b_sh_right ( b_sh_right ) |
|
|
|
); |
|
|
reg run; |
reg next_run; |
|
|
|
always@(posedge clk) |
if(reset) |
begin |
run <= 1'b0; |
alu_op_a_drv <= 8'h00; |
alu_op_b_drv <= 8'h00; |
alu_op_c_drv <= 1'b0; |
alu_op_b_inv_drv <= 1'b0; |
end |
else |
begin |
run <= next_run; |
alu_op_a_drv <= next_alu_op_a; |
alu_op_b_drv <= next_alu_op_b; |
alu_op_c_drv <= next_alu_op_c; |
alu_op_b_inv_drv <= next_alu_op_b_inv; |
end |
|
|
|
|
|
always@(*) |
begin |
next_run = run; |
next_alu_op_a = alu_op_a_drv; |
next_alu_op_b = alu_op_b_drv; |
next_alu_op_c = alu_op_c_drv; |
next_alu_op_b_inv = alu_op_b_inv_drv; |
|
|
if(run) |
begin |
next_run = 1'b1; |
next_alu_op_a = 8'h00; |
next_alu_op_b = 8'h00; |
next_alu_op_c = 1'b0; |
next_alu_op_b_inv = 1'b0; |
end |
else |
begin |
next_alu_op_a = alu_op_a_drv+8'h01; |
if(alu_op_a_drv == 8'hff) |
begin |
next_alu_op_b = alu_op_b_drv+8'h01; |
if(alu_op_b_drv == 8'hff) |
begin |
{next_run,next_alu_op_c , next_alu_op_b_inv} = {run,alu_op_c_drv, alu_op_b_inv_drv} + 3'b001; |
end |
end |
end |
end |
|
|
|
always@(*) |
begin |
exp_and_out = alu_op_a_drv & alu_op_b_drv; |
exp_orr_out = alu_op_a_drv | alu_op_b_drv; |
exp_eor_out = alu_op_a_drv ^ alu_op_b_drv; |
exp_a_sh_left = {alu_op_a_drv,alu_op_c_drv}; |
exp_a_sh_right = {alu_op_a_drv[0],alu_op_c_drv, alu_op_a_drv[7:1]}; |
exp_b_sh_left = {alu_op_b_drv,alu_op_c_drv}; |
exp_b_sh_right = {alu_op_b_drv[0],alu_op_c_drv, alu_op_b_drv[7:1]}; |
end |
|
|
always@(*) |
begin |
if(alu_op_b_inv_drv) |
begin |
{exp_r_result,exp_result} = alu_op_a_drv - alu_op_b_drv - (!alu_op_c_drv) ; |
exp_c_result = !exp_r_result ; |
exp_v_result = ((alu_op_a_drv[7] == alu_op_b_drv[7]) && (alu_op_a_drv[7] != exp_result[7])); |
end |
else |
begin |
{exp_r_result,exp_result} = alu_op_a_drv + alu_op_b_drv + alu_op_c_drv ; |
exp_c_result = exp_r_result ; |
exp_v_result = ((alu_op_a_drv[7] == alu_op_b_drv[7]) && (alu_op_a_drv[7] != exp_result[7])); |
end |
|
|
|
end |
|
|
|
|
|
|
|
io_probe |
#(.WIDTH (8), |
.RESET ({8{1'b0}}), |
.IN_DELAY (0), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
alu_op_a_tprb |
( |
.clk ( clk ), |
.drive_value ( alu_op_a_drv ), |
.expected_value (8'b0 ), |
.mask (8'b0 ), |
.signal ( alu_op_a ) |
|
); |
|
|
|
|
|
io_probe |
#(.WIDTH (8), |
.RESET ({8{1'b0}}), |
.IN_DELAY (0), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
alu_op_b_tprb |
( |
.clk ( clk ), |
.drive_value ( alu_op_b_drv ), |
.expected_value (8'b0 ), |
.mask (8'b0 ), |
.signal ( alu_op_b ) |
|
); |
|
|
|
|
|
|
|
io_probe |
#(.WIDTH (1), |
.RESET ({1{1'b0}}), |
.IN_DELAY (0), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
alu_op_c_tprb |
( |
.clk ( clk ), |
.drive_value ( alu_op_c_drv ), |
.expected_value (1'b0 ), |
.mask (1'b0 ), |
.signal ( alu_op_c ) |
|
); |
|
|
|
|
|
|
|
io_probe |
#(.WIDTH (1), |
.RESET ({1{1'b0}}), |
.IN_DELAY (0), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
alu_op_b_inv_tprb |
( |
.clk ( clk ), |
.drive_value ( alu_op_b_inv_drv ), |
.expected_value (1'b0 ), |
.mask (1'b0 ), |
.signal ( alu_op_b_inv ) |
|
); |
|
|
|
|
|
|
|
|
|
|
io_probe |
#(.MESG("result error"), |
.WIDTH (8), |
.RESET ({8{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
result_tprb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value ( exp_result ), |
.mask (8'b11111111 ), |
.signal ( result ) |
|
); |
|
|
|
|
|
|
io_probe |
#(.MESG("and_out error"), |
.WIDTH (8), |
.RESET ({8{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
and_out_tprb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value ( exp_and_out ), |
.mask (8'b11111111 ), |
.signal ( and_out ) |
|
); |
|
|
|
|
io_probe |
#(.MESG("orr_out error"), |
.WIDTH (8), |
.RESET ({8{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
orr_out_tprb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value ( exp_orr_out ), |
.mask (8'b11111111 ), |
.signal ( orr_out ) |
|
); |
|
|
|
|
io_probe |
#(.MESG("eor_out error"), |
.WIDTH (8), |
.RESET ({8{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
eor_out_tprb |
( |
.clk ( clk ), |
.drive_value (8'bzzzzzzzz), |
.expected_value ( exp_eor_out ), |
.mask (8'b11111111 ), |
.signal ( eor_out ) |
|
); |
|
|
|
|
|
|
io_probe |
#(.MESG("a_sh_left error"), |
.WIDTH (9), |
.RESET ({9{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
a_sh_left_tprb |
( |
.clk ( clk ), |
.drive_value (9'bzzzzzzzzz ), |
.expected_value ( exp_a_sh_left ), |
.mask (9'b111111111 ), |
.signal ( a_sh_left ) |
|
); |
|
|
|
io_probe |
#(.MESG("a_sh_right error"), |
.WIDTH (9), |
.RESET ({9{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
a_sh_right_tprb |
( |
.clk ( clk ), |
.drive_value (9'bzzzzzzzzz ), |
.expected_value ( exp_a_sh_right ), |
.mask (9'b111111111 ), |
.signal ( a_sh_right ) |
|
); |
|
|
|
|
io_probe |
#(.MESG("b_sh_left error"), |
.WIDTH (9), |
.RESET ({9{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
b_sh_left_tprb |
( |
.clk ( clk ), |
.drive_value (9'bzzzzzzzzz ), |
.expected_value ( exp_b_sh_left ), |
.mask (9'b111111111 ), |
.signal ( b_sh_left ) |
|
); |
|
|
|
io_probe |
#(.MESG("b_sh_right error"), |
.WIDTH (9), |
.RESET ({9{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
b_sh_right_tprb |
( |
.clk ( clk ), |
.drive_value (9'bzzzzzzzzz ), |
.expected_value ( exp_b_sh_right ), |
.mask (9'b111111111 ), |
.signal ( b_sh_right ) |
|
); |
|
|
|
|
io_probe |
#(.MESG("r_result error"), |
.WIDTH (1), |
.RESET ({1{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
r_result_tprb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_r_result ), |
.mask (1'b1 ), |
.signal ( r_result ) |
|
); |
|
|
|
|
|
io_probe |
#(.MESG("c_result error"), |
.WIDTH (1), |
.RESET ({1{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
c_result_tprb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_c_result ), |
.mask (1'b1 ), |
.signal ( c_result ) |
|
); |
|
|
|
|
|
io_probe |
#(.MESG("v_result error"), |
.WIDTH (1), |
.RESET ({1{1'bz}}), |
.IN_DELAY (5), |
.OUT_DELAY (15), |
.OUT_WIDTH (10) |
) |
v_result_tprb |
( |
.clk ( clk ), |
.drive_value (1'bz ), |
.expected_value ( exp_v_result ), |
.mask (1'b1 ), |
.signal ( v_result ) |
|
); |
|
|
|
|
|
/projects/Mos6502/ip/T6502/sim/run/alu_logic_test/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502_alu_logic |
test=alu_logic_test |
/projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist
5,3 → 5,5
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" |
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" |
|
|
|
/projects/Mos6502/ip/T6502/sim/run/io_poll_2/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=T6502 |
test=io_poll_2 |
/projects/Mos6502/ip/T6502/sim/cov/T6502/liblist
0,0 → 1,9
`include "../../lib/cde_sram/cde_sram.v" |
`include "../../lib/cde_divider/cde_divider.v" |
`include "../../lib/cde_fifo/cde_fifo.v" |
`include "../../lib/cde_lifo/cde_lifo.v" |
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" |
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" |
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" |
|
|
projects/Mos6502/ip/T6502/sim/cov/T6502/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502/TB.defs
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502/TB.defs (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502/TB.defs (revision 49)
@@ -0,0 +1,15 @@
+`define TIMEOUT 100000
+
+
+
+
+`define PROG_ROM_WORDS 2048
+`define PROG_ROM_ADD 11
+`define PROG_ROM_FILE "../../../../../../Mos6502/sw/inst_2_test/inst_2_test.abs16"
+
+
+
+`define ROM_WORDS 128
+`define ROM_ADD 7
+`define ROM_FILE "../../../../../../Mos6502/sw/table/table.abs16"
+
projects/Mos6502/ip/T6502/sim/cov/T6502/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502/filelist (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502/filelist (revision 49)
@@ -0,0 +1,9 @@
+`include "../../../rtl/gen/syn/T6502.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
+
+
+
projects/Mos6502/ip/T6502/sim/cov/T6502/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502/dut
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502/dut (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502/dut (revision 49)
@@ -0,0 +1,83 @@
+
+
+wire serial_txd;
+wire serial_rxd;
+
+wire [7:0] alu_status;
+
+wire [23:1] ext_add;
+wire [15:0] ext_wdata;
+wire [15:0] ext_rdata;
+wire ext_ub;
+wire ext_lb;
+wire ext_rd;
+wire ext_wr;
+wire [1:0] ext_cs;
+
+
+wire [7:0] gpio_0_out;
+wire [7:0] gpio_1_out;
+
+wire ps2_clk_in;
+wire ps2_data_in;
+wire ps2_clk_oe;
+wire ps2_data_oe;
+
+
+wire ps2_clk;
+wire ps2_data;
+
+
+
+
+T6502
+
+#(.ROM_WORDS(`ROM_WORDS),
+ .ROM_ADD (`ROM_ADD),
+ .ROM_FILE (`ROM_FILE),
+
+ .PROG_ROM_WORDS(`PROG_ROM_WORDS),
+ .PROG_ROM_ADD (`PROG_ROM_ADD),
+ .PROG_ROM_FILE (`PROG_ROM_FILE)
+
+
+ )
+
+dut
+(
+ .clk ( clk ),
+ .reset ( reset ),
+ .alu_status ( alu_status ),
+ .ext_irq_in ( 4'b0000 ),
+ .ext_add ( ext_add ),
+ .ext_wdata ( ext_wdata ),
+ .ext_rdata ( 16'h0000 ),
+ .ext_ub ( ext_ub ),
+ .ext_lb ( ext_lb ),
+ .ext_rd ( ext_rd ),
+ .ext_wr ( ext_wr ),
+ .ext_cs ( ext_cs ),
+
+ .gpio_0_out ( gpio_0_out ),
+ .gpio_0_in ( gpio_0_out ),
+ .gpio_0_oe ( ),
+ .gpio_0_lat ( ),
+
+ .gpio_1_out ( gpio_1_out ),
+ .gpio_1_in ( gpio_1_out ),
+ .gpio_1_oe ( ),
+ .gpio_1_lat ( ),
+
+ .ps2_clk_oe ( ps2_clk_oe ),
+ .ps2_clk_in ( ps2_clk_in ),
+ .ps2_data_oe ( ps2_data_oe ),
+ .ps2_data_in ( ps2_data_in ),
+
+ .txd_pad_out ( serial_txd ),
+ .rxd_pad_in ( serial_rxd ),
+ .cts_pad_in ( loop ),
+ .rts_pad_out ( loop )
+);
+
+
+
projects/Mos6502/ip/T6502/sim/cov/T6502/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502/Makefile
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502/Makefile (revision 49)
@@ -0,0 +1,48 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > T6502.v ;\
+ covered score -i TB.dut.cpu -t T6502_cpu -I ./ -v ./T6502.v -o T6502_cpu.cdd 2> T6502_cpu_cov.log | tee >> T6502_cpu_cov.log ;\
+ covered score -i TB.dut.io_module -t io_module -I ./ -v ./T6502.v -o io_module.cdd 2> io_module_cov.log | tee >> io_module_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd T6502_cpu.cdd -vcd ../../out/$(TEST).vcd 2>> cpu_sco_cov.log | tee >> cpu_sco_cov.log ;\
+ covered score -cdd io_module.cdd -vcd ../../out/$(TEST).vcd 2>> io_sco_cov.log | tee >> io_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd T6502_cpu.cdd 2> cpu_rep_cov.log | tee >> cpu_rep_cov.log ;\
+ covered report -cdd io_module.cdd 2> io_rep_cov.log | tee >> io_rep_cov.log ;\
\ No newline at end of file
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/liblist
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/liblist (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/liblist (revision 49)
@@ -0,0 +1,7 @@
+`include "../../lib/cde_sram/cde_sram.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+`include "../../lib/cde_lifo/cde_lifo.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
\ No newline at end of file
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/TB.defs
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/TB.defs (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/TB.defs (revision 49)
@@ -0,0 +1,10 @@
+`define TIMEOUT 2000000
+
+
+
+
+
+
+
+
+
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist (revision 49)
@@ -0,0 +1,6 @@
+`include "../../../rtl/gen/syn/T6502.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
\ No newline at end of file
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/dut
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/dut (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/dut (revision 49)
@@ -0,0 +1,87 @@
+
+
+wire [7:0] alu_op_a;
+wire [7:0] alu_op_b;
+wire alu_op_c;
+wire alu_op_b_inv;
+
+
+reg [7:0] alu_op_a_drv;
+reg [7:0] alu_op_b_drv;
+reg alu_op_c_drv;
+reg alu_op_b_inv_drv;
+
+
+reg [7:0] next_alu_op_a;
+reg [7:0] next_alu_op_b;
+reg next_alu_op_c;
+reg next_alu_op_b_inv;
+
+
+
+
+
+wire [7:0] result;
+wire r_result;
+wire c_result;
+wire v_result;
+
+wire [7:0] and_out;
+wire [7:0] orr_out;
+wire [7:0] eor_out;
+
+
+wire [8:0] a_sh_left;
+wire [8:0] a_sh_right;
+wire [8:0] b_sh_left;
+wire [8:0] b_sh_right;
+
+
+
+reg [7:0] exp_result;
+reg exp_r_result;
+reg exp_c_result;
+reg exp_v_result;
+
+reg [7:0] exp_and_out;
+reg [7:0] exp_orr_out;
+reg [7:0] exp_eor_out;
+
+
+reg [8:0] exp_a_sh_left;
+reg [8:0] exp_a_sh_right;
+reg [8:0] exp_b_sh_left;
+reg [8:0] exp_b_sh_right;
+
+
+
+
+
+
+
+T6502_alu_logic
+dut (
+ .alu_op_a ( alu_op_a ),
+ .alu_op_b ( alu_op_b ),
+ .alu_op_c ( alu_op_c ),
+ .alu_op_b_inv ( alu_op_b_inv ),
+
+ .result ( result ),
+ .r_result ( r_result ),
+ .c_result ( c_result ),
+ .v_result ( v_result ),
+
+ .and_out ( and_out ),
+ .orr_out ( orr_out ),
+ .eor_out ( eor_out ),
+
+ .a_sh_left ( a_sh_left ),
+ .a_sh_right ( a_sh_right ),
+ .b_sh_left ( b_sh_left ),
+ .b_sh_right ( b_sh_right )
+
+
+
+);
+
+
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/Makefile
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/Makefile (revision 49)
@@ -0,0 +1,45 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > T6502.v ;\
+ covered score -i TB.dut -t T6502_alu_logic -I ./ -v ./T6502.v -o T6502_alu_logic.cdd 2> T6502_alu_logic_cov.log | tee >> T6502_alu_logic_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd T6502_alu_logic.cdd -vcd ../../out/$(TEST).vcd 2>> alu_logic_sco_cov.log | tee >> alu_logic_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd T6502_alu_logic.cdd 2> alu_logic_rep_cov.log | tee >> alu_logic_rep_cov.log ;\
Index: projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist (revision 48)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist (revision 49)
@@ -1,11 +1,8 @@
verilog work ./target/Pad_Ring.v
-
-
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
/projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/def_file
1,9 → 1,9
`define SYNTHESIS |
`define ROM_FILE "../../../../../../../projects/Mos6502/sw/table_tim1/table_tim1.abs16" |
`define ROM_FILE "../../../../../../Mos6502/sw/table_tim1/table_tim1.abs16" |
`define ROM_WORDS 128 |
`define ROM_ADD 7 |
|
`define PROG_ROM_FILE "../../../../../../../projects/Mos6502/sw/tim_2/tim_2.abs16" |
`define PROG_ROM_FILE "../../../../../../Mos6502/sw/tim_2/tim_2.abs16" |
`define PROG_ROM_WORDS 2048 |
`define PROG_ROM_ADD 11 |
|
/projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/filelist
1,6 → 1,5
verilog work ./target/Pad_Ring.v |
|
|
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v |
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v |
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v |
/projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/def_file
3,7 → 3,7
`define ROM_WORDS 128 |
`define ROM_ADD 7 |
|
`define PROG_ROM_FILE "../../../../../../../projects/Mos6502/sw/irq_2_test/irq_2_test.abs16" |
`define PROG_ROM_FILE "../../../../../../Mos6502/sw/irq_2_test/irq_2_test.abs16" |
`define PROG_ROM_WORDS 2048 |
`define PROG_ROM_ADD 11 |
|
/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/filelist
1,6 → 1,5
verilog work ./target/Pad_Ring.v |
|
|
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v |
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v |
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v |
/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/def_file
3,7 → 3,7
`define ROM_WORDS 128 |
`define ROM_ADD 7 |
|
`define PROG_ROM_FILE "../../../../../../../projects/Mos6502/sw/io_poll_2/io_poll_2.abs16" |
`define PROG_ROM_FILE "../../../../../../Mos6502/sw/io_poll_2/io_poll_2.abs16" |
`define PROG_ROM_WORDS 128 |
`define PROG_ROM_ADD 7 |
|
/projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/filelist
1,6 → 1,5
verilog work ./target/Pad_Ring.v |
|
|
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v |
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v |
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v |
/projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/def_file
1,9 → 1,9
`define SYNTHESIS |
`define ROM_FILE "../../../../../../../projects/Mos6502/sw/table_tim1/table_tim1.abs16" |
`define ROM_FILE "../../../../../../Mos6502/sw/table_tim1/table_tim1.abs16" |
`define ROM_WORDS 128 |
`define ROM_ADD 7 |
|
`define PROG_ROM_FILE "../../../../../../../projects/Mos6502/sw/kim_2/kim_2.abs16" |
`define PROG_ROM_FILE "../../../../../../Mos6502/sw/kim_2/kim_2.abs16" |
`define PROG_ROM_WORDS 2048 |
`define PROG_ROM_ADD 11 |
|
/projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/filelist
1,6 → 1,4
verilog work ./target/Pad_Ring.v |
|
|
verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v |
verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v |
verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v |
/projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/def_file
3,7 → 3,7
`define ROM_WORDS 128 |
`define ROM_ADD 7 |
|
`define PROG_ROM_FILE "../../../../../../../projects/Mos6502/sw/io_irq_2/io_irq_2.abs16" |
`define PROG_ROM_FILE "../../../../../../Mos6502/sw/io_irq_2/io_irq_2.abs16" |
`define PROG_ROM_WORDS 128 |
`define PROG_ROM_ADD 7 |
|
/projects/logic/bin/Makefile.root
0,0 → 1,349
SHELL=/bin/sh |
MAKE=make |
|
VPP_NAME=vppreproc |
VERILOG_NAME=iverilog |
|
CUR_DIR=$(shell pwd) |
VAR_DIR=$(CUR_DIR)/variants |
SRC_DIR=$(CUR_DIR)/verilog |
GEN_DIR=$(CUR_DIR)/gen |
|
|
|
|
|
|
################################################################################ |
# Build rtl code |
################################################################################ |
|
prepare_dirs: |
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi |
|
|
build_fsm: prepare_dirs |
@for COMP in `ls $(CUR_DIR)/fzm`; do \ |
echo "################################################"; \ |
echo; \ |
echo "FSM : $$COMP ####"; echo; \ |
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\ |
done; \ |
|
|
|
|
|
|
|
build_hw: build_fsm |
@echo |
@for VARIANT in `ls $(VAR_DIR)`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Building: $$VARIANT ####"; echo; \ |
cp $(VAR_DIR)/$$VARIANT/defines.v defines.v; \ |
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIANT.v ; \ |
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIANT.v ; \ |
$(VPP_NAME) --noline --noblank -DSYNTHESIS defines.v $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIANT.v ; \ |
rm defines.v; \ |
done; \ |
|
|
################################################################################ |
# Build software |
################################################################################ |
|
.PHONY asm_6502: |
asm_6502: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
crasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs16 $(code); \ |
hex2abs $(code); \ |
hex2abs_split $(code); \ |
) |
|
|
|
|
|
|
|
.PHONY asm_pic: |
asm_pic: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
gpasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs12 $(code); \ |
) |
|
|
|
|
|
|
|
|
|
.PHONY asm_msp430: |
asm_msp430: |
(\ |
echo "#######################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
cp ../$(io)/template.def ./$(io).def ;\ |
sed -i "s/PMEM_BASE/$(start)/g" $(io).def;\ |
sed -i "s/PMEM_SIZE/$(pmem)/g" $(io).def;\ |
sed -i "s/DMEM_SIZE/$(dmem)/g" $(io).def;\ |
msp430-as -alsm $(code).s43 -o $(io).o > $(io).l43 ;\ |
msp430-objdump -xdsStr $(io).o >> $(io).l43 ;\ |
msp430-ld -T ./$(io).def $(io).o -o $(io).elf ;\ |
msp430-objcopy -O ihex $(io).elf $(io).hex ;\ |
hex2abs_split $(io); \ |
) |
|
|
|
|
|
|
################################################################################ |
# set up coverage |
################################################################################ |
|
|
|
.PHONY build_cov: |
build_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make build_cdd ;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
################################################################################ |
# run coverage report |
################################################################################ |
|
|
|
.PHONY report_cov: |
report_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Report Coverage: $$VARIANT ####"; echo; \ |
cd $(CUR_DIR)/../cov/$$VARIANT/;\ |
make report_cov;\ |
cd $(CUR_DIR) ;\ |
done; \ |
|
|
|
|
|
|
################################################################################ |
# run simulation suite |
################################################################################ |
|
|
.PHONY clean_sims: |
clean_sims: |
(\ |
rm -f $(CUR_DIR)/../out/*;\ |
rm -f $(CUR_DIR)/../log/*;\ |
) |
|
|
.PHONY run_sims: |
run_sims: clean_sims build_cov |
@for VARIANT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Simulating: $$VARIANT_PROG ####"; echo; \ |
cd $(CUR_DIR)/../run/$$VARIANT_PROG/;\ |
make sim;\ |
done; \ |
|
|
.PHONY sim: |
sim: |
(\ |
$(VERILOG_NAME) -D VCD ../../bench/verilog/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\ |
mv *.log ../../log;\ |
mv TestBench.vcd ../../out/${test}.vcd ;\ |
rm a.out;\ |
cd ../../cov/${comp};\ |
make score_cov TEST=${test} ;\ |
) |
|
|
|
|
.PHONY rtlsim: |
rtlsim: |
(\ |
$(VERILOG_NAME) -D VCD ../../../bench/verilog/TestBench;\ |
./a.out | tee ./${test}_sim.log ;\ |
mv *.log ../../../log;\ |
mv TestBench.vcd ../../../out/${test}.vcd ;\ |
rm a.out;\ |
) |
|
|
|
|
|
|
|
.PHONY group_build_fpgas: |
group_build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make build_fpgas;\ |
done; \ |
|
|
|
|
|
|
|
|
.PHONY build_fpgas: |
build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../syn`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../syn/$$COMP/;\ |
make fpga;\ |
done; \ |
|
|
|
|
|
|
PHONY: fpga |
fpga: |
(\ |
rm -r xilinx;\ |
mkdir xilinx;\ |
cd xilinx;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
xst -ifn ./Xst -ofn $(board)_$(Design).log;\ |
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\ |
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\ |
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\ |
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../target/Pad_Ring.ucf ;\ |
netgen -s 5 -pcf $(board)_$(Design).pcf -sdf_anno true -sdf_path "../gate_sims/par" -insert_glbl true -insert_pp_buffers true -w -dir ../gate_sims/par -ofmt verilog -sim $(board)_$(Design).ncd $(board)_$(Design).v;\ |
bitgen -f ../target/cclk.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_cclk.bit ;\ |
promgen -u 0 Board_Design_cclk ; \ |
mv Board_Design_cclk.mcs ../debug ;\ |
bitgen -f ../target/jtag.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit Board_Design_jtag.bit ;\ |
impact -batch ../debug/impact_bat ;\ |
mv *.bit ../debug ;\ |
) |
|
|
|
|
|
|
|
|
.PHONY group_composite: |
group_composite: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make comp_lnk;\ |
done; \ |
|
|
|
|
|
.PHONY group_build_hw: |
group_build_hw: group_start_hw |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/rtl;\ |
echo "include ../../../bin/Makefile.root" > Makefile;\ |
make build_hw;\ |
done; \ |
|
|
|
.PHONY group_start_hw: |
group_start_hw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_hw;\ |
done; \ |
|
|
|
|
.PHONY group_build_sw: |
group_build_sw: group_start_sw |
@for COMP in `ls $(CUR_DIR)/../sw`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../sw/$$COMP;\ |
make all;\ |
done; \ |
|
|
.PHONY group_start_sw: |
group_start_sw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_sw;\ |
done; \ |
|
|
|
.PHONY group_run_sims: |
group_run_sims: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims COMP=$$COMP ;\ |
make report_cov ;\ |
done; \ |
|
|
|
|
projects/logic/bin/Makefile.root
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/bin/Makefile
===================================================================
--- projects/logic/bin/Makefile (revision 48)
+++ projects/logic/bin/Makefile (revision 49)
@@ -1,2 +1 @@
include ./Makefile.root
-
Index: projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
===================================================================
--- projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml (nonexistent)
+++ projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ ps2_interface
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/ps2_interface/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/ps2_interface/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=ps2_interface
+test=default
Index: projects/logic/ip/ps2_interface/sim/run/mouse/Makefile
===================================================================
--- projects/logic/ip/ps2_interface/sim/run/mouse/Makefile (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/run/mouse/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=ps2_interface
+test=mouse
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/liblist
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/liblist (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/liblist (revision 49)
@@ -0,0 +1,4 @@
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+
projects/logic/ip/ps2_interface/sim/cov/ps2_interface/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/TB.defs
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/TB.defs (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/TB.defs (revision 49)
@@ -0,0 +1,4 @@
+
+
+
+
projects/logic/ip/ps2_interface/sim/cov/ps2_interface/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist (revision 49)
@@ -0,0 +1,3 @@
+
+`include "../../../rtl/gen/syn/ps2_interface.v"
+
projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/dut
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/dut (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/dut (revision 49)
@@ -0,0 +1,48 @@
+
+wire ps2_clk_pad_in;
+wire ps2_data_pad_in;
+wire ps2_clk_pad_oe;
+wire ps2_data_pad_oe;
+wire ps2_clk;
+wire ps2_data;
+wire host_busy;
+wire [7:0] host_tx_data;
+wire host_tx_write;
+wire [7:0] host_rx_data;
+wire host_rx_read;
+wire host_rx_clear;
+wire host_rx_full;
+wire host_rx_parity_error;
+wire host_rx_parity_rcv;
+wire host_rx_parity_cal;
+wire host_rx_frame_error;
+wire host_tx_ack_error;
+wire host_tx_buffer_empty;
+
+
+
+ps2_interface
+#(.FREQ(25))
+dut(
+ .clk ( clk ),
+ .reset ( reset ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .busy ( host_busy ),
+ .tx_data ( host_tx_data ),
+ .tx_buffer_empty ( host_tx_buffer_empty ),
+ .tx_write ( host_tx_write ),
+ .rx_data ( host_rx_data ),
+ .rx_read ( host_rx_read ),
+ .rx_full ( host_rx_full ),
+ .rx_parity_error ( host_rx_parity_error ),
+ .rx_parity_rcv ( host_rx_parity_rcv ),
+ .rx_parity_cal ( host_rx_parity_cal ),
+ .rx_frame_error ( host_rx_frame_error ),
+ .tx_ack_error ( host_tx_ack_error ),
+ .rx_clear ( host_rx_clear )
+);
+
+
projects/logic/ip/ps2_interface/sim/cov/ps2_interface/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/Makefile
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/Makefile (nonexistent)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/Makefile (revision 49)
@@ -0,0 +1,45 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > ps2_interface.v ;\
+ covered score -i TB.dut -t ps2_interface -I ./ -v ./ps2_interface.v -o ps2_interface.cdd 2> ps2_interface_cov.log | tee >> ps2_interface_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd ps2_interface.cdd -vcd ../../out/$(TEST).vcd 2>> ps2_interface_sco_cov.log | tee >> ps2_interface_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd ps2_interface.cdd 2> ps2_interface_rep_cov.log | tee >> ps2_interface_rep_cov.log ;\
Index: projects/logic/ip/disp_io/rtl/xml/disp_io.xml
===================================================================
--- projects/logic/ip/disp_io/rtl/xml/disp_io.xml (nonexistent)
+++ projects/logic/ip/disp_io/rtl/xml/disp_io.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ disp_io
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/disp_io/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/disp_io/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/disp_io/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=disp_io
+test=default
Index: projects/logic/ip/disp_io/sim/cov/disp_io/liblist
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/liblist (nonexistent)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/liblist (revision 49)
@@ -0,0 +1,2 @@
+`include "../../lib/cde_divider/cde_divider.v"
+
projects/logic/ip/disp_io/sim/cov/disp_io/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/disp_io/sim/cov/disp_io/TB.defs
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/TB.defs (nonexistent)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/TB.defs (revision 49)
@@ -0,0 +1,2 @@
+`define PERIOD 40.00000
+
projects/logic/ip/disp_io/sim/cov/disp_io/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/disp_io/sim/cov/disp_io/test_define
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/test_define (nonexistent)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/test_define (revision 49)
@@ -0,0 +1,46 @@
+initial
+ begin
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Test Start",$realtime);
+ $display(" ===================================================");
+ $display(" ");
+ PosD = 16'b0000000000000000;
+ PosL = 8'b00000000;
+ sw_pad_in = 8'b00000000;
+ btn_pad_in = 4'b0000;
+
+ cg.next(8);
+ cg.reset_off;
+ cg.next(88);
+ $display("%t Start xmit test ",$realtime );
+
+ cg.next(1000);
+
+ PosD = 16'b1010101010101010;
+ PosL = 8'b10101010;
+ sw_pad_in = 8'b10101010;
+ btn_pad_in = 4'b1010;
+
+ cg.next(1000);
+
+ PosD = 16'b1111111111111111;
+ PosL = 8'b11111111;
+ sw_pad_in = 8'b11111111;
+ btn_pad_in = 4'b1111;
+
+
+
+
+ cg.next(1000);
+
+
+ cg.exit;
+end
+
+
+
+
+
+
+
projects/logic/ip/disp_io/sim/cov/disp_io/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/disp_io/sim/cov/disp_io/filelist
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/filelist (nonexistent)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/filelist (revision 49)
@@ -0,0 +1,3 @@
+
+`include "../../../rtl/gen/syn/disp_io.v"
+
projects/logic/ip/disp_io/sim/cov/disp_io/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/disp_io/sim/cov/disp_io/dut
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/dut (nonexistent)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/dut (revision 49)
@@ -0,0 +1,137 @@
+
+
+
+
+reg [3:0] btn_pad_in;
+reg [7:0] sw_pad_in;
+
+wire [7:0] led;
+wire [6:0] seg;
+wire dp;
+wire [3:0] an;
+
+reg [15:0] PosD;
+reg [7:0] PosL;
+wire [7:0] PosS;
+wire [3:0] PosB;
+
+
+wire clk_tgen;
+wire out_tgen;
+wire in_tgen;
+
+
+disp_io
+dut ( .clk (clk),
+ .reset (reset),
+ .btn_pad_in (btn_pad_in),
+ .sw_pad_in (sw_pad_in),
+ .PosD (PosD),
+ .PosL (PosL),
+ .PosB (PosB),
+ .PosS (PosS),
+ .led_pad_out (led),
+ .seg_pad_out (seg),
+ .dp_pad_out (dp),
+ .an_pad_out (an)
+ );
+
+
+
+
+
+reg [3:0] test_cnt;
+wire [3:0] test_cnt_src;
+
+reg [3:0] test_tar;
+
+always@(posedge clk)
+if(reset ) test_cnt <= 4'h0;
+else test_cnt <= test_cnt+4'b0001;
+
+always@(posedge clk)
+if(reset ) test_tar <= 4'h0;
+else test_tar <= test_tar+4'b0011;
+
+
+
+ timing_gen
+#(.DELAY(10),
+ .WIDTH(20))
+clk_tgenx
+( .clk (clk),
+ .reset (reset),
+ .tgen (clk_tgen));
+
+
+timing_gen
+#(.DELAY(5),
+ .WIDTH(35))
+out_tgenx
+( .clk (clk),
+ .reset (reset),
+ .tgen (out_tgen));
+
+
+
+timing_gen
+#(.DELAY(15),
+ .WIDTH(25))
+in_tgenx
+( .clk (clk),
+ .reset (reset),
+ .tgen (in_tgen));
+
+
+
+
+ic_test_probe
+clk_timer ( .signal ( clk_src ),
+ .assert_value ( 1'b1 ),
+ .drive_value ( 1'b1 ),
+ .clk ( clk ),
+ .tgen_out ( clk_tgen ),
+ .probe_type (2'b10 )
+ );
+
+
+
+/*
+
+ic_test_probe
+#(.SIGNAL_WIDTH(4))
+test_cnt_timer
+ (.signal ( test_cnt_src ),
+ .assert_value ( 1'b1 ),
+ .drive_value ( test_cnt ),
+ .clk ( clk ),
+ .tgen_out ( out_tgen ),
+ .probe_type (2'b00 )
+ );
+
+*/
+
+timed_driver
+#(.WIDTH(4),
+ .PROBE_TYPE(2'b00))
+test_cnt_timer (
+ .clk ( clk ),
+ .signal ( test_cnt_src ),
+ .drive_value ( test_cnt ),
+ .tgen ( out_tgen )
+ );
+
+
+timed_tester
+#(.WIDTH(4))
+tx
+(
+ .clk ( clk ),
+ .expected_value ( test_tar ),
+ .mask (4'b1001 ),
+ .tgen ( in_tgen ),
+ .signal ( test_cnt_src ),
+ .filtered_value ( ),
+ .fail ( )
+
+);
projects/logic/ip/disp_io/sim/cov/disp_io/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
===================================================================
--- projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml (nonexistent)
+++ projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ serial_rcvr
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/serial_rcvr/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/serial_rcvr/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=serial_rcvr
+test=default
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/liblist
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/liblist (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/liblist (revision 49)
@@ -0,0 +1,5 @@
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+`include "../../lib/cde_sram/cde_sram.v"
+
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/TB.defs
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/TB.defs (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/TB.defs (revision 49)
@@ -0,0 +1,5 @@
+`define PERIOD 40.0000
+
+
+
+
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/test_define
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/test_define (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/test_define (revision 49)
@@ -0,0 +1,57 @@
+
+
+
+initial
+ begin
+ while(1)
+ begin
+ cg.next(20);
+ edge_enable = 1'b1;
+ cg.next(1);
+ edge_enable = 1'b0;
+ end
+ end
+
+
+
+initial
+ begin
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Start Test ",$realtime );
+ $display(" ===================================================");
+ $display(" ");
+
+ edge_enable = 1'b0;
+ parity_enable = 1'b1;
+ parity_type = 1'b0;
+ parity_force = 1'b0;
+ start_value = 1'b0;
+ stop_value = 1'b1;
+ pad_in = 1'b1;
+ rcv_stb = 1'b0;
+
+ cg.next(12);
+ cg.reset_off;
+ cg.next(88);
+
+ $display("%t Test enabled ",$realtime );
+ parity_enable = 1'b1;
+ pad_in = 1'b0;
+ cg.next(1800);
+ pad_in = 1'b1;
+ cg.next(400);
+ pad_in = 1'b0;
+
+ cg.next(2000);
+
+pad_in = 1'b1;
+
+ cg.next(9000);
+
+ cg.exit;
+end
+
+
+
+
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist (revision 49)
@@ -0,0 +1,3 @@
+
+`include "../../../rtl/gen/syn/serial_rcvr.v"
+
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/dut
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/dut (nonexistent)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/dut (revision 49)
@@ -0,0 +1,44 @@
+
+ reg edge_enable;
+ reg parity_enable;
+ reg parity_type;
+ reg parity_force;
+ reg start_value;
+ reg stop_value;
+
+ reg rcv_stb;
+ reg pad_in;
+
+
+ wire [7:0] data_out;
+
+ wire data_avail;
+ wire parity_error;
+ wire stop_error;
+
+
+
+
+serial_rcvr
+ dut(
+ .clk ( clk ),
+ .reset ( reset ),
+ .edge_enable ( edge_enable ),
+ .parity_enable ( parity_enable ),
+ .parity_type ( parity_type ),
+ .parity_force ( parity_force ),
+ .start_value ( start_value ),
+ .stop_value ( stop_value ),
+
+ .pad_in ( pad_in ),
+ .rcv_stb ( rcv_stb ),
+ .data_out ( data_out ),
+ .parity_error ( parity_error ),
+ .stop_error ( stop_error ),
+ .data_avail ( data_avail )
+);
+
+
+
+
+
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/uart/rtl/xml/uart.xml
===================================================================
--- projects/logic/ip/uart/rtl/xml/uart.xml (nonexistent)
+++ projects/logic/ip/uart/rtl/xml/uart.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ uart
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/uart/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/uart/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/uart/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=uart
+test=default
Index: projects/logic/ip/uart/sim/run/divide/Makefile
===================================================================
--- projects/logic/ip/uart/sim/run/divide/Makefile (nonexistent)
+++ projects/logic/ip/uart/sim/run/divide/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=uart
+test=divide
Index: projects/logic/ip/uart/sim/cov/uart/liblist
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/liblist (nonexistent)
+++ projects/logic/ip/uart/sim/cov/uart/liblist (revision 49)
@@ -0,0 +1,8 @@
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+`include "../../lib/cde_sram/cde_sram.v"
+
+
+
projects/logic/ip/uart/sim/cov/uart/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/cov/uart/TB.defs
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/TB.defs (nonexistent)
+++ projects/logic/ip/uart/sim/cov/uart/TB.defs (revision 49)
@@ -0,0 +1,6 @@
+`define PERIOD 41.6666667
+
+
+
+
+
projects/logic/ip/uart/sim/cov/uart/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/cov/uart/filelist
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/filelist (nonexistent)
+++ projects/logic/ip/uart/sim/cov/uart/filelist (revision 49)
@@ -0,0 +1,5 @@
+
+`include "../../../rtl/gen/syn/uart.v"
+`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+
+
\ No newline at end of file
projects/logic/ip/uart/sim/cov/uart/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/cov/uart/dut
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/dut (nonexistent)
+++ projects/logic/ip/uart/sim/cov/uart/dut (revision 49)
@@ -0,0 +1,54 @@
+
+wire host_parity_enable ;
+
+wire host_txd_parity ;
+wire host_txd_force_parity ;
+wire [7:0] host_txd_data_in ;
+wire host_txd_buffer_empty ;
+wire host_txd_load ;
+wire host_txd_break ;
+
+wire host_rxd_parity ;
+wire host_rxd_force_parity ;
+wire [7:0] host_rxd_data_out ;
+wire host_rxd_data_avail ;
+wire host_rxd_data_avail_stb ;
+wire host_rxd_stop_error ;
+wire host_rxd_parity_error ;
+wire host_rx_data_avail ;
+
+
+uart
+#(
+ .RX_FIFO(1),
+ .RX_FIFO_SIZE(4),
+ .RX_FIFO_WORDS(16),
+ .TX_FIFO(1),
+ .TX_FIFO_SIZE(3),
+ .TX_FIFO_WORDS(8))
+ dut(
+ .clk ( clk ),
+ .reset ( reset ),
+ .parity_enable ( host_parity_enable ),
+ .divider_in ( 4'b0000 ),
+ .txd_parity ( host_txd_parity ),
+ .txd_force_parity ( host_txd_force_parity ),
+ .txd_data_in ( host_txd_data_in ),
+ .txd_buffer_empty ( host_txd_buffer_empty ),
+ .txd_load ( host_txd_load ),
+ .txd_break ( host_txd_break ),
+ .rxd_parity ( host_rxd_parity ),
+ .rxd_force_parity ( host_rxd_force_parity ),
+ .rxd_data_out ( host_rxd_data_out ),
+ .rxd_stop_error ( host_rxd_stop_error ),
+ .rxd_parity_error ( host_rxd_parity_error ),
+ .rxd_data_avail ( host_rxd_data_avail ),
+ .rxd_data_avail_stb ( host_rxd_data_avail_stb ),
+ .txd_pad_out ( serial_txd ),
+ .rxd_pad_in ( serial_rxd ),
+ .cts_pad_in ( 1'b0 ),
+ .rts_pad_out ( ),
+ .cts_out ( ),
+ .rts_in ( 1'b0 )
+);
+
projects/logic/ip/uart/sim/cov/uart/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/cov/uart/Makefile
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/Makefile (nonexistent)
+++ projects/logic/ip/uart/sim/cov/uart/Makefile (revision 49)
@@ -0,0 +1,45 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > uart.v ;\
+ covered score -i TB.dut -t uart -I ./ -v ./uart.v -o uart.cdd 2> uart_cov.log | tee >> uart_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd uart.cdd -vcd ../../out/$(TEST).vcd 2>> uart_sco_cov.log | tee >> uart_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd uart.cdd 2> uart_rep_cov.log | tee >> uart_rep_cov.log ;\
Index: projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml
===================================================================
--- projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml (nonexistent)
+++ projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ io_module_mouse
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/io_module/rtl/xml/io_module.xml
===================================================================
--- projects/logic/ip/io_module/rtl/xml/io_module.xml (nonexistent)
+++ projects/logic/ip/io_module/rtl/xml/io_module.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ io_module
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/io_module/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/io_module/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/io_module/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=io_module
+test=default
Index: projects/logic/ip/io_module/sim/run/mouse/filelist
===================================================================
--- projects/logic/ip/io_module/sim/run/mouse/filelist (revision 48)
+++ projects/logic/ip/io_module/sim/run/mouse/filelist (revision 49)
@@ -1,5 +1,5 @@
-`include "../../../rtl/gen/sim/io_module.v"
+`include "../../../rtl/gen/sim/io_module_mouse.v"
`include "../../../../uart/rtl/gen/sim/uart.v"
`include "../../../../ps2_interface/rtl/gen/sim/ps2_interface.v"
`include "../../../../vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
/projects/logic/ip/io_module/sim/run/mouse/dut
34,7 → 34,7
reg start; |
|
|
io_module |
io_module_mouse |
dut ( |
.clk ( clk ), |
.reset ( reset ), |
/projects/logic/ip/io_module/sim/run/mouse/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=io_module_mouse |
test=mouse |
/projects/logic/ip/io_module/sim/cov/io_module_mouse/liblist
0,0 → 1,6
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" |
`include "../../lib/cde_divider/cde_divider.v" |
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" |
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" |
`include "../../lib/cde_fifo/cde_fifo.v" |
`include "../../lib/cde_sram/cde_sram.v" |
projects/logic/ip/io_module/sim/cov/io_module_mouse/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module_mouse/TB.defs
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module_mouse/TB.defs (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module_mouse/TB.defs (revision 49)
@@ -0,0 +1,4 @@
+`define PERIOD 20.00000
+`define TIMEOUT 8000000
+
+
projects/logic/ip/io_module/sim/cov/io_module_mouse/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist (revision 49)
@@ -0,0 +1,6 @@
+
+`include "../../../rtl/gen/syn/io_module_mouse.v"
+`include "../../../../uart/rtl/gen/syn/uart.v"
+`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
+`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
\ No newline at end of file
projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module_mouse/dut
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module_mouse/dut (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module_mouse/dut (revision 49)
@@ -0,0 +1,87 @@
+
+wire wr;
+wire rd;
+wire [15:0] addr;
+wire [7:0] wdata;
+wire [15:0] rdata;
+wire [7:0] gpio_0_out;
+wire [7:0] gpio_0_oe;
+wire [7:0] gpio_0_lat;
+wire [7:0] gpio_1_out;
+wire [7:0] gpio_1_oe;
+wire [7:0] gpio_1_lat;
+wire loop_back;
+wire rts_pad_out;
+wire pic_irq;
+wire pic_nmi;
+wire [1:0] timer_irq;
+wire rx_irq;
+wire tx_irq;
+wire ps2_data_avail;
+
+wire ps2_clk_pad_oe;
+wire ps2_data_pad_oe;
+wire ps2_clk_pad_in;
+wire ps2_data_pad_in;
+wire [9:0] y_pos;
+wire [9:0] x_pos;
+wire new_packet;
+wire ms_mid;
+wire ms_right;
+wire ms_left;
+
+reg [7:0] reading;
+reg start;
+
+
+io_module_mouse
+dut (
+ .clk ( clk ),
+ .reset ( reset ),
+ .enable ( 1'b1 ),
+ .cs_i ( 1'b1 ),
+ .cs_m ( 1'b0 ),
+ .wr ( wr ),
+ .rd ( rd ),
+ .addr ( addr ),
+ .wdata ( wdata ),
+ .rdata ( rdata ),
+
+ .gpio_0_out ( gpio_0_out ),
+ .gpio_0_oe ( gpio_0_oe ),
+ .gpio_0_lat ( gpio_0_lat ),
+ .gpio_0_in ( gpio_0_out ),
+
+ .gpio_1_out ( gpio_1_out ),
+ .gpio_1_oe ( gpio_1_oe ),
+ .gpio_1_lat ( gpio_1_lat ),
+ .gpio_1_in ( gpio_1_out ),
+
+ .txd_pad_out ( loop_back ),
+ .rxd_pad_in ( loop_back ),
+ .cts_pad_in ( 1'b0 ),
+ .rts_pad_out ( rts_pad_out ),
+ .ext_irq_in ( {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq} ),
+ .pic_irq ( pic_irq ),
+ .pic_nmi ( pic_nmi ),
+ .timer_irq ( timer_irq ),
+ .rx_irq ( rx_irq ),
+ .tx_irq ( tx_irq ),
+ .ps2_data_avail ( ps2_data_avail ),
+ .ps2_clk_pad_in ( ps2_clk_pad_in ),
+ .ps2_data_pad_in ( ps2_data_pad_in ),
+ .ps2_clk_pad_oe ( ps2_clk_pad_oe ),
+ .ps2_data_pad_oe ( ps2_data_pad_oe ),
+ .y_pos ( x_pos ),
+ .x_pos ( y_pos ),
+ .new_packet ( new_packet ),
+ .ms_mid ( ms_mid ),
+ .ms_right ( ms_right ),
+ .ms_left ( ms_left )
+ );
+
+
+
+
+
+
projects/logic/ip/io_module/sim/cov/io_module_mouse/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module/liblist
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module/liblist (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module/liblist (revision 49)
@@ -0,0 +1,6 @@
+`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../lib/cde_divider/cde_divider.v"
+`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../lib/cde_fifo/cde_fifo.v"
+`include "../../lib/cde_sram/cde_sram.v"
\ No newline at end of file
projects/logic/ip/io_module/sim/cov/io_module/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module/TB.defs
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module/TB.defs (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module/TB.defs (revision 49)
@@ -0,0 +1,4 @@
+`define PERIOD 20.00000
+
+
+
projects/logic/ip/io_module/sim/cov/io_module/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module/filelist
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module/filelist (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module/filelist (revision 49)
@@ -0,0 +1,6 @@
+
+`include "../../../rtl/gen/syn/io_module.v"
+`include "../../../../uart/rtl/gen/syn/uart.v"
+`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
+`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+`include "../../../../vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
projects/logic/ip/io_module/sim/cov/io_module/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module/dut
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module/dut (nonexistent)
+++ projects/logic/ip/io_module/sim/cov/io_module/dut (revision 49)
@@ -0,0 +1,95 @@
+
+ wire wr;
+ wire rd;
+ wire [15:0] addr;
+ wire [7:0] wdata;
+
+ wire [15:0] rdata;
+
+ wire [7:0] gpio_0_out;
+ wire [7:0] gpio_0_oe;
+ wire [7:0] gpio_0_lat;
+
+ wire [7:0] gpio_1_out;
+ wire [7:0] gpio_1_oe;
+ wire [7:0] gpio_1_lat;
+
+ wire loop_back;
+ wire rts_pad_out;
+
+ wire pic_irq;
+ wire pic_nmi;
+
+ wire [1:0] timer_irq;
+ wire rx_irq;
+ wire tx_irq;
+
+
+
+ wire ps2_data_avail;
+
+ wire ps2_clk_oe;
+
+ wire ps2_data_oe;
+
+
+
+
+ wire [9:0] y_pos;
+ wire [9:0] x_pos;
+ wire new_packet;
+ wire ms_mid;
+ wire ms_right;
+ wire ms_left;
+
+
+
+
+
+io_module
+dut (
+ .clk ( clk ),
+ .reset ( reset ),
+ .enable ( 1'b1 ),
+ .cs_i ( 1'b1 ),
+ .cs_m ( 1'b0 ),
+ .wr ( wr ),
+ .rd ( rd ),
+ .addr ( addr ),
+ .wdata ( wdata ),
+ .rdata ( rdata ),
+
+ .gpio_0_out ( gpio_0_out ),
+ .gpio_0_oe ( gpio_0_oe ),
+ .gpio_0_lat ( gpio_0_lat ),
+ .gpio_0_in ( gpio_0_out ),
+
+ .gpio_1_out ( gpio_1_out ),
+ .gpio_1_oe ( gpio_1_oe ),
+ .gpio_1_lat ( gpio_1_lat ),
+ .gpio_1_in ( gpio_1_out ),
+
+ .txd_pad_out ( loop_back ),
+ .rxd_pad_in ( loop_back ),
+ .cts_pad_in ( 1'b0 ),
+ .rts_pad_out ( rts_pad_out ),
+ .ext_irq_in ( {3'h0,ps2_data_avail,tx_irq,rx_irq,timer_irq} ),
+ .pic_irq ( pic_irq ),
+ .pic_nmi ( pic_nmi ),
+ .timer_irq ( timer_irq ),
+ .rx_irq ( rx_irq ),
+ .tx_irq ( tx_irq ),
+ .ps2_data_avail ( ps2_data_avail ),
+ .ps2_clk_pad_in (1'b1),
+ .ps2_data_pad_in (1'b1),
+ .ps2_clk_pad_oe (),
+ .ps2_data_pad_oe (),
+ .y_pos (),
+ .x_pos (),
+ .new_packet (),
+ .ms_mid (),
+ .ms_right (),
+ .ms_left ()
+ );
+
+
projects/logic/ip/io_module/sim/cov/io_module/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
===================================================================
--- projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml (nonexistent)
+++ projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ flash_memcontrl
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/flash_memcontrl/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=flash_memcontrl
+test=default
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/liblist
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/liblist (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/liblist (revision 49)
@@ -0,0 +1,2 @@
+
+
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/TB.defs
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/TB.defs (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/TB.defs (revision 49)
@@ -0,0 +1,3 @@
+
+
+
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/test_define
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/test_define (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/test_define (revision 49)
@@ -0,0 +1,80 @@
+
+
+
+
+reg [31:0] d;
+
+ parameter SPI_TX_0 = 5'h0;
+ parameter SPI_CTRL = 5'h10;
+ parameter SPI_DIVIDE = 5'h14;
+ parameter SPI_SS = 5'h18;
+
+
+initial
+ begin
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Test Start",$realtime );
+ $display(" ===================================================");
+ $display(" ");
+ cg.next(8);
+ cg.reset_off;
+ $display("%t Out of reset ",$realtime );
+ cg.next(88);
+
+
+ bus16.u_write(24'h004002, 16'h0011);
+ cg.next(10);
+ bus16.u_write(24'h004004, 16'h0022);
+ cg.next(10);
+ bus16.u_write(24'h004002, 16'h00ff);
+ cg.next(10);
+ bus16.u_write(24'h004004, 16'h00aa);
+ cg.next(10);
+ bus16.u_write(24'h004024, 16'h000f);
+ cg.next(10);
+ bus16.u_write(24'h004028, 16'h000e);
+ cg.next(10);
+ bus16.u_write(24'h004044, 16'h000d);
+ cg.next(10);
+ bus16.u_write(24'h004048, 16'h000c);
+ cg.next(10);
+ bus16.u_write(24'h004060, 16'h000b);
+ cg.next(10);
+ bus16.u_write(24'h004062, 16'h000a);
+ cg.next(10);
+ bus16.u_write(24'h004064, 16'h0009);
+ cg.next(10);
+
+ bus16.u_cmp(24'h004002, 16'h00ff);
+ cg.next(10);
+ bus16.u_cmp(24'h004004, 16'h00aa);
+ cg.next(10);
+ bus16.u_cmp(24'h004024, 16'h000f);
+ cg.next(10);
+ bus16.u_cmp(24'h004028, 16'h000e);
+ cg.next(10);
+ bus16.u_cmp(24'h004044, 16'h000d);
+ cg.next(10);
+ bus16.u_cmp(24'h004048, 16'h000c);
+ cg.next(10);
+ bus16.u_cmp(24'h004060, 16'h000b);
+ cg.next(10);
+ bus16.u_cmp(24'h004062, 16'h000a);
+ cg.next(10);
+ bus16.u_cmp(24'h004064, 16'h0009);
+
+ cg.next(100);
+
+
+cg.exit;
+end
+
+
+
+
+
+
+
+
+
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist (revision 49)
@@ -0,0 +1,5 @@
+
+`include "../../../rtl/gen/syn/flash_memcontrl.v"
+
+
+
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/dut
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/dut (nonexistent)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/dut (revision 49)
@@ -0,0 +1,238 @@
+
+
+
+
+wire [23:0] micro_addr;
+wire [15:0] micro_wdata;
+wire micro_rd;
+wire micro_wr;
+wire micro_ub;
+wire micro_lb;
+wire [1:0] micro_cs;
+wire micro_ack;
+
+wire [15:0] micro_rdata;
+
+wire [23:1] memadr_out;
+wire memoe_n_out;
+wire memdb_oe;
+wire [15:0] memdb_out;
+wire [15:0] memdb_in;
+wire [15:0] memdb_io;
+wire memwr_n_out;
+wire ramcs_n_out;
+wire ramlb_n_out;
+wire ramadv_out_n;
+wire ramclk_out;
+wire ramcre_out;
+wire ramub_n_out;
+
+
+flash_memcontrl
+dut
+(
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .addr ( micro_addr[23:1]),
+ .wdata ( micro_wdata ),
+ .cs ( micro_cs ),
+ .stb (|micro_cs ),
+ .rd ( micro_rd ),
+ .wr ( micro_wr ),
+ .ub ( micro_ub ),
+ .lb ( micro_lb ),
+ .ack ( micro_ack ),
+ .rdata ( micro_rdata ),
+
+ .memadr_out ( memadr_out ),
+ .memoe_n_out ( memoe_n_out ),
+ .memdb_oe ( memdb_oe ),
+ .memdb_out ( memdb_out ),
+ .memdb_in ( memdb_in ),
+ .memwr_n_out ( memwr_n_out ),
+ .ramcs_n_out ( ramcs_n_out ),
+ .ramlb_n_out ( ramlb_n_out ),
+ .ramadv_out_n ( ramadv_out_n ),
+ .ramclk_out ( ramclk_out ),
+ .ramcre_out ( ramcre_out ),
+ .ramub_n_out ( ramub_n_out )
+ );
+
+
+
+
+micro_bus16_model
+bus16
+ (
+ .clk ( clk ),
+ .reset ( reset ),
+ .addr ( micro_addr ),
+ .wdata ( micro_wdata ),
+ .cs ( micro_cs ),
+ .rd ( micro_rd ),
+ .wr ( micro_wr ),
+ .ub ( micro_ub ),
+ .lb ( micro_lb ),
+ .rdata ( micro_rdata )
+);
+
+
+
+
+iobuftri memdb_buff_0
+ (
+ .i (memdb_out[0] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[0] ),
+ .pad (memdb_io[0] )
+ );
+
+iobuftri memdb_buff_1
+ (
+ .i (memdb_out[1] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[1] ),
+ .pad (memdb_io[1] )
+ );
+
+iobuftri memdb_buff_2
+ (
+ .i (memdb_out[2] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[2] ),
+ .pad (memdb_io[2] )
+ );
+
+iobuftri memdb_buff_3
+ (
+ .i (memdb_out[3] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[3] ),
+ .pad (memdb_io[3] )
+ );
+
+iobuftri memdb_buff_4
+ (
+ .i (memdb_out[4] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[4] ),
+ .pad (memdb_io[4] )
+ );
+
+iobuftri memdb_buff_5
+ (
+ .i (memdb_out[5] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[5] ),
+ .pad (memdb_io[5] )
+ );
+
+
+iobuftri memdb_buff_6
+ (
+ .i (memdb_out[6] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[6] ),
+ .pad (memdb_io[6] )
+ );
+
+iobuftri memdb_buff_7
+ (
+ .i (memdb_out[7] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[7] ),
+ .pad (memdb_io[7] )
+ );
+
+iobuftri memdb_buff_8
+ (
+ .i (memdb_out[8] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[8] ),
+ .pad (memdb_io[8] )
+ );
+
+iobuftri memdb_buff_9
+ (
+ .i (memdb_out[9] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[9] ),
+ .pad (memdb_io[9] )
+ );
+
+iobuftri memdb_buff_10
+ (
+ .i (memdb_out[10] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[10] ),
+ .pad (memdb_io[10] )
+ );
+
+
+iobuftri memdb_buff_11
+ (
+ .i (memdb_out[11] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[11] ),
+ .pad (memdb_io[11] )
+ );
+
+iobuftri memdb_buff_12
+ (
+ .i (memdb_out[12] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[12] ),
+ .pad (memdb_io[12] )
+ );
+
+iobuftri memdb_buff_13
+ (
+ .i (memdb_out[13] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[13] ),
+ .pad (memdb_io[13] )
+ );
+
+iobuftri memdb_buff_14
+ (
+ .i (memdb_out[14] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[14] ),
+ .pad (memdb_io[14] )
+ );
+
+
+iobuftri memdb_buff_15
+ (
+ .i (memdb_out[15] ),
+ .oe (memdb_oe ),
+ .o (memdb_in[15] ),
+ .pad (memdb_io[15] )
+ );
+
+
+pullup pu_ramwait ( ramwait_n );
+
+mt45w8mw12
+psram (
+ .clk ( ramclk_out ),
+ .adv_n ( ramadv_out_n ),
+ .cre ( ramcre_out ),
+ .o_wait ( ramwait_n ),
+ .ce_n ( ramcs_n_out ),
+ .oe_n ( memoe_n_out ),
+ .we_n ( memwr_n_out ),
+ .lb_n ( ramlb_n_out ),
+ .ub_n ( ramub_n_out ),
+ .addr ( memadr_out ),
+ .dq ( memdb_io )
+);
+
+
+
+
+
+
+
+
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
===================================================================
--- projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml (nonexistent)
+++ projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ usb_epp
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/usb_epp/sim/run/default/Makefile
===================================================================
--- projects/logic/ip/usb_epp/sim/run/default/Makefile (nonexistent)
+++ projects/logic/ip/usb_epp/sim/run/default/Makefile (revision 49)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=usb_epp
+test=default
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/liblist
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/liblist (nonexistent)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/liblist (revision 49)
@@ -0,0 +1,2 @@
+
+
projects/logic/ip/usb_epp/sim/cov/usb_epp/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/TB.defs
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/TB.defs (nonexistent)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/TB.defs (revision 49)
@@ -0,0 +1,2 @@
+`define PERIOD 40.00000
+
projects/logic/ip/usb_epp/sim/cov/usb_epp/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/test_define
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/test_define (nonexistent)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/test_define (revision 49)
@@ -0,0 +1,21 @@
+initial
+ begin
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Test Start",$realtime);
+ $display(" ===================================================");
+ $display(" ");
+
+
+ cg.next(1000);
+
+
+ cg.exit;
+end
+
+
+
+
+
+
+
projects/logic/ip/usb_epp/sim/cov/usb_epp/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist (nonexistent)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist (revision 49)
@@ -0,0 +1,3 @@
+
+`include "../../../rtl/gen/syn/usb_epp.v"
+
projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/dut
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/dut (nonexistent)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/dut (revision 49)
@@ -0,0 +1,3 @@
+
+
+
projects/logic/ip/usb_epp/sim/cov/usb_epp/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml
===================================================================
--- projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ vga_char_ctrl_600x432
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
===================================================================
--- projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml (revision 49)
@@ -0,0 +1,19 @@
+
+
+ vga_char_ctrl
+ logic
+
+
+ cde_sram
+ cde_sram
+ cde
+
+
+ cde_sync_with_hystersis
+ cde_synchronizers
+ cde
+
+
+
+
+
Index: projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation.v
===================================================================
--- projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation.v (revision 48)
+++ projects/logic/ip/vga_char_ctrl/rtl/verilog/svga_timing_generation.v (revision 49)
@@ -83,17 +83,17 @@
always @ (posedge clk ) begin
if (reset)
// on reset remove v_synch
- v_synch = 1'b0;
+ v_synch <= 1'b0;
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
(pixel_count == `H_TOTAL - 1)))
// start of v_synch
- v_synch = 1'b1;
+ v_synch <= 1'b1;
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
(pixel_count == (`H_TOTAL - 1)))
// end of v_synch
- v_synch = 1'b0;
+ v_synch <= 1'b0;
end
/projects/logic/ip/vga_char_ctrl/rtl/verilog/char_gen.v
141,45 → 141,41
always @ (posedge clk ) begin |
if (reset) |
begin |
pixel_on = 1'b0; |
latched_low_char_data = 4'h0; |
latched_char_data = 8'h00; |
pixel_on <= 1'b0; |
latched_low_char_data <= 4'h0; |
latched_char_data <= 8'h00; |
end |
|
else if (shift_high) |
begin |
pixel_on = latched_char_data [7]; |
latched_char_data [7] = latched_char_data [6]; |
latched_char_data [6] = latched_char_data [5]; |
latched_char_data [5] = latched_char_data [4]; |
latched_char_data [4] = latched_char_data [7]; |
pixel_on <= latched_char_data [7]; |
latched_char_data [7] <= latched_char_data [6]; |
latched_char_data [6] <= latched_char_data [5]; |
latched_char_data [5] <= latched_char_data [4]; |
latched_char_data [4] <= latched_char_data [7]; |
if(latch_low_data) begin |
latched_low_char_data [3:0] = latched_char_data [3:0]; |
latched_low_char_data [3:0] <= latched_char_data [3:0]; |
end |
else begin |
latched_low_char_data [3:0] = latched_low_char_data [3:0]; |
latched_low_char_data [3:0] <= latched_low_char_data [3:0]; |
end |
end |
|
else if (shift_low) |
begin |
pixel_on = latched_low_char_data [3]; |
latched_low_char_data [3] = latched_low_char_data [2]; |
latched_low_char_data [2] = latched_low_char_data [1]; |
latched_low_char_data [1] = latched_low_char_data [0]; |
latched_low_char_data [0] = latched_low_char_data [3]; |
if (latch_data) begin |
latched_char_data [7:0] = char_gen_rom_data[7:0]; |
end |
else begin |
latched_char_data [7:0] = latched_char_data [7:0]; |
end |
end |
pixel_on <= latched_low_char_data [3]; |
latched_low_char_data [3] <= latched_low_char_data [2]; |
latched_low_char_data [2] <= latched_low_char_data [1]; |
latched_low_char_data [1] <= latched_low_char_data [0]; |
latched_low_char_data [0] <= latched_low_char_data [3]; |
if (latch_data) latched_char_data [7:0] <= char_gen_rom_data[7:0]; |
else latched_char_data [7:0] <= latched_char_data [7:0]; |
end |
else |
begin |
latched_low_char_data [3:0] = latched_low_char_data [3:0]; |
latched_char_data [7:0] = latched_char_data [7:0]; |
pixel_on = pixel_on; |
begin |
latched_low_char_data [3:0] <= latched_low_char_data [3:0]; |
latched_char_data [7:0] <= latched_char_data [7:0]; |
pixel_on <= pixel_on; |
end |
end |
|
/projects/logic/ip/vga_char_ctrl/sim/run/default/Makefile
0,0 → 1,3
include ../../../../../bin/Makefile.root |
comp=vga_char_ctrl |
test=default |
/projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/liblist
0,0 → 1,3
`include "../../lib/cde_sram/cde_sram.v" |
|
|
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/TB.defs
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/TB.defs (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/TB.defs (revision 49)
@@ -0,0 +1,5 @@
+`define PERIOD 41.16667
+`define TIMEOUT 20000000
+`define STARTUP "../../../../../sw/startup/startup.abs"
+`define FONT "../../../../../sw/font/font.abs"
+
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist (revision 49)
@@ -0,0 +1,2 @@
+`include "../../../rtl/gen/syn/vga_char_ctrl.v"
+
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/dut
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/dut (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/dut (revision 49)
@@ -0,0 +1,46 @@
+wire h_sync;
+wire v_sync;
+
+wire red;
+wire green;
+wire blue;
+
+
+
+
+wire [7:0] wdata;
+wire [13:0] address;
+
+wire [2:0] vga_red_pad_out;
+wire [2:0] vga_green_pad_out;
+wire [1:0] vga_blue_pad_out;
+wire hsync_n_pad_out;
+wire vsync_n_pad_out;
+
+
+vga_char_ctrl
+#(.STARTUP(`STARTUP),
+ .FONT(`FONT))
+dut (
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ascii_load (1'b0),
+ .add_l_load (1'b0),
+ .add_h_load (1'b0),
+
+ .char_color (8'h92),
+ .back_color (8'h00),
+ .cursor_color (8'hff),
+
+ .wdata (8'h00),
+ .address ( address),
+
+ .vga_red_pad_out ( vga_red_pad_out ),
+ .vga_green_pad_out ( vga_green_pad_out ),
+ .vga_blue_pad_out ( vga_blue_pad_out ),
+
+ .hsync_n_pad_out ( hsync_n_pad_out ),
+ .vsync_n_pad_out ( vsync_n_pad_out )
+);
+
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/Makefile
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/Makefile (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/Makefile (revision 49)
@@ -0,0 +1,45 @@
+SHELL=/bin/sh
+MAKE=make
+
+VPP_NAME=vppreproc
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > vga_char_ctrl.v ;\
+ covered score -i TB.dut -t vga_char_ctrl -I ./ -v ./vga_char_ctrl.v -o vga_char_ctrl.cdd 2> vga_char_ctrl_cov.log | tee >> vga_char_ctrl_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd vga_char_ctrl.cdd -vcd ../../out/$(TEST).vcd 2>> vga_char_ctrl_sco_cov.log | tee >> vga_char_ctrl_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd vga_char_ctrl.cdd 2> vga_char_ctrl_rep_cov.log | tee >> vga_char_ctrl_rep_cov.log ;\
Index: Makefile
===================================================================
--- Makefile (revision 48)
+++ Makefile (revision 49)
@@ -19,93 +19,62 @@
.PHONY build_hw:
build_hw:
- @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ @for PROJECT in `ls $(CUR_DIR)/work`; do \
echo "################################################"; \
echo "build_hw: $$PROJECT ####"; echo; \
- cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ cd ${home}/${design}/work/$$PROJECT/bin;\
${MAKE} group_build_hw;\
done; \
.PHONY build_sw:
build_sw: build_hw
- @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ @for PROJECT in `ls $(CUR_DIR)/work`; do \
echo "################################################"; \
echo "build_sw: $$PROJECT ####"; echo; \
- cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ cd ${home}/${design}/work/$$PROJECT/bin;\
${MAKE} group_build_sw;\
done; \
.PHONY run_sims:
run_sims: build_sw
- @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ @for PROJECT in `ls $(CUR_DIR)/work`; do \
echo "################################################"; \
echo "run_sims: $$PROJECT ####"; echo; \
- cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ cd ${home}/${design}/work/$$PROJECT/bin;\
${MAKE} group_run_sims;\
done; \
.PHONY build_fpgas:
build_fpgas:
- @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ @for PROJECT in `ls $(CUR_DIR)/work`; do \
echo "################################################"; \
echo "build_fpgas: $$PROJECT ####"; echo; \
- cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ cd ${home}/${design}/work/$$PROJECT/bin;\
${MAKE} group_build_fpgas;\
done; \
+
+
+
+
.PHONY check_sims:
-check_sims:
- (\
- cd ${home}/${design}_cmp ;\
- echo " number of logic sims run";\
- find . | grep dut| grep -v children| grep logic | wc -l ;\
+check_sims:
+ @for COMP in `ls $(CUR_DIR)/work`; do \
+ echo "**************************************************************";\
+ echo " number of $$COMP sims run";\
+ find ./work | grep dut| grep -v children| grep -v cov | grep $$COMP | wc -l;\
echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep logic| wc -l ;\
+ find ./work | grep _sim.log | xargs grep PASSED $1 | grep $$COMP| wc -l ;\
echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep logic | wc -l ;\
+ find ./work | grep _sim.log | xargs grep WARNING $1 |grep $$COMP | wc -l ;\
echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep logic | wc -l ;\
- echo " number of pic_micro sims run";\
- find . | grep dut| grep -v children| grep pic_micro | wc -l ;\
- echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep pic_micro| wc -l ;\
+ find ./work | grep _sim.log | xargs grep ERROR $1 |grep $$COMP | wc -l ;\
+ echo " Code Coverage";\
echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep pic_micro | wc -l ;\
+ find ./work | grep _cov.log | xargs grep WARNING $1| grep $$COMP | wc -l ;\
echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep pic_micro | wc -l ;\
- echo " number of msp430 sims run";\
- find . | grep dut| grep -v children| grep msp430 | wc -l ;\
- echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep msp430| wc -l ;\
- echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep msp430 | wc -l ;\
- echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep msp430 | wc -l ;\
- echo " number of M6502 sims run";\
- find . | grep dut| grep -v children| grep Mos6502 | wc -l ;\
- echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep Mos6502| wc -l ;\
- echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep Mos6502 | wc -l ;\
- echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep Mos6502 | wc -l ;\
- echo " number of open sims run";\
- find . | grep dut| grep -v children| grep open | wc -l ;\
- echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep open| wc -l ;\
- echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep open | wc -l ;\
- echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep open | wc -l ;\
- echo " number of wish sims run";\
- find . | grep dut| grep -v children| grep wish | wc -l ;\
- echo " number of sims that finished";\
- find . | grep _sim.log | xargs grep PASSED $1 | grep wish| wc -l ;\
- echo " number of warnings";\
- find . | grep _sim.log | xargs grep WARNING $1 |grep wish | wc -l ;\
- echo " number of errors";\
- find . | grep _sim.log | xargs grep ERROR $1 |grep wish | wc -l ;\
- )
+ find ./work | grep _cov.log | xargs grep ERROR $1 | grep $$COMP | wc -l ;\
+ done;
.PHONY check_fpgas: