URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen/trunk
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/bench/verilog/TestBench
59,17 → 59,11
`define TIMEOUT 200000 |
`endif |
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`timescale `TIMESCALE |
`include "./filelist" |
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`timescale `TIMESCALE |
`include "./filelist.sim" |
`include "./modellist" |
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`timescale `TIMESCALE |
`include "./liblist" |
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module TB(); |
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/bench/verilog/TestBench.cov
45,8 → 45,7
`include "./TB.defs" |
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`timescale 1ns/1ns |
`include "./filelist" |
`include "./liblist" |
`include "./filelist.cov" |
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module TB(); |
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/tools/bin/Makefile.root
101,8 → 101,8
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.PHONY report_cov: |
report_cov: |
.PHONY print_cov: |
print_cov: |
@for VARIANT in `ls $(CUR_DIR)/../cov`; do \ |
echo "################################################################################"; \ |
echo; \ |
210,7 → 210,9
rm -r xilinx;\ |
mkdir xilinx;\ |
cd xilinx;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
cp ../target/filelist ../filelist;\ |
cat ../filelist.syn >> ../filelist ;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
xst -ifn ./Xst -ofn $(board)_$(Design).log;\ |
ngdbuild -dd _ngo -nt timestamp -p $(Part) -uc ../target/Pad_Ring.ucf $(board)_$(Design);\ |
map -p $(Part) -cm area -ir off -pr off -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\ |
269,7 → 271,7
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims COMP=$$COMP ;\ |
make report_cov ;\ |
make print_cov ;\ |
done; \ |
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/tools/bin/soc_link
46,9 → 46,9
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$root = "projects"; |
$dest = "work"; |
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use Cwd; |
use XML::LibXML; |
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55,12 → 55,12
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$home = cwd(); |
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@target_list = ( ); |
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print "Building socgen work area for $home \n" ; |
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&link_sub( $root ); |
&link_sub( $root,$root, "work" ); |
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@projects = qx(ls $home/work ); |
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77,11 → 77,11
chomp($component); |
$root = "bench"; |
$dest = "work/${project}/ip/${component}/sim/bench"; |
&link_sub( $root ); |
&link_sub( $root,$root, $dest ); |
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$root = "lib"; |
$dest = "work/${project}/ip/${component}/sim/lib"; |
&link_sub( $root ); |
&link_sub( $root,$root, $dest ); |
} |
} |
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93,6 → 93,9
foreach my $project (@projects) |
{ |
chomp($project); |
symlink( "${home}/tools/bin/Makefile.root", "${home}/work/${project}/bin/Makefile.root"); |
symlink( "${home}/tools/bin/Makefile", "${home}/work/${project}/bin/Makefile"); |
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my @components = qx(ls ${home}/work/${project}/ip ); |
foreach my $component (@components) |
{ |
107,10 → 110,11
my $doc = $parser->parse_file($filename); |
foreach my $comp ($doc->findnodes('/components/component')) |
{ |
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my($name) = $comp->findnodes('./name/text()')->to_literal ; |
my($variant) = $comp->findnodes('./variant/text()')->to_literal ; |
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print "making rt/gen directories for $project $component $name\n"; |
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print " work/${project}/ip/${component}/rtl/\n"; |
129,6 → 133,120
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print "CREATING sim and cov filelists for $project $component $name $variant \n"; |
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my $outfile ="work/${project}/ip/${component}/sim/cov/${variant}/filelist.cov"; |
open COVFILE,">$outfile" or die "unable to open $outfile"; |
print COVFILE "\`include \"../../../rtl/gen/syn/${variant}.v\" \n"; |
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$outfile ="work/${project}/ip/${component}/sim/cov/${variant}/filelist.sim"; |
open SIMFILE,">$outfile" or die "unable to open $outfile"; |
print SIMFILE "\`include \"../../../rtl/gen/sim/${variant}.v\" \n"; |
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$outfile ="work/${project}/ip/${component}/sim/cov/${variant}/filelist.syn"; |
open SYNFILE,">$outfile" or die "unable to open $outfile"; |
print SYNFILE "verilog work ../../../../../ip/${component}/rtl/gen/syn/${variant}.v \n"; |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/brothers/brother/variant")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../component/text()')->to_literal ; |
print COVFILE "\`include \"../../../../${child_parent}/rtl/gen/syn/${child}.v\"\n"; |
print SIMFILE "\`include \"../../../../${child_parent}/rtl/gen/sim/${child}.v\"\n"; |
print SYNFILE "verilog work ../../../../../ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
} |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/children/child/name")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
my($child_family) = $i_name ->findnodes('../family/text()')->to_literal ; |
print COVFILE "\`include \"../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v\"\n"; |
print SIMFILE "\`include \"../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/sim/${child}.v\"\n"; |
print SYNFILE "verilog work ../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
} |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/syn_children/child/name")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
my($child_family) = $i_name ->findnodes('../family/text()')->to_literal ; |
print SYNFILE "verilog work ../../../../../children/${child_family}/ip/${child_parent}/rtl/gen/syn/${child}.v\n"; |
} |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/library/child/name")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
print COVFILE "\`include \"../../lib/${child_parent}/${child}.v\"\n"; |
print SIMFILE "\`include \"../../lib/${child_parent}/${child}.v\"\n"; |
print SYNFILE "verilog work ./target/lib/syn/${child_parent}/${child}.v\n"; |
} |
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print "CREATING sim filelists for $project $component $chip $name $variant \n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/sims/sim/name")) |
{ |
my($chip) = $i_name ->findnodes('./text()')->to_literal ; |
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my $infile ="work/${project}/ip/${component}/sim/cov/${variant}/filelist.sim"; |
my $outfile ="work/${project}/ip/${component}/sim/run/${chip}/filelist.sim"; |
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$cmd = |
"cp $infile $outfile" ; |
if (system($cmd)) {} |
} |
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print "Linking targets for $project $component $name\n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/chips/chip/name")) |
{ |
my($chip) = $i_name ->findnodes('./text()')->to_literal ; |
my($chip_target) = $i_name ->findnodes('../target/text()')->to_literal ; |
print " work/${project}/ip/${component}/syn/${chip}/target/${chip_target}\n"; |
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$cmd = "cp work/${project}/ip/${component}/sim/cov/${variant}/filelist.syn ${home}/work/${project}/ip/${component}/syn/${chip}/filelist.syn" ; |
if (system($cmd)) {} |
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my $path = "work/${project}/ip/${component}/syn/${chip}/target"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$cmd = |
"lndir -silent ${home}/targets/${chip_target} ${home}/work/${project}/ip/${component}/syn/${chip}/target" ; |
if (system($cmd)) {} |
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$cmd = |
"lndir -silent ${home}/lib ${home}/work/${project}/ip/${component}/syn/${chip}/target/lib/syn" ; |
if (system($cmd)) {} |
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push @target_list ,$chip_target ; |
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} |
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print "Linking children for $project $component $name\n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/children/child/name")) |
{ |
135,7 → 253,6
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
my($child_family) = $i_name ->findnodes('../family/text()')->to_literal ; |
print " work/${project}/children/${child_family}/ip/${child_parent}\n"; |
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my $path = "work/${project}/children"; |
print "Creating $path\n" unless( -e $path ); |
153,6 → 270,8
$dest = "${home}/work/${project}/children/${child_family}/bin"; |
$cmd = "lndir ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
symlink( "${home}/tools/bin/Makefile.root", "${home}/work/${project}/children/${child_family}/bin/Makefile.root"); |
symlink( "${home}/tools/bin/Makefile", "${home}/work/${project}/children/${child_family}/bin/Makefile"); |
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my $path = "work/${project}/children/${child_family}/sw"; |
print "Creating $path\n" unless( -e $path ); |
160,7 → 279,7
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$root = "${home}/projects/${child_family}/sw"; |
$dest = "${home}/work/${project}/children/${child_family}/sw"; |
$cmd = "lndir ${root} ${dest} "; |
$cmd = "lndir -silent ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "work/${project}/children/${child_family}/ip"; |
173,7 → 292,7
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$root = "${home}/projects/${child_family}/ip/${child_parent}"; |
$dest = "${home}/work/${project}/children/${child_family}/ip/${child_parent}"; |
$cmd = "lndir ${root} ${dest} "; |
$cmd = "lndir -silent ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen"; |
187,29 → 306,68
my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/syn"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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} |
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print "Linking targets for $project $component $name\n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/chips/chip/name")) |
print "Linking syn_children for $project $component $name\n"; |
foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/syn_children/child/name")) |
{ |
my($chip) = $i_name ->findnodes('./text()')->to_literal ; |
my($chip_target) = $i_name ->findnodes('../target/text()')->to_literal ; |
print " work/${project}/ip/${component}/syn/${chip}/target/${chip_target}\n"; |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
my($child_family) = $i_name ->findnodes('../family/text()')->to_literal ; |
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my $path = "work/${project}/ip/${component}/syn/${chip}/target"; |
my $path = "work/${project}/children"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$cmd = |
"lndir ${home}/targets/${chip_target} ${home}/work/${project}/ip/${component}/syn/${chip}/target " ; |
if (system($cmd)) {} |
my $path = "work/${project}/children/${child_family}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$cmd = |
"lndir ${home}/lib ${home}/work/${project}/ip/${component}/syn/${chip}/target/lib/syn" ; |
if (system($cmd)) {} |
my $path = "work/${project}/children/${child_family}/bin"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/bin"; |
$dest = "${home}/work/${project}/children/${child_family}/bin"; |
$cmd = "lndir ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
symlink( "${home}/tools/bin/Makefile.root", "${home}/work/${project}/children/${child_family}/bin/Makefile.root"); |
symlink( "${home}/tools/bin/Makefile", "${home}/work/${project}/children/${child_family}/bin/Makefile"); |
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my $path = "work/${project}/children/${child_family}/sw"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/sw"; |
$dest = "${home}/work/${project}/children/${child_family}/sw"; |
$cmd = "lndir -silent ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "work/${project}/children/${child_family}/ip"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "work/${project}/children/${child_family}/ip/${child_parent}"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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$root = "${home}/projects/${child_family}/ip/${child_parent}"; |
$dest = "${home}/work/${project}/children/${child_family}/ip/${child_parent}"; |
$cmd = "lndir -silent ${root} ${dest} "; |
if (system($cmd)) {die "Failed ";} |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/sim"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
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my $path = "${home}/work/${project}/children/${child_family}/ip/${child_parent}/rtl/gen/syn"; |
print "Creating $path\n" unless( -e $path ); |
mkdir $path,0755 unless( -e $path ); |
} |
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216,7 → 374,6
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} |
} |
} |
224,36 → 381,27
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print "Done \n" ; |
@target_list = trim_sort(@target_list); |
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#foreach my $project (@projects) |
# { |
# chomp($project); |
# my @components = qx(ls ${home}/work/${project}/ip ); |
# foreach my $component (@components) |
# { |
# chomp($component); |
# my @variants = qx(ls ${home}/work/${project}/ip/${component}/rtl/variants ); |
# foreach my $variant (@variants) |
# { |
# chomp($variant); |
# print "$project $component $variant \n"; |
# } |
# } |
# } |
# |
foreach my $target (@target_list) |
{ |
print "Target $target \n" ; |
} |
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print "Done \n" ; |
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# recursively map directory information |
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sub link_sub { |
my $root = shift; |
my $path = shift; |
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my $dest = shift; |
return unless( -e $path ); |
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278,7 → 426,7
closedir( DIR ); |
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# recurse on items in the directory |
foreach my $item ( @contents ) { &link_sub( "$path/$item" );} |
foreach my $item ( @contents ) { &link_sub($root, "$path/$item", $dest );} |
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} else { |
287,3 → 435,15
} |
} |
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sub trim_sort { |
my @output_files = @_; |
my %trim = (); |
foreach $descriptor (@output_files) { $trim{$descriptor} = 1; } |
my @k = keys %trim; |
@output_files = sort(sort @k); |
return(@output_files); |
} |
/tools/bin/soc_builder
47,8 → 47,8
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$root = "projects"; |
$dest = "work"; |
$cde="cde"; |
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use Cwd; |
use XML::LibXML; |
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71,6 → 71,7
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@projects = qx(ls $home/work ); |
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111,6 → 112,20
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} |
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foreach my $i_name ($doc->findnodes("//component[name/text() = '$name']/syn_children/child/name")) |
{ |
my($child) = $i_name ->findnodes('./text()')->to_literal ; |
my($child_family) = $i_name ->findnodes('../family/text()')->to_literal ; |
my($child_parent) = $i_name ->findnodes('../parent/text()')->to_literal ; |
push @kids , "work/${project}/children/${child_family}/ip/${child_parent}/rtl/xml/${child}.xml"; |
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} |
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} |
} |
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168,13 → 183,13
$cmd ="cp ${home}/${prefix}/doc/copyright.v ${home}/${prefix}/rtl/gen/sim/${variant}.v"; |
if (system($cmd)) {} |
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$cmd ="vppreproc --noline --noblank ./defines.v ${home}/${prefix}/rtl/verilog/*.v >> ${home}/${prefix}/rtl/gen/sim/${variant}.v"; |
$cmd ="vppreproc --noline --noblank -DVARIANT=${variant} -DCDE=${cde} ./defines.v ${home}/${prefix}/rtl/verilog/*.v >> ${home}/${prefix}/rtl/gen/sim/${variant}.v"; |
if (system($cmd)) {} |
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$cmd ="cp ${home}/${prefix}/doc/copyright.v ${home}/${prefix}/rtl/gen/syn/${variant}.v"; |
if (system($cmd)) {} |
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$cmd ="vppreproc --noline --noblank -DSYNTHESIS ./defines.v ${home}/${prefix}/rtl/verilog/*.v >> ${home}/${prefix}/rtl/gen/syn/${variant}.v"; |
$cmd ="vppreproc --noline --noblank -DSYNTHESIS -DVARIANT=${variant} -DCDE=${cde} ./defines.v ${home}/${prefix}/rtl/verilog/*.v >> ${home}/${prefix}/rtl/gen/syn/${variant}.v"; |
if (system($cmd)) {} |
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$cmd ="rm ./defines.v "; |
/projects/pic_micro/ip/soc_mouse/rtl/xml/soc_mouse_mrisc.xml
1,7 → 1,17
<components> |
<component> |
<name>soc_mouse_mrisc</name> |
<parent>pic_micro</parent> |
<name>soc_mouse</name> |
<variant>soc_mouse_mrisc</variant> |
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<brothers> |
<brother> |
<variant>mrisc</variant> |
<component>mrisc</component> |
</brother> |
</brothers> |
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<children> |
<child> |
<name>ps2_interface</name> |
57,23 → 67,112
<parent>cde_sram</parent> |
<family>cde</family> |
</child> |
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<child> |
<name>cde_sync_with_hystersis</name> |
<name>cde_fifo</name> |
<parent>cde_fifo</parent> |
<family>cde</family> |
</child> |
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<child> |
<name>cde_divider</name> |
<parent>cde_divider</parent> |
<family>cde</family> |
</child> |
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<child> |
<name>cde_serial_xmit</name> |
<parent>cde_serial_xmit</parent> |
<family>cde</family> |
</child> |
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<child> |
<name>cde_serial_rcvr</name> |
<parent>cde_serial_rcvr</parent> |
<family>cde</family> |
</child> |
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<child> |
<name>cde_sync_with_hysteresis</name> |
<parent>cde_synchronizers</parent> |
<family>cde</family> |
</child> |
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</library> |
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<chips> |
<chip> |
<name>Nexys2_mouse_mrisc</name> |
<target>Nexys2</target> |
<children> |
<child> |
<name>disp_io</name> |
<parent>disp_io</parent> |
<family>logic</family> |
</child> |
<child> |
<name>flash_memcontrl</name> |
<parent>flash_memcontrl</parent> |
<family>logic</family> |
</child> |
<child> |
<name>usb_epp</name> |
<parent>usb_epp</parent> |
<family>logic</family> |
</child> |
</children> |
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</chip> |
<chip> |
<name>Basys_mouse_mrisc</name> |
<target>Basys</target> |
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<children> |
<child> |
<name>disp_io</name> |
<parent>disp_io</parent> |
<family>logic</family> |
</child> |
</children> |
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</chip> |
</chips> |
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<sims> |
<sim> |
<name>mouse_mrisc</name> |
</sim> |
</sims> |
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<syn_children> |
<child> |
<name>disp_io</name> |
<parent>disp_io</parent> |
<family>logic</family> |
</child> |
<child> |
<name>flash_memcontrl</name> |
<parent>flash_memcontrl</parent> |
<family>logic</family> |
</child> |
<child> |
<name>usb_epp</name> |
<parent>usb_epp</parent> |
<family>logic</family> |
</child> |
</syn_children> |
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</component> |
</components> |
/projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse_mrisc/defines.v
1,3 → 1,2
`define VARIANT soc_mouse_mrisc |
`define CDE cde |
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/projects/pic_micro/ip/soc_mouse/rtl/variants/soc_mouse/defines.v
1,3 → 1,2
`define VARIANT soc_mouse |
`define CDE cde |
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`define CPU pic16c5x |
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse_mrisc/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist (revision 56)
+++ projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/syn/soc_mouse.v"
-`include "../../../../pic16c5x/rtl/gen/syn/pic16c5x.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
-
projects/pic_micro/ip/soc_mouse/sim/cov/soc_mouse/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist (revision 56)
+++ projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist (nonexistent)
@@ -1,19 +0,0 @@
-verilog work ./target/Pad_Ring.v
-verilog work ../../../rtl/gen/syn/soc_mouse_mrisc.v
-verilog work ../../../../mrisc/rtl/gen/syn/mrisc.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-
Index: projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/filelist
===================================================================
--- projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/filelist (revision 56)
+++ projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/filelist (nonexistent)
@@ -1,20 +0,0 @@
-verilog work ./target/Pad_Ring.v
-verilog work ../../../rtl/gen/syn/soc_mouse_mrisc.v
-verilog work ../../../../mrisc/rtl/gen/syn/mrisc.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module_mouse.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-
Index: projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
===================================================================
--- projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml (revision 56)
+++ projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml (revision 57)
@@ -1,15 +1,9 @@
mrisc
- pic_micro
-
-
- ps2_interface
- ps2_interface
- logic
-
-
+ mrisc
+
cde_sram
@@ -17,7 +11,7 @@
cde
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
@@ -29,7 +23,37 @@
Basys_loop
Basys
+
+
+ disp_io
+ disp_io
+ logic
+
+
+
+
+
+
+sanity1 rf3 sanity2 rf2 rf1 ind_mem loop
+
+
+
+ disp_io
+ disp_io
+ logic
+
+
+
+
/projects/pic_micro/ip/mrisc/rtl/variants/mrisc/defines.v
1,4 → 1,4
`define VARIANT mrisc |
|
`define ALU _alu |
`define PRESCLR_WDT _presclr_wdt |
`define REGISTER_FILE _register_file |
/projects/pic_micro/ip/mrisc/sim/run/rf1/filelist
File deleted
projects/pic_micro/ip/mrisc/sim/run/rf1/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/rf1/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/rf1/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/rf1/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/rf1/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/sim/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/loop/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/loop/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/loop/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/sim/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/loop/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/loop/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/loop/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/loop/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/loop/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/rf2/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/rf2/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/rf2/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/sim/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/rf2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/rf2/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/rf2/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/rf2/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/rf2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/sim/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/rf3/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/rf3/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/rf3/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/sim/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/rf3/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/run/rf3/filelist.cov
===================================================================
--- projects/pic_micro/ip/mrisc/sim/run/rf3/filelist.cov (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/run/rf3/filelist.cov (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/run/rf3/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist (nonexistent)
@@ -1,4 +0,0 @@
-`include "../../../rtl/gen/syn/mrisc.v"
-
-
-
projects/pic_micro/ip/mrisc/sim/cov/mrisc/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
===================================================================
--- projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist (revision 56)
+++ projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist (nonexistent)
@@ -1,12 +0,0 @@
-verilog work ./target/Pad_Ring.v
-verilog work ../../../../../ip/mrisc/rtl/gen/syn/mrisc.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-
-
projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
===================================================================
--- projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (revision 56)
+++ projects/Mos6502/ip/T6502/rtl/xml/T6502.xml (revision 57)
@@ -1,16 +1,15 @@
T6502
- Mos6502
+ T6502
+
+
+
+ T6502_alu_logic
+ T6502_alu_logic
+
+
-
-
- T6502
-
-
-
-
-
io_module
@@ -42,18 +41,7 @@
logic
-
- flash_memcontrl
- flash_memcontrl
- logic
-
-
- disp_io
- disp_io
- logic
-
-
@@ -95,60 +83,167 @@
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
-
- cde_pad_se_dig
- cde_pads
- cde
-
+
+
+ inst_2_test
+
+
+ io_irq_2
+
+
+ io_poll_2
+
+
+ irq_2_test
+
+
+ kim_2
+
+
+ tim_2
+
+
+
+
+
+
+ Nexys2_io_irq_2
+ Nexys2
+
- cde_clock_sys
- cde_clock_sys
- cde
+ disp_io
+ disp_io
+ logic
-
- cde_jtag
- cde_jtag
- cde
+ flash_memcontrl
+ flash_memcontrl
+ logic
-
- cde_jtag_rpc_reg
- cde_jtag
- cde
+ usb_epp
+ usb_epp
+ logic
-
+
-
-
-
- Nexys2_io_irq_2
- Nexys2
Nexys2_io_poll_2
Nexys2
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
Nexys2_irq_2_test
Nexys2
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
Nexys2_kim_2
Nexys2
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
Nexys2_tim_2
Nexys2
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
+
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
/projects/Mos6502/ip/T6502/rtl/variants/T6502/defines.v
1,4 → 1,3
`define VARIANT T6502 |
|
`define CPU _cpu |
`define CONTROL _control |
8,7 → 7,7
`define STATE_FSM _state_fsm |
`define SEQUENCER _sequencer |
|
`define CDE cde |
|
`define SRAM _sram |
`define LIFO _lifo |
|
/projects/Mos6502/ip/T6502/rtl/verilog/alu_logic.v
File deleted
/projects/Mos6502/ip/T6502/sim/run/kim_2/filelist
File deleted
/projects/Mos6502/ip/T6502/sim/run/kim_2/filelist.cov
File deleted
\ No newline at end of file
projects/Mos6502/ip/T6502/sim/run/kim_2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/kim_2/modellist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/kim_2/modellist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/kim_2/modellist (revision 57)
@@ -6,3 +6,4 @@
`include "../../bench/verilog/models/mt45w8mw12.v"
+`include "../../../../../children/logic/ip/flash_memcontrl/rtl/gen/sim/flash_memcontrl.v"
\ No newline at end of file
/projects/Mos6502/ip/T6502/sim/run/io_irq_2/filelist
File deleted
projects/Mos6502/ip/T6502/sim/run/io_irq_2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/tim_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/tim_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/tim_2/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/sim/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
-
-
-
projects/Mos6502/ip/T6502/sim/run/tim_2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/tim_2/filelist.cov
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/tim_2/filelist.cov (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/tim_2/filelist.cov (nonexistent)
@@ -1,7 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
projects/Mos6502/ip/T6502/sim/run/tim_2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/sim/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
-
-
-
Index: projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist.cov
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist.cov (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist.cov (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
-
-
projects/Mos6502/ip/T6502/sim/run/irq_2_test/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/alu_logic_test/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/alu_logic_test/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/alu_logic_test/filelist (nonexistent)
@@ -1,6 +0,0 @@
-`include "../../../rtl/gen/sim/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
\ No newline at end of file
Index: projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/sim/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
-
-
-
Index: projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist.cov
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist.cov (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist.cov (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
-
-
projects/Mos6502/ip/T6502/sim/run/inst_2_test/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/sim/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
-
-
-
Index: projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist.cov
===================================================================
--- projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist.cov (revision 56)
+++ projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist.cov (nonexistent)
@@ -1,7 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
projects/Mos6502/ip/T6502/sim/run/io_poll_2/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502/filelist (nonexistent)
@@ -1,9 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-
-
-
projects/Mos6502/ip/T6502/sim/cov/T6502/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist
===================================================================
--- projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/sim/cov/T6502_alu_logic/filelist (nonexistent)
@@ -1,6 +0,0 @@
-`include "../../../rtl/gen/syn/T6502.v"
-`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
-`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
-`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
\ No newline at end of file
Index: projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist (nonexistent)
@@ -1,26 +0,0 @@
-verilog work ./target/Pad_Ring.v
-verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
-verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-
-
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-
-
-
projects/Mos6502/ip/T6502/syn/Nexys2_tim_2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/filelist (nonexistent)
@@ -1,28 +0,0 @@
-verilog work ./target/Pad_Ring.v
-
-verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
-
-verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-
-
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-
-
-
projects/Mos6502/ip/T6502/syn/Nexys2_irq_2_test/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/filelist (nonexistent)
@@ -1,28 +0,0 @@
-verilog work ./target/Pad_Ring.v
-
-verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
-
-verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-
-
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-
-
-
projects/Mos6502/ip/T6502/syn/Nexys2_io_poll_2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/filelist (nonexistent)
@@ -1,28 +0,0 @@
-verilog work ./target/Pad_Ring.v
-
-verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
-
-verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-
-
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-
-
-
projects/Mos6502/ip/T6502/syn/Nexys2_kim_2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/filelist
===================================================================
--- projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/filelist (revision 56)
+++ projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/filelist (nonexistent)
@@ -1,27 +0,0 @@
-verilog work ./target/Pad_Ring.v
-verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v
-verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
-verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v
-
-
-verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v
-verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v
-verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v
-verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v
-verilog work ../../../../../children/logic/ip/flash_memcontrl/rtl/gen/syn/flash_memcontrl.v
-
-
-verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
-verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
-verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
-verilog work ./target/lib/syn/cde_sram/cde_sram.v
-verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
-verilog work ./target/lib/syn/cde_lifo/cde_lifo.v
-verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
-verilog work ./target/lib/syn/cde_divider/cde_divider.v
-verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
-verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
-
-
-
projects/Mos6502/ip/T6502/syn/Nexys2_io_irq_2/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/rtl/xml/T6502_alu_logic.xml
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/rtl/xml/T6502_alu_logic.xml (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/rtl/xml/T6502_alu_logic.xml (revision 57)
@@ -0,0 +1,16 @@
+
+
+ T6502_alu_logic
+ T6502_alu_logic
+
+
+
+
+ alu_logic_test
+
+
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/rtl/variants/T6502_alu_logic/defines.v
===================================================================
Index: projects/Mos6502/ip/T6502_alu_logic/rtl/verilog/top.v
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/rtl/verilog/top.v (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/rtl/verilog/top.v (revision 57)
@@ -0,0 +1,73 @@
+
+`include "defines.v"
+
+module
+`VARIANT
+
+(
+
+
+
+input wire [7:0] alu_op_a,
+input wire [7:0] alu_op_b,
+input wire alu_op_c,
+
+input wire alu_op_b_inv,
+
+
+output reg [7:0] result,
+output reg r_result,
+output reg c_result,
+output reg v_result,
+
+output reg [7:0] and_out,
+output reg [7:0] orr_out,
+output reg [7:0] eor_out,
+
+
+output reg [8:0] a_sh_left,
+output reg [8:0] a_sh_right,
+output reg [8:0] b_sh_left,
+output reg [8:0] b_sh_right
+
+
+
+);
+
+
+reg [8:0] alu_op_b_mod;
+
+always@(*)
+ begin
+ alu_op_b_mod = alu_op_b_inv ? ~alu_op_b : alu_op_b;
+ end
+
+
+always@(*)
+ begin
+
+ c_result = alu_op_b_inv ? !r_result : r_result;
+ v_result = ((alu_op_a[7] == alu_op_b[7]) && (alu_op_a[7] != result[7]));
+ end
+
+
+
+always @ (*)
+ begin
+ {r_result,result[7:0]} = alu_op_a + alu_op_b_mod + alu_op_c;
+ end
+
+
+always @ (*)
+ begin
+ a_sh_left = {alu_op_a, alu_op_c};
+ a_sh_right = {alu_op_a[0],alu_op_c, alu_op_a[7:1]};
+ b_sh_left = {alu_op_b, alu_op_c};
+ b_sh_right = {alu_op_b[0],alu_op_c, alu_op_b[7:1]};
+ and_out = alu_op_a & alu_op_b;
+ orr_out = alu_op_a | alu_op_b;
+ eor_out = alu_op_a ^ alu_op_b;
+ end
+
+
+endmodule
Index: projects/Mos6502/ip/T6502_alu_logic/doc/spec.odt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: projects/Mos6502/ip/T6502_alu_logic/doc/spec.odt
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/spec.odt (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/spec.odt (revision 57)
projects/Mos6502/ip/T6502_alu_logic/doc/spec.odt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/doc/geda/drawing/filelist
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/geda/drawing/filelist (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/geda/drawing/filelist (revision 57)
@@ -0,0 +1,14 @@
+`include "../../../rtl/gen/syn/T6502.v"
+`include "../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v"
+`include "../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v"
+`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v"
+
+`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
+`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v"
+
+`include "../../../../../../../../socgen/lib/cde_sram/cde_sram.v"
+`include "../../../../../../../../socgen/lib/cde_serial_xmit/cde_serial_xmit.v"
+`include "../../../../../../../../socgen/lib/cde_serial_rcvr/cde_serial_rcvr.v"
+`include "../../../../../../../../socgen/lib/cde_synchronizers/cde_sync_with_hysteresis.v"
+`include "../../../../../../../../socgen/lib/cde_fifo/cde_fifo.v"
+`include "../../../../../../../../socgen/lib/cde_divider/cde_divider.v"
\ No newline at end of file
projects/Mos6502/ip/T6502_alu_logic/doc/geda/drawing/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/doc/T6502_doc.txt
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/T6502_doc.txt (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/T6502_doc.txt (revision 57)
@@ -0,0 +1,1689 @@
+T6502 Embedded Microprocessor
+==================================================================================
+
+The T6502 IP is a processor that uses most of MosTechnology M6502 processor instructions
+and processor registers.It has been updated for a synthesized embedded design in a FGPA or ASIC.
+
+
+It differs from the original Mos6502 in the following ways
+
+
+
+1) Changed memory interface from asynchronous to synchronous.
+
+2) Number of clock cycles to execute instructions has changed
+
+3) Page Zero is fully filled with SRAM. Page zero is not usable as I/O space
+
+
+
+
+
+
+
+
+An extended version is also avaiable. Before we can extend we must first remove some features that either
+did not make sense at the time or made only made sense for a 40 pin part sitting in a sea or ttl parts.
+
+
+
+1) Remove Binary Coded Decimal mode. The D bit in the PSR does nothing.
+
+2) Moved stack from Page 01 into a seperate RAM. Stack size is now parameterized and only accessable via
+ pushes and pulls.Removed the TSX and TXS commands. If you need to manipulate the stack pointer and stack
+ data then you really should get a more powerfull processor
+
+3) Replaced old interrupt/brk system with vectored interrupt. Masking is done externally and vectors provide
+ as many interrupts as you like. PSR is not pushed on interrupt and rts/rti become one instruction
+
+4) Indirect addresses stored in page 00 MUST be aligned on even addresses. This is done by shifting a
+ page zero indirect address bu one bit and using both page 00 and 01.
+
+5) Bit (5) of the PSR is now a run bit. Forcing it to 0 will halt the processor until the next reset/interrupt
+
+6) Added Debugging logic and error checking
+
+7) self modifying code is no longer supported. You must provide a single rom image with all executable code
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+History
+=========================================================================================
+
+
+
+
+This component is derived from the opencores t6507lp project.
+
+The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini
+was a atari 2600 on a chip. This takes the t6507 portion and turns it into a fully functional updated 6502.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Processor Model
+===============================================================================================
+
+ +----------+
+ | Acc | Accumulator (A)
+ +----------+
+ | X | X Index Register (X)
+ +----------+
+ | Y | Y Index Register (Y)
+ +----------+----------+
+ | PCH | PCL | Program Counter (PC)
+ +----------+----------+
+ | 00000001 | SP | Stack Pointer (SP)
+ +----------+----------+
+ | P | Processor Status Word (P)
+ +----------+
+ NV1BDIZC
+ |||||||+---- Carry Flag 1 = True
+ ||||||+----- Zero Flag 1 = Result == 8'h00
+ |||||+------ IRQ Disable 1 = Disable
+ ||||+------- Decimal Mode Not used
+ |||+-------- Break Command 1 = In break routine
+ ||+--------- Run Mode 1 = Processor is running
+ |+---------- Overflow Flag 1 = True
+ +----------- Negative 1 = Negative Number
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Memory Model
+===============================================================================================
+
+0000-00FF | Page Zero RAM
+0010-01FF | Stack RAM
+0200-FFF9 | Program and Data RAM
+ FFFA | NMI Vector Low
+ FFFB | NMI Vector High
+ FFFC | Boot Vector Low
+ FFFD | Boot Vector High
+ FFFE | IRQ/BRK Vector Low
+ FFFF | IRQ/BRK Vector High
+
+
+
+
+
+
+
+
+
+Definitions
+===============================================================================================
+Opcode Current Instruction byte
+New_opcode Next Instruction byte
+Opc_Add Address of current instruction
+Next_Op_Add Address of next instruction byte
+Operand Data operand
+Address Address of data operand if in memory
+Offset Value added to Opc_Add if branch is taken
+Pointer Address to store the address of data opeand if in memory
+Vector Address to store the Next_Op_Add
+
+
+
+
+
+
+
+
+
+Instruction Set
+===============================================================================================
+
+Inst Description Effect on flags
+-----------------------------------------------------------------------------------------------
+ADC Operand Add Acc to Operand with Carry NZCV
+SBC Operand Subract Operand from Acc with Borrow NZXV
+AND Operand Logical AND Acc and Operand NZ
+CMP Operand Compare Acc with Operand NZC
+CPX Operand Compare X_index with Operand NZC
+CPY Operand Compare Y_index with Operand NZC
+EOR Operand Exclusive Or Acc with Operand NZ
+LDA Operand Load Operand into Acc NZ
+LDX Operand Load Operand into X_index NZ
+LDY Operand Load Operand into Y_index NZ
+ORA Operand Logical Or Acc with Operand NZ
+BIT Operand Bit Test Acc with operand Z67
+STA Address Store Acc @ address NONE
+STX Address Store X_Index @ address NONE
+STY Address Store Y_Index @ address NONE
+ASL Operand Arithmetic Shift Left Operand into Carry NZC
+DEC Operand Decrement Operand NZ
+INC Operand Incremement Operand NZ
+DEX Decrement X Index NZ
+INX Incremement X Index NZ
+DEY Decrement Y Index NZ
+INY Incremement Y Index NZ
+LSR Operand Logical Shift Right Operand into Carry NZC
+ROL Operand Rotate Left Operand thru Carry NZC
+ROR Operand Rotate Right Operand thru Carry NZC
+NOP No Operation NONE
+SEC Set Carry Flag 1 -> C
+SED Set Decimal Flag 1 -> D
+SEI Set Interrupt Flag 1 -> I
+CLC Clear Carry Flag 0 -> C
+CLD Clear Decimal Flag 0 -> D
+CLI Clear Interrupt Flag 0 -> I
+CLV Clear Overflow Flag 0 -> V
+TAX Transfer Acc into X_Index NZ
+TAY Transfer Acc into Y_Index NZ
+TXA Transfer X_Index into Acc NZ
+TYA Transfer Y_Index into Acc NZ
+BCC Offset Branch if C == 0 NONE
+BCS Offset Branch if C == 1 NONE
+BNE Offset Branch if Z == 0 NONE
+BEQ Offset Branch if Z == 1 NONE
+BVC Offset Branch if V == 0 NONE
+BVS Offset Branch if V == 1 NONE
+BPL Offset Branch if N == 0 NONE
+BMI Offset Branch if N == 1 NONE
+PLA Pull Acc from Stack NZ
+PLP Pull PSR from Stack RESTORE
+PHA Push Acc onto Stack NONE
+PHP Push PSR onto Stack NONE
+JMP Next_Op_Add Jump to New Address NONE
+JMP Vector Jump to New Address found by vector NONE
+JSR Next_Op_Add Save PC+2 on stack and jump to New Address NONE
+BRK Save status and PC+1 on stack and jump to New Address set 1 -> B
+RTI Pull Status and PC from stack RESTORED
+RTS Pull PC from stack NONE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Definitions
+===============================================================================================
+Opcode Current Instruction byte
+New_opcode Next Instruction byte
+Opc_Add Address of current instruction
+Next_Op_Add Address of next instruction byte
+Operand Data operand
+Address Address of data operand if in memory
+Offset Value added to Opc_Add if branch is taken
+Pointer Address to store the address of data opeand if in memory
+Vector Address to store the Next_Op_Add
+
+
+
+
+
+
+
+
+
+
+Addressing Modes
+===============================================================================================
+
+
+Immediate Read
+-----------------------------------------------------------------------------------------------------
+Operand is located in memory following the opcode
+
+
+Opcode Operand
+
+
+
+
+Absolute Read/Write/ReadModifyWrite
+-----------------------------------------------------------------------------------------------------
+16 bit address of operand is located in memory following opcode (low byte,high byte)
+
+Opcode Address_l,Address_h
+
+
+
+Absolute Indexed Read/Write/ReadModifyWrite
+-----------------------------------------------------------------------------------------------------
+Operand is found by adding index value to 16 bit address following opcode.(no wraparound)
+
+Opcode Address_l,Address_h
+
+
+
+Page Zero Read/Write/ReadModifyWrite
+-----------------------------------------------------------------------------------------------------
+8 bit page zero address of operand is located in memory following opcode.
+
+
+Opcode Address_l
+
+
+
+Page Zero Indexed Read/Write/ReadModifyWrite
+-----------------------------------------------------------------------------------------------------
+Operand is found in page zero by adding index value to 8 bit address following opcode.(wraps around)
+
+
+Opcode Address_l
+
+
+
+Page Zero Indirect X Read/Write
+-----------------------------------------------------------------------------------------------------
+Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
+the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
+
+Opcode Pointer_l
+
+
+
+
+Page Zero Indirect Y Read/Write
+-----------------------------------------------------------------------------------------------------
+8 bit page zero address containing a 16 bit address is located in memory following opcode. Y index is added to this address
+(no wraparound).
+
+
+Opcode Pointer_l
+
+
+Implied Read/Write/Read_Modify_Write
+-----------------------------------------------------------------------------------------------------
+Operand is specified in the Opcode
+
+Opcode
+
+
+Branch Read
+-----------------------------------------------------------------------------------------------------
+Opcode is followed by the relative offset for the branch
+
+Opcode Offset
+
+
+Stack StackRead/StackWrite
+-----------------------------------------------------------------------------------------------------
+Operation uses the Stack
+
+Opcode
+
+
+Stack_Pointer
+-----------------------------------------------------------------------------------------------------
+Transfer between Stack_pointer and X index
+
+Opcode
+
+
+Jump Absolute Read
+-----------------------------------------------------------------------------------------------------
+16 bit destination address follows opcode
+
+
+Opcode Next_Op_add_l,Next_Op_add_h
+
+
+
+Jump Indirect Read
+-----------------------------------------------------------------------------------------------------
+16 bit Address following opcode points to destination address
+
+Opcode Vector_l, Vector_h
+
+
+JumpSub Absolute Read_Stackwrite
+-----------------------------------------------------------------------------------------------------
+16 bit destination address follows opcode. Return address is pushed on stack
+
+Opcode Next_Op_add_l,Next_Op_add_h
+
+
+Break Read_Stackwrite
+-----------------------------------------------------------------------------------------------------
+Return address is pushed on stack and the IRQ vector is taken
+
+Opcode
+
+
+Return from Interrupt Read_Stackread
+-----------------------------------------------------------------------------------------------------
+PSR and Prog_counter are pulled from stack
+
+
+Opcode
+
+
+
+
+
+Return from Subroutine Read_Stackread
+-----------------------------------------------------------------------------------------------------
+Prog_counter is pulled from stack
+
+
+Opcode
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Instruction Opcodes (hex)
+====================================================================================================
+
+
+
+ ADC abs 6D
+ ADC abs,X 7D
+ ADC abs,Y 79
+ ADC #n 69
+ ADC zp 65
+ ADC (zp,X) 61
+ ADC zp,X 75
+ ADC (zp),Y 71
+
+ AND abs 2D
+ AND abs,X 3D
+ AND abs,Y 39
+ AND #n 29
+ AND zp 25
+ AND (zp,X) 21
+ AND zp,X 35
+ AND (zp),Y 31
+
+ ASL A 0A
+ ASL abs 0E
+ ASL abs,X 1E
+ ASL zp 06
+ ASL zp,X 16
+
+ BCC rel 90
+ BCS rel B0
+ BEQ rel F0
+
+ BIT abs 2C
+ BIT zp 24
+
+ BMI rel 30
+ BNE rel D0
+ BPL rel 10
+
+ BRK 00
+
+ BVC rel 50
+ BVS rel 70
+
+
+ CLC 18
+ CLD D8
+ CLI 58
+ CLV B8
+
+ CMP abs CD
+ CMP abs,X DD
+ CMP abs,Y D9
+ CMP #n C9
+ CMP zp C5
+ CMP (zp,X) C1
+ CMP zp,X D5
+ CMP (zp),Y D1
+
+ CPX abs EC
+ CPX #n E0
+ CPX zp E4
+ CPY abs CC
+ CPY #n C0
+ CPY zp C4
+
+ DEC abs CE
+ DEC abs,X DE
+ DEC zp C6
+ DEC zp,X D6
+
+ DEX CA
+ DEY 88
+
+ EOR abs 4D
+ EOR abs,X 5D
+ EOR abs,Y 59
+ EOR #n 49
+ EOR zp 45
+ EOR (zp,X) 41
+ EOR zp,X 55
+ EOR (zp),Y 51
+
+ INC abs EE
+ INC abs,X FE
+ INC zp E6
+ INC zp,X F6
+ INX E8
+ INY C8
+
+ JMP abs 4C
+ JMP (abs) 6C
+ JSR abs 20
+
+ LDA abs AD
+ LDA abs,X BD
+ LDA abs,Y B9
+ LDA #n A9
+ LDA zp A5
+ LDA (zp,X) A1
+ LDA zp,X B5
+ LDA (zp),Y B1
+
+ LDX abs AE
+ LDX abs,Y BE
+ LDX #n A2
+ LDX zp A6
+ LDX zp,Y B6
+
+ LDY abs AC
+ LDY abs,X BC
+ LDY #n A0
+ LDY zp A4
+ LDY zp,X B4
+
+ LSR A 4A
+ LSR abs 4E
+ LSR abs,X 5E
+ LSR zp 46
+ LSR zp,X 56
+
+ NOP EA
+
+ ORA abs 0D
+ ORA abs,X 1D
+ ORA abs,Y 19
+ ORA #n 09
+ ORA zp 05
+ ORA (zp,X) 01
+ ORA zp,X 15
+ ORA (zp),Y 11
+
+ PHA 48
+ PHP 08
+
+ PLA 68
+ PLP 28
+
+ ROL A 2A
+ ROL abs 2E
+ ROL abs,X 3E
+ ROL zp 26
+ ROL zp,X 36
+
+ ROR A 6A
+ ROR abs 6E
+ ROR abs,X 7E
+ ROR zp 66
+ ROR zp,X 76
+
+ RTI 40
+
+ RTS 60
+
+ SBC abs ED
+ SBC abs,X FD
+ SBC abs,Y F9
+ SBC #n E9
+ SBC zp E5
+ SBC (zp,X) E1
+ SBC zp,X F5
+ SBC (zp),Y F1
+
+ SEC 38
+ SED F8
+ SEI 78
+
+ STA abs 8D
+ STA abs,X 9D
+ STA abs,Y 99
+ STA zp 85
+ STA (zp,X) 81
+ STA zp,X 95
+ STA (zp),Y 91
+
+ STX abs 8E
+ STX zp 86
+ STX zpy 96
+
+ STY abs 8C
+ STY zp 84
+ STY zp,X 94
+
+ TAX AA
+ TAY A8
+ TXA 8A
+ TYA 98
+
+
+
+
+
+
+
+
+
+Instruction Decode
+======================================================================================================================================================
+
+
+
+
+
+
+
+
+
+
+// alu_mode
+`define alu_mode_add 3'b000
+`define alu_mode_and 3'b001
+`define alu_mode_orr 3'b010
+`define alu_mode_eor 3'b011
+`define alu_mode_sfl 3'b100
+`define alu_mode_sfr 3'b101
+`define alu_mode_afl 3'b110
+`define alu_mode_afr 3'b111
+
+// alu_op_a_sel
+
+`define alu_op_a_00 3'b000
+`define alu_op_a_acc 3'b001
+`define alu_op_a_x 3'b010
+`define alu_op_a_y 3'b011
+`define alu_op_a_ff 3'b100
+`define alu_op_a_psr 3'b101
+
+// alu_op_b_sel
+
+`define alu_op_b_00 2'b00
+`define alu_op_b_prog 2'b01
+`define alu_op_b_sp 2'b10
+`define alu_op_b_temp 2'b11
+
+// alu_op_b_inv 1=invert
+
+
+
+// alu_op_c_sel
+
+`define alu_op_c_00 2'b00
+`define alu_op_c_01 2'b01
+`define alu_op_c_cin 2'b10
+`define alu_op_c_xx 2'b11
+
+
+// alu_status_update
+`define alu_status_update_none 3'b000
+`define alu_status_update_nz 3'b001
+`define alu_status_update_nzc 3'b010
+`define alu_status_update_nzcv 3'b011
+`define alu_status_update_wr 3'b100
+`define alu_status_update_z67 3'b101
+`define alu_status_update_res 3'b110
+
+
+
+// dest
+`define dest_none 3'b000
+`define dest_alu_a 3'b001
+`define dest_alu_x 3'b010
+`define dest_alu_y 3'b011
+`define dest_mem 3'b100
+
+
+// ctrl
+`define ctrl_none 3'b000
+`define ctrl_jsr 3'b001
+`define ctrl_jmp 3'b010
+`define ctrl_jmp_ind 3'b011
+`define ctrl_brk 3'b100
+`define ctrl_rti 3'b101
+`define ctrl_rts 3'b110
+`define ctrl_branch 3'b111
+
+// cmd
+`define cmd_none 2'b00
+`define cmd_push_psr 2'b01
+`define cmd_push_pc 2'b10
+`define cmd_load_vec 2'b11
+
+
+// ins_type
+`define ins_type_none 2'b00
+`define ins_type_read 2'b01
+`define ins_type_write 2'b10
+`define ins_type_rmw 2'b11
+
+
+// idx_sel
+`define idx_sel_00 2'b00
+`define idx_sel_x 2'b01
+`define idx_sel_y 2'b10
+
+
+
+// branch_value
+
+
+// branch_enable
+
+
+
+
+
+
+
+
+
+
+Immediate
+
+ alu alu alu alu alu
+ op_a op_b op_b op_c status alu ins idx branch branch
+ src src inv src update mode type sel value enable dest ctrl cmd
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC #n | | alu_a prog 0 cin NZCV ADD R 0 00 00 A none none
+ AND #n | | alu_a prog 0 0 NZ AND R 0 00 00 A none none
+ CMP #n | | alu_a prog 1 1 NZC ADD R 0 00 00 0 none none
+ CPX #n | | alu_x prog 1 1 NZC ADD R 0 00 00 0 none none
+ CPY #n | | alu_y prog 1 1 NZC ADD R 0 00 00 0 none none
+ EOR #n | | alu_a prog 0 0 NZ EOR R 0 00 00 A none none
+ LDA #n | | 00 prog 0 0 NZ ADD R 0 00 00 A none none
+ LDX #n | | 00 prog 0 0 NZ ADD R 0 00 00 X none none
+ LDY #n | | 00 prog 0 0 NZ ADD R 0 00 00 Y none none
+ ORA #n | | alu_a prog 0 0 NZ ORR R 0 00 00 A none none
+ SBC #n | | alu_a prog 1 cin NZXV ADD R 0 00 00 A none none
+
+
+
+
+Absolute
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC abs | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
+ AND abs | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
+ BIT abs | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
+ CMP abs | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
+ CPX abs | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
+ CPY abs | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
+ EOR abs | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
+ LDA abs | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
+ LDX abs | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
+ LDY abs | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
+ ORA abs | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
+ SBC abs | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
+ STA abs | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
+ STX abs | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
+ STY abs | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
+ ASL abs | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
+ DEC abs | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
+ INC abs | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
+ LSR abs | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
+ ROL abs | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
+ ROR abs | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
+
+
+Absolute indexed
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC abs,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
+ AND abs,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
+ CMP abs,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
+ EOR abs,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
+ LDA abs,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
+ LDY abs,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
+ ORA abs,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
+ SBC abs,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
+ ADC abs,Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
+ AND abs,Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
+ CMP abs,Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
+ EOR abs,Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
+ LDA abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
+ LDX abs,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
+ ORA abs,Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
+ SBC abs,Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
+ STA abs,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
+ STA abs,Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
+ ASL abs,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
+ DEC abs,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
+ INC abs,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
+ LSR abs,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
+ ROL abs,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
+ ROR abs,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
+
+
+
+
+
+
+Page Zero
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC zp | | alu_a temp 0 cin NZCV ADD R 0 00 00 A none none
+ AND zp | | alu_a temp 0 0 NZ AND R 0 00 00 A none none
+ BIT zp | | alu_a temp 0 0 Z67 AND R 0 00 00 0 none none
+ CMP zp | | alu_a temp 1 1 NZC ADD R 0 00 00 0 none none
+ CPX zp | | alu_x temp 1 1 NZC ADD R 0 00 00 0 none none
+ CPY zp | | alu_y temp 1 1 NZC ADD R 0 00 00 0 none none
+ EOR zp | | alu_a temp 0 0 NZ EOR R 0 00 00 A none none
+ LDA zp | | 00 temp 0 0 NZ ADD R 0 00 00 A none none
+ LDX zp | | 00 temp 0 0 NZ ADD R 0 00 00 X none none
+ LDY zp | | 00 temp 0 0 NZ ADD R 0 00 00 Y none none
+ ORA zp | | alu_a temp 0 0 NZ ORR R 0 00 00 A none none
+ SBC zp | | alu_a temp 1 cin NZXV ADD R 0 00 00 A none none
+ STA zp | | alu_a temp 0 0 NONE ADD W 0 00 00 M none none
+ STX zp | | alu_x temp 0 0 NONE ADD W 0 00 00 M none none
+ STY zp | | alu_y temp 0 0 NONE ADD W 0 00 00 M none none
+ ASL zp | | 00 temp 0 0 NZC SFL RMW 0 00 00 M none none
+ DEC zp | | FF temp 0 0 NZ ADD RMW 0 00 00 M none none
+ INC zp | | 00 temp 0 1 NZ ADD RMW 0 00 00 M none none
+ LSR zp | | 00 temp 0 0 NZC SFR RMW 0 00 00 M none none
+ ROL zp | | 00 temp 0 cin NZC SFL RMW 0 00 00 M none none
+ ROR zp | | 00 temp 0 cin NZC SFR RMW 0 00 00 M none none
+
+
+
+Page Zero indexed
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC zp,X | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
+ AND zp,X | | alu_a temp 0 0 NZ AND R X 00 00 A none none
+ CMP zp,X | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
+ EOR zp,X | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
+ LDA zp,X | | 00 temp 0 0 NZ ADD R X 00 00 A none none
+ LDY zp,X | | 00 temp 0 0 NZ ADD R X 00 00 Y none none
+ ORA zp,X | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
+ SBC zp,X | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
+ LDX zp,Y | | 00 temp 0 0 NZ ADD R Y 00 00 X none none
+ STA zp,X | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
+ STY zp,X | | alu_y temp 0 0 NONE ADD W X 00 00 M none none
+ STX zp,Y | | alu_x temp 0 0 NONE ADD W Y 00 00 M none none
+ ASL zp,X | | 00 temp 0 0 NZC SFL RMW X 00 00 M none none
+ DEC zp,X | | FF temp 0 0 NZ ADD RMW X 00 00 M none none
+ INC zp,X | | 00 temp 0 1 NZ ADD RMW X 00 00 M none none
+ LSR zp,X | | 00 temp 0 0 NZC SFR RMW X 00 00 M none none
+ ROR zp,X | | 00 temp 0 cin NZC SFR RMW X 00 00 M none none
+ ROL zp,X | | 00 temp 0 cin NZC SFL RMW X 00 00 M none none
+
+
+
+Page Zero indirectX
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC (zp,X) | | alu_a temp 0 cin NZCV ADD R X 00 00 A none none
+ AND (zp,X) | | alu_a temp 0 0 NZ AND R X 00 00 A none none
+ CMP (zp,X) | | alu_a temp 1 1 NZC ADD R X 00 00 0 none none
+ EOR (zp,X) | | alu_a temp 0 0 NZ EOR R X 00 00 A none none
+ LDA (zp,X) | | 00 temp 0 0 NZ ADD R X 00 00 A none none
+ ORA (zp,X) | | alu_a temp 0 0 NZ ORR R X 00 00 A none none
+ SBC (zp,X) | | alu_a temp 1 cin NZXV ADD R X 00 00 A none none
+ STA (zp,X) | | alu_a temp 0 0 NONE ADD W X 00 00 M none none
+
+
+
+======================================================================================================================================================
+
+
+Page Zero IndirectY
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ ADC (zp),Y | | alu_a temp 0 cin NZCV ADD R Y 00 00 A none none
+ AND (zp),Y | | alu_a temp 0 0 NZ AND R Y 00 00 A none none
+ CMP (zp),Y | | alu_a temp 1 1 NZC ADD R Y 00 00 0 none none
+ EOR (zp),Y | | alu_a temp 0 0 NZ EOR R Y 00 00 A none none
+ LDA (zp),Y | | 00 temp 0 0 NZ ADD R Y 00 00 A none none
+ ORA (zp),Y | | alu_a temp 0 0 NZ ORR R Y 00 00 A none none
+ SBC (zp),Y | | alu_a temp 1 cin NZXV ADD R Y 00 00 A none none
+ STA (zp),Y | | alu_a temp 0 0 NONE ADD W Y 00 00 M none none
+
+
+
+
+
+Implied
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ NOP | | 00 00 0 0 NONE ADD 0 0 00 00 0 none none
+ SEC | | 00 00 0 0 WR ADD 0 0 01 01 0 none none
+ SED | | 00 00 0 0 WR ADD 0 0 08 08 0 none none
+ SEI | | 00 00 0 0 WR ADD 0 0 04 04 0 none none
+ CLC | | 00 00 0 0 WR ADD 0 0 00 01 0 none none
+ CLD | | 00 00 0 0 WR ADD 0 0 00 08 0 none none
+ CLI | | 00 00 0 0 WR ADD 0 0 00 04 0 none none
+ CLV | | 00 00 0 0 WR ADD 0 0 00 40 0 none none
+ ASL A | | alu_a 00 0 0 NZC SFL RMW 0 00 00 A none none
+ DEX | | alu_x 00 0 0 NZ ADD RMW 0 00 00 X none none
+ DEY | | alu_y 00 0 0 NZ ADD RMW 0 00 00 Y none none
+ INX | | alu_x 00 0 1 NZ ADD RMW 0 00 00 X none none
+ INY | | alu_y 00 0 1 NZ ADD RMW 0 00 00 Y none none
+ LSR A | | alu_a 00 0 0 NZC SFR RMW 0 00 00 A none none
+ ROL A | | alu_a 00 0 cin NZC SFL RMW 0 00 00 A none none
+ ROR A | | alu_a 00 0 cin NZC SFR RMW 0 00 00 A none none
+ TAX | | alu_a 00 0 0 NZ ADD RMW 0 00 00 A none none
+ TAY | | alu_a 00 0 0 NZ ADD RMW 0 00 00 X none none
+ TXA | | alu_x 00 0 0 NZ ADD RMW 0 00 00 A none none
+ TYA | | alu_y 00 0 0 NZ ADD RMW 0 00 00 A none none
+
+
+
+Branch
+ alu alu alu alu alu
+ op_a op_b op_b op_c status alu branch branch
+ src src inv src update mode type index value enable dest
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ BCC rel | | 00 00 0 0 NONE ADD 0 0 00 01 0 branch none
+ BCS rel | | 00 00 0 0 NONE ADD 0 0 01 01 0 branch none
+ BNE rel | | 00 00 0 0 NONE ADD 0 0 00 02 0 branch none
+ BEQ rel | | 00 00 0 0 NONE ADD 0 0 02 02 0 branch none
+ BVC rel | | 00 00 0 0 NONE ADD 0 0 00 40 0 branch none
+ BVS rel | | 00 00 0 0 NONE ADD 0 0 40 40 0 branch none
+ BPL rel | | 00 00 0 0 NONE ADD 0 0 00 80 0 branch none
+ BMI rel | | 00 00 0 0 NONE ADD 0 0 80 80 0 branch none
+
+
+
+Stack
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ PLA | | 00 00 0 0 NZ ADD R 0 00 00 A
+ PLP | | 00 00 0 0 RESTORE ADD R 0 00 00 PSR
+ PHA | | alu_a 00 0 0 NONE ADD W 0 00 00 M
+ PHP | | psr 00 0 0 NONE ADD W 0 00 00 M
+
+
+
+Jump absolute
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ JMP abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
+
+
+
+Jump indirect
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ JMP (abs) | | 00 00 0 0 NONE ADD 0 0 00 00 0
+
+
+
+Jump Sub absolute
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ JSR abs | | 00 00 0 0 NONE ADD 0 0 00 00 0
+
+
+
+Break
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ BRK | | alu_a 00 0 0 WR ADD 0 0 10 10 0
+
+
+
+Return from
+Interrupt
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ RTI | | 00 00 0 0 RESTORE ADD 0 0 00 00 P
+
+
+
+Return from
+Subroutine
+------------------------------------------------------------------------------------------------------------------------------------------------------
+ RTS | | 00 00 0 0 NONE ADD 0 0 00 00 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Opcode Current Instruction byte
+New_opcode Next Instruction byte
+Opc_Add Address of current instruction
+Next_Op_Add Address of next instruction byte
+Operand Data operand
+Address Address of data operand if in memory
+Offset Value added to Opc_Add if branch is taken
+Pointer Address to store the address of data opeand if in memory
+Vector Address to store the Next_Op_Add
+
+
+
+
+
+
+
+
+
+Address Sequence Decodes
+=========================================================================
+
+
+
+
+
+
+Implied Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+______________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add Opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 Opcode 1 Set
+3 1 Opc_Add+1 New_Opcode opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 New_Opcode updated
+
+
+
+
+Immediate Addressing Mode
+
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+____________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+----------------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 operand operand Set
+----------------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 operand 1 Set
+5 1 Opc_Add+2 new_op opcode 1 Set
+----------------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op updated
+
+
+
+
+
+
+
+Absolute Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi Set
+5 1 Opc_Add+3 new_op addr r 00 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op addr r 00 operand Set
+7 1 Opc_Add+3 new_op addr r 00 operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op 1 Set
+9 1 Opc_Add+3 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+
+
+
+Absolute Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi Set
+5 1 Opc_Add+3 new_op opcode addr w operand 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+4 new_op updated
+7 1 Opc_Add+4
+
+
+
+
+
+Absolute Read/Modify/Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi Set
+5 1 Opc_Add+3 new_op addr r Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op operand Set
+7 1 Opc_Add+3 new_op Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op addr w result 1 Set
+9 1 Opc_Add+3 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+
+
+
+
+Absolute Indexed Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi Set
+5 1 Opc_Add+3 new_op addr+i r 00 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op addr+i r 00 operand Set
+7 1 Opc_Add+3 new_op addr+i r 00 operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op 1 Set
+9 1 Opc_Add+3 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+Absolute Indexed Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi 1 Set
+5 1 Opc_Add+3 new_op opcode addr+i w operand 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+4 new_op updated
+7 1 Opc_Add+4
+
+
+
+
+
+Absolute Indexed Read/Modify/Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+2 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+3 add_hi add_hi Set
+5 1 Opc_Add+3 new_op addr+i r Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op operand Set
+7 1 Opc_Add+3 new_op Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op addr+i w result 1 Set
+9 1 Opc_Add+3 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+
+
+
+
+
+
+
+
+
+Page Zero Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr r Set
+5 1 Opc_Add+2 new_op operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op 1 Set
+7 1 Opc_Add+2 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op updated
+
+
+
+
+
+
+
+
+Page Zero Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo 1 Set
+5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op updated
+7 1 Opc_Add+3
+
+
+
+
+
+
+
+Page Zero Read/Modify/Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr r Set
+5 1 Opc_Add+2 new_op operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op 1 Set
+7 1 Opc_Add+2 new_op opcode addr w result 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op updated
+
+
+
+
+
+
+
+
+
+
+Page Zero Indexed Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr+i r Set
+5 1 Opc_Add+2 new_op operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op 1 Set
+7 1 Opc_Add+2 new_op opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op updated
+
+
+
+
+
+Page Zero Indexed Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo 1 Set
+5 1 Opc_Add+2 new_op opcode addr w operand 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+3 new_op updated
+7 1 Opc_Add+3
+
+
+
+
+
+
+
+Page Zero Indexed Read/Modify/Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr r Set
+5 1 Opc_Add+2 new_op operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op 1 Set
+7 1 Opc_Add+2 new_op opcode addr w result 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op updated
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Page Zero Indirect X Read
+-------------------------------------------------------
+Operand address lower byte is read from the address found by adding X index value to 8 bit address following opcode and
+the upper byte is read from the address found by adding X index value to 8 bit address plus 1 (no wraparound)
+
+
+
+
+Page Zero IndirectX Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr+i r Set
+5 1 Opc_Add+2 new_op addr+i+1 r add_l Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op add_h Set
+7 1 Opc_Add+2 new_op addr r Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+2 new_op operand 1 Set
+9 1 opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+
+
+Page Zero IndirectX Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr+i r Set
+5 1 Opc_Add+2 new_op addr+i+1 add_l Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op add_h 1 Set
+7 1 Opc_Add+2 new_op opcode addr w result 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op updated
+9 1
+
+
+
+
+
+
+
+
+
+Page Zero IndirectY Read Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo addr_lo r Set
+5 1 Opc_Add+2 new_op addr Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op addr+i r Set
+7 1 Opc_Add+2 new_op addr+i r operand Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+2 new_op 1 Set
+9 1 opcode 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+10 0 updated
+
+
+
+
+Page Zero IndirectX Write Addressing Mode
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+___________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+--------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 add_lo add_lo Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Opc_Add+2 add_lo add_lo r 1 Set
+5 1 Opc_Add+2 new_op addr 1 Set
+--------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Opc_Add+2 new_op addr+i w result Set
+7 1 Opc_Add+2 new_op opcode Set updated
+--------------------------------------------------------------------------------------------------------------------------------------------
+8 0 Opc_Add+3 new_op
+9 1
+
+
+
+
+
+
+Relative Addressing Mode
+
+
+c e ALU
+l n prog prog prog data memory page zero stack Control Processsor
+k b counter data fetch add rw wdata rdata add rw wdata rdata op rdata wdata execute Signals registers
+____________________________________________________________________________________________________________________________________________________________
+0 0 Opc_Add
+1 1 Opc_Add opcode opcode
+----------------------------------------------------------------------------------------------------------------------------------------------------
+2 0 Opc_Add+1 opcode Set
+3 1 Opc_Add+1 offset offset Set
+----------------------------------------------------------------------------------------------------------------------------------------------------
+4 0 Next_Op_Add offset 1
+5 1 Next_Op_Add new_op opcode 1
+----------------------------------------------------------------------------------------------------------------------------------------------------
+6 0 Next_Op_Add+1 new_op
+
+
+
+
+
+Addressing Modes
+===============================================================================================
+
+
+
+
+
+Stack StackRead/StackWrite
+-------------------------------------------------------
+Operation uses the Stack
+
+
+
+Jump Absolute Read
+-------------------------------------------------------
+16 bit destination address follows opcode
+
+
+Jump Indirect Read
+-------------------------------------------------------
+16 bit Address following opcode points to destination address
+
+
+
+
+Jump Sub Absolute Read_Stackwrite
+-------------------------------------------------------
+16 bit destination address follows opcode. Return address is pushed on stack
+
+
+
+Break Read_Stackwrite
+-------------------------------------------------------
+Return address is pushed on stack and the IRQ vector is taken
+
+
+
+Return from Interrupt Read_Stackread
+-------------------------------------------------------
+PSR and Prog_counter are pulled from stack
+
+
+
+
+Return from Subroutine Read_Stackread
+-------------------------------------------------------
+Prog_counter is pulled from stack
+
+
+
+
+
+
+
+
+
+
+
+
+
+Interrupts
+===============================================================================================
+
+Non-Maskable (NMI)
+
+ 1) Finish current instruction
+ 2) Push Address of next instruction on stack
+ 3) Read Vector Address from FFFA
+ 4) Execute code @ vector address
+
+
+
+Maskable (IRQ) ( if I bit is clear)
+
+ 1) Finish current instruction
+ 2) Push Address of next instruction on stack
+ 3) Push PSR on stack
+ 4) Read Vector Address from FFFE
+ 5) Execute code @ vector address
+
+
+Reset
+
+ 1) Clear A,X,Y: Set PSR to 20h
+ 2) Wait for Reset to deassert
+ 3) Read Vector Address from FFFC
+ 4) Execute code @ vector address
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/doc/Readme.txt
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/Readme.txt (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/Readme.txt (revision 57)
@@ -0,0 +1,57 @@
+
+
+
+
+This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor and uses it as a 6502. It had some documentation and a test suite that was somewhat working.
+
+I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made:
+
+
+
+1) Converted to a full 16 bit address bus.
+
+ also hardcoded the 8 bit data bus. Hasn't changed in thirty five years.
+
+2) Converted parameters to `defines
+
+3) Converted reset to synchronous active high
+
+4) Converted test suite to socgen format
+
+ Each test is in it's own subdirectory and any needed code is assembled and loaded into sram
+
+5) Design had no reset/interrupt vectors. Added reset vector. May add interupt(s) later.
+
+6) Added enable logic so that it could work with synchronous sram
+
+7) Design doesn't appear to be fully functional.
+ CLC followed by BCC missed the offset by one clock cycle.
+ JSR doesn't push high address on stack. puts wrong data in page 00
+ Branch backwards doesn't work.
+ read/modify/write did not work
+ pha pushed onto page 0
+ pha data latched one clock to late
+ jmp indirect didn't work
+
+8) Split T6502_fsm into smaller blocks for ease of documenting and verifying
+
+9) Move branch decision logic into sequencer block
+
+10) removed BCD logic
+
+11) moved alu_opcode to instr_decode block
+
+12) created datapath logic for alu_operand_a, alu_operand_b and alu_operand_c
+
+13) split alu into alu_control and alu blocks
+
+14) reworked the inst_decode signals to alu and pulled datapath out of sequencer
+
+15) removed the latched alu_result. Outside of alu now uses raw
+
+
+
+
+This appears to be a work in progress with numerous issues. I fixed enough of them so that I can
+synthesize into an fpga and it runs the io_poll program on a Nexys2 Board. I will commit this as
+a start but it is alpha code and will have bugs.
projects/Mos6502/ip/T6502_alu_logic/doc/Readme.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/doc/orig6502.txt
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/orig6502.txt (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/orig6502.txt (revision 57)
@@ -0,0 +1,151 @@
+ ADC abs | 6D | ADC abs |
+ ADC abs,X | 7D | ADC abs,X |
+ ADC abs,Y | 79 | ADC abs,Y |
+ ADC #n | 69 | ADC #n |
+ ADC zp | 65 | ADC zp |
+ ADC (zp,X) | 61 | ADC (zp,X) |
+ ADC zp,X | 75 | ADC zp,X |
+ ADC (zp),Y | 71 | ADC (zp),Y |
+ AND abs | 2D | AND abs |
+ AND abs,X | 3D | AND abs,X |
+ AND abs,Y | 39 | AND abs,Y |
+ AND #n | 29 | AND #n |
+ AND zp | 25 | AND zp |
+ AND (zp,X) | 21 | AND (zp,X) |
+ AND zp,X | 35 | AND zp,X |
+ AND (zp),Y | 31 | AND (zp),Y |
+ ASL A | 0A | ASL A |
+ ASL abs | 0E | ASL abs |
+ ASL abs,X | 1E | ASL abs,X |
+ ASL zp | 06 | ASL zp |
+ ASL zp,X | 16 | ASL zp,X |
+ BCC rel | 90 | BCC rel |
+ BCS rel | B0 | BCS rel |
+ BEQ rel | F0 | BEQ rel |
+ BIT abs | 2C | BIT abs |
+ BIT zp | 24 | BIT zp |
+ BMI rel | 30 | BMI rel |
+ BNE rel | D0 | BNE rel |
+ BPL rel | 10 | BPL rel |
+ BRK | 00 | BRK |
+ BVC rel | 50 | BVC rel |
+ BVS rel | 70 | BVS rel |
+ CLC | 18 | CLC |
+ CLD | D8 | CLD |
+ CLI | 58 | CLI |
+ CLV | B8 | CLV |
+ CMP abs | CD | CMP abs |
+ CMP abs,X | DD | CMP abs,X |
+ CMP abs,Y | D9 | CMP abs,Y |
+ CMP #n | C9 | CMP #n |
+ CMP zp | C5 | CMP zp |
+ CMP (zp,X) | C1 | CMP (zp,X) |
+ CMP zp,X | D5 | CMP zp,X |
+ CMP (zp),Y | D1 | CMP (zp),Y |
+ CPX abs | EC | CPX abs |
+ CPX #n | E0 | CPX #n |
+ CPX zp | E4 | CPX zp |
+ CPY abs | CC | CPY abs |
+ CPY #n | C0 | CPY #n |
+ CPY zp | C4 | CPY zp |
+ DEC abs | CE | DEC abs |
+ DEC abs,X | DE | DEC abs,X |
+ DEC zp | C6 | DEC zp |
+ DEC zp,X | D6 | DEC zp,X |
+ DEX | CA | DEX |
+ DEY | 88 | DEY |
+ EOR abs | 4D | EOR abs |
+ EOR abs,X | 5D | EOR abs,X |
+ EOR abs,Y | 59 | EOR abs,Y |
+ EOR #n | 49 | EOR #n |
+ EOR zp | 45 | EOR zp |
+ EOR (zp,X) | 41 | EOR (zp,X) |
+ EOR zp,X | 55 | EOR zp,X |
+ EOR (zp),Y | 51 | EOR (zp),Y |
+ INC abs | EE | INC abs |
+ INC abs,X | FE | INC abs,X |
+ INC zp | E6 | INC zp |
+ INC zp,X | F6 | INC zp,X |
+ INX | E8 | INX |
+ INY | C8 | INY |
+ JMP abs | 4C | JMP abs |
+ JMP (abs) | 6C | JMP (abs) |
+ JSR abs | 20 | JSR abs |
+ LDA abs | AD | LDA abs |
+ LDA abs,X | BD | LDA abs,X |
+ LDA abs,Y | B9 | LDA abs,Y |
+ LDA #n | A9 | LDA #n |
+ LDA zp | A5 | LDA zp |
+ LDA (zp,X) | A1 | LDA (zp,X) |
+ LDA zp,X | B5 | LDA zp,X |
+ LDA (zp),Y | B1 | LDA (zp),Y |
+ LDX abs | AE | LDX abs |
+ LDX abs,Y | BE | LDX abs,Y |
+ LDX #n | A2 | LDX #n |
+ LDX zp | A6 | LDX zp |
+ LDX zp,Y | B6 | LDX zp,Y |
+ LDY abs | AC | LDY abs |
+ LDY abs,X | BC | LDY abs,X |
+ LDY #n | A0 | LDY #n |
+ LDY zp | A4 | LDY zp |
+ LDY zp,X | B4 | LDY zp,X |
+ LSR A | 4A | LSR A |
+ LSR abs | 4E | LSR abs |
+ LSR abs,X | 5E | LSR abs,X |
+ LSR zp | 46 | LSR zp |
+ LSR zp,X | 56 | LSR zp,X |
+ NOP | EA | NOP |
+ ORA abs | 0D | ORA abs |
+ ORA abs,X | 1D | ORA abs,X |
+ ORA abs,Y | 19 | ORA abs,Y |
+ ORA #n | 09 | ORA #n |
+ ORA zp | 05 | ORA zp |
+ ORA (zp,X) | 01 | ORA (zp,X) |
+ ORA zp,X | 15 | ORA zp,X |
+ ORA (zp),Y | 11 | ORA (zp),Y |
+ PHA | 48 | PHA |
+ PHP | 08 | PHP |
+ PLA | 68 | PLA |
+ PLP | 28 | PLP |
+ ROL A | 2A | ROL A |
+ ROL abs | 2E | ROL abs |
+ ROL abs,X | 3E | ROL abs,X |
+ ROL zp | 26 | ROL zp |
+ ROL zp,X | 36 | ROL zp,X |
+ ROR A | 6A | ROR A |
+ ROR abs | 6E | ROR abs |
+ ROR abs,X | 7E | ROR abs,X |
+ ROR zp | 66 | ROR zp |
+ ROR zp,X | 76 | ROR zp,X |
+ RTI | 40 | RTI |
+ RTS | 60 | RTS |
+ SBC abs | ED | SBC abs |
+ SBC abs,X | FD | SBC abs,X |
+ SBC abs,Y | F9 | SBC abs,Y |
+ SBC #n | E9 | SBC #n |
+ SBC zp | E5 | SBC zp |
+ SBC (zp,X) | E1 | SBC (zp,X) |
+ SBC zp,X | F5 | SBC zp,X |
+ SBC (zp),Y | F1 | SBC (zp),Y |
+ SEC | 38 | SEC |
+ SED | F8 | SED |
+ SEI | 78 | SEI |
+ STA abs | 8D | STA abs |
+ STA abs,X | 9D | STA abs,X |
+ STA abs,Y | 99 | STA abs,Y |
+ STA zp | 85 | STA zp |
+ STA (zp,X) | 81 | STA (zp,X) |
+ STA zp,X | 95 | STA zp,X |
+ STA (zp),Y | 91 | STA (zp),Y |
+ STX abs | 8E | STX abs |
+ STX zp | 86 | STX zp |
+ STX zpy | 96 | STX zpy |
+ STY abs | 8C | STY abs |
+ STY zp | 84 | STY zp |
+ STY zp,X | 94 | STY zp,X |
+ TAX | AA | TAX |
+ TAY | A8 | TAY |
+ TSX | BA | TSX |
+ TXA | 8A | TXA |
+ TXS | 9A | TXS |
+ TYA | 98 | TYA |
projects/Mos6502/ip/T6502_alu_logic/doc/orig6502.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/doc/copyright.v
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/doc/copyright.v (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/doc/copyright.v (revision 57)
@@ -0,0 +1,80 @@
+////////////////////////////////////////////////////////////////////
+// -------------- //
+// / SOC \ //
+// / GEN \ //
+// / COMPONENT \ //
+// ==================== //
+// |digital done right| //
+// |__________________| //
+// //
+// //
+// //
+// Copyright (C) <2010> //
+// //
+// //
+// This source file may be used and distributed without //
+// restriction provided that this copyright statement is not //
+// removed from the file and that any derivative work contains //
+// the original copyright notice and the associated disclaimer. //
+// //
+// This source file is free software; you can redistribute it //
+// and/or modify it under the terms of the GNU Lesser General //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any //
+// later version. //
+// //
+// This source is distributed in the hope that it will be //
+// useful, but WITHOUT ANY WARRANTY; without even the implied //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
+// PURPOSE. See the GNU Lesser General Public License for more //
+// details. //
+// //
+// You should have received a copy of the GNU Lesser General //
+// Public License along with this source; if not, download it //
+// from http://www.opencores.org/lgpl.shtml //
+// //
+////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////
+//// ////
+//// T6507LP IP Core ////
+//// ////
+//// This file is part of the T6507LP project ////
+//// http://www.opencores.org/cores/t6507lp/ ////
+//// ////
+//// Description ////
+//// Implementation of a 6507-compatible microprocessor ////
+//// ////
+//// To Do: ////
+//// - Everything ////
+//// ////
+//// Author(s): ////
+//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
+//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
+//// ////
+////////////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+////////////////////////////////////////////////////////////////////////////
projects/Mos6502/ip/T6502_alu_logic/doc/copyright.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/bin/Makefile
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/bin/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/bin/Makefile (revision 57)
@@ -0,0 +1,2 @@
+include ../../../bin/Makefile.root
+
projects/Mos6502/ip/T6502_alu_logic/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/liblist
===================================================================
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/TB.defs
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/TB.defs (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/TB.defs (revision 57)
@@ -0,0 +1,10 @@
+`define TIMEOUT 2000000
+
+
+
+
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/test_define
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/test_define (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/test_define (revision 57)
@@ -0,0 +1,23 @@
+initial
+begin
+$display(" ");
+$display(" ===================================================");
+$display(" Test Start");
+$display(" ===================================================");
+$display(" ");
+cg.next(20);
+cg.reset_off;
+
+while (run == 1'b0)
+begin
+
+
+cg.next(1);
+end
+
+
+cg.exit;
+end
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dmp_define
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dmp_define (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dmp_define (revision 57)
@@ -0,0 +1,7 @@
+ $dumpfile ("TestBench.vcd");
+ $dumpvars (0, TB);
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dut
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dut (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/dut (revision 57)
@@ -0,0 +1,513 @@
+
+
+wire [7:0] alu_op_a;
+wire [7:0] alu_op_b;
+wire alu_op_c;
+wire alu_op_b_inv;
+
+
+reg [7:0] alu_op_a_drv;
+reg [7:0] alu_op_b_drv;
+reg alu_op_c_drv;
+reg alu_op_b_inv_drv;
+
+
+reg [7:0] next_alu_op_a;
+reg [7:0] next_alu_op_b;
+reg next_alu_op_c;
+reg next_alu_op_b_inv;
+
+
+
+
+
+wire [7:0] result;
+wire r_result;
+wire c_result;
+wire v_result;
+
+wire [7:0] and_out;
+wire [7:0] orr_out;
+wire [7:0] eor_out;
+
+
+wire [8:0] a_sh_left;
+wire [8:0] a_sh_right;
+wire [8:0] b_sh_left;
+wire [8:0] b_sh_right;
+
+
+
+reg [7:0] exp_result;
+reg exp_r_result;
+reg exp_c_result;
+reg exp_v_result;
+
+reg [7:0] exp_and_out;
+reg [7:0] exp_orr_out;
+reg [7:0] exp_eor_out;
+
+
+reg [8:0] exp_a_sh_left;
+reg [8:0] exp_a_sh_right;
+reg [8:0] exp_b_sh_left;
+reg [8:0] exp_b_sh_right;
+
+
+
+
+
+
+
+T6502_alu_logic
+dut (
+ .alu_op_a ( alu_op_a ),
+ .alu_op_b ( alu_op_b ),
+ .alu_op_c ( alu_op_c ),
+ .alu_op_b_inv ( alu_op_b_inv ),
+
+ .result ( result ),
+ .r_result ( r_result ),
+ .c_result ( c_result ),
+ .v_result ( v_result ),
+
+ .and_out ( and_out ),
+ .orr_out ( orr_out ),
+ .eor_out ( eor_out ),
+
+ .a_sh_left ( a_sh_left ),
+ .a_sh_right ( a_sh_right ),
+ .b_sh_left ( b_sh_left ),
+ .b_sh_right ( b_sh_right )
+
+
+
+);
+
+
+reg run;
+reg next_run;
+
+
+
+always@(posedge clk)
+ if(reset)
+ begin
+ run <= 1'b0;
+ alu_op_a_drv <= 8'h00;
+ alu_op_b_drv <= 8'h00;
+ alu_op_c_drv <= 1'b0;
+ alu_op_b_inv_drv <= 1'b0;
+ end
+ else
+ begin
+ run <= next_run;
+ alu_op_a_drv <= next_alu_op_a;
+ alu_op_b_drv <= next_alu_op_b;
+ alu_op_c_drv <= next_alu_op_c;
+ alu_op_b_inv_drv <= next_alu_op_b_inv;
+ end
+
+
+
+
+
+always@(*)
+ begin
+ next_run = run;
+ next_alu_op_a = alu_op_a_drv;
+ next_alu_op_b = alu_op_b_drv;
+ next_alu_op_c = alu_op_c_drv;
+ next_alu_op_b_inv = alu_op_b_inv_drv;
+
+
+ if(run)
+ begin
+ next_run = 1'b1;
+ next_alu_op_a = 8'h00;
+ next_alu_op_b = 8'h00;
+ next_alu_op_c = 1'b0;
+ next_alu_op_b_inv = 1'b0;
+ end
+ else
+ begin
+ next_alu_op_a = alu_op_a_drv+8'h01;
+ if(alu_op_a_drv == 8'hff)
+ begin
+ next_alu_op_b = alu_op_b_drv+8'h01;
+ if(alu_op_b_drv == 8'hff)
+ begin
+ {next_run,next_alu_op_c , next_alu_op_b_inv} = {run,alu_op_c_drv, alu_op_b_inv_drv} + 3'b001;
+ end
+ end
+ end
+ end
+
+
+
+always@(*)
+ begin
+ exp_and_out = alu_op_a_drv & alu_op_b_drv;
+ exp_orr_out = alu_op_a_drv | alu_op_b_drv;
+ exp_eor_out = alu_op_a_drv ^ alu_op_b_drv;
+ exp_a_sh_left = {alu_op_a_drv,alu_op_c_drv};
+ exp_a_sh_right = {alu_op_a_drv[0],alu_op_c_drv, alu_op_a_drv[7:1]};
+ exp_b_sh_left = {alu_op_b_drv,alu_op_c_drv};
+ exp_b_sh_right = {alu_op_b_drv[0],alu_op_c_drv, alu_op_b_drv[7:1]};
+ end
+
+
+always@(*)
+ begin
+ if(alu_op_b_inv_drv)
+ begin
+ {exp_r_result,exp_result} = alu_op_a_drv - alu_op_b_drv - (!alu_op_c_drv) ;
+ exp_c_result = !exp_r_result ;
+ exp_v_result = ((alu_op_a_drv[7] == alu_op_b_drv[7]) && (alu_op_a_drv[7] != exp_result[7]));
+ end
+ else
+ begin
+ {exp_r_result,exp_result} = alu_op_a_drv + alu_op_b_drv + alu_op_c_drv ;
+ exp_c_result = exp_r_result ;
+ exp_v_result = ((alu_op_a_drv[7] == alu_op_b_drv[7]) && (alu_op_a_drv[7] != exp_result[7]));
+ end
+
+
+
+ end
+
+
+
+
+
+
+
+io_probe
+#(.WIDTH (8),
+ .RESET ({8{1'b0}}),
+ .IN_DELAY (0),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+alu_op_a_tprb
+(
+ .clk ( clk ),
+ .drive_value ( alu_op_a_drv ),
+ .expected_value (8'b0 ),
+ .mask (8'b0 ),
+ .signal ( alu_op_a )
+
+);
+
+
+
+
+
+io_probe
+#(.WIDTH (8),
+ .RESET ({8{1'b0}}),
+ .IN_DELAY (0),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+alu_op_b_tprb
+(
+ .clk ( clk ),
+ .drive_value ( alu_op_b_drv ),
+ .expected_value (8'b0 ),
+ .mask (8'b0 ),
+ .signal ( alu_op_b )
+
+);
+
+
+
+
+
+
+
+io_probe
+#(.WIDTH (1),
+ .RESET ({1{1'b0}}),
+ .IN_DELAY (0),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+alu_op_c_tprb
+(
+ .clk ( clk ),
+ .drive_value ( alu_op_c_drv ),
+ .expected_value (1'b0 ),
+ .mask (1'b0 ),
+ .signal ( alu_op_c )
+
+);
+
+
+
+
+
+
+
+io_probe
+#(.WIDTH (1),
+ .RESET ({1{1'b0}}),
+ .IN_DELAY (0),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+alu_op_b_inv_tprb
+(
+ .clk ( clk ),
+ .drive_value ( alu_op_b_inv_drv ),
+ .expected_value (1'b0 ),
+ .mask (1'b0 ),
+ .signal ( alu_op_b_inv )
+
+);
+
+
+
+
+
+
+
+
+
+
+io_probe
+#(.MESG("result error"),
+ .WIDTH (8),
+ .RESET ({8{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+result_tprb
+(
+ .clk ( clk ),
+ .drive_value (8'bzzzzzzzz),
+ .expected_value ( exp_result ),
+ .mask (8'b11111111 ),
+ .signal ( result )
+
+);
+
+
+
+
+
+
+io_probe
+#(.MESG("and_out error"),
+ .WIDTH (8),
+ .RESET ({8{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+and_out_tprb
+(
+ .clk ( clk ),
+ .drive_value (8'bzzzzzzzz),
+ .expected_value ( exp_and_out ),
+ .mask (8'b11111111 ),
+ .signal ( and_out )
+
+);
+
+
+
+
+io_probe
+#(.MESG("orr_out error"),
+ .WIDTH (8),
+ .RESET ({8{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+orr_out_tprb
+(
+ .clk ( clk ),
+ .drive_value (8'bzzzzzzzz),
+ .expected_value ( exp_orr_out ),
+ .mask (8'b11111111 ),
+ .signal ( orr_out )
+
+);
+
+
+
+
+io_probe
+#(.MESG("eor_out error"),
+ .WIDTH (8),
+ .RESET ({8{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+eor_out_tprb
+(
+ .clk ( clk ),
+ .drive_value (8'bzzzzzzzz),
+ .expected_value ( exp_eor_out ),
+ .mask (8'b11111111 ),
+ .signal ( eor_out )
+
+);
+
+
+
+
+
+
+io_probe
+#(.MESG("a_sh_left error"),
+ .WIDTH (9),
+ .RESET ({9{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+a_sh_left_tprb
+(
+ .clk ( clk ),
+ .drive_value (9'bzzzzzzzzz ),
+ .expected_value ( exp_a_sh_left ),
+ .mask (9'b111111111 ),
+ .signal ( a_sh_left )
+
+);
+
+
+
+io_probe
+#(.MESG("a_sh_right error"),
+ .WIDTH (9),
+ .RESET ({9{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+a_sh_right_tprb
+(
+ .clk ( clk ),
+ .drive_value (9'bzzzzzzzzz ),
+ .expected_value ( exp_a_sh_right ),
+ .mask (9'b111111111 ),
+ .signal ( a_sh_right )
+
+);
+
+
+
+
+io_probe
+#(.MESG("b_sh_left error"),
+ .WIDTH (9),
+ .RESET ({9{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+b_sh_left_tprb
+(
+ .clk ( clk ),
+ .drive_value (9'bzzzzzzzzz ),
+ .expected_value ( exp_b_sh_left ),
+ .mask (9'b111111111 ),
+ .signal ( b_sh_left )
+
+);
+
+
+
+io_probe
+#(.MESG("b_sh_right error"),
+ .WIDTH (9),
+ .RESET ({9{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+b_sh_right_tprb
+(
+ .clk ( clk ),
+ .drive_value (9'bzzzzzzzzz ),
+ .expected_value ( exp_b_sh_right ),
+ .mask (9'b111111111 ),
+ .signal ( b_sh_right )
+
+);
+
+
+
+
+io_probe
+#(.MESG("r_result error"),
+ .WIDTH (1),
+ .RESET ({1{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+r_result_tprb
+(
+ .clk ( clk ),
+ .drive_value (1'bz ),
+ .expected_value ( exp_r_result ),
+ .mask (1'b1 ),
+ .signal ( r_result )
+
+);
+
+
+
+
+
+io_probe
+#(.MESG("c_result error"),
+ .WIDTH (1),
+ .RESET ({1{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+c_result_tprb
+(
+ .clk ( clk ),
+ .drive_value (1'bz ),
+ .expected_value ( exp_c_result ),
+ .mask (1'b1 ),
+ .signal ( c_result )
+
+);
+
+
+
+
+
+io_probe
+#(.MESG("v_result error"),
+ .WIDTH (1),
+ .RESET ({1{1'bz}}),
+ .IN_DELAY (5),
+ .OUT_DELAY (15),
+ .OUT_WIDTH (10)
+ )
+v_result_tprb
+(
+ .clk ( clk ),
+ .drive_value (1'bz ),
+ .expected_value ( exp_v_result ),
+ .mask (1'b1 ),
+ .signal ( v_result )
+
+);
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/modellist
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/modellist (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/modellist (revision 57)
@@ -0,0 +1,5 @@
+`include "../../bench/verilog/models/clock_gen.v"
+`include "../../bench/verilog/models/io_probe.v"
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/Makefile
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/run/alu_logic_test/Makefile (revision 57)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=T6502_alu_logic
+test=alu_logic_test
Index: projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/TB.defs
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/TB.defs (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/TB.defs (revision 57)
@@ -0,0 +1,10 @@
+`define TIMEOUT 2000000
+
+
+
+
+
+
+
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/dut
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/dut (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/dut (revision 57)
@@ -0,0 +1,87 @@
+
+
+wire [7:0] alu_op_a;
+wire [7:0] alu_op_b;
+wire alu_op_c;
+wire alu_op_b_inv;
+
+
+reg [7:0] alu_op_a_drv;
+reg [7:0] alu_op_b_drv;
+reg alu_op_c_drv;
+reg alu_op_b_inv_drv;
+
+
+reg [7:0] next_alu_op_a;
+reg [7:0] next_alu_op_b;
+reg next_alu_op_c;
+reg next_alu_op_b_inv;
+
+
+
+
+
+wire [7:0] result;
+wire r_result;
+wire c_result;
+wire v_result;
+
+wire [7:0] and_out;
+wire [7:0] orr_out;
+wire [7:0] eor_out;
+
+
+wire [8:0] a_sh_left;
+wire [8:0] a_sh_right;
+wire [8:0] b_sh_left;
+wire [8:0] b_sh_right;
+
+
+
+reg [7:0] exp_result;
+reg exp_r_result;
+reg exp_c_result;
+reg exp_v_result;
+
+reg [7:0] exp_and_out;
+reg [7:0] exp_orr_out;
+reg [7:0] exp_eor_out;
+
+
+reg [8:0] exp_a_sh_left;
+reg [8:0] exp_a_sh_right;
+reg [8:0] exp_b_sh_left;
+reg [8:0] exp_b_sh_right;
+
+
+
+
+
+
+
+T6502_alu_logic
+dut (
+ .alu_op_a ( alu_op_a ),
+ .alu_op_b ( alu_op_b ),
+ .alu_op_c ( alu_op_c ),
+ .alu_op_b_inv ( alu_op_b_inv ),
+
+ .result ( result ),
+ .r_result ( r_result ),
+ .c_result ( c_result ),
+ .v_result ( v_result ),
+
+ .and_out ( and_out ),
+ .orr_out ( orr_out ),
+ .eor_out ( eor_out ),
+
+ .a_sh_left ( a_sh_left ),
+ .a_sh_right ( a_sh_right ),
+ .b_sh_left ( b_sh_left ),
+ .b_sh_right ( b_sh_right )
+
+
+
+);
+
+
Index: projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/Makefile
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/cov/T6502_alu_logic/Makefile (revision 57)
@@ -0,0 +1,46 @@
+SHELL=/bin/sh
+MAKE=make
+VARIANT=T6502_alu_logic
+VPP_NAME=vppreproc
+
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\
+ covered score -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd $(VARIANT).cdd -vcd ../../out/$(TEST).vcd 2>> $(VARIANT)_sco_cov.log | tee >> $(VARIANT)_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd $(VARIANT).cdd 2> $(VARIANT)_rep_cov.log | tee >> $(VARIANT)_rep_cov.log ;\
Index: projects/Mos6502/ip/T6502_alu_logic/sim/bin/Makefile
===================================================================
--- projects/Mos6502/ip/T6502_alu_logic/sim/bin/Makefile (nonexistent)
+++ projects/Mos6502/ip/T6502_alu_logic/sim/bin/Makefile (revision 57)
@@ -0,0 +1,3 @@
+include ../../../../bin/Makefile.root
+
+
projects/Mos6502/ip/T6502_alu_logic/sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
===================================================================
--- projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml (revision 56)
+++ projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml (revision 57)
@@ -1,7 +1,7 @@
ps2_interface
- logic
+ ps2_interface
cde_sram
@@ -9,11 +9,32 @@
cde
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+ cde_serial_xmit
+ cde_serial_xmit
+ cde
+
+
+
+ cde_serial_rcvr
+ cde_serial_rcvr
+ cde
+
+
+
+
+
+default
+
+
+mouse
+
+
/projects/logic/ip/ps2_interface/rtl/variants/ps2_interface/defines.v
1,6 → 1,4
|
`define VARIANT ps2_interface |
`define CDE cde |
|
`define FSM _fsm |
|
projects/logic/ip/ps2_interface/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/run/mouse/filelist
===================================================================
--- projects/logic/ip/ps2_interface/sim/run/mouse/filelist (revision 56)
+++ projects/logic/ip/ps2_interface/sim/run/mouse/filelist (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/sim/ps2_interface.v"
-
Index: projects/logic/ip/ps2_interface/sim/run/mouse/filelist.cov
===================================================================
--- projects/logic/ip/ps2_interface/sim/run/mouse/filelist.cov (revision 56)
+++ projects/logic/ip/ps2_interface/sim/run/mouse/filelist.cov (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/ps2_interface.v"
-
projects/logic/ip/ps2_interface/sim/run/mouse/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist
===================================================================
--- projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist (revision 56)
+++ projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/ps2_interface.v"
-
projects/logic/ip/ps2_interface/sim/cov/ps2_interface/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/disp_io/rtl/xml/disp_io.xml
===================================================================
--- projects/logic/ip/disp_io/rtl/xml/disp_io.xml (revision 56)
+++ projects/logic/ip/disp_io/rtl/xml/disp_io.xml (revision 57)
@@ -1,19 +1,21 @@
disp_io
- logic
+ disp_io
- cde_sram
- cde_sram
+ cde_divider
+ cde_divider
cde
-
- cde_sync_with_hystersis
- cde_synchronizers
- cde
-
+
-
+
+
+
+default
+
+
+
/projects/logic/ip/disp_io/rtl/variants/disp_io/defines.v
File deleted
\ No newline at end of file
/projects/logic/ip/disp_io/sim/run/default/filelist
File deleted
projects/logic/ip/disp_io/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/disp_io/sim/cov/disp_io/filelist
===================================================================
--- projects/logic/ip/disp_io/sim/cov/disp_io/filelist (revision 56)
+++ projects/logic/ip/disp_io/sim/cov/disp_io/filelist (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/disp_io.v"
-
projects/logic/ip/disp_io/sim/cov/disp_io/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
===================================================================
--- projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml (revision 56)
+++ projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml (revision 57)
@@ -1,7 +1,7 @@
serial_rcvr
- logic
+ serial_rcvr
cde_sram
@@ -9,11 +9,37 @@
cde
- cde_sync_with_hystersis
+ cde_fifo
+ cde_fifo
+ cde
+
+
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+ cde_divider
+ cde_divider
+ cde
+
+
+ cde_serial_rcvr
+ cde_serial_rcvr
+ cde
+
+
+
+
+
+
+
+
+default
+
+
+
projects/logic/ip/serial_rcvr/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist
===================================================================
--- projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist (revision 56)
+++ projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/serial_rcvr.v"
-
projects/logic/ip/serial_rcvr/sim/cov/serial_rcvr/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/uart/rtl/xml/uart.xml
===================================================================
--- projects/logic/ip/uart/rtl/xml/uart.xml (revision 56)
+++ projects/logic/ip/uart/rtl/xml/uart.xml (revision 57)
@@ -1,7 +1,18 @@
uart
- logic
+ uart
+
+
+
+
+ serial_rcvr
+ serial_rcvr
+
+
+
+
+
cde_sram
@@ -9,11 +20,46 @@
cde
- cde_sync_with_hystersis
+ cde_fifo
+ cde_fifo
+ cde
+
+
+
+ cde_divider
+ cde_divider
+ cde
+
+
+
+ cde_serial_xmit
+ cde_serial_xmit
+ cde
+
+
+
+ cde_serial_rcvr
+ cde_serial_rcvr
+ cde
+
+
+
+
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+
+
+default
+
+
+divide
+
+
+
/projects/logic/ip/uart/rtl/variants/uart/defines.v
1,4 → 1,2
|
`define VARIANT uart |
`define CDE cde |
|
/projects/logic/ip/uart/sim/run/default/filelist
File deleted
\ No newline at end of file
/projects/logic/ip/uart/sim/run/default/filelist.cov
File deleted
\ No newline at end of file
projects/logic/ip/uart/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/run/divide/filelist
===================================================================
--- projects/logic/ip/uart/sim/run/divide/filelist (revision 56)
+++ projects/logic/ip/uart/sim/run/divide/filelist (nonexistent)
@@ -1,5 +0,0 @@
-
-`include "../../../rtl/gen/sim/uart.v"
-`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
-
-
Index: projects/logic/ip/uart/sim/run/divide/filelist.cov
===================================================================
--- projects/logic/ip/uart/sim/run/divide/filelist.cov (revision 56)
+++ projects/logic/ip/uart/sim/run/divide/filelist.cov (nonexistent)
@@ -1,5 +0,0 @@
-
-`include "../../../rtl/gen/syn/uart.v"
-`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-
-
projects/logic/ip/uart/sim/run/divide/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/uart/sim/cov/uart/filelist
===================================================================
--- projects/logic/ip/uart/sim/cov/uart/filelist (revision 56)
+++ projects/logic/ip/uart/sim/cov/uart/filelist (nonexistent)
@@ -1,5 +0,0 @@
-
-`include "../../../rtl/gen/syn/uart.v"
-`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-
-
\ No newline at end of file
projects/logic/ip/uart/sim/cov/uart/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml
===================================================================
--- projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml (revision 56)
+++ projects/logic/ip/io_module/rtl/xml/io_module_mouse.xml (revision 57)
@@ -1,7 +1,24 @@
- io_module_mouse
- logic
+ io_module
+ io_module_mouse
+
+
+
+
+ uart
+ uart
+
+
+ serial_rcvr
+ serial_rcvr
+
+
+ ps2_interface
+ ps2_interface
+
+
+
cde_sram
@@ -8,12 +25,44 @@
cde_sram
cde
+
- cde_sync_with_hystersis
+ cde_fifo
+ cde_fifo
+ cde
+
+
+
+
+ cde_divider
+ cde_divider
+ cde
+
+
+
+ cde_serial_rcvr
+ cde_serial_rcvr
+ cde
+
+
+
+ cde_serial_xmit
+ cde_serial_xmit
+ cde
+
+
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
-
+
+
+mouse
+
+
+
+
/projects/logic/ip/io_module/rtl/xml/io_module.xml
1,20 → 1,67
<components> |
<component> |
<name>io_module</name> |
<parent>logic</parent> |
<library> |
<variant>io_module</variant> |
|
<brothers> |
<brother> |
<variant>uart</variant> |
<component>uart</component> |
</brother> |
|
<brother> |
<variant>serial_rcvr</variant> |
<component>serial_rcvr</component> |
</brother> |
<brother> |
<variant>vga_char_ctrl</variant> |
<component>vga_char_ctrl</component> |
</brother> |
<brother> |
<variant>ps2_interface</variant> |
<component>ps2_interface</component> |
</brother> |
</brothers> |
|
<library> |
<child> |
<name>cde_sram</name> |
<parent>cde_sram</parent> |
<family>cde</family> |
</child> |
|
<child> |
<name>cde_sync_with_hystersis</name> |
<name>cde_fifo</name> |
<parent>cde_fifo</parent> |
<family>cde</family> |
</child> |
|
|
<child> |
<name>cde_divider</name> |
<parent>cde_divider</parent> |
<family>cde</family> |
</child> |
|
<child> |
<name>cde_serial_rcvr</name> |
<parent>cde_serial_rcvr</parent> |
<family>cde</family> |
</child> |
|
<child> |
<name>cde_serial_xmit</name> |
<parent>cde_serial_xmit</parent> |
<family>cde</family> |
</child> |
<child> |
<name>cde_sync_with_hysteresis</name> |
<parent>cde_synchronizers</parent> |
<family>cde</family> |
</child> |
</library> |
|
</library> |
|
<mem_map> |
<mem_space> |
<name>gpio_0</name> |
150,5 → 197,11
</mem_map> |
|
|
<sims> |
<sim> |
<name>default</name> |
</sim> |
</sims> |
|
</component> |
</components> |
/projects/logic/ip/io_module/rtl/variants/io_module_mouse/defines.v
1,5 → 1,4
`define VARIANT io_module_mouse |
`define CDE cde |
|
`define TIMER _timer |
`define TIMER_MICRO_REG _timer_micro_reg |
`define GPIO _gpio |
/projects/logic/ip/io_module/rtl/variants/io_module/defines.v
1,5 → 1,4
`define VARIANT io_module |
`define CDE cde |
|
`define TIMER _timer |
`define TIMER_MICRO_REG _timer_micro_reg |
`define GPIO _gpio |
projects/logic/ip/io_module/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/run/mouse/filelist
===================================================================
--- projects/logic/ip/io_module/sim/run/mouse/filelist (revision 56)
+++ projects/logic/ip/io_module/sim/run/mouse/filelist (nonexistent)
@@ -1,6 +0,0 @@
-
-`include "../../../rtl/gen/sim/io_module_mouse.v"
-`include "../../../../uart/rtl/gen/sim/uart.v"
-`include "../../../../ps2_interface/rtl/gen/sim/ps2_interface.v"
-`include "../../../../vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
-`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
\ No newline at end of file
Index: projects/logic/ip/io_module/sim/run/mouse/filelist.cov
===================================================================
--- projects/logic/ip/io_module/sim/run/mouse/filelist.cov (revision 56)
+++ projects/logic/ip/io_module/sim/run/mouse/filelist.cov (nonexistent)
@@ -1,6 +0,0 @@
-
-`include "../../../rtl/gen/syn/io_module.v"
-`include "../../../../uart/rtl/gen/syn/uart.v"
-`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
\ No newline at end of file
projects/logic/ip/io_module/sim/run/mouse/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist (revision 56)
+++ projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist (nonexistent)
@@ -1,6 +0,0 @@
-
-`include "../../../rtl/gen/syn/io_module_mouse.v"
-`include "../../../../uart/rtl/gen/syn/uart.v"
-`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
-`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
\ No newline at end of file
projects/logic/ip/io_module/sim/cov/io_module_mouse/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/io_module/sim/cov/io_module/filelist
===================================================================
--- projects/logic/ip/io_module/sim/cov/io_module/filelist (revision 56)
+++ projects/logic/ip/io_module/sim/cov/io_module/filelist (nonexistent)
@@ -1,6 +0,0 @@
-
-`include "../../../rtl/gen/syn/io_module.v"
-`include "../../../../uart/rtl/gen/syn/uart.v"
-`include "../../../../ps2_interface/rtl/gen/syn/ps2_interface.v"
-`include "../../../../serial_rcvr/rtl/gen/syn/serial_rcvr.v"
-`include "../../../../vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v"
projects/logic/ip/io_module/sim/cov/io_module/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
===================================================================
--- projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml (revision 56)
+++ projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml (revision 57)
@@ -1,7 +1,7 @@
flash_memcontrl
- logic
+ flash_memcontrl
cde_sram
@@ -9,11 +9,17 @@
cde
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+
+default
+
+
+
/projects/logic/ip/flash_memcontrl/rtl/variants/flash_memcontrl/defines.v
1,2 → 1,2
`define VARIANT flash_memcontrl |
|
|
projects/logic/ip/flash_memcontrl/sim/run/default/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/run/default/filelist.cov
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/run/default/filelist.cov (revision 56)
+++ projects/logic/ip/flash_memcontrl/sim/run/default/filelist.cov (nonexistent)
@@ -1,5 +0,0 @@
-
-`include "../../../rtl/gen/syn/flash_memcontrl.v"
-
-
-
projects/logic/ip/flash_memcontrl/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist
===================================================================
--- projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist (revision 56)
+++ projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist (nonexistent)
@@ -1,5 +0,0 @@
-
-`include "../../../rtl/gen/syn/flash_memcontrl.v"
-
-
-
projects/logic/ip/flash_memcontrl/sim/cov/flash_memcontrl/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
===================================================================
--- projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml (revision 56)
+++ projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml (revision 57)
@@ -1,7 +1,7 @@
usb_epp
- logic
+ usb_epp
cde_sram
@@ -9,11 +9,20 @@
cde
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+
+
+
+default
+
+
+
+
/projects/logic/ip/usb_epp/rtl/variants/usb_epp/defines.v
1,3 → 1,2
|
`define VARIANT usb_epp |
`define CDE cde |
/projects/logic/ip/usb_epp/sim/run/default/filelist
File deleted
projects/logic/ip/usb_epp/sim/run/default/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/run/default/filelist.cov
===================================================================
--- projects/logic/ip/usb_epp/sim/run/default/filelist.cov (revision 56)
+++ projects/logic/ip/usb_epp/sim/run/default/filelist.cov (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/usb_epp.v"
-
projects/logic/ip/usb_epp/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist
===================================================================
--- projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist (revision 56)
+++ projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist (nonexistent)
@@ -1,3 +0,0 @@
-
-`include "../../../rtl/gen/syn/usb_epp.v"
-
projects/logic/ip/usb_epp/sim/cov/usb_epp/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml
===================================================================
--- projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml (revision 56)
+++ projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_600x432.xml (revision 57)
@@ -1,7 +1,7 @@
- vga_char_ctrl_600x432
- logic
+ vga_char_ctrl
+ vga_char_ctrl_600x432
cde_sram
@@ -9,11 +9,19 @@
cde
- cde_sync_with_hystersis
+ cde_sync_with_hysteresis
cde_synchronizers
cde
+
+
+
+default_600x432
+
+
+
+
/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
1,7 → 1,7
<components> |
<component> |
<name>vga_char_ctrl</name> |
<parent>logic</parent> |
<variant>vga_char_ctrl</variant> |
<library> |
<child> |
<name>cde_sram</name> |
9,11 → 9,18
<family>cde</family> |
</child> |
<child> |
<name>cde_sync_with_hystersis</name> |
<name>cde_sync_with_hysteresis</name> |
<parent>cde_synchronizers</parent> |
<family>cde</family> |
</child> |
|
</library> |
|
<sims> |
<sim> |
<name>default</name> |
</sim> |
</sims> |
|
</component> |
</components> |
/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl_600x432/defines.v
1,6 → 1,4
|
`define VARIANT vga_char_ctrl_600x432 |
`define CDE cde |
`define CHAR_DISPLAY _char_display |
`define CHAR_GEN _char_gen |
`define SVGA_TIMING_GENERATION _svga_timing_generation |
/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl/defines.v
1,6 → 1,4
|
`define VARIANT vga_char_ctrl |
`define CDE cde |
`define CHAR_DISPLAY _char_display |
`define CHAR_GEN _char_gen |
`define SVGA_TIMING_GENERATION _svga_timing_generation |
projects/logic/ip/vga_char_ctrl/sim/run/default/filelist.cov
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/liblist
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/liblist (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/liblist (revision 57)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/liblist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/TB.defs
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/TB.defs (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/TB.defs (revision 57)
@@ -0,0 +1,5 @@
+`define PERIOD 41.16667
+`define TIMEOUT 20000000
+`define STARTUP "../../../../../sw/startup/startup.abs"
+`define FONT "../../../../../sw/font/font.abs"
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/test_define
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/test_define (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/test_define (revision 57)
@@ -0,0 +1,16 @@
+initial
+ begin
+ $display(" ");
+ $display(" ===================================================");
+ $display("%8d Test Start",$realtime/`PERIOD );
+ $display(" ===================================================");
+ $display(" ");
+ cg.next(12);
+ cg.reset_off;
+ cg.next(1300000);
+ cg.exit;
+end
+
+
+
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/test_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dmp_define
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dmp_define (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dmp_define (revision 57)
@@ -0,0 +1,8 @@
+
+ $dumpfile ("TestBench.vcd");
+ $dumpvars (0, TB);
+
+
+
+
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dmp_define
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dut
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dut (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dut (revision 57)
@@ -0,0 +1,46 @@
+wire h_sync;
+wire v_sync;
+
+wire red;
+wire green;
+wire blue;
+
+
+
+
+wire [7:0] wdata;
+wire [13:0] address;
+
+wire [2:0] vga_red_pad_out;
+wire [2:0] vga_green_pad_out;
+wire [1:0] vga_blue_pad_out;
+wire hsync_n_pad_out;
+wire vsync_n_pad_out;
+
+
+vga_char_ctrl_600x432
+#(.STARTUP(`STARTUP),
+ .FONT(`FONT))
+dut (
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ascii_load (1'b0),
+ .add_l_load (1'b0),
+ .add_h_load (1'b0),
+
+ .char_color (8'h92),
+ .back_color (8'h00),
+ .cursor_color (8'hff),
+
+ .wdata (8'h00),
+ .address ( address),
+
+ .vga_red_pad_out ( vga_red_pad_out ),
+ .vga_green_pad_out ( vga_green_pad_out ),
+ .vga_blue_pad_out ( vga_blue_pad_out ),
+
+ .hsync_n_pad_out ( hsync_n_pad_out ),
+ .vsync_n_pad_out ( vsync_n_pad_out )
+);
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/modellist
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/modellist (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/modellist (revision 57)
@@ -0,0 +1,3 @@
+`include "../../bench/verilog/models/clock_gen.v"
+
+
projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/modellist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/Makefile
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/Makefile (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/run/default_600x432/Makefile (revision 57)
@@ -0,0 +1,3 @@
+include ../../../../../bin/Makefile.root
+comp=vga_char_ctrl_600x432
+test=default_600x432
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/TB.defs
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/TB.defs (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/TB.defs (revision 57)
@@ -0,0 +1,5 @@
+`define PERIOD 41.16667
+`define TIMEOUT 20000000
+`define STARTUP "../../../../../sw/startup/startup.abs"
+`define FONT "../../../../../sw/font/font.abs"
+
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/dut
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/dut (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/dut (revision 57)
@@ -0,0 +1,46 @@
+wire h_sync;
+wire v_sync;
+
+wire red;
+wire green;
+wire blue;
+
+
+
+
+wire [7:0] wdata;
+wire [13:0] address;
+
+wire [2:0] vga_red_pad_out;
+wire [2:0] vga_green_pad_out;
+wire [1:0] vga_blue_pad_out;
+wire hsync_n_pad_out;
+wire vsync_n_pad_out;
+
+
+vga_char_ctrl_600x432
+#(.STARTUP(`STARTUP),
+ .FONT(`FONT))
+dut (
+ .clk ( clk ),
+ .reset ( reset ),
+
+ .ascii_load (1'b0),
+ .add_l_load (1'b0),
+ .add_h_load (1'b0),
+
+ .char_color (8'h92),
+ .back_color (8'h00),
+ .cursor_color (8'hff),
+
+ .wdata (8'h00),
+ .address ( address),
+
+ .vga_red_pad_out ( vga_red_pad_out ),
+ .vga_green_pad_out ( vga_green_pad_out ),
+ .vga_blue_pad_out ( vga_blue_pad_out ),
+
+ .hsync_n_pad_out ( hsync_n_pad_out ),
+ .vsync_n_pad_out ( vsync_n_pad_out )
+);
+
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/dut
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/Makefile
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/Makefile (nonexistent)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl_600x432/Makefile (revision 57)
@@ -0,0 +1,46 @@
+SHELL=/bin/sh
+MAKE=make
+VARIANT=vga_char_ctrl_600x432
+VPP_NAME=vppreproc
+
+
+
+################################################################################
+# set up coverage
+################################################################################
+
+
+
+.PHONY build_cdd:
+build_cdd:
+ echo "################################################################################"; \
+ echo; \
+ $(VPP_NAME) --noline --noblank -DSYNTHESIS ../../bench/verilog/TestBench.cov > $(VARIANT).v ;\
+ covered score -i TB.dut -t $(VARIANT) -I ./ -v ./$(VARIANT).v -o $(VARIANT).cdd 2> $(VARIANT)_cov.log | tee >> $(VARIANT)_cov.log ;\
+ echo "################################################################################"; \
+
+
+################################################################################
+# score coverage from vcd
+################################################################################
+
+
+
+.PHONY score_cov:
+score_cov:
+ echo "################################################################################"; \
+ echo " Scoring ${$TEST} ";\
+ covered score -cdd $(VARIANT).cdd -vcd ../../out/$(TEST).vcd 2>> $(VARIANT)_sco_cov.log | tee >> $(VARIANT)_sco_cov.log ;\
+
+
+
+################################################################################
+# run coverage report
+################################################################################
+
+
+
+.PHONY report_cov:
+report_cov:
+ echo "################################################################################"; \
+ covered report -cdd $(VARIANT).cdd 2> $(VARIANT)_rep_cov.log | tee >> $(VARIANT)_rep_cov.log ;\
Index: projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist
===================================================================
--- projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist (revision 56)
+++ projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist (nonexistent)
@@ -1,2 +0,0 @@
-`include "../../../rtl/gen/syn/vga_char_ctrl.v"
-
projects/logic/ip/vga_char_ctrl/sim/cov/vga_char_ctrl/filelist
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: targets/Basys/target.xml
===================================================================
--- targets/Basys/target.xml (nonexistent)
+++ targets/Basys/target.xml (revision 57)
@@ -0,0 +1,12 @@
+
+
+BASYS
+
+
+ disp_io
+ disp_io
+ logic
+
+
+
+
Index: targets/Basys/filelist
===================================================================
--- targets/Basys/filelist (nonexistent)
+++ targets/Basys/filelist (revision 57)
@@ -0,0 +1,8 @@
+verilog work ./target/Pad_Ring.v
+verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
+verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
+
+
+
targets/Basys/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: targets/Nexys2/target.xml
===================================================================
--- targets/Nexys2/target.xml (nonexistent)
+++ targets/Nexys2/target.xml (revision 57)
@@ -0,0 +1,23 @@
+
+
+NEXYS2
+
+
+ disp_io
+ disp_io
+ logic
+
+
+ flash_memcontrl
+ flash_memcontrl
+ logic
+
+
+ usb_epp
+ usb_epp
+ logic
+
+
+
+
+
Index: targets/Nexys2/filelist
===================================================================
--- targets/Nexys2/filelist (nonexistent)
+++ targets/Nexys2/filelist (revision 57)
@@ -0,0 +1,8 @@
+verilog work ./target/Pad_Ring.v
+verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v
+verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag.v
+verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
+
+
+
targets/Nexys2/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: Makefile
===================================================================
--- Makefile (revision 56)
+++ Makefile (revision 57)
@@ -7,18 +7,28 @@
all: run_sims build_fpgas check_sims check_fpgas
+
+
.PHONY build_soc:
build_soc:
(\
rm -r work ;\
- soc_link ;\
- soc_builder;\
+ find . | grep "~" | xargs rm $1 ;\
+ ${home}/tools/bin/soc_link ;\
)
+.PHONY build_hw:
+build_hw:
+ (\
+ ${home}/tools/bin/soc_builder;\
+ )
+
+
+
.PHONY build_sw:
-build_sw: build_soc
+build_sw: build_hw
@for PROJECT in `ls $(CUR_DIR)/work`; do \
echo "################################################"; \
echo "build_sw: $$PROJECT ####"; echo; \