OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /socgen/trunk
    from Rev 92 to Rev 93
    ↔ Reverse comparison
  •

Rev 92 → Rev 93

/bench/verilog/TestBench
51,6 → 51,7
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`endif
 
`timescale `TIMESCALE
 
module TB();
 
/tools/simulation/TestBench
0,0 → 1,85
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Testbench file used for all simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
`ifndef TIMESCALE
`define TIMESCALE 1ns/1ns
`endif
 
`ifndef TIMEFORMAT
`define TIMEFORMAT $timeformat(-6, 2, " us", 14);
`endif
 
 
module TB();
 
 
`include "./params.sim"
 
 
 
initial
begin
`TIMEFORMAT
end
 
 
 
`include "./dat.sim"
 
 
`ifdef VCD
initial
begin
`include "./dmp_define"
end
`endif
 
 
 
 
endmodule
 
 
 
/tools/lint/TestBench
0,0 → 1,59
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Testbench file used for all simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
module TB(
input wire clk,
input wire reset
 
);
 
`include "./params.ver"
`include "./dat.ver"
 
 
 
endmodule
 
 
 
/tools/lint/sim_main.cpp
0,0 → 1,54
#include "VTB.h"
#include "verilated.h"
 
VTB *TB;
unsigned int main_time = 0;
double sc_time_stamp () {
return main_time;
}
 
int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
 
 
TB = new VTB;
TB-> reset = 1;
 
 
 
 
while (!Verilated::gotFinish())
 
{
if (main_time > 100) {
TB->reset = 0;
// Deassert reset
}
if ((main_time % 10) == 1) {
TB->clk = 1;
// Toggle clock
}
if ((main_time % 10) == 6) {
TB->clk = 0;
}
 
 
 
 
TB->eval();
// Evaluate model
 
 
 
main_time++;
 
 
 
 
 
}
 
 
exit(0);
}
 
/tools/bin/Makefile.root
131,7 → 131,7
.PHONY sim:
sim:
(\
$(VERILOG_NAME) -f filelist.sim -D VCD ../../bench/verilog/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\
$(VERILOG_NAME) -f filelist.sim -D VCD ../../../../../../../tools/simulation/TestBench 2> ./${test}_sim.log | tee >> ./${test}_sim.log ;\
./a.out 2>> ./${test}_sim.log | tee >> ./${test}_sim.log ;\
rm a.out;\
cd ../../cov/${comp};\
/tools/coverage/TestBench
0,0 → 1,63
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Testbench file used for all codecoverage */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
`define SYNTHESIS
 
 
 
`timescale 1ns/1ns
 
 
module TB();
 
 
`include "./dat.sim"
 
 
 
 
 
 
endmodule
 
 
 
/tools/sys/soc_link_1
44,124 → 44,79
#/* */
#/**********************************************************************/
 
 
 
 
 
 
use Cwd;
use XML::LibXML;
 
 
 
 
my $root = "projects";
$home = cwd();
$lib_comp_sep = "/ip/";
$comp_xml_sep = "/rtl/xml/";
$lib_comp_sep = "/ip/";
 
 
my $project = $ARGV[0];
my $component = $ARGV[1];
 
 
my $prefix = "work/${project}";
$root = "bench";
$dest = "${prefix}${lib_comp_sep}${component}/sim/bench";
&link_sub( $root,$root, $dest );
$root = "lib";
$dest = "${prefix}${lib_comp_sep}${component}/sim/lib";
&link_sub( $root,$root, $dest );
 
my $parser = XML::LibXML->new();
my $doc = $parser->parse_file("${home}/${prefix}${lib_comp_sep}${component}/soc/design.soc");
 
my $prefix = "work/${project}";
$root = "bench";
$dest = "work/${project}${lib_comp_sep}${component}/sim/bench";
&link_sub( $root,$root, $dest );
$root = "lib";
$dest = "work/${project}${lib_comp_sep}${component}/sim/lib";
&link_sub( $root,$root, $dest );
 
#/*********************************************************************************************/
#/ */
#/ Every component needs a rtl/verilog,gen/sim and /gen/syn subdirectory */
#/ */
#/*********************************************************************************************/
#/*********************************************************************************************/
#/ link chip files */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/rtl/verilog";
mkdir $path,0755 unless( -e $path );
print "Linking targets for $project $component \n";
foreach my $i_name ($doc->findnodes("//chips/chip/name"))
{
my($chip) = $i_name ->findnodes('./text()')->to_literal ;
my($chip_target) = $i_name ->findnodes('../target/text()')->to_literal ;
my($configuration) = $i_name ->findnodes('../configuration/text()')->to_literal ;
my($variant) = $i_name ->findnodes('../variant/text()')->to_literal ;
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/rtl/gen";
mkdir $path,0755 unless( -e $path );
$outfile ="${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/Makefile";
open MAKSYNFILE,">$outfile" or die "unable to open $outfile";
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/rtl/gen/sim";
mkdir $path,0755 unless( -e $path );
print MAKSYNFILE "include ../../../../bin/Makefile.root\n";
print MAKSYNFILE "include ./target/Makefile.brd\n";
print MAKSYNFILE "Design=${chip_target}_${configuration}\n";
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/rtl/gen/syn";
mkdir $path,0755 unless( -e $path );
my $path = "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target";
mkdir $path,0755 unless( -e $path );
 
&link_dir( "${home}/targets/${chip_target}", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target" );
&link_dir( "${home}/lib", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target/lib/syn" );
&link_dir( "${home}/tools/Jtag_programmers/debug", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/debug" );
}
 
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/sim/gen";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/sim/gen/sim";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/sim/gen/syn";
mkdir $path,0755 unless( -e $path );
 
 
 
print "Start component $component \n";
my $prefix = "work/${project}";
 
my $parser = XML::LibXML->new();
my $doc = $parser->parse_file("${home}/${prefix}${lib_comp_sep}${component}/soc/design.soc");
 
{
 
#/*********************************************************************************************/
#/ link chip files */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
print "Linking targets for $project $component \n";
foreach my $i_name ($doc->findnodes("//chips/chip/name"))
{
my($chip) = $i_name ->findnodes('./text()')->to_literal ;
my($chip_target) = $i_name ->findnodes('../target/text()')->to_literal ;
my($configuration) = $i_name ->findnodes('../configuration/text()')->to_literal ;
my($variant) = $i_name ->findnodes('../variant/text()')->to_literal ;
 
$outfile ="${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/Makefile";
open MAKSYNFILE,">$outfile" or die "unable to open $outfile";
 
print MAKSYNFILE "include ../../../../bin/Makefile.root\n";
print MAKSYNFILE "include ./target/Makefile.brd\n";
print MAKSYNFILE "Design=${chip_target}_${configuration}\n";
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target";
mkdir $path,0755 unless( -e $path );
 
&link_dir( "${home}/targets/${chip_target}", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target" );
&link_dir( "${home}/lib", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/target/lib/syn" );
&link_dir( "${home}/tools/Jtag_programmers/debug", "${home}/${prefix}${lib_comp_sep}${component}/syn/${chip}/debug" );
}
 
 
 
 
 
}
 
 
 
 
 
 
 
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ */
182,19 → 137,19
 
my $dest_path = $path;
$dest_path =~ s/$root/$dest/;
$dest_path =~ s/$root/$dest/;
 
 
if( -d $path ) {
 
mkdir $dest_path,0755;
mkdir $dest_path,0755;
 
my @contents = ( );
opendir( DIR, $path );
while( my $item = readdir( DIR )) {
next if( $item eq '.' or $item eq '..' or $item eq '.svn' );
push( @contents, $item );
}
my @contents = ( );
opendir( DIR, $path );
while( my $item = readdir( DIR )) {
next if( $item eq '.' or $item eq '..' or $item eq '.svn' );
push( @contents, $item );
}
closedir( DIR );
# recurse on items in the directory
249,25 → 204,7
 
 
 
#/*********************************************************************************************/
#/ */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
sub trim_sort {
my @output_files = @_;
my %trim = ();
foreach $descriptor (@output_files) { $trim{$descriptor} = 1; }
my @k = keys %trim;
@output_files = sort(sort @k);
return(@output_files);
}
eval 'exec `which perl` -S $0 ${1+"$@"}'
if 0;
 
 
 
278,73 → 215,3
 
 
 
 
 
 
 
#/*********************************************************************************************/
#/ */
#/ */
#/ */
#/ */
#/ */
#/ */
#/*********************************************************************************************/
 
sub parse_hier
{
my @params = @_;
my $variant = pop(@params);
my $component = pop(@params);
my $project = pop(@params);
 
$home = cwd();
$cde="cde";
 
 
 
my $parser = XML::LibXML->new();
my $doc = $parser->parse_file("${home}/projects/${project}${lib_comp_sep}${component}${comp_xml_sep}${variant}.xml");
 
foreach my $comp ($doc->findnodes('//spirit:component'))
{
 
my($vendor) = $comp->findnodes('./spirit:vendor/text()')->to_literal ;
my($library) = $comp->findnodes('./spirit:library/text()')->to_literal ;
my($name) = $comp->findnodes('./spirit:name/text()')->to_literal ;
my($version) = $comp->findnodes('./spirit:version/text()')->to_literal ;
 
my $variant = "";
if($version) {$variant = "${name}_${version}"}
else {$variant = "${name}"}
 
#/*********************************************************************************************/
#/ */
#/ Create filelists for simulation, code coverage, linting and synthesis */
#/ */
#/ */
#/*********************************************************************************************/
 
push(@filelist_hier,"::${library}::${name}::${variant}::");
 
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
my($library_name) = $i_name ->findnodes('../spirit:componentRef/spirit:library/text()')->to_literal ;
my($component_name) = $i_name ->findnodes('../spirit:componentRef/spirit:name/text()')->to_literal ;
my($version_name) = $i_name ->findnodes('../spirit:componentRef/spirit:version/text()')->to_literal ;
 
my $variant_name = "";
if($version_name) {$variant_name = "${component_name}_${version_name}";}
else {$variant_name = "${component_name}";}
 
if($library_name ne "cde")
{
my @filelist_sub = parse_hier("$library_name","$component_name","$variant_name");
foreach $line (@filelist_sub) { push(@filelist_hier,"$line"); }
}
else { push(@filelist_hier,"::${library_name}::${component_name}::${variant_name}::"); }
}
}
@filelist_hier = trim_sort(@filelist_hier);
return(@filelist_hier);
}
/tools/sys/build_sim_filelists
150,8 → 150,8
}
elsif($new_proj eq $project )
{
push(@filelist_cov,"-v ../../../../${new_comp}${new_comp_xml}../gen/sim/${new_variant}.v\n");
push(@filelist_ver,"cat ../../../../${new_comp}${new_comp_xml}../gen/sim/${new_variant}.v >> TB.v\n");
push(@filelist_cov,"-v ../../../../${new_comp}${new_comp_xml}../gen/syn/${new_variant}.v\n");
push(@filelist_ver,"cat ../../../../${new_comp}${new_comp_xml}../gen/syn/${new_variant}.v >> TB.v\n");
push(@filelist_sim,"../../../../${new_comp}${new_comp_xml}../gen/sim/${new_variant}.v\n");
}
else
/tools/sys/build_leaf
62,6 → 62,7
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h",
"view=s" => \$view,
"prefix=s" => \$prefix,
"lib_comp_sep=s" => \$lib_comp_sep,
"component=s" => \$component,
89,8 → 90,9
use XML::LibXML;
 
$home = cwd();
$cde ="cde";
 
$cde="cde";
my $dest_dir = $ARGV[0];
 
#############################################################################
##
97,12 → 99,18
##
#############################################################################
 
print " Building RTL for $prefix $component $variant \n" ;
 
 
 
print " Building RTL for $prefix $component $variant \n" ;
my $path = "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}";
mkdir $path,0755 unless( -e $path );
 
 
 
my $parser = XML::LibXML->new();
my $doc = $parser->parse_file("${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${variant}.xml");
foreach my $comp ($doc->findnodes('//spirit:component'))
112,92 → 120,119
my($vendor) = $comp->findnodes('./spirit:vendor/text()')->to_literal ;
my($library) = $comp->findnodes('./spirit:library/text()')->to_literal ;
 
#/**********************************************************************/
#/* */
#/* build a `define file for module names */
#/* */
#/* */
#/* */
#/* */
#/**********************************************************************/
 
my $outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/deflist";
open DEFLIST,">$outfile" or die "unable to open $outfile";
print DEFLIST " \n";
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:logicalName"))
{
my($def_logic) = $i_name ->findnodes('./text()')->to_literal ;
my($def_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
if($def_logic ) {print DEFLIST sprintf( "\`define %s _%s\n", uc($def_logic) , $def_logic );}
}
 
#/**********************************************************************/
#/* */
#/* build a fileset in the following order */
#/* */
#/* deflist for module names */
#/* all include files */
#/* verilogSourceTop file */
#/* all the remaining verilogSource files */
#/* */
#/* */
#/**********************************************************************/
 
my $outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/filelist";
open FILELIST,">$outfile" or die "unable to open $outfile";
foreach my $comp_view ($doc->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view/spirit:fileSetRef'))
{
my($view_fileset) = $comp_view->findnodes('./spirit:localName/text()')->to_literal ;
my($view_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
 
print FILELIST "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/deflist";
 
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
if($file_type eq "verilogInclude"){ print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
if($view eq $view_name)
{
#/**********************************************************************/
#/* */
#/* build a `define file for module names */
#/* */
#/* */
#/* */
#/* */
#/**********************************************************************/
my $outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}deflist";
open DEFLIST,">$outfile" or die "unable to open $outfile";
print DEFLIST " \n";
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:logicalName"))
{
my($def_logic) = $i_name ->findnodes('./text()')->to_literal ;
my($def_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
if($def_logic ) {print DEFLIST sprintf( "\`define %s _%s\n", uc($def_logic) , $def_logic );}
}
#/**********************************************************************/
#/* */
#/* build a fileset in the following order */
#/* */
#/* deflist for module names */
#/* all include files */
#/* verilogSourceTop file */
#/* all the remaining verilogSource files */
#/* */
#/* */
#/**********************************************************************/
my $outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}filelist";
open FILELIST,">$outfile" or die "unable to open $outfile";
print FILELIST "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}deflist";
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
if(($file_type eq "verilogInclude")&& (($view_file eq $view_fileset) || ($view_file eq "all")))
{ print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
if(($file_type eq "verilogSourceTop")&& (($view_file eq $view_fileset) || ($view_file eq "all")))
{ print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
if(($file_type eq "verilogSource")&& (($view_file eq $view_fileset) || ($view_file eq "all")))
{ print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
#/**********************************************************************/
#/* */
#/* Every leaf cell is processed through a the verilog preprocessor */
#/* to customize the module names,remove all verilog tic(`) statements */
#/* and to create seperate versions for simulation and synthesys */
#/* */
#/* */
#/**********************************************************************/
print "BUILD HW $view $prefix $component $variant\n";
$cmd ="cp ${home}/${prefix}${lib_comp_sep}${component}/doc/copyright.v ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}/${variant}.v";
if (system($cmd)) {}
$cmd ="vppreproc --noline --noblank -DVARIANT=${variant} -DCDE=${cde} -f ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}filelist >> ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}/${variant}.v";
if (system($cmd)) {}
 
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
if($file_type eq "verilogSourceTop"){ print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
}
}
}
 
 
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($file_name) = $i_name ->findnodes('./text()')->to_literal ;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal ;
if($file_type eq "verilogSource") { print FILELIST " ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${file_name}\n"};
}
 
 
#/**********************************************************************/
#/* */
#/* Every leaf cell is processed through a the verilog preprocessor */
#/* to customize the module names,remove all verilog tic(`) statements */
#/* and to create seperate versions for simulation and synthesys */
#/* */
#/* */
#/**********************************************************************/
 
print "BUILD HW $prefix $component $variant\n";
 
$cmd ="cp ${home}/${prefix}${lib_comp_sep}${component}/doc/copyright.v ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/sim/${variant}.v";
if (system($cmd)) {}
 
$cmd ="vppreproc --noline --noblank -DVARIANT=${variant} -DCDE=${cde} -y ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../verilog -f ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/filelist >> ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/sim/${variant}.v";
if (system($cmd)) {}
 
$cmd ="cp ${home}/${prefix}${lib_comp_sep}${component}/doc/copyright.v ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/syn/${variant}.v";
if (system($cmd)) {}
 
$cmd ="vppreproc --noline --noblank -DSYNTHESIS -DVARIANT=${variant} -DCDE=${cde} -y ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../verilog -f ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/filelist >> ${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}../gen/syn/${variant}.v";
if (system($cmd)) {}
}
 
 
1
 
 
/tools/sys/build_verilog
62,6 → 62,7
############################################################################
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h",
"view=s" => \$view,
"prefix=s" => \$prefix,
"lib_comp_sep=s" => \$lib_comp_sep,
"component=s" => \$component,
100,12 → 101,20
#############################################################################
 
my $destination = $ARGV[0];
my $dest_dir = $ARGV[1];
 
 
 
print " Building $destination for $prefix $component $variant \n" ;
 
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}";
mkdir $path,0755 unless( -e $path );
 
my $path = "${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}";
mkdir $path,0755 unless( -e $path );
 
 
 
my $parser = XML::LibXML->new();
my $doc = $parser->parse_file("${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${variant}.xml");
foreach my $comp ($doc->findnodes('//spirit:component'))
124,222 → 133,240
#/* */
#/**********************************************************************/
 
print "BUILD design $prefix\n $component $variant\n";
print "CREATING verilog for Proj $project Comp $component Name $name Var $variant \n";
my $outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${destination}";
open DEST_FILE,">$outfile" or die "unable to open $outfile";
my $name = $variant;
print DEST_FILE "\n module \n\n $variant \n ";
 
#/**********************************************************************/
#/* */
#/* Add any and all parameters with their default values */
#/* */
#/**********************************************************************/
 
 
foreach my $comp_view ($doc->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view/spirit:fileSetRef'))
{
my($view_fileset) = $comp_view->findnodes('./spirit:localName/text()')->to_literal ;
my($view_name) = $comp_view->findnodes('../spirit:name/text()')->to_literal ;
 
my $first = 1;
foreach my $i_name ($doc->findnodes('//spirit:model/spirit:modelParameters/spirit:modelParameter/spirit:value/@spirit:id'))
{
my($parameter_name) = $i_name ->to_literal;
my($parameter_default) = $i_name ->findnodes('../text()')->to_literal ;
if($first)
{
print DEST_FILE " #( parameter ${parameter_name}=${parameter_default}";
$first=0;
}
else
{
print DEST_FILE ",\n parameter ${parameter_name}=${parameter_default}";
}
}
 
if($first == 0)
{
print DEST_FILE ")\n";
}
 
#/**********************************************************************/
#/* */
#/* Now add all ports with their type, size and direction */
#/* */
#/**********************************************************************/
 
 
print DEST_FILE "\n ( \n";
$first = 1;
 
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:model/spirit:ports/spirit:port/name"))
{
my($port_name) = $i_name ->findnodes('./text()')->to_literal ;
my($direction) = $i_name ->findnodes('../spirit:wire/spirit:direction/text()')->to_literal ;
my($left) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:left/text()')->to_literal ;
my($right) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:right/text()')->to_literal ;
my($type) = $i_name ->findnodes('../spirit:wireTypeDefs/spirit:wireTypeDef/spirit:typeName/text()')->to_literal ;
my $width = " ";
if($left) {$width = "[${left}:${right}]"}
 
 
if($first)
{
print DEST_FILE "$direction $type $width $port_name";
$first=0;
}
else
{
print DEST_FILE ",\n$direction $type $width $port_name";
}
}
print DEST_FILE ");\n\n\n\n";
 
#/**********************************************************************/
#/* */
#/* Add all internal wires and regs with their sizes */
#/* */
#/**********************************************************************/
 
 
 
foreach my $i_name ($doc->findnodes("//spirit:component/nodes/node/name"))
{
my($node_name) = $i_name ->findnodes('./text()')->to_literal ;
my($left) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:left/text()')->to_literal ;
my($right) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:right/text()')->to_literal ;
my($type) = $i_name ->findnodes('../spirit:wireTypeDefs/spirit:wireTypeDef/spirit:typeName/text()')->to_literal ;
 
my $width = " ";
if($left) {$width = "[${left}:${right}]"}
 
 
print DEST_FILE "$type $width $node_name;\n";
}
 
print DEST_FILE "\n\n\n";
 
#/**********************************************************************/
#/* */
#/* Instantiate each component with parameters and port connections */
#/* */
#/* If the component doesn't have a instance name then this is skipped */
#/* */
#/**********************************************************************/
 
 
 
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
my($instance_name) = $i_name ->findnodes('./text()')->to_literal ;
my($component_name) = $i_name ->findnodes('../spirit:componentRef/spirit:name/text()')->to_literal ;
my($version_name) = $i_name ->findnodes('../spirit:componentRef/spirit:version/text()')->to_literal ;
 
my $variant_name = "";
if($version_name) {$variant_name = "${component_name}_${version_name}";}
else {$variant_name = "${component_name}";}
 
 
 
if($instance_name)
{
print DEST_FILE "$variant_name\n";
$first = 1;
foreach my $i_parameter ($doc->findnodes("//spirit:componentInstance[spirit:instanceName/text() = '$instance_name']/parameters/parameter/name"))
{
my($foo_name) = $i_parameter ->findnodes('./text()')->to_literal ;
my($foo_value) = $i_parameter ->findnodes('../value/text()')->to_literal ;
if($first)
{
print DEST_FILE "#( .${foo_name} (${foo_value})";
$first = 0;
}
else
{
print DEST_FILE ",\n .${foo_name} (${foo_value})";
}
}
if($first == 0)
{
print DEST_FILE ")\n";
}
print DEST_FILE "$instance_name \n (\n ";
$first = 1;
foreach my $i_xame ($doc->findnodes('//spirit:adHocConnections/spirit:adHocConnection/spirit:internalPortReference/@spirit:componentRef'))
{
my($comp_name) = $i_xame ->to_literal;
my($int_value) = $i_xame ->findnodes('../../spirit:name/text()')->to_literal ;
my($int_name) = $i_xame ->findnodes('../@spirit:portRef')->to_literal ;
my($vec_left) = $i_xame ->findnodes('../@spirit:left')->to_literal ;
my($vec_right) = $i_xame ->findnodes('../@spirit:right')->to_literal ;
if($instance_name eq $comp_name )
{
if($vec_left ne "")
{
my $vecs = "";
if($vec_left ne $vec_right ){$vecs ="[${vec_left}:${vec_right}]";}
else {$vecs ="[${vec_right}]";}
if($view eq $view_name)
{
$outfile ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${dest_dir}${view}/${destination}";
open DEST_FILE,">$outfile" or die "unable to open $outfile";
my $name = $variant;
print DEST_FILE "\n module \n\n $variant \n ";
#/**********************************************************************/
#/* */
#/* Add any and all parameters with their default values */
#/* */
#/**********************************************************************/
my $first = 1;
foreach my $i_name ($doc->findnodes('//spirit:model/spirit:modelParameters/spirit:modelParameter/spirit:value/@spirit:id'))
{
my($parameter_name) = $i_name ->to_literal;
my($parameter_default) = $i_name ->findnodes('../text()')->to_literal ;
if($first)
{
print DEST_FILE " .${int_name} (${int_value}${vecs})";
$first =0;
print DEST_FILE " #( parameter ${parameter_name}=${parameter_default}";
$first=0;
}
else
{
print DEST_FILE ",\n .${int_name} (${int_value}${vecs})";
print DEST_FILE ",\n parameter ${parameter_name}=${parameter_default}";
}
}
else
{
if($first)
}
if($first == 0)
{
print DEST_FILE ")\n";
}
#/**********************************************************************/
#/* */
#/* Now add all ports with their type, size and direction */
#/* */
#/**********************************************************************/
print DEST_FILE "\n ( \n";
$first = 1;
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:model/spirit:ports/spirit:port/name"))
{
my($port_name) = $i_name ->findnodes('./text()')->to_literal ;
my($direction) = $i_name ->findnodes('../spirit:wire/spirit:direction/text()')->to_literal ;
my($left) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:left/text()')->to_literal ;
my($right) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:right/text()')->to_literal ;
my($type) = $i_name ->findnodes('../spirit:wireTypeDefs/spirit:wireTypeDef/spirit:typeName/text()')->to_literal ;
my $width = " ";
if($left) {$width = "[${left}:${right}]"}
if($first)
{
print DEST_FILE "$direction $type $width $port_name";
$first=0;
}
else
{
print DEST_FILE ",\n$direction $type $width $port_name";
}
}
print DEST_FILE ");\n\n\n\n";
#/**********************************************************************/
#/* */
#/* Add all internal wires and regs with their sizes */
#/* */
#/**********************************************************************/
foreach my $i_name ($doc->findnodes("//spirit:component/nodes/node/name"))
{
my($node_name) = $i_name ->findnodes('./text()')->to_literal ;
my($left) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:left/text()')->to_literal ;
my($right) = $i_name ->findnodes('../spirit:wire/spirit:vector/spirit:right/text()')->to_literal ;
my($type) = $i_name ->findnodes('../spirit:wireTypeDefs/spirit:wireTypeDef/spirit:typeName/text()')->to_literal ;
my $width = " ";
if($left) {$width = "[${left}:${right}]"}
print DEST_FILE "$type $width $node_name;\n";
}
print DEST_FILE "\n\n\n";
#/**********************************************************************/
#/* */
#/* Instantiate each component with parameters and port connections */
#/* */
#/* If the component doesn't have a instance name then this is skipped */
#/* */
#/**********************************************************************/
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:componentInstances/spirit:componentInstance/spirit:instanceName"))
{
my($instance_name) = $i_name ->findnodes('./text()')->to_literal ;
my($component_name) = $i_name ->findnodes('../spirit:componentRef/spirit:name/text()')->to_literal ;
my($version_name) = $i_name ->findnodes('../spirit:componentRef/spirit:version/text()')->to_literal ;
my $variant_name = "";
if($version_name) {$variant_name = "${component_name}_${version_name}";}
else {$variant_name = "${component_name}";}
if($instance_name)
{
print DEST_FILE "$variant_name\n";
$first = 1;
foreach my $i_parameter ($doc->findnodes("//spirit:componentInstance[spirit:instanceName/text() = '$instance_name']/parameters/parameter/name"))
{
print DEST_FILE " .${int_name} (${int_value})";
$first =0;
my($foo_name) = $i_parameter ->findnodes('./text()')->to_literal ;
my($foo_value) = $i_parameter ->findnodes('../value/text()')->to_literal ;
if($first)
{
print DEST_FILE "#( .${foo_name} (${foo_value})";
$first = 0;
}
else
{
print DEST_FILE ",\n .${foo_name} (${foo_value})";
}
}
else
if($first == 0)
{
print DEST_FILE ")\n";
}
print DEST_FILE "$instance_name \n (\n ";
$first = 1;
foreach my $i_xame ($doc->findnodes('//spirit:adHocConnections/spirit:adHocConnection/spirit:internalPortReference/@spirit:componentRef'))
{
print DEST_FILE ",\n .${int_name} (${int_value})";
my($comp_name) = $i_xame ->to_literal;
my($int_value) = $i_xame ->findnodes('../../spirit:name/text()')->to_literal ;
my($int_name) = $i_xame ->findnodes('../@spirit:portRef')->to_literal ;
my($vec_left) = $i_xame ->findnodes('../@spirit:left')->to_literal ;
my($vec_right) = $i_xame ->findnodes('../@spirit:right')->to_literal ;
if($instance_name eq $comp_name )
{
if($vec_left ne "")
{
my $vecs = "";
if($vec_left ne $vec_right ){$vecs ="[${vec_left}:${vec_right}]";}
else {$vecs ="[${vec_right}]";}
if($first)
{
print DEST_FILE " .${int_name} (${int_value}${vecs})";
$first =0;
}
else
{
print DEST_FILE ",\n .${int_name} (${int_value}${vecs})";
}
}
else
{
if($first)
{
print DEST_FILE " .${int_name} (${int_value})";
$first =0;
}
else
{
print DEST_FILE ",\n .${int_name} (${int_value})";
}
}
}
}
}
}
}
print DEST_FILE ");\n\n";
print DEST_FILE ");\n\n";
}
}
#/**********************************************************************/
#/* */
#/* After all the data from the ip-xact file has been entered we now */
#/* insert any and all verilog fragments at the end before closing */
#/* the module */
#/* */
#/**********************************************************************/
foreach my $i_name ($doc->findnodes("//spirit:fileSets/spirit:fileSet/spirit:file/spirit:name"))
{
my($rtl_file) = $i_name ->findnodes('./text()')->to_literal;
my($file_type) = $i_name ->findnodes('../spirit:fileType/text()')->to_literal;
my($view_file) = $i_name ->findnodes('../../spirit:name/text()')->to_literal ;
if(($file_type eq "verilogFragment")&& (($view_file eq $view_fileset) || ($view_file eq "all")))
{
$SRCFILE ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${rtl_file}";
open(SRCFILE) or die("Could not open src file. $SRCFILE ");
foreach $line (<SRCFILE>)
{
chomp($line);
print DEST_FILE "${line}\n";
}
}
}
print DEST_FILE "\n\n\n endmodule\n\n";
}
}
 
#/**********************************************************************/
#/* */
#/* After all the data from the ip-xact file has been entered we now */
#/* insert any and all verilog fragments at the end before closing */
#/* the module */
#/* */
#/**********************************************************************/
 
 
foreach my $i_name ($doc->findnodes("//spirit:component/spirit:fileSets/spirit:fileSet/spirit:file"))
{
my($rtl_file) = $i_name ->findnodes('./spirit:name/text()')->to_literal;
my($file_type) = $i_name ->findnodes('./spirit:fileType/text()')->to_literal;
 
if($file_type eq "verilogFragment")
{
$SRCFILE ="${home}/${prefix}${lib_comp_sep}${component}${comp_xml_sep}${rtl_file}";
open(SRCFILE) or die("Could not open src file. $SRCFILE ");
foreach $line (<SRCFILE>)
{
chomp($line);
print DEST_FILE "${line}\n";
}
}
}
print DEST_FILE "\n\n\n endmodule\n\n";
}
}
 
 
1
 
/tools/sys/build_fizzim
62,6 → 62,7
 
Getopt::Long::config("require_order", "prefix=-");
GetOptions("h",
"view=s" => \$view,
"prefix=s" => \$prefix,
"lib_comp_sep=s" => \$lib_comp_sep,
"component=s" => \$component,
/tools/sys/soc_builder
163,8 → 163,6
if($version) {$variant = "${name}_${version}"}
else {$variant = "${name}"}
 
print " XXXXX Testbench $project $component $variant \n" ;
 
$cmd ="./tools/sys/build_coverage -work_site $work_site -project $project -lib_comp_sep $lib_comp_sep -component $component /n";
if (system($cmd)) {}
print "exit build_coverage \n";
/tools/sys/soc_generate
114,45 → 114,47
print "VLNV $vendor $library $name $version \n\n" ;
 
 
#/**********************************************************************/
#/* */
#/* */
#/* */
#/* */
#/* */
#/**********************************************************************/
foreach my $view ($doc->findnodes('//spirit:component/spirit:model/spirit:views/spirit:view'))
{
my($view_name) = $view->findnodes('./spirit:name/text()')->to_literal ;
 
foreach my $i_name ($doc->findnodes("//spirit:componentGenerator/spirit:name"))
{
my($gen_name) = $i_name ->findnodes('./text()')->to_literal ;
my($gen_phase) = $i_name ->findnodes('../spirit:phase/text()')->to_literal ;
my($gen_apiType) = $i_name ->findnodes('../spirit:apiType/text()')->to_literal ;
my($gen_generatorExe) = $i_name ->findnodes('../spirit:generatorExe/text()')->to_literal ;
my($gen_group) = $i_name ->findnodes('../spirit:group/text()')->to_literal ;
 
my $cmd;
 
$cmd = "$gen_generatorExe -prefix $prefix -lib_comp_sep $lib_comp_sep -component $component -comp_xml_sep $comp_xml_sep -variant $variant ";
 
print "$gen_name $gen_phase $gen_group \n";
 
foreach my $i_name ($doc->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:parameters/spirit:parameter"))
{
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
 
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}/${prefix}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}/${prefix}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "dash") {$cmd = "$cmd -${gen_param}";}
else {$cmd = "$cmd $gen_param";}
}
 
$cmd = "${cmd}\n";
print " $cmd";
if (system($cmd)) {}
print "\n";
}
 
#/**********************************************************************/
#/* */
#/* */
#/* */
#/* */
#/* */
#/**********************************************************************/
foreach my $i_name ($doc->findnodes("//spirit:componentGenerator/spirit:name"))
{
my($gen_name) = $i_name ->findnodes('./text()')->to_literal ;
my($gen_phase) = $i_name ->findnodes('../spirit:phase/text()')->to_literal ;
my($gen_apiType) = $i_name ->findnodes('../spirit:apiType/text()')->to_literal ;
my($gen_generatorExe) = $i_name ->findnodes('../spirit:generatorExe/text()')->to_literal ;
my($gen_group) = $i_name ->findnodes('../spirit:group/text()')->to_literal ;
my $cmd;
$cmd =
"$gen_generatorExe -view $view_name -prefix $prefix -lib_comp_sep $lib_comp_sep -component $component -comp_xml_sep $comp_xml_sep -variant $variant ";
foreach my $i_name ($doc->findnodes("//spirit:componentGenerator[spirit:name/text() = '$gen_name']/spirit:parameters/spirit:parameter"))
{
my($gen_param) = $i_name ->findnodes('./spirit:value/text()')->to_literal ;
my($gen_param_name) = $i_name ->findnodes('./spirit:name/text()')->to_literal ;
if ($gen_param_name eq "in_pipe") {$cmd = "$cmd <${home}/${prefix}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "out_pipe") {$cmd = "$cmd >${home}/${prefix}${lib_comp_sep}${component}/${gen_param}";}
elsif($gen_param_name eq "dash") {$cmd = "$cmd -${gen_param}";}
else {$cmd = "$cmd $gen_param";}
}
$cmd = "${cmd}\n";
print " $cmd";
if (system($cmd)) {}
print "\n";
}
}
}
 
 
/lib/cde_clock_sys/cde_clock_sys.v
185,3 → 185,4
 
endmodule
 
 
/projects/Testbench/ip/mt45w8mw12/rtl/xml/mt45w8mw12.xml
51,11 → 51,53
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
69,6 → 111,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
156,26 → 208,10
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
 
</spirit:component>
/projects/Testbench/ip/mt45w8mw12/rtl/verilog/top File deleted
/projects/Testbench/ip/mt45w8mw12/rtl/verilog/sim/top
0,0 → 1,75
 
 
module mt45w8mw12
#(
parameter ADDR_BITS = 23,
parameter DQ_BITS = 16,
parameter MEM_BITS = 16,
parameter INIT_FILE_E = "NONE",
parameter INIT_FILE_O = "NONE"
 
)
(
input wire clk,
input wire adv_n,
input wire cre,
output wire o_wait,
input wire ce_n,
input wire oe_n,
input wire we_n,
input wire lb_n,
input wire ub_n,
input wire [ADDR_BITS-1 : 0] addr,
inout wire [DQ_BITS-1 : 0] dq
);
 
reg [7:0] memoryl [1<<MEM_BITS-1:0];
reg [7:0] memoryu [1<<MEM_BITS-1:0];
reg [DQ_BITS-1 : 0] dq_out;
// Load any rom images
initial
begin
if( INIT_FILE_E == "NONE")
begin
end
else $readmemh(INIT_FILE_E, memoryl);
end
 
initial
begin
if( INIT_FILE_O == "NONE")
begin
end
else $readmemh(INIT_FILE_O, memoryu);
end
 
 
// Write Memory
 
always@(*)
if(!ce_n && !we_n && !lb_n) memoryl[addr] = dq[7:0];
 
always@(*)
if(!ce_n && !we_n && !ub_n) memoryu[addr] = dq[15:8];
 
// Read Memory
 
always@(*) dq_out[7:0] = memoryl[addr];
always@(*) dq_out[15:8] = memoryu[addr];
// Tristate output
assign dq = (!ce_n && !oe_n) ? dq_out[DQ_BITS-1:0]: {DQ_BITS{1'bz}};
 
 
endmodule
 
 
/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml
45,12 → 45,59
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
64,6 → 111,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
143,28 → 200,9
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/ps2_host/rtl/verilog/top File deleted
/projects/Testbench/ip/ps2_host/rtl/verilog/sim/top
0,0 → 1,179
 
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* ps2 host model for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
module ps2_host
 
(
input wire clk,
input wire reset,
input wire busy,
 
inout wire [7:0] rx_data,
input wire rx_read,
input wire rx_full,
input wire rx_parity_error,
input wire rx_parity_rcv,
input wire rx_parity_cal,
input wire rx_frame_error,
inout wire tx_ack_error,
 
output reg rx_clr,
output reg [7:0] tx_data,
output reg tx_write
);
 
 
reg exp_tx_ack_err;
reg mask_tx_ack_err;
 
reg [7:0] exp_rcv_byte;
reg [7:0] mask_rcv_byte;
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
always@(posedge clk)
if(reset)
begin
tx_data <= 8'h00;
tx_write <= 1'b0;
rx_clr <= 1'b0;
exp_tx_ack_err <= 1'b0;
mask_tx_ack_err <= 1'b0;
exp_rcv_byte <= 8'h00;
mask_rcv_byte <= 8'h00;
 
 
end
 
 
task clear_rx_host;
begin
rx_clr <= 1'b1;
next(1);
rx_clr <= 1'b0;
end
endtask
 
 
task send_byte;
input [7:0] byte_out;
begin
$display("%t %m %2h",$realtime ,byte_out );
tx_data <= byte_out;
next(1);
tx_write <= 1'b1;
next(1);
tx_write <= 1'b0;
next(1);
while(busy) next(1);
mask_tx_ack_err <= 1'b1;
next(1);
mask_tx_ack_err <= 1'b0;
end
endtask // send_byte
 
 
 
io_probe
#( .MESG("ps2_host tx_ack error")
)
tx_ack_err_tpb
(
.clk ( clk ),
.drive_value ( 1'bz ),
.expected_value ( exp_tx_ack_err ),
.mask ( mask_tx_ack_err ),
.signal ( tx_ack_error )
);
 
 
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rcv_byte <= byte_in;
while(!rx_read) next(1);
$display("%t checking %h",$realtime,byte_in);
mask_rcv_byte <= 8'hff;
next(1);
mask_rcv_byte <= 8'h00;
end
endtask
 
io_probe
#( .MESG("ps2_host receive error"),
.WIDTH (8)
)
rcv_byte_tpb
(
.clk ( clk ),
.drive_value ( {8{1'bz}} ),
.expected_value ( exp_rcv_byte ),
.mask ( mask_rcv_byte ),
.signal ( rx_data )
);
 
 
endmodule
/projects/Testbench/ip/micro_bus_model/rtl/xml/micro_bus_model.xml
51,11 → 51,54
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
69,6 → 112,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
130,23 → 183,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/micro_bus_model/rtl/verilog/top File deleted
/projects/Testbench/ip/micro_bus_model/rtl/verilog/sim/top
0,0 → 1,138
 
module micro_bus_model
#(parameter OUT_DELAY = 15,
parameter OUT_WIDTH = 10
)
 
(
input wire clk,
input wire reset,
 
output reg [15:0] addr,
output reg [7:0] wdata,
output reg rd,
output reg wr,
 
inout wire [7:0] rdata
);
 
reg [7:0] exp_rdata;
reg [7:0] mask_rdata;
 
always@(posedge clk)
if(reset)
begin
addr <= 16'h0000;
wdata <= 8'h00;
wr <= 1'b0;
rd <= 1'b0;
exp_rdata <= 8'h00;
mask_rdata <= 8'h00;
end
 
 
 
io_probe
#(.MESG ("micro rdata Error"),
.WIDTH (8),
.RESET ({8{1'bz}}),
.OUT_DELAY (OUT_DELAY),
.OUT_WIDTH (OUT_WIDTH)
)
rdata_tpb
(
.clk ( clk ),
.drive_value (8'bzzzzzzzz ),
.expected_value ( exp_rdata ),
.mask ( mask_rdata ),
.signal ( rdata )
);
 
 
// Tasks
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
// write cycle
task u_write;
input [15:0] a;
input [7:0] d;
begin
 
$display("%t %m cycle %x %x",$realtime,a,d );
addr <= a;
wdata <= d;
rd <= 1'b0;
wr <= 1'b1;
next(1);
wr <= 1'b0;
next(1);
 
end
endtask
// read cycle
task u_read;
input [15:0] a;
output [7:0] d;
begin
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
next(2);
d <= rdata;
$display("%t %m cycle %x %x",$realtime,a,rdata );
rd <= 1'b1;
next(1);
rd <= 1'b0;
end
endtask
// Compare cycle (read data from location and compare with expected data)
task u_cmp;
input [15:0] a;
input [7:0] d_exp;
 
begin
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
exp_rdata <= d_exp;
next(1);
mask_rdata <= 8'hff;
 
next(1);
$display("%t %m cycle %x %x",$realtime,a,d_exp );
mask_rdata <= 8'h00;
rd <= 1'b0;
end
endtask
 
 
 
 
endmodule
/projects/Testbench/ip/clock_gen/rtl/verilog/top File deleted
/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml
46,17 → 46,24
 
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>leaf_maker</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:fileSets>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
70,6 → 77,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
102,25 → 119,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/projects/Testbench/ip/clock_gen/rtl/gen/sim/clock_gen.v
0,0 → 1,138
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Clock and Reset generator for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
`timescale 1ns/1ns
 
module clock_gen
#(parameter PERIOD=10,
parameter TIMEOUT=0
)
(output reg clk,
output reg reset
);
 
 
 
`ifndef SYNTHESIS
reg failed;
reg [31:0] fail_count;
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
task reset_on;
reset = 1;
endtask // reset_on
 
 
task automatic fail;
input [799:0] message;
begin
failed = 1;
fail_count = fail_count+1;
$display("%t Simulation FAILURE: %s ",$realtime,message );
end
endtask
 
task reset_off;
begin
reset = 0;
end
endtask // reset_off
 
 
task exit;
begin
if(failed)
begin
$display("%t Sim over: ERROR %d failures",$realtime ,fail_count );
end
else
begin
$display("%t Sim over: PASSED",$realtime );
end // else: !if(failed)
$dumpflush;
$finish;
end
endtask
 
 
initial
begin
clk=0;
reset=1;
failed=0;
fail_count =32'h00000000;
end
 
always
#(PERIOD/2) clk = !clk;
 
 
 
initial
begin
if(TIMEOUT)
begin
next(TIMEOUT);
$display("%t Sim over :ERROR TIMEOUT",$realtime );
$finish;
end
end
 
`endif
 
endmodule
 
 
 
/projects/Testbench/ip/clock_gen/rtl/gen/syn/clock_gen.v
0,0 → 1,62
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Clock and Reset generator for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
`timescale 1ns/1ns
 
module clock_gen
#(parameter PERIOD=10,
parameter TIMEOUT=0
)
(output reg clk,
output reg reset
);
 
 
 
 
endmodule
 
 
 
/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml
47,16 → 47,106
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>verilog_maker</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>leaf_maker</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.tasks</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
 
 
 
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
70,6 → 160,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
<spirit:modelParameters>
110,27 → 211,8
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/ps2_model/rtl/verilog/top File deleted
/projects/Testbench/ip/ps2_model/rtl/verilog/top.rtl
0,0 → 1,258
 
 
//********************************************************************
//*** TAP Controller State Machine
//********************************************************************
 
// TAP state parameters
parameter RESET = 2'b00,
WAIT_63US = 2'b01,
CLOCK = 2'b10,
IDLE = 2'b11;
 
 
reg device_rx_parity;
reg [7:0] device_rx_data;
 
wire prb_device_rx_parity;
wire [7:0] prb_device_rx_data;
wire device_rx_read;
reg ps2_data_out;
reg dev_host;
reg [1:0] tap_state, next_tap_state;
reg [9:0] count;
reg clk_out;
reg [4:0] bit_cnt;
reg ack;
reg [10:0] frame;
reg clk_fall;
reg clk_rise;
reg device_write;
reg [7:0] device_tx_data;
reg device_tx_parity;
reg device_ack;
reg device_stop;
reg [7:0] exp_device_rx_data;
reg [7:0] mask_device_rx_data;
reg exp_device_rx_parity;
reg mask_device_rx_parity;
 
 
 
 
 
 
assign prb_device_rx_parity = device_rx_parity;
assign prb_device_rx_data = device_rx_data;
 
 
 
 
 
 
 
io_probe
#(.MESG ( "ps2 data receive error"),
.WIDTH ( 8))
device_rx_data_tpb (
.clk ( clk ),
.drive_value (8'bzzzzzzzz ),
.expected_value ( exp_device_rx_data ),
.mask ( mask_device_rx_data ),
.signal ( prb_device_rx_data )
);
 
 
 
io_probe
#(.MESG ( "ps2 parity receive error"))
device_rx_parity_tpb (
.clk ( clk ),
.drive_value (1'bz ),
.expected_value ( exp_device_rx_parity ),
.mask ( mask_device_rx_parity ),
.signal ( prb_device_rx_parity )
);
 
 
assign ps2_clk = clk_out ? 1'b0 : 1'bz ;
assign ps2_data = ps2_data_out ? 1'b0 : 1'bz ;
 
 
 
 
 
 
always @(posedge clk or posedge reset )
begin
if (reset)
begin
tap_state <= RESET;
ps2_data_out <= 1'b0;
end
else
begin
tap_state <= next_tap_state;
ps2_data_out <= ( (tap_state == CLOCK) && (dev_host? frame[0] : ack) );
end
end
 
 
 
always @(posedge clk or posedge reset )
begin
if (reset) dev_host <= 1'b0;
else
if( device_write) dev_host <= 1'b1;
else
if( bit_cnt == 5'h16 ) dev_host <= 1'b0;
else dev_host <= dev_host ;
end
 
 
always@(*) ack = (((bit_cnt == 5'h14)|| (bit_cnt == 5'h15)) && device_ack ) ;
 
 
 
// next state decode for tap controller
always @(*)
begin
if(device_write) next_tap_state = CLOCK;
else
case (tap_state) // synopsys parallel_case
RESET:
begin
next_tap_state = ps2_clk ? RESET : WAIT_63US ;
end
 
WAIT_63US:
begin
next_tap_state = ps2_clk ? CLOCK : WAIT_63US ;
end
 
CLOCK:
begin
next_tap_state = ((bit_cnt == 5'h16)&& (count == 10'h000)) ? IDLE : CLOCK;
end
 
IDLE:
begin
next_tap_state = ps2_data ? IDLE : WAIT_63US;
end
endcase
end
 
 
always @(posedge clk or posedge reset )
begin
if (reset)
begin
count <= CLKCNT;
clk_out <= 1'b0;
bit_cnt <= 5'h00;
clk_fall <= 1'b0;
clk_rise <= 1'b0;
end
else
if((next_tap_state != CLOCK))
begin
count <= CLKCNT;
clk_out <= 1'b0;
bit_cnt <= 5'h00;
clk_fall <= 1'b0;
clk_rise <= 1'b0;
end
else
if((count == 10'h000) )
begin
count <= CLKCNT;
clk_out <= !clk_out;
bit_cnt <= bit_cnt+5'b0001;
clk_fall <= !clk_out;
clk_rise <= clk_out;
end
else
begin
count <= count - 10'h001;
clk_out <= clk_out;
bit_cnt <= bit_cnt;
clk_fall <= 1'b0;
clk_rise <= 1'b0;
end
end
 
 
 
always @(posedge clk or posedge reset )
begin
if (reset)
begin
frame <= {device_ack,10'h000};
end
else
if(device_write)
begin
frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1};
end
else
if((tap_state == WAIT_63US) || (tap_state == IDLE))
begin
frame <= {device_ack,10'h000};
end
else
if((tap_state == CLOCK) && clk_fall && !dev_host ) frame <= { ps2_data,frame[10:1]};
else
if((tap_state == CLOCK) && clk_rise && dev_host ) frame <= { 1'b0,frame[10:1]};
else frame <= frame;
end
 
 
 
always @(posedge clk or posedge reset )
begin
if (reset)
begin
device_rx_data <= 8'h00;
device_rx_parity <= 1'b0;
end
else
if(tap_state == WAIT_63US)
begin
device_rx_data <= 8'h00;
device_rx_parity <= 1'b0;
end
else
if((bit_cnt == 5'h12) && clk_rise)
begin
device_rx_data <= frame[10:3];
device_rx_parity <= ps2_data;
end
else
begin
device_rx_data <= device_rx_data;
device_rx_parity <= device_rx_parity;
end
 
end
 
 
assign device_rx_read = (bit_cnt == 5'h13) && !dev_host && clk_fall;
 
/projects/Testbench/ip/ps2_model/rtl/verilog/top.tasks
0,0 → 1,82
 
 
 
 
 
 
 
initial
begin
device_write <= 1'b0;
device_tx_data <= 8'h00;
device_tx_parity <= 1'b0;
device_ack <= 1'b1;
device_stop <= 1'b1;
 
exp_device_rx_data <= 8'h00;
mask_device_rx_data <= 8'h00;
exp_device_rx_parity <= 1'b0;
mask_device_rx_parity <= 1'b0;
end
 
 
task next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(tap_state != IDLE) next(1);
$display("%t %m %2h parity %b",$realtime ,byte_out,device_tx_parity );
device_tx_data <= byte_out;
next(1);
device_write <= 1'b1;
next(1);
device_write <= 1'b0;
end
endtask // send_byte
 
 
 
 
 
task rcv_byte;
input [7:0] byte_in;
input parity;
begin
 
exp_device_rx_data <= byte_in;
exp_device_rx_parity <= parity;
 
while(!device_rx_read) next(1);
$display("%t checking %h %b",$realtime,byte_in,parity);
mask_device_rx_data <= 8'hff;
mask_device_rx_parity <= 1'b1;
next(1);
 
mask_device_rx_data <= 8'h00;
mask_device_rx_parity <= 1'b0;
 
end
endtask
 
always@(posedge clk)
if( device_rx_read)
$display ("%t %m device rec %h parity %b",$realtime,device_rx_data,device_rx_parity);
 
always@(posedge clk)
if(device_write)
$display ("%t %m device send %h parity %b stop %b ",$realtime,device_tx_data,device_tx_parity,device_stop);
 
 
/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml
45,12 → 45,55
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
64,6 → 107,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
113,26 → 167,9
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/uart_host/rtl/verilog/top File deleted
/projects/Testbench/ip/uart_host/rtl/verilog/sim/top
0,0 → 1,211
 
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* uart host model for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
module uart_host (
input wire clk,
input wire reset,
output reg parity_enable,
output reg txd_parity,
output reg txd_force_parity,
output reg [7:0] txd_data_in,
input wire txd_buffer_empty,
output reg txd_load,
output reg txd_break,
output reg rxd_parity,
output reg rxd_force_parity,
output reg rxd_data_avail_stb,
inout wire [7:0] rxd_data_out,
input wire rxd_data_avail,
inout wire rxd_stop_error,
inout wire rxd_parity_error
);
 
reg exp_rxd_stop_error;
reg exp_rxd_parity_error;
reg [7:0] exp_rxd_data_out;
 
reg mask_rxd_stop_error;
reg mask_rxd_parity_error;
reg [7:0] mask_rxd_data_out;
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
always@(posedge clk)
if(reset)
begin
parity_enable <= 1'b0;
txd_data_in <= 8'h00;
txd_parity <= 1'b0;
txd_force_parity <= 1'b0;
txd_load <= 1'b0;
txd_break <= 1'b0;
rxd_parity <= 1'b0;
rxd_force_parity <= 1'b0;
rxd_data_avail_stb <= 1'b0;
exp_rxd_stop_error <= 1'b0;
exp_rxd_parity_error <= 1'b0;
exp_rxd_data_out <= 8'h00;
 
mask_rxd_stop_error <= 1'b0;
mask_rxd_parity_error <= 1'b0;
mask_rxd_data_out <= 8'h00;
 
end
 
 
task clear_rx_host;
begin
next(1);
end
endtask
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out);
txd_data_in <= byte_out;
next(1);
txd_load <= 1'b1;
next(1);
txd_load <= 1'b0;
next(1);
end
endtask // send_byte
 
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rxd_data_out <= byte_in;
while(!rxd_data_avail) next(1);
$display("%t %m checking %h",$realtime,byte_in);
mask_rxd_stop_error <= 1'b1;
mask_rxd_parity_error <= 1'b1;
mask_rxd_data_out <= 8'hff;
next(1);
mask_rxd_stop_error <= 1'b0;
mask_rxd_parity_error <= 1'b0;
mask_rxd_data_out <= 8'h00;
rxd_data_avail_stb <= 1'b1;
next(1);
rxd_data_avail_stb <= 1'b0;
next(1);
end
endtask
 
io_probe
#(.MESG("uart_host receive error"),
.WIDTH(8))
rxd_data_out_prb
(
.clk ( clk ),
.drive_value (8'bzzzzzzzz ),
.expected_value ( exp_rxd_data_out ),
.mask ( mask_rxd_data_out ),
.signal ( rxd_data_out )
 
);
 
 
 
 
io_probe
#(.MESG("uart_host stop error"))
rxd_stop_error_prb
(
.clk ( clk ),
.drive_value (1'bz ),
.expected_value ( exp_rxd_stop_error ),
.mask ( mask_rxd_stop_error ),
.signal ( rxd_stop_error )
 
);
 
 
 
 
io_probe
#(.MESG("uart_host parity error"))
rxd_parity_error_prb
(
.clk ( clk ),
.drive_value (1'bz ),
.expected_value ( exp_rxd_parity_error ),
.mask ( mask_rxd_parity_error ),
.signal ( rxd_parity_error )
 
);
 
 
 
endmodule
/projects/Testbench/ip/uart_host/rtl/verilog/syn/top
0,0 → 1,211
 
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* uart host model for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
module uart_host (
input wire clk,
input wire reset,
output reg parity_enable,
output reg txd_parity,
output reg txd_force_parity,
output reg [7:0] txd_data_in,
input wire txd_buffer_empty,
output reg txd_load,
output reg txd_break,
output reg rxd_parity,
output reg rxd_force_parity,
output reg rxd_data_avail_stb,
inout wire [7:0] rxd_data_out,
input wire rxd_data_avail,
inout wire rxd_stop_error,
inout wire rxd_parity_error
);
 
reg exp_rxd_stop_error;
reg exp_rxd_parity_error;
reg [7:0] exp_rxd_data_out;
 
reg mask_rxd_stop_error;
reg mask_rxd_parity_error;
reg [7:0] mask_rxd_data_out;
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
always@(posedge clk)
if(reset)
begin
parity_enable <= 1'b0;
txd_data_in <= 8'h00;
txd_parity <= 1'b0;
txd_force_parity <= 1'b0;
txd_load <= 1'b0;
txd_break <= 1'b0;
rxd_parity <= 1'b0;
rxd_force_parity <= 1'b0;
rxd_data_avail_stb <= 1'b0;
exp_rxd_stop_error <= 1'b0;
exp_rxd_parity_error <= 1'b0;
exp_rxd_data_out <= 8'h00;
 
mask_rxd_stop_error <= 1'b0;
mask_rxd_parity_error <= 1'b0;
mask_rxd_data_out <= 8'h00;
 
end
 
 
task clear_rx_host;
begin
next(1);
end
endtask
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out);
txd_data_in <= byte_out;
next(1);
txd_load <= 1'b1;
next(1);
txd_load <= 1'b0;
next(1);
end
endtask // send_byte
 
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rxd_data_out <= byte_in;
while(!rxd_data_avail) next(1);
$display("%t %m checking %h",$realtime,byte_in);
mask_rxd_stop_error <= 1'b1;
mask_rxd_parity_error <= 1'b1;
mask_rxd_data_out <= 8'hff;
next(1);
mask_rxd_stop_error <= 1'b0;
mask_rxd_parity_error <= 1'b0;
mask_rxd_data_out <= 8'h00;
rxd_data_avail_stb <= 1'b1;
next(1);
rxd_data_avail_stb <= 1'b0;
next(1);
end
endtask
 
io_probe
#(.MESG("uart_host receive error"),
.WIDTH(8))
rxd_data_out_prb
(
.clk ( clk ),
.drive_value (8'bzzzzzzzz ),
.expected_value ( exp_rxd_data_out ),
.mask ( mask_rxd_data_out ),
.signal ( rxd_data_out )
 
);
 
 
 
 
io_probe
#(.MESG("uart_host stop error"))
rxd_stop_error_prb
(
.clk ( clk ),
.drive_value (1'bz ),
.expected_value ( exp_rxd_stop_error ),
.mask ( mask_rxd_stop_error ),
.signal ( rxd_stop_error )
 
);
 
 
 
 
io_probe
#(.MESG("uart_host parity error"))
rxd_parity_error_prb
(
.clk ( clk ),
.drive_value (1'bz ),
.expected_value ( exp_rxd_parity_error ),
.mask ( mask_rxd_parity_error ),
.signal ( rxd_parity_error )
 
);
 
 
 
endmodule
/projects/Testbench/ip/micro_bus16_model/rtl/xml/micro_bus16_model.xml
51,11 → 51,50
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
69,6 → 108,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
141,23 → 190,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/micro_bus16_model/rtl/verilog/top File deleted
/projects/Testbench/ip/micro_bus16_model/rtl/verilog/sim/top
0,0 → 1,229
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Microprocessor bus functional model (BFM) for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
 
 
 
module micro_bus16_model
#(parameter OUT_DELAY = 15,
parameter OUT_WIDTH = 10
)
 
(
input wire clk,
input wire reset,
 
output reg [23:0] addr,
output reg [15:0] wdata,
output reg [1:0] cs,
output reg rd,
output reg wr,
output reg ub,
output reg lb,
 
inout wire [15:0] rdata
);
 
reg [15:0] exp_rdata;
reg [15:0] mask_rdata;
 
always@(posedge clk)
if(reset)
begin
addr <= 24'h0000;
wdata <= 16'h0000;
wr <= 1'b0;
rd <= 1'b0;
cs <= 2'b00;
ub <= 1'b0;
lb <= 1'b0;
exp_rdata <= 16'h0000;
mask_rdata <= 16'h0000;
end
 
 
 
io_probe
#(.MESG ("micro rdata Error"),
.WIDTH (16),
.RESET ({16{1'bz}}),
.OUT_DELAY (OUT_DELAY),
.OUT_WIDTH (OUT_WIDTH)
)
rdata_tpb
(
.clk ( clk ),
.drive_value (16'bzzzzzzzzzzzzzzzz ),
.expected_value ( exp_rdata ),
.mask ( mask_rdata ),
.signal ( rdata )
);
 
 
// Tasks
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
 
// idle cycle
task u_idle;
begin
addr <= 24'h000000;
wdata <= 16'h0000;
rd <= 1'b0;
cs <= 2'b00;
wr <= 1'b0;
ub <= 1'b0;
lb <= 1'b0;
mask_rdata <= 16'h0000;
next(1);
end
endtask
 
 
// write cycle
task u_write;
input [23:0] a;
input [15:0] d;
begin
 
$display("%t %m cycle %x %x",$realtime,a,d );
addr <= a;
wdata <= d;
rd <= 1'b0;
cs <= 2'b01;
wr <= 1'b1;
ub <= 1'b1;
lb <= 1'b1;
next(4);
rd <= 1'b0;
cs <= 2'b00;
wr <= 1'b0;
ub <= 1'b0;
lb <= 1'b0;
next(1);
end
endtask
// read cycle
task u_read;
input [23:0] a;
output [15:0] d;
begin
addr <= a;
wdata <= 16'h0000;
rd <= 1'b1;
cs <= 2'b01;
wr <= 1'b0;
ub <= 1'b1;
lb <= 1'b1;
next(4);
d <= rdata;
$display("%t %m cycle %x %x",$realtime,a,rdata );
rd <= 1'b1;
next(1);
rd <= 1'b0;
ub <= 1'b0;
lb <= 1'b0;
cs <= 2'b00;
next(1);
end
endtask
// Compare cycle (read data from location and compare with expected data)
task u_cmp;
input [23:0] a;
input [15:0] d_exp;
 
begin
addr <= a;
wdata <= 16'h0000;
rd <= 1'b1;
ub <= 1'b1;
lb <= 1'b1;
cs <= 2'b01;
wr <= 1'b0;
exp_rdata <= d_exp;
next(5);
mask_rdata <= 16'hffff;
 
next(1);
$display("%t %m cycle %x %x",$realtime,a,d_exp );
mask_rdata <= 16'h0000;
rd <= 1'b0;
ub <= 1'b0;
lb <= 1'b0;
cs <= 2'b00;
next(1);
end
endtask
 
 
 
 
endmodule
/projects/Testbench/ip/template/rtl/xml/xxx.xml
52,10 → 52,52
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
</spirit:componentGenerator>
 
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
69,6 → 111,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
107,24 → 159,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml
47,16 → 47,139
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>verilog_maker</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
 
<spirit:componentGenerator>
<spirit:name>leaf_maker</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
 
 
<spirit:fileSet>
<spirit:name>all</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_rcvr</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_xmit</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/divider</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.tasks</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
 
 
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
70,6 → 193,17
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
113,44 → 247,12
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_rcvr</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/serial_xmit</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/divider</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:componentInstances>
 
<spirit:componentInstance>
/projects/Testbench/ip/uart_model/rtl/verilog/top
1,64 → 1,23
 
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* uart device model for simulations */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
module
 
`timescale 1ns/1ns
uart_model
#( parameter CLKCNT=4'h5,
parameter SIZE=4)
 
module uart_model
#(parameter CLKCNT = 4'h5,
parameter SIZE = 4)
(
input wire clk,
input wire reset,
input wire txd_in,
output wire rxd_out);
 
(
input wire clk,
input wire reset,
input wire txd_in,
output wire rxd_out
 
);
 
 
 
 
 
 
reg rx_parity_enable; // 0 = no parity bit sent; 1= parity bit sent
reg rx_parity ;
reg rx_force_parity ;
136,56 → 95,6
 
 
task next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
 
 
task wait_tx;
 
begin
while(!txd_buffer_empty) next(1);
end
endtask // wait_tx
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out );
txd_data_in = byte_out;
next(1);
txd_load = 1'b1;
next(1);
txd_load = 1'b0;
next(1);
end
endtask // send_byte
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rx_shift_buffer <= byte_in;
while(!rx_frame_rdy) next(1);
$display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in);
mask_rx_frame_err <= 1'b1;
mask_rx_parity_err <= 1'b1;
mask_rx_shift_buffer <= 8'hff;
next(1);
mask_rx_frame_err <= 1'b0;
mask_rx_parity_err <= 1'b0;
mask_rx_shift_buffer <= 8'h00;
end
endtask
 
 
wire [7:0] prb_rx_shift_buffer;
wire prb_rx_frame_err;
wire prb_rx_parity_err;
402,7 → 311,64
 
 
 
 
endmodule
 
task next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
 
 
task wait_tx;
 
begin
while(!txd_buffer_empty) next(1);
end
endtask // wait_tx
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out );
txd_data_in = byte_out;
next(1);
txd_load = 1'b1;
next(1);
txd_load = 1'b0;
next(1);
end
endtask // send_byte
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rx_shift_buffer <= byte_in;
while(!rx_frame_rdy) next(1);
$display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in);
mask_rx_frame_err <= 1'b1;
mask_rx_parity_err <= 1'b1;
mask_rx_shift_buffer <= 8'hff;
next(1);
mask_rx_frame_err <= 1'b0;
mask_rx_parity_err <= 1'b0;
mask_rx_shift_buffer <= 8'h00;
end
endtask
 
 
 
 
 
 
 
endmodule
 
/projects/Testbench/ip/uart_model/rtl/verilog/top.rtl
0,0 → 1,295
 
 
reg rx_parity_enable; // 0 = no parity bit sent; 1= parity bit sent
reg rx_parity ;
reg rx_force_parity ;
reg rx_stop_value; // value out for stop bit
reg rx_start_detect;
reg [7:0] rx_shift_buffer;
reg rx_parity_calc;
reg rx_parity_samp;
reg rx_parity_error;
reg rx_frame_err;
reg [7:0] exp_rx_shift_buffer;
reg exp_rx_parity_err;
reg exp_rx_frame_err;
reg [7:0] mask_rx_shift_buffer;
reg mask_rx_parity_err;
reg mask_rx_frame_err;
reg rx_frame_rdy;
reg rx_baud_enable;
wire rx_stop_cnt;
wire rx_last_cnt;
wire [7:0] next_rx_shift_buffer;
wire next_rx_parity_calc;
wire next_rx_parity_samp;
wire next_rx_frame_err;
reg rxd_pad_sig;
reg [1:0] rx_rdy_del;
reg [SIZE-1:0] rx_baudgen;
reg edge_enable;
reg [SIZE-1:0] divide_cnt;
 
 
wire xmit_enable;
reg txd_parity_enable;
reg txd_force_parity;
reg txd_parity;
reg txd_load;
reg txd_break;
reg [7:0] txd_data_in;
wire txd_buffer_empty;
//
// watch for start bit
//
 
always@(posedge clk)
if(reset)
begin
rx_parity_enable <= 1'b0;
rx_parity <= 1'b0;
rx_force_parity <= 1'b0;
rx_stop_value <= 1'b1;
exp_rx_frame_err <= 1'b0;
exp_rx_parity_err <= 1'b0;
exp_rx_shift_buffer <= 8'h00;
mask_rx_frame_err <= 1'b0;
mask_rx_parity_err <= 1'b0;
mask_rx_shift_buffer <= 8'h00;
txd_parity_enable <= 1'b0;
txd_force_parity <= 1'b0;
txd_parity <= 1'b0;
txd_load <= 1'b0;
txd_break <= 1'b0;
txd_data_in <= 8'h00;
end
 
 
 
wire [7:0] prb_rx_shift_buffer;
wire prb_rx_frame_err;
wire prb_rx_parity_err;
 
assign prb_rx_shift_buffer = rx_shift_buffer;
assign prb_rx_frame_err = rx_frame_err;
assign prb_rx_parity_err = rx_parity_error;
 
 
io_probe
#(.MESG ("uart data receive error"),
.WIDTH (8)
)
rx_shift_buffer_prb
(
.clk ( clk ),
.drive_value (8'bzzzzzzzz),
.expected_value( exp_rx_shift_buffer),
.mask ( mask_rx_shift_buffer),
.signal ( prb_rx_shift_buffer)
);
 
 
io_probe
#(.MESG ("uart parity error"))
rx_parity_err_prb
(
.clk ( clk ),
.drive_value (1'bz),
.expected_value( exp_rx_parity_err),
.mask ( mask_rx_parity_err),
.signal ( prb_rx_parity_err)
);
 
 
 
 
 
 
 
 
always@(posedge clk)
if(reset) rx_baudgen <= CLKCNT;
else
if(rx_baudgen == 4'h0) rx_baudgen <= CLKCNT;
else rx_baudgen <= rx_baudgen - 1'h1;
 
 
always@(posedge clk)
if(reset) edge_enable <= 1'b0;
else edge_enable <= (rx_baudgen == {SIZE{1'b0}});
 
 
 
 
always@(posedge clk)
if(reset) rxd_pad_sig <= 1'b1;
else rxd_pad_sig <= txd_in;
 
always@(posedge clk)
if(reset) rx_start_detect <= 1'b0;
else
if(rx_start_detect)
begin
if(rx_stop_cnt && edge_enable ) rx_start_detect <= !rxd_pad_sig;
else
if(rx_last_cnt) rx_start_detect <= 1'b0;
else rx_start_detect <= 1'b1;
end
else
if(!rxd_pad_sig ) rx_start_detect <= 1'b1;
else rx_start_detect <= rx_start_detect;
 
 
always@(posedge clk)
if(reset)
begin
rx_frame_rdy <= 1'b0;
rx_rdy_del <= 2'b00;
end
else
begin
rx_frame_rdy <= rx_rdy_del[1] ;
rx_rdy_del <= {rx_rdy_del[0],rx_last_cnt};
end
 
uart_model_serial_rcvr
#(.WIDTH(8), .SIZE(4) )
serial_rcvr
(
.clk ( clk ),
.reset ( reset ),
.edge_enable ( rx_baud_enable ),
.parity_enable ( rx_parity_enable ),
.parity_type ( {rx_force_parity, rx_parity } ),
.stop_cnt ( rx_stop_cnt ),
.last_cnt ( rx_last_cnt ),
.stop_value ( rx_stop_value ),
.ser_in ( txd_in ),
.shift_buffer ( next_rx_shift_buffer ),
.parity_calc ( next_rx_parity_calc ),
.parity_samp ( next_rx_parity_samp ),
.frame_err ( next_rx_frame_err )
);
 
 
 
 
 
 
always@(posedge clk)
if( reset || (!rx_start_detect)) rx_baud_enable <= 1'b0;
else
if(!edge_enable) rx_baud_enable <= 1'b0;
else rx_baud_enable <= ( divide_cnt == 4'b1000 );
 
 
 
always@(posedge clk)
if( reset || (!rx_start_detect)) divide_cnt <= 4'b1111;
else
if(!edge_enable) divide_cnt <= divide_cnt;
else
if(!(|divide_cnt)) divide_cnt <= 4'b1111;
else divide_cnt <= divide_cnt - 'b1;
 
 
 
 
 
always@(posedge clk)
if(reset)
begin
rx_shift_buffer <= 8'h00;
rx_parity_calc <= 1'b0;
rx_parity_samp <= 1'b0;
rx_parity_error <= 1'b0;
rx_frame_err <= 1'b0;
end
else
if(rx_last_cnt )
begin
rx_shift_buffer <= next_rx_shift_buffer;
rx_parity_calc <= next_rx_parity_calc;
rx_parity_samp <= next_rx_parity_samp;
rx_parity_error <= (next_rx_parity_samp ^ next_rx_parity_calc) && rx_parity_enable;
rx_frame_err <= next_rx_frame_err;
end
else
begin
rx_shift_buffer <= rx_shift_buffer;
rx_parity_calc <= rx_parity_calc;
rx_parity_samp <= rx_parity_samp;
rx_parity_error <= rx_parity_error;
rx_frame_err <= rx_frame_err;
end
 
///////////////// Xmit
 
 
 
 
 
 
 
 
 
uart_model_divider
#(.SIZE(4))
x_divider (
.clk ( clk ),
.reset ( reset ),
.divider_in ( 4'b1111 ),
.enable ( edge_enable ),
.divider_out ( xmit_enable )
);
 
 
 
 
uart_model_serial_xmit
serial_xmit (
.clk ( clk ),
.reset ( reset ),
.edge_enable ( xmit_enable ),
.parity_enable ( txd_parity_enable ),
.two_stop_enable ( 1'b0 ),
.parity_type ( {txd_force_parity, txd_parity } ),
.load ( txd_load ),
.start_value ( 1'b0 ),
.stop_value (!txd_break ),
.data ( txd_data_in ),
.buffer_empty ( txd_buffer_empty ),
.ser_out ( rxd_out )
);
 
 
 
 
 
/projects/Testbench/ip/uart_model/rtl/verilog/top.tasks
0,0 → 1,56
 
 
task next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
 
 
task wait_tx;
 
begin
while(!txd_buffer_empty) next(1);
end
endtask // wait_tx
 
 
task send_byte;
input [7:0] byte_out;
 
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out );
txd_data_in = byte_out;
next(1);
txd_load = 1'b1;
next(1);
txd_load = 1'b0;
next(1);
end
endtask // send_byte
 
 
task rcv_byte;
input [7:0] byte_in;
begin
exp_rx_shift_buffer <= byte_in;
while(!rx_frame_rdy) next(1);
$display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in);
mask_rx_frame_err <= 1'b1;
mask_rx_parity_err <= 1'b1;
mask_rx_shift_buffer <= 8'hff;
next(1);
mask_rx_frame_err <= 1'b0;
mask_rx_parity_err <= 1'b0;
mask_rx_shift_buffer <= 8'h00;
end
endtask
 
 
 
 
/projects/Testbench/ip/gpio_model/rtl/xml/gpio_model.xml
51,12 → 51,59
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
70,6 → 117,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
107,26 → 164,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/projects/Testbench/ip/io_probe/rtl/xml/io_probe.xml
47,15 → 47,90
<spirit:componentGenerators>
 
<spirit:componentGenerator>
<spirit:name>verilog_maker</spirit:name>
<spirit:phase>104.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_verilog</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
<spirit:componentGenerator>
<spirit:name>leaf_maker</spirit:name>
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
69,17 → 144,27
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:value spirit:id="MESG"></spirit:value>" "</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="WIDTH"></spirit:value>1</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="RESET"></spirit:value>{WIDTH{1'bz}}</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="IN_DELAY"></spirit:value>5</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="OUT_DELAY"></spirit:value>15</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="OUT_WIDTH"></spirit:value>10</spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="MESG">" "</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="WIDTH">1</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="RESET">{WIDTH{1'bz}}</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="IN_DELAY">5</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="OUT_DELAY">15</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="OUT_WIDTH">10</spirit:value></spirit:modelParameter>
</spirit:modelParameters>
 
<spirit:ports>
130,25 → 215,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/projects/Testbench/ip/io_probe/rtl/verilog/top File deleted
/projects/Testbench/ip/io_probe/rtl/verilog/top.body
0,0 → 1,28
 
reg [WIDTH-1:0] filtered_value;
reg [WIDTH:1] fail;
assign signal = drive_value;
always @(posedge clk) filtered_value <= signal;
always @(posedge clk) fail <= mask & (signal^ expected_value);
 
 
initial
begin
cg.next(3);
while(1)
begin
if(fail !== {WIDTH{1'b0}})
begin
$display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail );
cg.fail(MESG);
end
cg.next(1);
end // while (1)
end // initial begin
 
/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
71,44 → 80,70
<spirit:fileSets>
 
<spirit:fileSet>
 
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse</spirit:name>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:name>../verilog/top.mdisp</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mdisp</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
130,6 → 165,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Basys_soc_mrisc/rtl/xml/Basys_soc_mrisc_io_mouse_mouse.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse_mouse</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse_mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,20 → 70,36
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
</spirit:fileSets>
 
 
96,6 → 116,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Basys_soc_mrisc/soc/design.soc
71,11 → 71,11
<code_coverage>
<cover>
<name>mrisc_cpu</name>
<componentInstance>TB.dut.dut.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.soc_misc_io.pic</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.soc_misc_io.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
/projects/fpgas/ip/Basys_soc_mrisc/sim/xml/Basys_soc_mrisc_io_mouse_mouse_sim.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse_mouse_sim</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse_mouse_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,18 → 70,24
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
96,6 → 106,29
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
112,6 → 145,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_tim_2.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_tim_2</spirit:value>
<spirit:value>top.T6502_tim_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,17 → 82,29
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_tim_2</spirit:name>
<spirit:name>../verilog/sim/top.T6502_tim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_tim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
100,6 → 121,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_irq_2_test.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_irq_2_test</spirit:value>
<spirit:value>top.T6502_irq_2_test</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,17 → 82,28
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_irq_2_test</spirit:name>
<spirit:name>../verilog/sim/top.T6502_irq_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_irq_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
100,6 → 120,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_poll_2.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_io_poll_2</spirit:value>
<spirit:value>top.T6502_io_poll_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,17 → 82,28
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_io_poll_2</spirit:name>
<spirit:name>../verilog/sim/top.T6502_io_poll_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_io_poll_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
100,6 → 120,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502</spirit:value>
<spirit:value>top.T6502</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
85,41 → 94,69
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502</spirit:name>
<spirit:name>../verilog/sim/top.T6502</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:name>../verilog/top.gpio</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rs_uart</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.gpio</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rs_uart</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
141,6 → 178,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_kim_2</spirit:value>
<spirit:value>top.T6502_kim_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,17 → 82,29
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_kim_2</spirit:name>
<spirit:name>../verilog/sim/top.T6502_kim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_kim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
100,6 → 121,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_io_irq_2.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_io_irq_2</spirit:value>
<spirit:value>top.T6502_io_irq_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,36 → 82,54
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_io_irq_2</spirit:name>
<spirit:name>../verilog/sim/top.T6502_io_irq_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_io_irq_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-sim</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
<spirit:modelParameters>
<spirit:modelParameter><spirit:value spirit:id="RAM_WORDS">2048</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:value spirit:id="RAM_ADD">11</spirit:value></spirit:modelParameter>
/projects/fpgas/ip/Nexys2_T6502/soc/design.soc
92,11 → 92,11
<code_coverage>
<cover>
<name>T6502_cpu</name>
<componentInstance>TB.dut.dut.T6502.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.cpu</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.T6502.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
110,11 → 110,11
<code_coverage>
<cover>
<name>T6502_cpu</name>
<componentInstance>TB.dut.dut.T6502.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.cpu</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.T6502.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
127,11 → 127,11
<code_coverage>
<cover>
<name>T6502_cpu</name>
<componentInstance>TB.dut.dut.T6502.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.cpu</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.T6502.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
145,11 → 145,11
<code_coverage>
<cover>
<name>T6502_cpu</name>
<componentInstance>TB.dut.dut.T6502.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.cpu</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.T6502.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
163,11 → 163,11
<code_coverage>
<cover>
<name>T6502_cpu</name>
<componentInstance>TB.dut.dut.T6502.cpu</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.cpu</componentInstance>
</cover>
<cover>
<name>io_module</name>
<componentInstance>TB.dut.dut.T6502.io_module</componentInstance>
<componentInstance>TB.dut.dut.core.T6502.io_module</componentInstance>
</cover>
</code_coverage>
</testbench>
/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_kim_2_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_kim_2_sim</spirit:value>
<spirit:value>top.T6502_kim_2_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,12 → 82,13
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_kim_2_sim</spirit:name>
<spirit:name>../verilog/sim/top.T6502_kim_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
97,7 → 107,27
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_kim_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
114,6 → 144,18
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_irq_2_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_io_irq_2_sim</spirit:value>
<spirit:value>top.T6502_io_irq_2_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,12 → 82,14
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_io_irq_2_sim</spirit:name>
<spirit:name>../verilog/sim/top.T6502_io_irq_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
95,14 → 106,31
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_io_irq_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
119,6 → 147,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_tim_2_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_tim_2_sim</spirit:value>
<spirit:value>top.T6502_tim_2_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
78,7 → 87,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_tim_2_sim</spirit:name>
<spirit:name>../verilog/sim/top.T6502_tim_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
98,8 → 107,28
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_tim_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
116,6 → 145,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_irq_2_test_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_irq_2_test_sim</spirit:value>
<spirit:value>top.T6502_irq_2_test_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,12 → 82,14
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_irq_2_test_sim</spirit:name>
<spirit:name>../verilog/sim/top.T6502_irq_2_test_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
103,6 → 114,32
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_irq_2_test_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
 
 
 
 
 
</spirit:fileSets>
 
 
119,6 → 156,19
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_T6502/sim/xml/Nexys2_T6502_io_poll_2_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.T6502_io_poll_2_sim</spirit:value>
<spirit:value>top.T6502_io_poll_2_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,12 → 82,13
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.T6502_io_poll_2_sim</spirit:name>
<spirit:name>../verilog/sim/top.T6502_io_poll_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
103,6 → 113,32
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.T6502_io_poll_2_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
119,6 → 155,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse_mouse.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse_mouse</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse_mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,17 → 82,27
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
103,6 → 122,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_soc_mrisc/rtl/xml/Nexys2_soc_mrisc_io_mouse.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
71,65 → 80,68
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:name>all</spirit:name>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rs_uart</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.disp_1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.disp_1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
149,6 → 161,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/fpgas/ip/Nexys2_soc_mrisc/sim/xml/Nexys2_soc_mrisc_io_mouse_mouse_sim.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.soc_mrisc_io_mouse_mouse_sim</spirit:value>
<spirit:value>top.soc_mrisc_io_mouse_mouse_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,12 → 82,13
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:name>../verilog/sim/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
101,7 → 111,31
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.soc_mrisc_io_mouse_mouse_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
121,6 → 155,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc_loop.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mrisc_loop</spirit:value>
<spirit:value>top.mrisc_loop</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,20 → 70,39
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mrisc_loop</spirit:name>
<spirit:name>../verilog/sim/top.mrisc_loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mrisc_loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
96,6 → 119,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Basys_mrisc/rtl/xml/Basys_mrisc.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mrisc</spirit:value>
<spirit:value>top.mrisc</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
61,7 → 65,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
71,52 → 80,80
<spirit:fileSets>
 
<spirit:fileSet>
 
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mrisc</spirit:name>
<spirit:name>../verilog/sim/top.mrisc</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:name>../verilog/top.ps2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.uart</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mrisc</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.vga</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.jabc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ps2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.uart</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
140,6 → 177,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/fpgas/ip/Basys_mrisc/sim/xml/Basys_mrisc_loop_sim.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mrisc_loop_sim</spirit:value>
<spirit:value>top.mrisc_loop_sim</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,7 → 70,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
77,7 → 86,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mrisc_loop_sim</spirit:name>
<spirit:name>../verilog/sim/top.mrisc_loop_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
90,6 → 99,20
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mrisc_loop_sim</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
106,6 → 129,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,96
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName>alu</spirit:logicalName>
<spirit:name>../verilog/alu</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>fifo</spirit:logicalName>
<spirit:name>../verilog/fifo</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>presclr_wdt</spirit:logicalName>
<spirit:name>../verilog/presclr_wdt</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>register_file</spirit:logicalName>
<spirit:name>../verilog/register_file</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
 
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
85,6 → 173,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
206,60 → 304,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>alu</spirit:logicalName>
<spirit:name>../verilog/alu</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>fifo</spirit:logicalName>
<spirit:name>../verilog/fifo</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>presclr_wdt</spirit:logicalName>
<spirit:name>../verilog/presclr_wdt</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>register_file</spirit:logicalName>
<spirit:name>../verilog/register_file</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.io File deleted
/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.out File deleted
/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.sim
1,6 → 1,3
`ifndef SYNTHESIS
 
 
 
reg [8*8-1:0] inst_string;
54,8 → 51,9
 
 
`endif
 
 
 
 
 
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_ind_mem.xml
55,8 → 55,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.ind_mem</spirit:value>
<spirit:value>top.ind_mem</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 71,62
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.ind_mem</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
 
 
100,6 → 155,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
112,33 → 177,9
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.ind_mem</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf1.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf1</spirit:value>
<spirit:value>top.rf1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,64
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
 
 
100,6 → 156,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
112,33 → 178,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity1.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.sanity1</spirit:value>
<spirit:value>top.sanity1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,63
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
 
 
101,45 → 156,31
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
</spirit:model>
 
 
 
</spirit:model>
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_loop.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.loop</spirit:value>
<spirit:value>top.loop</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
62,12 → 67,62
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.out</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.loop</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.out</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
 
 
96,6 → 151,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
108,33 → 174,8
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.out</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.loop</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf2.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf2</spirit:value>
<spirit:value>top.rf2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,62
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
 
 
100,45 → 154,32
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
</spirit:model>
 
 
 
</spirit:model>
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_sanity2.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.sanity2</spirit:value>
<spirit:value>top.sanity2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,66
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
 
 
100,6 → 158,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
112,33 → 180,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc_cpu/sim/xml/mrisc_cpu_rf3.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf3</spirit:value>
<spirit:value>top.rf3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,63
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf3</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
 
 
100,6 → 155,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
112,33 → 177,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.io</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf3</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/soc/rtl/xml/soc_mrisc_io.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mrisc_io</spirit:value>
<spirit:value>top.mrisc_io</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,11 → 66,58
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.mrisc_io</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mrisc_io</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
81,6 → 132,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
520,30 → 581,8
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mrisc_io</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
</spirit:component>
 
 
/projects/pic_micro/ip/soc/rtl/verilog/top.ext.mouse_mrisc File deleted
/projects/pic_micro/ip/soc/soc/design.soc
40,6 → 40,9
 
 
 
 
 
 
</components>
 
 
73,6 → 76,7
 
 
 
 
</testbenchs>
 
 
/projects/pic_micro/ip/soc/sim/xml/soc_mrisc_io_mouse_mrisc.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mrisc_io_mouse_mrisc</spirit:value>
<spirit:value>top.mrisc_io_mouse_mrisc</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,11 → 66,67
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse_mrisc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse_mrisc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.mrisc_io_mouse_mrisc</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse_mrisc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mrisc_io_mouse_mrisc</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
81,6 → 141,18
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
416,37 → 488,8
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse_mrisc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse_mrisc</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mrisc_io_mouse_mrisc</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
</spirit:component>
 
 
/projects/pic_micro/ip/mrisc/rtl/xml/mrisc.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,46
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 119,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
203,22 → 252,9
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><spirit:wire><spirit:vector><spirit:left>11</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire><name>inst_data</name></node>
</nodes>
/projects/pic_micro/ip/mrisc/rtl/verilog/top.ext File deleted
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_ind_mem.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.ind_mem</spirit:value>
<spirit:value>top.ind_mem</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,68
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.ind_mem</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
80,6 → 141,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
104,38 → 175,10
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ind_mem</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.ind_mem</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf1.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf1</spirit:value>
<spirit:value>top.rf1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,67
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
<spirit:model>
<spirit:views>
 
80,6 → 140,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
104,38 → 174,10
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity1.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.sanity1</spirit:value>
<spirit:value>top.sanity1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,70
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 143,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
109,38 → 182,9
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sanity1</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity1</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_loop.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.loop</spirit:value>
<spirit:value>top.loop</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,71
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.loop</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 144,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
104,38 → 179,8
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.loop</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.loop</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf2.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf2</spirit:value>
<spirit:value>top.rf2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,69
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 142,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
104,38 → 176,8
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_sanity2.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.sanity2</spirit:value>
<spirit:value>top.sanity2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,69
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 142,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
104,38 → 176,9
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sanity2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.sanity2</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/pic_micro/ip/mrisc/sim/xml/mrisc_rf3.xml
51,8 → 51,13
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rf3</spirit:value>
<spirit:value>top.rf3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
 
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 66,69
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf3</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
80,6 → 142,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
104,38 → 176,9
</spirit:model>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rf3</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rf3</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
<nodes>
 
<node><name>clk</name>
/projects/io/ip/io_pic/rtl/xml/io_pic.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,12 → 69,72
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
84,6 → 148,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
204,36 → 278,8
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
</spirit:component>
/projects/io/ip/io_uart/rtl/xml/io_uart.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,7 → 69,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
72,7 → 81,61
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
86,6 → 149,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
440,33 → 513,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/io/ip/io_vga/rtl/xml/io_vga.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,7 → 69,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
79,7 → 88,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
98,6 → 107,33
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
114,6 → 150,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,13 → 68,65
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
84,6 → 140,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
244,29 → 310,6
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/io/ip/io_gpio/rtl/xml/io_gpio.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,7 → 69,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
72,6 → 81,51
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
85,6 → 139,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
251,28 → 315,6
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/io/ip/io_timer/rtl/xml/io_timer.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,79
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
 
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
 
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 154,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
189,35 → 270,6
</mem_map>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
 
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/io/ip/io_vic/rtl/xml/io_vic.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,7 → 69,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
72,7 → 81,48
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
86,6 → 136,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
206,24 → 267,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/io/ip/io_ps2/rtl/xml/io_ps2.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,7 → 69,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
72,6 → 81,63
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
85,6 → 151,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
348,35 → 424,7
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
<spirit:adHocConnections>
 
 
/projects/io/ip/io_ps2/rtl/verilog/top.ext File deleted
/projects/io/ip/io_ps2/sim/xml/io_ps2_default.xml
53,8 → 53,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
71,6 → 80,64
 
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
84,6 → 151,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
222,38 → 299,6
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
<spirit:adHocConnections>
 
 
/projects/io/ip/io_module/rtl/xml/io_module_mouse.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mouse</spirit:value>
<spirit:value>top.mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,13 → 66,60
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
82,6 → 133,18
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
783,31 → 846,9
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
 
</spirit:component>
/projects/io/ip/io_module/rtl/xml/io_module_gpio.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.gpio</spirit:value>
<spirit:value>top.gpio</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
69,6 → 78,49
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.gpio.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.gpio</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.gpio.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.gpio</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
82,6 → 134,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
633,31 → 696,9
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.gpio.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.gpio</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
 
</spirit:component>
/projects/io/ip/io_module/rtl/xml/io_module.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,12 → 66,57
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
83,6 → 132,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
1118,30 → 1177,9
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<mem_map>
<mem_space>
<name>gpio_0</name>
/projects/io/ip/io_module/rtl/verilog/top.ext.mouse File deleted
/projects/io/ip/io_module/rtl/verilog/top.ext File deleted
/projects/io/ip/io_module/sim/xml/io_module_default.xml
50,8 → 50,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
61,12 → 65,66
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
82,6 → 140,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
780,42 → 849,12
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
 
 
 
</spirit:component>
 
 
/projects/io/ip/io_module/sim/xml/io_module_mouse_mouse.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mouse_mouse</spirit:value>
<spirit:value>top.mouse_mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,13 → 66,65
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse_mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
655,37 → 711,11
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext.mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse_mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse_mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
 
</spirit:component>
/projects/io/ip/io_utimer/rtl/xml/io_utimer.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,13 → 68,71
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
84,6 → 146,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
171,33 → 243,7
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>micro_reg</spirit:logicalName>
<spirit:name>../verilog/micro_reg</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/Mos6502/ip/T6502/rtl/xml/T6502.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
85,16 → 94,37
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
106,24 → 136,29
 
<spirit:model>
<spirit:views>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-sim</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
 
<spirit:modelParameters>
<spirit:modelParameters>
 
 
<spirit:modelParameter><spirit:value spirit:id="RAM_WORDS">2048</spirit:value></spirit:modelParameter>
/projects/Mos6502/ip/T6502/sim/xml/T6502_kim_2.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.kim_2</spirit:value>
<spirit:value>tb.kim_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
84,7 → 93,12
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.kim_2</spirit:name>
93,12 → 107,23
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.kim_2</spirit:name>
<spirit:name>../verilog/sim/tb.kim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.kim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
120,6 → 145,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/Mos6502/ip/T6502/sim/xml/T6502_io_irq_2.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.io_irq_2</spirit:value>
<spirit:value>tb.io_irq_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
84,7 → 93,12
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.io_irq_2</spirit:name>
93,12 → 107,25
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.io_irq_2</spirit:name>
<spirit:name>../verilog/sim/tb.io_irq_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.io_irq_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
120,6 → 147,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/Mos6502/ip/T6502/sim/xml/T6502_tim_2.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.tim_2</spirit:value>
<spirit:value>tb.tim_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
84,7 → 93,12
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.tim_2</spirit:name>
93,12 → 107,24
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.tim_2</spirit:name>
<spirit:name>../verilog/sim/tb.tim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.tim_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
120,6 → 146,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/Mos6502/ip/T6502/sim/xml/T6502_irq_2_test.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.irq_2_test</spirit:value>
<spirit:value>tb.irq_2_test</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
85,6 → 94,11
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.irq_2_test</spirit:name>
93,12 → 107,24
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.irq_2_test</spirit:name>
<spirit:name>../verilog/sim/tb.irq_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.irq_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
120,6 → 146,19
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
895,7 → 934,6
 
<spirit:adHocConnection>
<spirit:name>ramwait_in</spirit:name>
<spirit:externalPortReference spirit:portRef="ramwait_in"/>
<spirit:internalPortReference spirit:componentRef="fmc" spirit:portRef="ramwait_in"/>
</spirit:adHocConnection>
 
/projects/Mos6502/ip/T6502/sim/xml/T6502_inst_2_test.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.inst_2_test</spirit:value>
<spirit:value>tb.inst_2_test</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
85,6 → 94,15
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.inst_2_test</spirit:name>
93,12 → 111,28
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.inst_2_test</spirit:name>
<spirit:name>../verilog/sim/tb.inst_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.inst_2_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
120,6 → 154,18
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
446,6 → 492,8
</node>
 
 
 
 
<node><name>ramadv_out_n</name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire></spirit:wire>
/projects/Mos6502/ip/T6502/sim/xml/T6502_io_poll_2.xml
51,8 → 51,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/tb.io_poll_2</spirit:value>
<spirit:value>tb.io_poll_2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
63,7 → 67,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
 
76,7 → 85,7
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
84,7 → 93,11
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.io_poll_2</spirit:name>
93,12 → 106,23
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.io_poll_2</spirit:name>
<spirit:name>../verilog/sim/tb.io_poll_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.io_poll_2</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
120,6 → 144,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/Mos6502/ip/T6502/sim/verilog/tb.ext_m
3,24 → 3,24
pullup ua1(ps2_data);
 
 
pullup mdb_00(MEMDB(00));
pullup mdb_01(MEMDB(01));
pullup mdb_02(MEMDB(02));
pullup mdb_03(MEMDB(03));
pullup mdb_04(MEMDB(04));
pullup mdb_05(MEMDB(05));
pullup mdb_06(MEMDB(06));
pullup mdb_07(MEMDB(07));
pullup mdb_08(MEMDB(08));
pullup mdb_09(MEMDB(09));
pullup mdb_10(MEMDB(10));
pullup mdb_11(MEMDB(11));
pullup mdb_12(MEMDB(12));
pullup mdb_13(MEMDB(13));
pullup mdb_14(MEMDB(14));
pullup mdb_15(MEMDB(15));
pullup mdb_00(MEMDB[00]);
pullup mdb_01(MEMDB[01]);
pullup mdb_02(MEMDB[02]);
pullup mdb_03(MEMDB[03]);
pullup mdb_04(MEMDB[04]);
pullup mdb_05(MEMDB[05]);
pullup mdb_06(MEMDB[06]);
pullup mdb_07(MEMDB[07]);
pullup mdb_08(MEMDB[08]);
pullup mdb_09(MEMDB[09]);
pullup mdb_10(MEMDB[10]);
pullup mdb_11(MEMDB[11]);
pullup mdb_12(MEMDB[12]);
pullup mdb_13(MEMDB[13]);
pullup mdb_14(MEMDB[14]);
pullup mdb_15(MEMDB[15]);
 
pullup pu_ramwait ( ramwait_n );
pullup pu_ramwait ( ramwait_in );
 
mt45w8mw12
psram (
27,7 → 27,7
.clk ( ramclk_out ),
.adv_n ( ramadv_out_n ),
.cre ( ramcre_out ),
.o_wait ( ramwait_n ),
.o_wait ( ramwait_in ),
.ce_n ( ramcs_n_out ),
.oe_n ( memoe_n_out ),
.we_n ( memwr_n_out ),
/projects/Mos6502/ip/T6502_cpu_alu_logic/rtl/xml/T6502_cpu_alu_logic.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,29 → 68,87
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName><spirit:fileSetRef><spirit:localName>fs-sim</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName><spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
 
<spirit:ports>
 
<spirit:port><name>alu_op_a</name>
179,29 → 241,7
</spirit:model>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/Mos6502/ip/T6502_cpu_alu_logic/sim/xml/T6502_cpu_alu_logic_alu_logic_test.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.alu_logic_test</spirit:value>
<spirit:value>tb.alu_logic_test</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,75
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/tb.alu_logic_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.alu_logic_test</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/tb.alu_logic_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 150,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
<spirit:modelParameters>
101,6 → 179,16
 
<nodes>
 
<node><name>clk</name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire></spirit:wire>
</node>
 
<node><name>reset</name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire></spirit:wire>
</node>
 
<node><name>alu_op_a</name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire>
342,36 → 430,6
</spirit:componentInstances>
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.alu_logic_test</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.alu_logic_test</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
</spirit:component>
/projects/Mos6502/ip/T6502_cpu/rtl/xml/T6502_cpu.xml
49,8 → 49,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
60,25 → 64,156
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/defines</spirit:name>
<spirit:fileType>verilogInclude</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>alu</spirit:logicalName>
<spirit:name>../verilog/alu</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>alu_logic</spirit:logicalName>
<spirit:name>../verilog/alu_logic</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>control</spirit:logicalName>
<spirit:name>../verilog/control</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>inst_decode</spirit:logicalName>
<spirit:name>../verilog/inst_decode</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>sequencer</spirit:logicalName>
<spirit:name>../verilog/sequencer</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>state_fsm</spirit:logicalName>
<spirit:name>../verilog/state_fsm</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
 
 
 
 
</spirit:fileSet>
 
 
 
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
 
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-sim</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef><spirit:localName>fs-syn</spirit:localName></spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
223,87 → 358,4
 
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/defines</spirit:name>
<spirit:fileType>verilogInclude</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>alu</spirit:logicalName>
<spirit:name>../verilog/alu</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>alu_logic</spirit:logicalName>
<spirit:name>../verilog/alu_logic</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>control</spirit:logicalName>
<spirit:name>../verilog/control</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName>inst_decode</spirit:logicalName>
<spirit:name>../verilog/inst_decode</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>sequencer</spirit:logicalName>
<spirit:name>../verilog/sequencer</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName>state_fsm</spirit:logicalName>
<spirit:name>../verilog/state_fsm</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
 
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/Mos6502/ip/T6502_cpu/rtl/verilog/top.sim
4,10 → 4,6
 
 
 
`ifndef SYNTHESIS
 
 
 
 
1088,11 → 1084,7
 
 
 
 
`endif // `ifndef SYNTHESIS
 
 
 
 
/projects/Mos6502/ip/T6502_cpu/sim/xml/T6502_cpu_inst_2_test.xml
50,8 → 50,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.inst_2_test</spirit:value>
<spirit:value>tb.inst_2_test</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
70,7 → 79,22
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>all</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
 
77,7 → 101,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.inst_2_test</spirit:name>
<spirit:name>../verilog/sim/tb.inst_2_test</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
89,17 → 113,26
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rtl</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
<spirit:name>../verilog/syn/tb.inst_2_test</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
119,6 → 152,18
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
396,6 → 441,16
</node>
 
 
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>rts_pad_out</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>txd_pad_out</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ps2_clk_pad_oe</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ps2_data_pad_oe</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_ub</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_lb</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_rd</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_stb</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_wr</name></node>
<node><spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs><name>ext_ack</name></node>
 
 
</nodes>
/projects/logic/ip/micro_bus/rtl/xml/micro_bus.xml
56,8 → 56,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,18 → 70,88
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
 
<spirit:views>
 
<spirit:view>
<spirit:name>sim</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-sim</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
 
<spirit:ports>
 
<spirit:port><name>clk</name>
174,27 → 248,9
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>verilogSource</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/ps2_interface/rtl/xml/ps2_interface.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,80
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>fsm</spirit:logicalName>
<spirit:name>../verilog/fsm</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>fsm</spirit:logicalName>
<spirit:name>../verilog/fsm</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 155,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
597,37 → 680,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>fsm</spirit:logicalName>
<spirit:name>../verilog/fsm</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/ps2_interface/rtl/verilog/top.sim
1,9 → 1,4
 
`ifndef SYNTHESIS
 
 
always@(posedge clk)
if(rx_read)
$display ("%t %m host rec %h parity_rcv %b parity_cal %b parity_error %b",$realtime,rx_data,rx_parity_rcv,rx_parity_cal,rx_parity_error);
15,7 → 10,6
$display ("%t %m host send %h ",$realtime,tx_data);
 
`endif
 
 
/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,65
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
83,6 → 140,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
397,31 → 464,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/ps2_interface/sim/xml/ps2_interface_mouse.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.mouse</spirit:value>
<spirit:value>top.mouse</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,66
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 141,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
396,32 → 465,4
 
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.mouse</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.mouse</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/disp_io/rtl/xml/disp_io.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,65
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
85,6 → 142,18
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
184,28 → 253,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/disp_io/sim/xml/disp_io_default.xml
55,8 → 55,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,12 → 70,71
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
85,6 → 148,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
</spirit:model>
265,35 → 338,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,18 → 68,24
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
87,6 → 97,26
 
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
103,6 → 133,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.fifo</spirit:value>
<spirit:value>top.fifo</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,7 → 68,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
73,6 → 82,7
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
79,7 → 89,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.fifo</spirit:name>
<spirit:name>../verilog/sim/top.fifo</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
91,6 → 101,28
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.fifo</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.fifo</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
109,6 → 141,18
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
/projects/logic/ip/serial_rcvr/rtl/verilog/top.ext File deleted
/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_fifo_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.fifo_default</spirit:value>
<spirit:value>top.fifo_default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,7 → 70,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
79,7 → 88,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.fifo_default</spirit:name>
<spirit:name>../verilog/sim/top.fifo_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
98,6 → 107,27
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.fifo_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
115,6 → 145,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
/projects/logic/ip/serial_rcvr/sim/xml/serial_rcvr_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
66,7 → 70,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
79,7 → 88,7
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
98,6 → 107,23
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
115,6 → 141,19
</spirit:fileSetRef>
</spirit:view>
 
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
/projects/logic/ip/uart/rtl/xml/uart_rxtx.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rxtx</spirit:value>
<spirit:value>top.rxtx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
69,7 → 78,61
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rxtx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rxtx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rxtx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rxtx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 146,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
321,33 → 394,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rxtx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rxtx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/rtl/xml/uart_rx.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rx</spirit:value>
<spirit:value>top.rx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
70,6 → 79,57
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 143,18
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
 
</spirit:views>
 
 
321,32 → 393,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.rx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/rtl/xml/uart_tx.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.tx</spirit:value>
<spirit:value>top.tx</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,14 → 66,69
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.tx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.tx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.tx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.tx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 142,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
321,32 → 391,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.tx</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body.tx</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/rtl/xml/uart.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,14 → 66,65
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 138,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
319,32 → 384,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.sim</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/rtl/verilog/top.sim
1,8 → 1,5
 
`ifdef SYNTHESIS
 
`else
always@(posedge serial_rcvr.frame_rdy)
begin
18,7 → 15,7
end
end
 
`endif
 
 
 
 
/projects/logic/ip/uart/sim/xml/uart_rxtx_default.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rxtx_default</spirit:value>
<spirit:value>top.rxtx_default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,14 → 66,62
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rxtx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rxtx_default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rxtx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
83,6 → 135,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
432,32 → 494,8
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rxtx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rxtx_default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/sim/xml/uart_rx_default.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.rx_default</spirit:value>
<spirit:value>top.rx_default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
69,7 → 78,53
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.rx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rx_default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.rx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 138,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
432,32 → 498,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.rx_default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.rx_default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/sim/xml/uart_default.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,7 → 66,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
69,7 → 78,54
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 139,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
428,32 → 494,8
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/uart/sim/xml/uart_divide.xml
52,8 → 52,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.divide</spirit:value>
<spirit:value>top.divide</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
62,14 → 66,63
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.divide</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.divide</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.divide</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 136,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
428,32 → 491,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.divide</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.divide</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
 
 
</spirit:component>
/projects/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,59
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
83,6 → 134,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
252,24 → 313,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/flash_memcontrl/sim/xml/flash_memcontrl_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
64,12 → 68,68
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
83,6 → 143,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
472,32 → 543,6
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/usb_epp/rtl/xml/usb_epp.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,12 → 69,63
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
84,6 → 139,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
274,25 → 340,5
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/usb_epp/sim/xml/usb_epp_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
65,12 → 69,53
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
</spirit:fileSets>
 
 
<spirit:model>
<spirit:views>
 
84,6 → 129,17
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
 
</spirit:views>
 
 
317,25 → 373,7
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.test_define.default</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
</spirit:fileSets>
 
 
</spirit:component>
/projects/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top</spirit:value>
<spirit:value>top</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
67,7 → 71,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
74,6 → 83,100
 
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/sim/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_display</spirit:logicalName>
<spirit:name>../verilog/char_display</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_gen</spirit:logicalName>
<spirit:name>../verilog/char_gen</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>svga_timing_generation</spirit:logicalName>
<spirit:name>../verilog/svga_timing_generation</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>video_out</spirit:logicalName>
<spirit:name>../verilog/video_out</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_display</spirit:logicalName>
<spirit:name>../verilog/char_display</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_gen</spirit:logicalName>
<spirit:name>../verilog/char_gen</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>svga_timing_generation</spirit:logicalName>
<spirit:name>../verilog/svga_timing_generation</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>video_out</spirit:logicalName>
<spirit:name>../verilog/video_out</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
<spirit:model>
<spirit:views>
 
87,6 → 190,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
205,57 → 318,11
 
 
 
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_display</spirit:logicalName>
<spirit:name>../verilog/char_display</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>char_gen</spirit:logicalName>
<spirit:name>../verilog/char_gen</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>svga_timing_generation</spirit:logicalName>
<spirit:name>../verilog/svga_timing_generation</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName>video_out</spirit:logicalName>
<spirit:name>../verilog/video_out</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.body</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
 
 
 
<nodes>
 
<node><name>h_synch</name>
/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default</spirit:value>
<spirit:value>top.default</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
67,7 → 71,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
74,12 → 83,13
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default</spirit:name>
<spirit:name>../verilog/sim/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
101,6 → 111,28
 
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
 
</spirit:fileSet>
 
 
 
 
</spirit:fileSets>
 
 
121,6 → 153,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/projects/logic/ip/vga_char_ctrl/sim/xml/vga_char_ctrl_default_600x432.xml
54,8 → 54,12
<spirit:parameters>
<spirit:parameter>
<spirit:name>destination</spirit:name>
<spirit:value>../verilog/top.default_600x432</spirit:value>
<spirit:value>top.default_600x432</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../verilog/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
67,7 → 71,12
<spirit:phase>105.0</spirit:phase>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>./tools/sys/build_leaf</spirit:generatorExe>
<spirit:parameters>
<spirit:parameter>
<spirit:name>dest_dir</spirit:name>
<spirit:value>../gen/</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:componentGenerator>
 
</spirit:componentGenerators>
74,12 → 83,13
 
 
<spirit:fileSets>
 
<spirit:fileSet>
<spirit:name>fs-sim</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/top.default_600x432</spirit:name>
<spirit:name>../verilog/sim/top.default_600x432</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
100,7 → 110,26
</spirit:fileSet>
 
 
<spirit:fileSet>
<spirit:name>fs-syn</spirit:name>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/syn/top.default_600x432</spirit:name>
<spirit:fileType>verilogSourceTop</spirit:fileType>
</spirit:file>
 
<spirit:file>
<spirit:logicalName></spirit:logicalName>
<spirit:name>../verilog/tb.ext</spirit:name>
<spirit:fileType>verilogFragment</spirit:fileType>
</spirit:file>
 
 
</spirit:fileSet>
 
 
 
</spirit:fileSets>
 
 
121,6 → 150,16
</spirit:fileSetRef>
</spirit:view>
 
<spirit:view>
<spirit:name>syn</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:language>Verilog</spirit:language>
<spirit:modelName></spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>fs-syn</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
 
</spirit:views>
 
 
/targets/Basys/filelist File deleted
targets/Basys/filelist Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: targets/Basys/target.xml =================================================================== --- targets/Basys/target.xml (revision 92) +++ targets/Basys/target.xml (nonexistent) @@ -1,12 +0,0 @@ - - -BASYS - - - disp_io - disp_io - logic - - - - Index: targets/Nexys2/filelist =================================================================== --- targets/Nexys2/filelist (revision 92) +++ targets/Nexys2/filelist (nonexistent) @@ -1,7 +0,0 @@ - - - - - - -
targets/Nexys2/filelist Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: targets/Nexys2/target.xml =================================================================== --- targets/Nexys2/target.xml (revision 92) +++ targets/Nexys2/target.xml (nonexistent) @@ -1,23 +0,0 @@ - - -NEXYS2 - - - disp_io - disp_io - logic - - - flash_memcontrl - flash_memcontrl - logic - - - usb_epp - usb_epp - logic - - - - -

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