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URL https://opencores.org/ocsvn/socgen/socgen/trunk

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  • This comparison shows the changes necessary to convert path 
    /socgen
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/trunk/bench/verilog/models/uart_model.v
150,10 → 150,10
input [7:0] byte_in;
begin
while(!rx_frame_rdy) next(1);
$display("%t %m check %h",$realtime,byte_in);
if(rx_shift_buffer != byte_in) cg.fail("uart data receive error");
if(rx_frame_err != exp_rx_frame_err) cg.fail("uart frame error");
if(rx_parity_error == 1'b1) cg.fail("uart parity receive error");
$display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in);
if(!(rx_shift_buffer === byte_in)) cg.fail("uart data receive error");
if(!(rx_frame_err === exp_rx_frame_err)) cg.fail("uart frame error");
if( (rx_parity_error === 1'b1)) cg.fail("uart parity receive error");
next(1);
end
endtask
/trunk/bench/verilog/models/timed_driver.v
0,0 → 1,94
 
 
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* source driver for timed input signals */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
module timed_driver
#(parameter WIDTH = 1,
parameter PROBE_TYPE = 2'b00,
parameter RESET = 1'b0)
(
input wire clk,
input wire [WIDTH-1:0] drive_value,
input wire tgen,
output wire [WIDTH-1:0] signal
);
 
 
reg [WIDTH-1:0] drive_latch;
reg [WIDTH-1:0] test;
initial
begin
drive_latch = RESET;
test = RESET;
end
 
reg [1:0] probe_type;
always@(posedge clk) probe_type <= PROBE_TYPE;
always@(drive_value or tgen)
if(tgen) drive_latch = drive_value;
else drive_latch = drive_latch;
 
always@( probe_type or drive_value or tgen)
if(tgen) test = drive_value;
else
case(probe_type)
2'b00: test = drive_latch;
2'b01: test = ~drive_latch;
2'b10: test = {WIDTH{1'b0}};
2'b11: test = {WIDTH{1'b1}};
endcase // case(probe_type)
assign signal = test;
 
 
endmodule
/trunk/bench/verilog/models/timing_gen.v
0,0 → 1,74
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* timing generator for simulation probes */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
module timing_gen
#(parameter DELAY=10,
parameter WIDTH=20
)
(input wire clk,
input wire reset,
output reg tgen
);
initial
begin
tgen = 1'b0;
end
 
 
always@(posedge clk ) tgen = #DELAY 1'b1;
always@(posedge tgen ) tgen = #WIDTH 1'b0;
 
 
 
 
 
endmodule
 
 
 
/trunk/bench/verilog/models/ps2_host.v
67,30 → 67,32
 
 
reg expect_tx_ack_err;
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
initial
begin
tx_data = 8'h00;
tx_write = 1'b0;
rx_clr = 1'b0;
expect_tx_ack_err = 1'b0;
always@(posedge clk)
if(reset)
begin
tx_data <= 8'h00;
tx_write <= 1'b0;
rx_clr <= 1'b0;
expect_tx_ack_err <= 1'b0;
end
 
 
task clear_rx_host;
begin
rx_clr = 1'b1;
rx_clr <= 1'b1;
next(1);
rx_clr = 1'b0;
rx_clr <= 1'b0;
end
endtask
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
98,14 → 100,14
input [7:0] byte_out;
begin
$display("%t %m %2h",$realtime ,byte_out );
tx_data = byte_out;
tx_data <= byte_out;
next(1);
tx_write = 1'b1;
tx_write <= 1'b1;
next(1);
tx_write = 1'b0;
tx_write <= 1'b0;
next(1);
while(busy) next(1);
if(tx_ack_error != expect_tx_ack_err) cg.fail("tx ack");
if(!(tx_ack_error === expect_tx_ack_err)) cg.fail("tx ack");
end
endtask // send_byte
 
116,7 → 118,7
begin
while(!rx_read) next(1);
$display("%t checking %h",$realtime,byte_in);
if(rx_data != byte_in) cg.fail("ps2_host receive error");
if(!(rx_data === byte_in)) cg.fail("ps2_host receive error");
next(1);
end
/trunk/bench/verilog/models/micro_bus_model.v
63,27 → 63,27
 
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
always@(posedge clk)
if(reset)
begin
addr = 16'h0000;
wdata = 8'h00;
wr = 1'b0;
rd = 1'b0;
addr <= 16'h0000;
wdata <= 8'h00;
wr <= 1'b0;
rd <= 1'b0;
end
 
 
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask // next
 
 
 
// write cycle
task u_write;
93,14 → 93,14
begin
 
$display("%t %m cycle %x %x",$realtime,a,d );
#1
addr = a;
wdata = d;
rd = 1'b0;
wr = 1'b1;
addr <= a;
wdata <= d;
rd <= 1'b0;
wr <= 1'b1;
next(1);
#1
wr = 1'b0;
wr <= 1'b0;
next(1);
 
end
112,18 → 112,18
output [7:0] d;
begin
#1
addr = a;
wdata = 8'h00;
rd = 1'b1;
wr = 1'b0;
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
next(2);
#1
d = rdata;
d <= rdata;
$display("%t %m cycle %x %x",$realtime,a,rdata );
rd = 1'b1;
rd <= 1'b1;
next(1);
rd = 1'b0;
rd <= 1'b0;
end
endtask
133,16 → 133,15
input [7:0] d_exp;
 
begin
#1
addr = a;
wdata = 8'h00;
rd = 1'b1;
wr = 1'b0;
addr <= a;
wdata <= 8'h00;
rd <= 1'b1;
wr <= 1'b0;
next(1);
#1
$write("%t %m cycle %x %x",$realtime,a,rdata );
rd = 1'b1;
 
if (d_exp != rdata)
begin
$display(" Data compare error. Expected %x ", d_exp);
150,7 → 149,7
else $display("");
 
next(1);
rd = 1'b0;
rd <= 1'b0;
end
endtask
/trunk/bench/verilog/models/clock_gen.v
67,7 → 67,7
endtask // reset_on
 
 
task fail;
task automatic fail;
input [799:0] message;
begin
failed = 1;
/trunk/bench/verilog/models/uart_host.v
56,28 → 56,38
output reg txd_break,
output reg rxd_parity,
output reg rxd_force_parity,
output reg rxd_data_avail_stb,
input wire [7:0] rxd_data_out,
input wire rxd_buffer_full,
input wire rxd_data_avail,
input wire rxd_stop_error,
input wire rxd_parity_error
);
 
reg exp_rxd_stop_error ;
reg exp_rxd_parity_error ;
reg exp_rxd_stop_error;
reg exp_rxd_parity_error;
 
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
initial
always@(posedge clk)
if(reset)
begin
parity_enable = 1'b0;
txd_data_in = 8'h00;
txd_parity = 1'b0;
txd_force_parity = 1'b0;
txd_load = 1'b0;
txd_break = 1'b0;
rxd_parity = 1'b0;
rxd_force_parity = 1'b0;
exp_rxd_stop_error = 1'b0;
exp_rxd_parity_error = 1'b0;
parity_enable <= 1'b0;
txd_data_in <= 8'h00;
txd_parity <= 1'b0;
txd_force_parity <= 1'b0;
txd_load <= 1'b0;
txd_break <= 1'b0;
rxd_parity <= 1'b0;
rxd_force_parity <= 1'b0;
rxd_data_avail_stb <= 1'b0;
exp_rxd_stop_error <= 1'b0;
exp_rxd_parity_error <= 1'b0;
end
 
 
87,10 → 97,6
end
endtask
task automatic next;
input [31:0] num;
repeat (num) @ (posedge clk);
endtask
 
 
100,11 → 106,11
begin
while(!txd_buffer_empty) next(1);
$display("%t %m %2h",$realtime ,byte_out);
txd_data_in = byte_out;
txd_data_in <= byte_out;
next(1);
txd_load = 1'b1;
txd_load <= 1'b1;
next(1);
txd_load = 1'b0;
txd_load <= 1'b0;
next(1);
end
endtask // send_byte
114,13 → 120,16
task rcv_byte;
input [7:0] byte_in;
begin
while(!rxd_buffer_full) next(1);
while(!rxd_data_avail) next(1);
$display("%t %m checking %h",$realtime,byte_in);
if(rxd_data_out != byte_in) cg.fail("uart_host receive error");
if(rxd_stop_error != exp_rxd_stop_error) cg.fail("uart_host receive stop error");
if(rxd_parity_error != exp_rxd_parity_error) cg.fail("uart_host receive parity error");
if(!(rxd_data_out === byte_in)) cg.fail("uart_host receive error");
if(!(rxd_stop_error === exp_rxd_stop_error)) cg.fail("uart_host receive stop error");
if(!(rxd_parity_error === exp_rxd_parity_error)) cg.fail("uart_host receive parity error");
next(1);
rxd_data_avail_stb <= 1'b1;
next(1);
rxd_data_avail_stb <= 1'b0;
next(1);
end
endtask
/trunk/bench/verilog/models/timed_tester.v
0,0 → 1,79
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / SIM \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* receive tester for timed output signals */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
module timed_tester
#(parameter WIDTH = 1)
(
input wire clk,
input wire [WIDTH-1:0] expected_value,
input wire [WIDTH-1:0] mask,
input wire tgen,
input wire [WIDTH-1:0] signal,
 
output reg [WIDTH-1:0] filtered_value,
output reg [WIDTH-1:0] fail
);
 
 
always@(*)
if(tgen) filtered_value = signal;
else filtered_value = filtered_value;
 
always@(*)
begin
if(tgen) fail = mask & ((signal^ expected_value)| fail);
else fail = {WIDTH{1'b0}};
end
 
 
 
 
 
endmodule
/trunk/tools/install/Ubuntu_10.4/Makefile
32,6 → 32,7
sudo apt-get install -y libncurses5-dev;\
sudo apt-get install -y build-essential;\
sudo apt-get install -y tkdiff;\
sudo apt-get install -y librxtx-java;\
)
 
 
/trunk/doc/src/guides/guide_verification.html
24,9 → 24,12
module and checking that it produces the correct outputs. Stimulations
are designed to
ensure that all of the components functions are exercised and any
deviation from the expected value is reported as an error. Every
deviation from the expected behaviour&nbsp; is reported as an error.
Every
component must have at least one test case but may have as many as
needed to fully verify the design.<br>
needed to fully verify the design. All components will have at least
one interface and a bus functional model (bfm) must be created for each
and every interface.<br>
</p>
<p>A complete test suite is required for every component module.&nbsp;
Each test_case is simulated and the log file will indicate whether the
85,8 → 88,10
<p>Every interface on the component is connected to it's own bfm model
that contains all the tasks needed to test the interface. The calling
sequences needed to preform a particular test are all loaded from a
sperate file. It is important that each interface has its task calls in
a seperate code block. The goal is to develope these models and task
sperate test_define file. It is important that each interface has its
task calls in
a seperate code block in the test_define file. The goal is to develop
these models and task
calls on&nbsp; the component simulation and then reuse them as the
component is used in larger designs.&nbsp; Interleaving task calls for
different models makes that difficult.<br>
94,7 → 99,34
<p><br>
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>Protocol checkers and monitors<br>
</h2>
<br>
&nbsp;
Protocol checkers and monitors are similar to a bus functional
models&nbsp; except that they are for obsevation only and cannot
control any signals. They watch every transaction that occurs on the
interface and reports a failure when anything violates that interfaces
defined protocols. <span style="font-family: serif;"> They are created
in a seperate module and may be instantiated in the testbench&nbsp; and
connected to an interface.<br>
<br>
The same protocol checker can also be included in the rtl code so it
can monitor an interface that is buried deep inside a chip. Once
inserted in the rtl source it will watch for&nbsp; and report errors
that may occur during the regression suite. Since protocol checkers
are&nbsp; not synthesizable they must be excluded from synthesis with a
`ifndef SYNTHESYS statement.<br>
<br>
Monitors are similar to protocol checkers except that they are designed
to be implemetent in actual logic.&nbsp; If they ever fire during
product usage then these events should be latched and saved for later
debugging.<br>
&nbsp; <br>
</span>
<p><br>
<br>
</p>
<p><br>
</p>
132,6 → 164,8
<li><big>Message&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 
 
 
 
</big><br>
</li>
</ul>
170,6 → 204,28
</p>
<p><br>
</p>
<h2><a name="manifesto"></a>Gate and Post Route Simulations<br>
</h2>
<br>
&nbsp; All signals between the DUT and the bfms change only at the
rising edge of clk. This is fine for RTL sims but will not work for
real logic with setup and hold time requirements. For these the signals
driving the dut must be delayed from clk and from each other to provide
the required setup and hold times. Signals from the DUT will have
delays and must only be tested during a prescribed time window.<br>
This is accomplished with a set of modules that mimic the functions of
a IC tester. These modules provide the interface between the BFM's and
the DUT.<br>
<br>
<br>
<img style="width: 800px; height: 600px;" alt=""
src="../png/ver_fig4.png"><br>
<br style="font-family: serif;">
<br style="font-family: serif;">
&nbsp;<span style="font-family: serif;"></span><span
style="font-family: serif;"><br>
</span>
<p></p>
<p><br>
</p>
<p><br>
482,7 → 538,9
</p>
<code><br>
`include "../../bench/verilog/models/clock_gen.v"<br>
`include "../../bench/verilog/models/ps2_model.v"&nbsp;&nbsp;&nbsp; <br>
`include "../../bench/verilog/models/ps2_model.v"<br>
</code><code>`include "../../bench/verilog/models/uart_model.v"</code><code>&nbsp;&nbsp;
<br>
`include "../../bench/verilog/models/iobuftri.v"&nbsp;&nbsp;&nbsp; <br>
</code><span style="font-family: monospace;"></span><code><br>
</code>
495,25 → 553,14
</p>
<h2><a name="manifesto"></a>dut<br>
</h2>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span></p>
<p><code>reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
device_write;<br>
reg&nbsp; [7:0]&nbsp;&nbsp; device_tx_data;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_parity;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_ack;<br>
reg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_stop;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_rx_read;<br>
wire [7:0]&nbsp;&nbsp; device_rx_data;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; device_rx_parity;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_data;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ps2_clk;<br>
<p><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><code><br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; ps2_data_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ps2_data_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; ps2_data;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ps2_clk_pad_oe;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; ps2_clk_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ps2_clk;<br>
<br>
<br>
<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portaout;<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portbout;<br>
wire [7:0]&nbsp;&nbsp;&nbsp;&nbsp; portcout;<br>
533,16 → 580,12
<br>
<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
txd_pad_out;<br>
serial_txd;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
rxd_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
cts_pad_in;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
rts_pad_out;&nbsp; <br>
serial_rxd;<br>
wire&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; loop;<br>
&nbsp; <br>
<br>
<br>
// Instantiate one CPU to be tested.<br>
soc_mouse<br>
#(<br>
.ROM_WORDS ( `ROM_WORDS ), <br>
551,10 → 594,10
.ROM_FILE&nbsp; ( `ROM_FILE&nbsp; )<br>
)<br>
dut(<br>
&nbsp;&nbsp; .clk&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; (
clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .reset&nbsp;&nbsp;&nbsp; (
reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .clk&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp; (
clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ),<br>
&nbsp;&nbsp; .reset &nbsp;&nbsp; &nbsp; &nbsp; &nbsp;&nbsp; (
reset&nbsp;&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; &nbsp; ),<br>
<br>
&nbsp;&nbsp; .ps2_data_pad_in ( ps2_data_pad_in ),<br>
&nbsp;&nbsp; .ps2_clk_pad_in&nbsp; ( ps2_clk_pad_in&nbsp; ),<br>
562,37 → 605,69
&nbsp;&nbsp; .ps2_data_pad_oe ( ps2_data_pad_oe ),<br>
&nbsp;&nbsp; .ps2_clk_pad_oe&nbsp; ( ps2_clk_pad_oe&nbsp; ),<br>
<br>
&nbsp;&nbsp; .portaout&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; (
portaout&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ),<br>
&nbsp;&nbsp; .portbout&nbsp; &nbsp; &nbsp; &nbsp; ( portbout&nbsp;
&nbsp; &nbsp; &nbsp; ),<br>
&nbsp;&nbsp; .portcout&nbsp; &nbsp; &nbsp; &nbsp; (
portcout&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ),<br>
<br>
&nbsp;&nbsp; .portaout&nbsp;&nbsp;&nbsp; ( portaout&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .portbout&nbsp;&nbsp;&nbsp; ( portbout&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .portcout&nbsp;&nbsp;&nbsp; ( portcout&nbsp;&nbsp;&nbsp; ),<br>
<br>
<br>
&nbsp;&nbsp; .y_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
y_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .x_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
x_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .new_packet&nbsp; ( new_packet&nbsp; ),<br>
&nbsp;&nbsp; .ms_mid&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
ms_mid&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ), <br>
&nbsp;&nbsp; .ms_right&nbsp;&nbsp;&nbsp; ( ms_right&nbsp;&nbsp;&nbsp;
&nbsp;&nbsp; .y_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; (
y_pos&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .x_pos&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; (
x_pos&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .new_packet &nbsp; &nbsp;&nbsp; ( new_packet &nbsp;
&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .ms_mid&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; &nbsp; (
ms_mid&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; ), <br>
&nbsp;&nbsp; .ms_right&nbsp; &nbsp; &nbsp; &nbsp; (
ms_right&nbsp;&nbsp; &nbsp; &nbsp;&nbsp;
),&nbsp; <br>
&nbsp;&nbsp; .ms_left&nbsp;&nbsp;&nbsp;&nbsp; (
ms_left&nbsp;&nbsp;&nbsp;&nbsp; ),&nbsp; <br>
&nbsp;&nbsp; .ms_left&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; (
ms_left&nbsp;&nbsp;&nbsp; &nbsp; &nbsp;&nbsp; ),&nbsp; <br>
<br>
<br>
<br>
&nbsp;&nbsp; .txd_pad_out ( loop1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .rxd_pad_in&nbsp; (
loop1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .cts_pad_in&nbsp; (
loop2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .rts_pad_out ( loop2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp;&nbsp; .txd_pad_out&nbsp;&nbsp;&nbsp;&nbsp; (
serial_txd&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .rxd_pad_in&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
serial_rxd&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .cts_pad_in&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
loop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp; .rts_pad_out&nbsp;&nbsp;&nbsp;&nbsp; (
loop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
)&nbsp; <br>
<br>
&nbsp;&nbsp; );<br>
</code></p>
<p><code>uart_model <br>
#(.CLKCNT(4'hc))<br>
uart_model<br>
(<br>
&nbsp;&nbsp;
.clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
reset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),
<br>
&nbsp;&nbsp;
.txd_in &nbsp;&nbsp; &nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
( serial_txd&nbsp; ),<br>
&nbsp;&nbsp;
.rxd_out &nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
( serial_rxd&nbsp; )<br>
<br>
);</code><br>
<code></code></p>
<p><code><br>
</code></p>
<p><code><br>
iobuftri<br>
data_tri_buf<br>
&nbsp; (<br>
622,7 → 697,7
<br>
ps2_model <br>
#(.CLKCNT(10'h177))<br>
ps2<br>
ps2_model<br>
(<br>
&nbsp;&nbsp;
.clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
636,38 → 711,6
),
<br>
&nbsp;&nbsp;
.send&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_write&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.send_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_tx_data&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_parity&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_parity&nbsp;&nbsp;&nbsp; ),<br>
&nbsp;&nbsp;
.device_ack&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_ack&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_stop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
device_stop&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
),<br>
&nbsp;&nbsp;
.device_rx_read&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_read&nbsp;&nbsp; ),<br>
&nbsp;&nbsp;
.device_rx_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_data&nbsp;&nbsp; ),<br>
&nbsp;&nbsp; .device_rx_parity&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (
device_rx_parity ),<br>
<br>
&nbsp;&nbsp;
.ps2_clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(
ps2_clk&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
678,7 → 721,10
ps2_data&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
)<br>
<br>
);<br>
);</code></p>
<p><code><br>
</code></p>
<p><code><br>
</code><span style="font-family: monospace;">--------------------------------------------------------------------------------------------------------------------------------------</span><br>
</p>
<p>This file is a verilog code segment that declares all the wires and
698,10 → 744,9
</p>
<p><span style="font-family: monospace;">initial</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">begin</span><br
<span style="font-family: monospace;">begin</span><span
style="font-family: monospace;"></span><br
style="font-family: monospace;">
<span style="font-family: monospace;">&nbsp;`TIMEFORMAT</span><br
style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
");</span><br style="font-family: monospace;">
<span style="font-family: monospace;">$display("&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
/trunk/doc/src/guides/reset_sys_design.html
275,7 → 275,8
You are looking at activity that is measured in the milliseconds on a
system clock that is measured in the nanoseconds. Performing a reset in
one clock cycle&nbsp; requires adding logic to every single flipflop<br>
for no good reason. A designer should only add reset logic as a last
to provide nanosecond resolution to an event that is measured in
microseconds. A designer should only add reset logic as a last
resort. The preferred method is to use the existing mission mode logic
to perform the reset. If you have a computational block with a fifty
stage deep pipeline then reset should force it's inputs to 0 and open
479,9 → 480,21
<br>
</p>
<p><br>
<br>
</p>
<h3 class="western">8) Seperate Synchronous and&nbsp; Asynchronous
resets<br>
</h3>
Asynchronous
resets connect to the asynchronouse reset/preset ports of a flip/flop.
Synchronous resets connect through the logic cone to the D flip/flop
port. They are the logicaly the same signal in mission mode but must be
sperate&nbsp; during scan testing. It is very easy to make a mistake in
rtl coding.&nbsp; The recomendation is the use active low signals for
all asynchronous resets and active high signals for all synchronous
ones.<br>
<p><br>
</p>
<p><br>
<br>
</p>
<p><br>
/trunk/doc/src/png/ver_fig1.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/png/ver_fig4.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/png/ver_fig4.png
trunk/doc/src/png/ver_fig4.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/drawing/sch/ver_fig4.sch =================================================================== --- trunk/doc/src/drawing/sch/ver_fig4.sch (nonexistent) +++ trunk/doc/src/drawing/sch/ver_fig4.sch (revision 28) @@ -0,0 +1,96 @@ +v 20100214 2 +C 48900 14100 1 0 0 frame_800x600.sym +B 52000 17400 800 2300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 50100 18100 1400 1600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 52100 18500 9 10 1 0 0 0 3 + BFM +MODEL + +T 50100 18600 9 10 1 0 0 0 2 + TEST_DEFINE + +L 51500 18900 52000 18900 3 0 0 0 -1 -1 +L 51500 18800 52000 18800 3 0 0 0 -1 -1 +L 52000 18800 51900 18700 3 0 0 0 -1 -1 +L 52000 18900 51900 19000 3 0 0 0 -1 -1 +L 52800 19500 53100 19500 3 0 0 0 -1 -1 +L 52800 19400 53100 19400 3 0 0 0 -1 -1 +T 53200 19600 9 10 1 0 0 0 1 +TIMED_DRIVER +B 53100 18900 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 55500 17000 1700 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 54900 17700 55000 17800 3 0 0 0 -1 -1 +L 54900 17600 55000 17500 3 0 0 0 -1 -1 +T 56100 18700 9 16 1 0 0 0 1 +DUT +T 49200 20300 9 20 1 0 0 0 1 +GATE SIMS +L 53100 19400 53000 19300 3 0 0 0 -1 -1 +L 53100 19500 53000 19600 3 0 0 0 -1 -1 +L 54900 19500 55500 19500 3 0 0 0 -1 -1 +L 54900 19400 55500 19400 3 0 0 0 -1 -1 +L 55500 19400 55400 19300 3 0 0 0 -1 -1 +L 55500 19500 55400 19600 3 0 0 0 -1 -1 +L 52800 18000 53100 18000 3 0 0 0 -1 -1 +L 52800 17900 53100 17900 3 0 0 0 -1 -1 +B 53100 17100 1800 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 54900 17700 55500 17700 3 0 0 0 -1 -1 +L 54900 17600 55500 17600 3 0 0 0 -1 -1 +T 53200 17800 9 10 1 0 0 0 1 +TIMED_TESTER +L 51500 18900 51600 19000 3 0 0 0 -1 -1 +L 51500 18800 51600 18700 3 0 0 0 -1 -1 +L 53100 17900 53000 17800 3 0 0 0 -1 -1 +L 53100 18000 53000 18100 3 0 0 0 -1 -1 +B 50100 14900 1300 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 50100 15400 9 10 1 0 0 0 2 + CLOCK_GEN + +B 51400 15400 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 51500 15400 9 10 1 0 0 0 2 + TIMING_GEN + +B 51400 14900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 51500 14900 9 10 1 0 0 0 2 + TIMING_GEN + +B 51400 15900 1500 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 51500 15900 9 10 1 0 0 0 2 + TIMING_GEN + +T 53000 16100 9 10 1 0 0 0 1 +CLK_TGEN +T 53000 15600 9 10 1 0 0 0 1 +IN_TGEN +T 53000 15100 9 10 1 0 0 0 1 +OUT_TGEN +L 53100 17200 51200 17200 3 0 0 0 -1 -1 +L 51200 17200 51400 17300 3 0 0 0 -1 -1 +L 51200 17200 51400 17100 3 0 0 0 -1 -1 +T 50300 17100 9 10 1 0 0 0 1 +FAILURE +L 52800 17600 52900 17700 3 0 0 0 -1 -1 +L 52800 17500 52900 17400 3 0 0 0 -1 -1 +L 52800 17600 53100 17600 3 0 0 0 -1 -1 +L 52800 17500 53100 17500 3 0 0 0 -1 -1 +T 52500 19400 9 10 1 0 0 0 1 +out +T 52200 17900 9 10 1 0 0 0 1 +expect +T 52200 17500 9 10 1 0 0 0 1 +actual +T 53200 16700 9 10 1 0 0 0 1 +mask +L 53400 16900 53400 17100 3 0 0 0 -1 -1 +L 53400 17100 53300 17000 3 0 0 0 -1 -1 +L 53400 17100 53500 17000 3 0 0 0 -1 -1 +L 54500 16900 54500 17100 3 0 0 0 -1 -1 +L 54500 17100 54400 17000 3 0 0 0 -1 -1 +L 54500 17100 54600 17000 3 0 0 0 -1 -1 +T 54300 16700 9 10 1 0 0 0 1 +in_tgen +L 54500 18700 54500 18900 3 0 0 0 -1 -1 +L 54500 18900 54400 18800 3 0 0 0 -1 -1 +L 54500 18900 54600 18800 3 0 0 0 -1 -1 +T 54300 18500 9 10 1 0 0 0 1 +out_tgen Index: trunk/doc/src/drawing/sch/ver_fig1.sch =================================================================== --- trunk/doc/src/drawing/sch/ver_fig1.sch (revision 27) +++ trunk/doc/src/drawing/sch/ver_fig1.sch (revision 28) @@ -66,25 +66,38 @@ L 56400 20300 56283 20335 3 0 0 0 -1 -1 L 56400 20300 56301 20223 3 0 0 0 -1 -1 L 56400 19300 56300 19400 3 0 0 0 -1 -1 -L 56400 19300 56300 19200 3 0 0 0 -1 -1 -T 51500 20100 9 10 1 0 0 0 2 +L 56400 19300 56289 19228 3 0 0 0 -1 -1 +T 51300 20600 9 10 1 0 0 0 2 COMMAND LINE OPTIONS -T 51600 19100 9 10 1 0 0 0 2 +T 51400 19800 9 10 1 0 0 0 2 FIRMWARE BIT IMAGE -T 51600 18200 9 10 1 0 0 0 2 -FIRMWARE -BIT IMAGE -B 51400 19900 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -B 51400 18900 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -B 51400 18000 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -L 52900 20300 53800 20100 3 0 0 0 -1 -1 -L 52900 19200 53700 19500 3 0 0 0 -1 -1 -L 52900 18300 54000 19000 3 0 0 0 -1 -1 -L 54000 19000 53839 18974 3 0 0 0 -1 -1 -L 54000 19000 53910 18837 3 0 0 0 -1 -1 -L 53800 20100 53700 20200 3 0 0 0 -1 -1 -L 53800 20100 53682 20051 3 0 0 0 -1 -1 -L 53700 19500 53521 19519 3 0 0 0 -1 -1 -L 53700 19500 53587 19345 3 0 0 0 -1 -1 +T 51400 18900 9 10 1 0 0 0 2 +EXPECTED +VALUES +B 51200 20400 1500 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 51200 19600 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 51200 18700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 52700 20800 53800 20100 3 0 0 0 -1 -1 +L 52700 20000 53700 19500 3 0 0 0 -1 -1 +L 52700 19000 54000 19000 3 0 0 0 -1 -1 +L 54000 19000 53772 19084 3 0 0 0 -1 -1 +L 54000 19000 53811 18890 3 0 0 0 -1 -1 +L 53800 20100 53690 20271 3 0 0 0 -1 -1 +L 53800 20100 53621 20122 3 0 0 0 -1 -1 +L 53700 19500 53529 19692 3 0 0 0 -1 -1 +L 53700 19500 53486 19480 3 0 0 0 -1 -1 +B 56400 18100 2800 500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 55400 19000 56400 18300 3 0 0 0 -1 -1 +L 56400 18300 56325 18474 3 0 0 0 -1 -1 +L 56400 18300 56253 18287 3 0 0 0 -1 -1 +T 56500 18300 9 10 1 0 0 0 1 +RECORDED VALUES +B 51200 17700 1500 700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 51400 17900 9 10 1 0 0 0 2 +INPUT +DATA +L 52700 18000 54284 18789 3 0 0 0 -1 -1 +L 54300 18800 54100 18800 3 0 0 0 -1 -1 +L 54300 18800 54210 18637 3 0 0 0 -1 -1 Index: trunk/lib/doc/png/cde_asyncdisable.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/lib/doc/drawing/sch/cde_asyncdisable.sch =================================================================== --- trunk/lib/doc/drawing/sch/cde_asyncdisable.sch (revision 27) +++ trunk/lib/doc/drawing/sch/cde_asyncdisable.sch (revision 28) @@ -1,146 +1,31 @@ -C 2000 10000 1 0 0 ipad.sym +v 20100214 1 +C 2300 300 1 0 0 in_port_v.sym { -T 2000 9800 5 10 1 1 0 2 -refdes=atg_asyncdisable +T 2300 300 5 10 1 1 0 6 1 1 +refdes=sync_reset[WIDTH-1:0] } -C 2000 11200 1 0 0 ipad.sym +C 2300 700 1 0 0 in_port.sym { -T 2000 11000 5 10 1 1 0 2 -refdes=reset -} -C 2000 12400 1 0 0 ipad.sym -{ -T 2000 12200 5 10 1 1 0 2 +T 2300 700 5 10 1 1 0 6 1 1 refdes=reset_n } -C 2000 13600 1 0 0 ipad_bus.sym +C 2300 1100 1 0 0 in_port.sym { -T 2000 13400 5 10 1 1 0 2 -refdes=sync_reset[WIDTH - 1:0] +T 2300 1100 5 10 1 1 0 6 1 1 +refdes=reset } -C 11000 10000 1 0 0 opad_bus.sym +C 2300 1500 1 0 0 in_port.sym { -T 11000 9800 5 10 1 1 0 0 -refdes=reset_n_out[WIDTH - 1:0] +T 2300 1500 5 10 1 1 0 6 1 1 +refdes=atg_asyncdisable } -C 11000 11200 1 0 0 opad_bus.sym +C 5800 300 1 0 0 out_port_v.sym { -T 11000 11000 5 10 1 1 0 0 -refdes=reset_out[WIDTH - 1:0] +T 6800 300 5 10 1 1 0 0 1 1 +refdes=reset_out[WIDTH-1:0] } -v 20040111 1 -C 40200 12700 1 0 0 and2-1.sym +C 5800 700 1 0 0 out_port_v.sym { -T 40600 12600 5 10 1 1 0 2 1 -refdes=AND +T 6800 700 5 10 1 1 0 0 1 1 +refdes=reset_n_out[WIDTH-1:0] } -C 38700 12500 1 0 0 or2-1.sym -{ -T 39100 12400 5 10 1 1 0 2 1 -refdes=OR -} -C 34900 11700 1 0 0 ipad.sym -{ -T 33500 11710 5 10 1 1 0 0 1 -refdes=SYNC_RESET -} -C 34900 11300 1 0 0 ipad.sym -{ -T 34200 11310 5 10 1 1 0 0 1 -refdes=RESET -} -C 34800 12900 1 0 0 ipad.sym -{ -T 32700 12910 5 10 1 1 0 0 1 -refdes=ATG_ASYNCDISABLE -} -C 34800 13600 1 0 0 ipad.sym -{ -T 33000 13610 5 10 1 1 0 0 1 -refdes=RESET_N -} -C 41800 11500 1 0 0 opad.sym -{ -T 42900 11510 5 10 1 1 0 0 1 -refdes=RESET_OUT -} -C 37500 12100 1 0 0 not-1.sym -{ -T 38000 12300 5 10 1 1 0 2 1 -refdes=INV -} -C 41800 12900 1 0 0 opad.sym -{ -T 42900 12910 5 10 1 1 0 0 1 -refdes=RESET_N_OUT -} -N 35700 13700 40200 13700 4 -N 40000 11600 41800 11600 4 -N 38700 13000 35700 13000 4 -N 38700 12600 38600 12600 4 -N 41800 13000 41500 13000 4 -L 32600 12100 32400 12100 3 0 0 0 -1 -1 -L 32600 16100 32400 16100 3 0 0 0 -1 -1 -L 36400 8300 36400 8100 3 0 0 0 -1 -1 -L 40400 8300 40400 8100 3 0 0 0 -1 -1 -L 34400 8300 34400 8100 3 0 0 0 -1 -1 -L 38400 8300 38400 8100 3 0 0 0 -1 -1 -L 42400 8300 42400 8100 3 0 0 0 -1 -1 -B 32400 8100 12000 9000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -L 32600 10100 32400 10100 3 0 0 0 -1 -1 -L 32600 14100 32400 14100 3 0 0 0 -1 -1 -T 40200 8900 9 20 1 0 0 0 1 -CDE_ASYNCDISABLE -C 38700 11300 1 0 0 or2-1.sym -{ -T 39100 11200 5 10 1 1 0 2 1 -refdes=OR -} -N 35800 11800 38700 11800 4 -N 35800 11400 38700 11400 4 -N 37500 12600 36200 12600 4 -N 36200 12600 36200 11800 4 -N 40200 12800 40000 12800 4 -N 40200 13200 40200 13700 4 -v 20040111 1 -C 9400 9800 1 0 0 and2-1.sym -{ -T 9800 9700 5 10 1 1 0 2 1 -refdes=AND -} -C 7900 9600 1 0 0 or2-1.sym -{ -T 8300 9500 5 10 1 1 0 2 1 -refdes=OR -} -C 6700 9200 1 0 0 not-1.sym -{ -T 7200 9400 5 10 1 1 0 2 1 -refdes=INV -} -N 9200 11300 11000 11300 4 -N 7900 9700 7800 9700 4 -N 11000 10100 10700 10100 4 -B 1400 7200 12000 9000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 1800 15600 9 20 1 0 0 0 1 -CDE_ASYNCDISABLE -C 7900 11000 1 0 0 or2-1.sym -{ -T 8300 10900 5 10 1 1 0 2 1 -refdes=OR -} -N 5400 11500 7900 11500 4 -N 6700 9700 5400 9700 4 -N 5400 9700 5400 13700 4 -N 9400 9900 9200 9900 4 -N 9400 10300 9400 10500 4 -N 2900 13700 5400 13700 4 -N 4300 11100 7900 11100 4 -N 4300 11100 4300 10100 4 -N 4300 10100 2900 10100 4 -N 6600 10500 9400 10500 4 -N 6600 10500 6600 12500 4 -N 6600 12500 2900 12500 4 -N 4600 10100 7900 10100 4 -N 4600 10100 4600 11300 4 -N 4600 11300 2900 11300 4 Index: trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v =================================================================== --- trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v (revision 27) +++ trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v (revision 28) @@ -49,7 +49,8 @@ input wire reset, input wire edge_enable, // one pulse per bit time for 16 x data rate timing input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent -input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1 +input wire parity_type, // 0= odd,1=even +input wire parity_force, // 1=force to parity_type input wire stop_value, // value out for stop bit input wire ser_in, // from pad_ring output reg [WIDTH-1:0] shift_buffer, @@ -69,7 +70,6 @@ // 0 Start bit // 1-> WIDTH Data bit lsb first // WIDTH+1 Parity bit if enabled -// 2^SIZE-2 Second stop bit if enabled // 2^SIZE-1 Last stop bit and idle always@(posedge clk) @@ -142,7 +142,7 @@ else if(!edge_enable) parity_calc <= parity_calc; else - if(parity_type[1] || (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type[0]; + if(parity_force || (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type; else if(shift_cnt <= WIDTH-1 ) parity_calc <= parity_calc ^ ser_in; else parity_calc <= parity_calc;
/trunk/lib/cde_serial_xmit/cde_serial_xmit.v
52,8 → 52,8
input wire reset,
input wire edge_enable, // one pulse per bit time for data rate timing
input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent
input wire two_stop_enable, // 0 = 1 stop bit, 1 = 2 stop bits
input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1
input wire parity_type, // 0= odd,1=even
input wire parity_force, // force parity_type
input wire load, // start transmiting data
input wire start_value, // value out at start bit time
input wire stop_value, // value out for stop bit also used for break
75,7 → 75,6
// 0 Start bit
// 1-> WIDTH Data bit lsb first
// WIDTH+1 Parity bit if enabled
// 2^SIZE-2 Second stop bit if enabled
// 2^SIZE-1 Last stop bit and idle
always@(posedge clk)
86,18 → 85,12
if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}};
else
if ( shift_cnt == WIDTH)
case({two_stop_enable,parity_enable})
(2'b00): shift_cnt <= {SIZE{1'b1}};
(2'b01): shift_cnt <= shift_cnt + 1'b1;
(2'b10): shift_cnt <= {SIZE{1'b1}} - 1'b1;
(2'b11): shift_cnt <= shift_cnt + 1'b1;
case(parity_enable)
(1'b0): shift_cnt <= {SIZE{1'b1}};
(1'b1): shift_cnt <= shift_cnt + 1'b1;
endcase // case ({two_stop_enable,parity_enable})
else
if ( shift_cnt == (WIDTH+1))
case( two_stop_enable)
(1'b0): shift_cnt <= {SIZE{1'b1}};
(1'b1): shift_cnt <= {SIZE{1'b1}} - 1'b1;
endcase
if ( shift_cnt == (WIDTH+1)) shift_cnt <= {SIZE{1'b1}};
else shift_cnt <= shift_cnt + 1'b1;
 
//
135,9 → 128,13
always@(posedge clk)
if(reset) shift_buffer <= {WIDTH{1'b0}};
else
if(load) shift_buffer <= data;
else
if(!edge_enable) shift_buffer <= shift_buffer;
else
if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= data;
if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= shift_buffer;
else
if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= shift_buffer;
else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]};
 
 
156,7 → 153,7
else
if(!edge_enable) parity_calc <= parity_calc;
else
if(parity_type[1] || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type[0];
if(parity_force || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type;
else parity_calc <= parity_calc ^ shift_buffer[0];
 
 
/trunk/lib/cde_sram/cde_sram.v
59,7 → 59,7
input wire [ADDR-1:0] raddr,
input wire wr,
input wire rd,
input wire [WIDTH-1:0] wdata,
input wire [WIDTH-1:0] wdata,
output reg [WIDTH-1:0] rdata
);
92,12 → 92,39
if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0];
 
 
// Read function
generate
 
if( WRITETHRU)
 
begin
// Read function gets new data if also a write cycle
 
// latch the read addr for next cycle
reg [ADDR-1:0] l_raddr;
always@(posedge clk) l_raddr <= raddr;
 
// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
 
wire [WIDTH-1:0] tmp_rdata;
 
assign tmp_rdata = (rd && cs )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
 
always@(*) rdata = tmp_rdata;
 
end
else
begin
// Read function gets old data if also a write cycle
always@(posedge clk)
if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}];
else rdata <= DEFAULT;
end
 
endgenerate
 
endmodule
 
 
/trunk/lib/cde_fifo/cde_fifo.v
0,0 → 1,277
/**********************************************************************/
/* */
/* ------- */
/* / SOC \ */
/* / GEN \ */
/* / LIB \ */
/* ============== */
/* | | */
/* |____________| */
/* */
/* Generic model for a fifo */
/* */
/* */
/* Author(s): */
/* - John Eaton, jt_eaton@opencores.org */
/* */
/**********************************************************************/
/* */
/* Copyright (C) <2010> <Ouabache Design Works> */
/* */
/* This source file may be used and distributed without */
/* restriction provided that this copyright statement is not */
/* removed from the file and that any derivative work contains */
/* the original copyright notice and the associated disclaimer. */
/* */
/* This source file is free software; you can redistribute it */
/* and/or modify it under the terms of the GNU Lesser General */
/* Public License as published by the Free Software Foundation; */
/* either version 2.1 of the License, or (at your option) any */
/* later version. */
/* */
/* This source is distributed in the hope that it will be */
/* useful, but WITHOUT ANY WARRANTY; without even the implied */
/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
/* PURPOSE. See the GNU Lesser General Public License for more */
/* details. */
/* */
/* You should have received a copy of the GNU Lesser General */
/* Public License along with this source; if not, download it */
/* from http://www.opencores.org/lgpl.shtml */
/* */
/**********************************************************************/
 
 
 
 
 
module
cde_fifo
#(parameter WIDTH = 8,
parameter SIZE = 2, // DEPTH = 2 ^ SIZE
parameter WORDS = 4
)
(
input wire clk,
input wire reset,
input wire push,
input wire [WIDTH-1:0] din,
input wire pop,
output wire [WIDTH-1:0] dout,
output reg full,
output reg empty,
output reg over_run,
output reg under_run
);
 
 
reg [SIZE-1:0] push_pointer;
reg [SIZE-1:0] pop_pointer;
 
 
reg r;
reg w;
reg [SIZE:0] push_1;
reg [SIZE:0] pop_1;
 
always@(*) push_1 = (push_pointer + 1'b1);
always@(*) pop_1 = (pop_pointer + 1'b1);
 
 
always@(*) r = (pop_pointer == push_1[SIZE-1:0]);
always@(*) w = (push_pointer == pop_1[SIZE-1:0]);
 
 
always@(posedge clk)
if(reset)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= {SIZE{1'b0}};
pop_pointer <= {SIZE{1'b0}};
end
else
if(empty && !full)
if( push && ~pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if(~push && pop)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b1;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if( push && pop)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(!empty && !full)
if( push && pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
if( push && !pop && r)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if( push && !pop && !r)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer+1;
pop_pointer <= pop_pointer;
end
else
if(~push && pop && w)
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
if(~push && pop && !w)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(!empty && full)
if( push && ~pop)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b1;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
else
if(~push && pop)
begin
full <= 1'b0;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer+1;
end
else
if( push && pop)
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer + 1;
pop_pointer <= pop_pointer + 1;
end
else
begin
full <= 1'b1;
empty <= 1'b0;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= push_pointer;
pop_pointer <= pop_pointer;
end
// full and empty at the same time should never occur
 
else
begin
full <= 1'b0;
empty <= 1'b1;
over_run <= 1'b0;
under_run <= 1'b0;
push_pointer <= {SIZE{1'b0}};
pop_pointer <= {SIZE{1'b0}};
end
 
 
 
 
 
cde_sram
#(.ADDR (SIZE),
.WIDTH (WIDTH),
.WORDS (WORDS),
.WRITETHRU (1)
)
fifo
(
.clk ( clk ),
.cs ( 1'b1 ),
.waddr ( push_pointer ),
.raddr ( pop_pointer ),
.wr ( push ),
.rd ( 1'b1 ),
.wdata ( din ),
.rdata ( dout )
);
 
 
endmodule
/trunk/projects/pic_micro/ip/soc_mouse/rtl/verilog/soc_mouse.v
9,8 → 9,13
parameter ROM_FILE = "NONE",
parameter ROM_WORDS = 0,
parameter ROM_ADDR = 0,
parameter ROM_WIDTH = 0
 
parameter ROM_WIDTH = 0,
parameter TX_FIFO = 0,
parameter TX_FIFO_SIZE = 3,
parameter TX_FIFO_WORDS = 8,
parameter RX_FIFO = 0,
parameter RX_FIFO_SIZE = 3,
parameter RX_FIFO_WORDS = 8
)
(
 
220,9 → 225,15
 
io_module_mouse
#(
.BASE_ADDR ( 1'b1),
.BASE_WIDTH ( 1),
.ADDR_WIDTH ( 9)
.BASE_ADDR ( 1'b1 ),
.BASE_WIDTH ( 1 ),
.ADDR_WIDTH ( 9 ),
.TX_FIFO ( TX_FIFO ),
.TX_FIFO_SIZE ( TX_FIFO_SIZE ),
.TX_FIFO_WORDS ( TX_FIFO_WORDS ),
.RX_FIFO ( RX_FIFO ),
.RX_FIFO_SIZE ( RX_FIFO_SIZE ),
.RX_FIFO_WORDS ( RX_FIFO_WORDS )
)
io_module (
/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/liblist
3,3 → 3,4
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v"
`include "../../lib/cde_fifo/cde_fifo.v"
/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/filelist
3,6 → 3,7
`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module_mouse.v"
 
`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v"
`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v"
`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v"
 
/trunk/projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist
14,5 → 14,6
verilog work ./target/lib/syn/cde_divider/cde_divider.v
verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
 
/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/filelist
13,6 → 13,7
verilog work ./target/lib/syn/cde_divider/cde_divider.v
verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v
verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v
verilog work ./target/lib/syn/cde_fifo/cde_fifo.v
verilog work ./target/lib/syn/cde_sram/cde_sram.v
verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v
 
/trunk/projects/pic_micro/ip/mrisc/doc/README.txt
1,4 → 1,30
 
This component takes the opencores minirisc project and makes it socgen compatible.
The original project checked in by Rudolf Usselmann consisted of serveral rtl files
and a small test suite.It had a little documentation(see below) and used xilinx primitives
in its code.
 
I chose it because it is very powerful for it's size and is well supported with free assemblers.
It fits in about 5% of a Nexys2 fpga.The following changes were made:
 
 
 
1) Split out each module into a seperate file with replaceable module names and
variants
 
2) Removed the xilinx primatives
 
3) Replaced the ram with a cde_ram.
 
4) Removed internal tristates that now must be done in pad_ring
 
 
 
 
 
 
-----------------------------------------------------------------
 
This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the
PIC 16C57 from Microchip.
 
/trunk/projects/pic_micro/sw/vga_font/vga_font.asm
0,0 → 1,313
 
cpu 6502
output HEX
* = $0000 ; assemble at $0000
code
;-------------------------------------------
; ;
;Code 00h defines a solid block ;
;Codes 01h-04h define block graphics ;
;Codes 05h-1Fh define line graphics ;
;Codes 20h-7Eh define the ASCII characters ;
;Code 7Fh defines a hash pattern ;
;Codes 80h-FFh user defined characters ;
;------------------------------------------- ;
;//// Solid Block ////
;// 00h: solid block address 000
db $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
;// Block graphics ////
; 01h: Left block up, right block down address 008
db $F0,$F0,$F0,$F0,$0F,$0F,$0F,$0F;
; 02h: Left block down, right block up address 010
db $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0;
; 03h: Both blocks down address 018
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 04h: Both blocks up address 020
db $FF,$FF,$FF,$FF,$00,$00,$00,$00;
;// Line Graphics ////
; 05h: corner upper left address 028
db $FF,$80,$80,$80,$80,$80,$80,$80;
; 06h: corner upper right address 030
db $FF,$01,$01,$01,$01,$01,$01,$01;
; 07h: corner lower left address 038
db $80,$80,$80,$80,$80,$80,$80,$FF;
; 08h: corner lower right address 040
db $01,$01,$01,$01,$01,$01,$01,$FF;
; 09h: cross junction address 048
db $10,$10,$10,$FF,$10,$10,$10,$10;
; 0Ah: "T" junction address 050
db $FF,$10,$10,$10,$10,$10,$10,$10;
; 0Bh: "T" juntion rotated 90 clockwise address 058
db $01,$01,$01,$FF,$01,$01,$01,$01;
; 0Ch: "T" juntion rotated 180 address 060
db $10,$10,$10,$10,$10,$10,$10,$FF;
; 0Dh: "T" junction rotated 270 clockwise address 068
db $80,$80,$80,$FF,$80,$80,$80,$80;
; 0Eh: arrow pointing right address 070
db $08,$04,$02,$FF,$02,$04,$08,$00;
; 0Fh: arrow pointing left address 078
db $10,$20,$40,$FF,$40,$20,$10,$00;
; 10h: first (top) horizontal line address 080
db $FF,$00,$00,$00,$00,$00,$00,$00;
; 11h: second horizontal line address 088
db $00,$FF,$00,$00,$00,$00,$00,$00;
; 12h: third horizontal line address 090
db $00,$00,$FF,$00,$00,$00,$00,$00;
; 13h: fourth horizontal line address 098
db $00,$00,$00,$FF,$00,$00,$00,$00;
; 14h: fifth horizontal line address 0A0
db $00,$00,$00,$00,$FF,$00,$00;
; 15h: sixth horizontal line address 0A7
db $00,$00,$00,$00,$00,$00,$FF,$00,$00;
; 16h: seventh horizontal line address 0B0
db $00,$00,$00,$00,$00,$00,$FF,$00;
; 17h: eighth (bottom) horizontal line address 0B8
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 18h: first (left) vertical line address 0C0
db $80,$80,$80,$80,$80,$80,$80,$80;
; 19h: second vertical line address 0C8
db $40,$40,$40,$40,$40,$40,$40,$40;
; 1Ah: third vertical line address 0D0
db $20,$20,$20,$20,$20,$20,$20,$20;
; 1Bh: fourth vertical line address 0D8
db $10,$10,$10,$10,$10,$10,$10,$10;
; 1Ch: fifth vertical line address 0E0
db $08,$08,$08,$08,$08,$08,$08,$08;
; 1Dh: sixth vertical line address 0E8
db $04,$04,$04,$04,$04,$04,$04,$04;
; 1Eh: seventh vertical line address 0F0
db $02,$02,$02,$02,$02,$02,$02,$02;
; 1Fh: eighth (right) vertical line address 0F8
db $01,$01,$01,$01,$01,$01,$01,$01;
;// ASCII Characters ////
; 20h: space address 100
db $00,$00,$00,$00,$00,$00,$00,$00;
; 21h: ! address 108
db $10,$10,$10,$10,$00,$00,$10,$00;
; 22h: " address 110
db $28,$28,$28,$00,$00,$00,$00,$00;
; 23h: # address 118
db $28,$28,$7C,$28,$7C,$28,$28,$00;
; 24h: $ address 120
db $10,$3C,$50,$38,$14,$78,$10,$00;
; 25h: % address 128
db $60,$64,$08,$10,$20,$46,$06,$00;
; 26h: & address 130
db $30,$48,$50,$20,$54,$48,$34,$00;
; 27h: ' address 138
db $30,$10,$20,$00,$00,$00,$00,$00;
; 28h: ( address 140
db $08,$10,$20,$20,$20,$10,$08,$00;
; 29h: ) address 148
db $20,$10,$08,$08,$08,$10,$20,$00;
; 2Ah: * address 150
db $00,$10,$54,$38,$54,$10,$00,$00;
; 2Bh: + address 158
db $00,$10,$10,$7C,$10,$10,$00,$00;
; 2Ch: , address 160
db $00,$00,$00,$00,$00,$30,$10,$20;
; 2Dh: - address 168
db $00,$00,$00,$7C,$00,$00,$00,$00;
; 2Eh: . address 170
db $00,$00,$00,$00,$00,$30,$30,$00;
; 2Fh: / address 178
db $00,$04,$08,$10,$20,$40,$00,$00;
; 30h: 0 address 180
db $38,$44,$4C,$54,$64,$44,$38,$00;
; 31h: 1 address 188
db $10,$30,$10,$10,$10,$10,$38,$00;
; 32h: 2 address 190
db $38,$44,$04,$08,$10,$20,$7C,$00;
; 33h: 3 address 198
db $7C,$08,$10,$08,$04,$44,$38,$00;
; 34h: 4 address 1A0
db $08,$18,$28,$48,$7C,$08,$08,$00;
; 35h: 5 address 1A8
db $7C,$40,$78,$04,$04,$44,$38,$00;
; 36h: 6 address 1B0
db $18,$20,$40,$78,$44,$44,$38,$00;
; 37h: 7 address 1B8
db $7C,$04,$08,$10,$20,$20,$20,$00;
; 38h: 8 address 1C0
db $38,$44,$44,$38,$44,$44,$38,$00;
; 39h: 9 address 1C8
db $38,$44,$44,$3C,$04,$08,$30,$00;
; 3Ah: : address 1D0
db $00,$30,$30,$00,$00,$30,$30,$00;
; 3Bh: ; address 1D8
db $00,$30,$30,$00,$00,$30,$10,$20;
; 3Ch: < address 1E0
db $08,$10,$20,$40,$20,$10,$08,$00;
; 3Dh: = address 1E8
db $00,$00,$7C,$00,$7C,$00,$00,$00;
; 3Eh: > address 1F0
db $20,$10,$08,$04,$08,$10,$20,$00;
; 3Fh: ? address 1F8
db $38,$44,$04,$08,$10,$00,$10,$00;
; 40h: @ address 200
db $38,$44,$04,$34,$54,$54,$38,$00;
; 41h: A address 208
db $38,$44,$44,$44,$7C,$44,$44,$00;
; 42h: B address 210
db $78,$44,$44,$78,$44,$44,$78,$00;
; 43h: C address 218
db $38,$44,$40,$40,$40,$44,$38,$00;
; 44h: D address 220
db $70,$48,$44,$44,$44,$48,$70,$00;
; 45h: E address 228
db $7C,$40,$40,$78,$40,$40,$7C,$00;
; 46h: F address 230
db $7C,$40,$40,$78,$40,$40,$40,$00;
; 47h: G address 238
db $38,$44,$40,$5C,$44,$44,$3C,$00;
; 48h: H address 240
db $44,$44,$44,$7C,$44,$44,$44,$00;
; 49h: I address 248
db $38,$10,$10,$10,$10,$10,$38,$00;
; 4Ah: J address 250
db $1C,$08,$08,$08,$08,$48,$30,$00;
; 4Bh: K address 258
db $44,$48,$50,$60,$50,$48,$44,$00;
; 4Ch: L address 260
db $40,$40,$40,$40,$40,$40,$7C,$00;
; 4Dh: M address 268
db $44,$6C,$54,$54,$44,$44,$44,$00;
; 4Eh: N address 270
db $44,$44,$64,$54,$4C,$44,$44,$00;
; 4Fh: O address 278
db $38,$44,$44,$44,$44,$44,$38,$00;
; 50h: P address 280
db $78,$44,$44,$78,$40,$40,$40,$00;
; 51h: Q address 288
db $38,$44,$44,$44,$54,$48,$34,$00;
; 52h: R address 290
db $78,$44,$44,$78,$50,$48,$44,$00;
; 53h: S address 298
db $3C,$40,$40,$38,$04,$04,$78,$00;
; 54h: T address 2A0
db $7C,$10,$10,$10,$10,$10,$10,$00;
; 55h: U address 2A8
db $44,$44,$44,$44,$44,$44,$38,$00;
; 56h: V address 2B0
db $44,$44,$44,$44,$44,$28,$10,$00;
; 57h: W address 2B8
db $44,$44,$44,$54,$54,$54,$28,$00;
; 58h: X address 2C0
db $44,$44,$28,$10,$28,$44,$44,$00;
; 59h: Y address 2C8
db $44,$44,$44,$28,$10,$10,$10,$00;
; 5Ah: Z address 2D0
db $7C,$04,$08,$10,$20,$40,$7C,$00;
; 5Bh: [ address 2D8
db $38,$20,$20,$20,$20,$20,$38,$00;
; 5Ch: \ address 2E0
db $00,$40,$20,$10,$08,$04,$00,$00;
; 5Dh: ] address 2E8
db $38,$08,$08,$08,$08,$08,$38,$00;
; 5Eh: ^ address 2F0
db $10,$28,$44,$00,$00,$00,$00,$00;
; 5Fh: _ address 2F8
db $00,$00,$00,$00,$00,$00,$7C,$00;
; 60h: ` address 300
db $20,$10,$08,$00,$00,$00,$00,$00;
; 61h: a address 308
db $00,$00,$38,$04,$3C,$44,$3C,$00;
; 62h: b address 310
db $40,$40,$58,$64,$44,$44,$78,$00;
; 63h: c address 318
db $00,$00,$38,$40,$40,$44,$38,$00;
; 64h: d address 320
db $04,$04,$34,$4C,$44,$44,$3C,$00;
; 65h: e address 328
db $00,$00,$38,$44,$7C,$40,$38,$00;
; 66h: f address 330
db $18,$24,$20,$70,$20,$20,$20,$00;
; 67h: g address 338
db $00,$00,$3C,$44,$44,$3C,$04,$38;
; 68h: h address 340
db $40,$40,$58,$64,$44,$44,$44,$00;
; 69h: i address 348
db $10,$10,$30,$10,$10,$10,$38,$00;
; 6Ah: j address 350
db $00,$08,$00,$18,$08,$08,$48,$30;
; 6Bh: k address 358
db $40,$40,$48,$50,$60,$50,$48,$00;
; 6Ch: l address 360
db $30,$10,$10,$10,$10,$10,$38,$00;
; 6Dh: m address 368
db $00,$00,$68,$54,$54,$44,$44,$00;
; 6Eh: n address 370
db $00,$00,$58,$64,$44,$44,$44,$00;
; 6Fh: o address 378
db $00,$00,$38,$44,$44,$44,$38,$00;
; 70h: p address 380
db $00,$00,$78,$44,$78,$40,$40,$40;
; 71h: q address 388
db $00,$00,$00,$34,$4C,$3C,$04,$04;
; 72h: r address 390
db $00,$00,$58,$64,$40,$40,$40,$00;
; 73h: s address 398
db $00,$00,$38,$40,$38,$04,$78,$00;
; 74h: t address 3A0
db $00,$20,$20,$70,$20,$20,$24,$18;
; 75h: u address 3A8
db $00,$00,$44,$44,$44,$4C,$34,$00;
; 76h: v address 3B0
db $00,$00,$44,$44,$44,$28,$10,$00;
; 77h: w address 3B8
db $00,$00,$44,$44,$54,$54,$28,$00;
; 78h: x address 3C0
db $00,$00,$44,$28,$10,$28,$44,$00;
; 79h: y address 3C8
db $00,$00,$00,$44,$44,$3C,$04,$38;
; 7Ah: z address 3D0
db $00,$00,$7C,$08,$10,$20,$7C,$00;
; 7Bh: { address 3D8
db $08,$10,$10,$20,$10,$10,$08,$00;
; 7Ch: | address 3E0
db $10,$10,$10,$10,$10,$10,$10,$00;
; 7Dh: } address 3E8
db $20,$10,$10,$08,$10,$10,$20,$00;
; 7Eh: ~ address 3F0
db $00,$00,$60,$92,$0C,$00,$00,$00;
;// Hash Pattern ////
; 7Fh: hash pattern address 3F8
db $55,$AA,$55,$AA,$55,$AA,$55,$AA;
;// User Defined Characters ////
; 80h: vertical to the left address 400
db $F0,$F0,$F0,$F0,$F0,$F0,$F0,$F0;
; 81h: vertical to the right address 408
db $0F,$0F,$0F,$0F,$0F,$0F,$0F,$0F;
; 82h: circle address 410
db $00,$18,$3C,$7E,$7E,$3C,$18,$00;
; 83h: Upper left block only address 418
db $F0,$F0,$F0,$F0,$00,$00,$00,$00;
; 84h: Upper right block only address 420
db $0F,$0F,$0F,$0F,$00,$00,$00,$00;
; 85h: Lower left block only address 428
db $00,$00,$00,$00,$F0,$F0,$F0,$F0;
; 86h: Lower right block only address 430
db $00,$00,$00,$00,$0F,$0F,$0F,$0F;
; 87h: One horizontal line address 438
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 88h: Two horizontal lines address 440
db $00,$00,$00,$00,$00,$00,$FF,$FF;
; 89h: Three horizontal lines address 448
db $00,$00,$00,$00,$00,$FF,$FF,$FF;
; 8Ah: Four horizontal lines address 450
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 8Bh: Five horizontal lines address 458
db $00,$00,$00,$FF,$FF,$FF,$FF,$FF;
; 8Ch: Six horizontal lines address 460
db $00,$00,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Dh: Seven horizontal lines address 468
db $00,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Eh: One vertical line address 470
db $80,$80,$80,$80,$80,$80,$80,$80;
; 8Fh: Two vertical lines address 478
db $c0,$c0,$c0,$c0,$c0,$c0,$c0,$c0;
 
 
code
/trunk/projects/pic_micro/sw/vga_font/Makefile
0,0 → 1,5
include ../../bin/Makefile.root
code=vga_font
 
 
all: asm_6502
/trunk/projects/pic_micro/sw/vga_startup_screen/Makefile
0,0 → 1,5
include ../../bin/Makefile.root
code=vga_startup_screen
 
 
all: asm_6502
/trunk/projects/pic_micro/sw/vga_startup_screen/vga_startup_screen.asm
0,0 → 1,69
 
cpu 6502
output HEX
* = $0000 ;
code
ASC "+------------------------------------------------------------------------------+";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| SOCGEN Project |";
ASC "| pic_micro/soc_mouse |";
ASC "| |";
ASC "| abcdefghijklmnopqrstuvwxyz |";
ASC "| |";
ASC "| ABCDEFGHIJKLMNOPQRSTUVWXYZ |";
ASC "| |";
ASC "| 1234567890 |";
ASC "| |";
ASC "| `~!@#$%^&*()-_=+[{]}|;:,<.>? |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "+------------------------------------------------------------------------------+";
 
code
/trunk/projects/Mos6502/bin/Makefile
0,0 → 1,2
include ./Makefile.root
 
/trunk/projects/Mos6502/ip/T6502/rtl/variants/T6502/T6502_defines.v
0,0 → 1,358
`define VARIANT T6502
 
`define CORE _core
`define FSM _fsm
`define ALU _alu
 
`define CDE cde
`define SRAM _sram
 
`define IO_MODULE io_module
 
////////////////////////////////////////////////////////////////////////////
//// ////
//// T6507LP IP Core ////
//// ////
//// This file is part of the T6507LP project ////
//// http://www.opencores.org/cores/t6507lp/ ////
//// ////
//// Description ////
//// T6507LP Package ////
//// ////
//// To Do: ////
//// - Documentation ////
//// - Check syntax & Compile ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////
//// ////
//// Processor Status Register ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// C - Carry Flag ////
//// Z - Zero Flag ////
//// I - Interrupt Disable ////
//// D - Decimal Mode ////
//// B - Break Command ////
//// 1 - Constant One ////
//// V - oVerflow Flag ////
//// N - Negative Flag ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// ------------------------------------------------- ////
//// | N | V | 1 | B | D | I | Z | C | ////
//// ------------------------------------------------- ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
`define C 3'b000
`define Z 3'b001
`define I 3'b010
`define D 3'b011
`define B 3'b100
`define V 3'b110
`define N 3'b111
 
 
// All opcodes are listed in alphabetic order.
 
////////////////////////////////////////////////////////////////////////////
//// ////
//// Addressing Modes ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// IMP - Implicit ////
//// ACC - Accumulator ////
//// IMM - Immediate ////
//// ZPG - Zero Page ////
//// ZPX - Zero Page,X ////
//// ZPY - Zero Page,Y ////
//// REL - Relative ////
//// ABS - Absolute ////
//// ABX - Absolute,X ////
//// ABY - Absolute,Y ////
//// IDX - (Indirect,X) ////
//// IDY - (Indirect),Y ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
`define IMP 4'h0
`define ACC 4'h1
`define IMM 4'h2
`define ZPG 4'h3
`define ZPX 4'h4
`define ZPY 4'h5
`define REL 4'h6
`define ABS 4'h7
`define ABX 4'h8
`define ABY 4'h9
`define IDX 4'hA
`define IDY 4'hB
 
 
//TODO: Document all opcodes
////////////////////////////////////////////////////////////////////////////
//// ////
//// ADC - Add with Carry ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// AZ,C,N A+M+C ////
//// ////
//// This instruction adds the contents of a memory location to the ////
//// accumulator together with the carry bit. If overflow occurs the ////
//// carry bit is set, this enables multiple byte addition to be ////
//// performed. ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// C - Not affected ////
//// Z - Not affected ////
//// I - Not affected ////
//// D - Not affected ////
//// B - Not affected ////
//// V - Not affected ////
//// N - Not affected ////
//// ////
////////////////////////////////////////////////////////////////////////////
`define ADC_IMM 8'h69
`define ADC_ZPG 8'h65
`define ADC_ZPX 8'h75
`define ADC_ABS 8'h6D
`define ADC_ABX 8'h7D
`define ADC_ABY 8'h79
`define ADC_IDX 8'h61
`define ADC_IDY 8'h71
 
`define AND_IMM 8'h29
`define AND_ZPG 8'h25
`define AND_ZPX 8'h35
`define AND_ABS 8'h2D
`define AND_ABX 8'h3D
`define AND_ABY 8'h39
`define AND_IDX 8'h21
`define AND_IDY 8'h31
 
`define ASL_ACC 8'h0A
`define ASL_ZPG 8'h06
`define ASL_ZPX 8'h16
`define ASL_ABS 8'h0E
`define ASL_ABX 8'h1E
 
`define BCC_REL 8'h90
 
`define BCS_REL 8'hB0
 
`define BEQ_REL 8'hF0
 
`define BIT_ZPG 8'h24
`define BIT_ABS 8'h2C
 
`define BMI_REL 8'h30
 
`define BNE_REL 8'hD0
 
`define BPL_REL 8'h10
 
`define BRK_IMP 8'h00
 
`define BVC_REL 8'h50
 
`define BVS_REL 8'h70
 
`define CLC_IMP 8'h18
 
`define CLD_IMP 8'hD8
 
`define CLI_IMP 8'h58
 
`define CLV_IMP 8'hB8
 
`define CMP_IMM 8'hC9
`define CMP_ZPG 8'hC5
`define CMP_ZPX 8'hD5
`define CMP_ABS 8'hCD
`define CMP_ABX 8'hDD
`define CMP_ABY 8'hD9
`define CMP_IDX 8'hC1
`define CMP_IDY 8'hD1
 
`define CPX_IMM 8'hE0
`define CPX_ZPG 8'hE4
`define CPX_ABS 8'hEC
 
`define CPY_IMM 8'hC0
`define CPY_ZPG 8'hC4
`define CPY_ABS 8'hCC
 
`define DEC_ZPG 8'hC6
`define DEC_ZPX 8'hD6
`define DEC_ABS 8'hCE
`define DEC_ABX 8'hDE
 
`define DEX_IMP 8'hCA
 
`define DEY_IMP 8'h88
 
`define EOR_IMM 8'h49
`define EOR_ZPG 8'h45
`define EOR_ZPX 8'h55
`define EOR_ABS 8'h4D
`define EOR_ABX 8'h5D
`define EOR_ABY 8'h59
`define EOR_IDX 8'h41
`define EOR_IDY 8'h51
 
`define INC_ZPG 8'hE6
`define INC_ZPX 8'hF6
`define INC_ABS 8'hEE
`define INC_ABX 8'hFE
 
`define INX_IMP 8'hE8
 
`define INY_IMP 8'hC8
 
`define JMP_ABS 8'h4C
`define JMP_IND 8'h6C
 
`define JSR_ABS 8'h20
 
`define LDA_IMM 8'hA9
`define LDA_ZPG 8'hA5
`define LDA_ZPX 8'hB5
`define LDA_ABS 8'hAD
`define LDA_ABX 8'hBD
`define LDA_ABY 8'hB9
`define LDA_IDX 8'hA1
`define LDA_IDY 8'hB1
 
`define LDX_IMM 8'hA2
`define LDX_ZPG 8'hA6
`define LDX_ZPY 8'hB6
`define LDX_ABS 8'hAE
`define LDX_ABY 8'hBE
 
`define LDY_IMM 8'hA0
`define LDY_ZPG 8'hA4
`define LDY_ZPX 8'hB4
`define LDY_ABS 8'hAC
`define LDY_ABX 8'hBC
 
`define LSR_ACC 8'h4A
`define LSR_ZPG 8'h46
`define LSR_ZPX 8'h56
`define LSR_ABS 8'h4E
`define LSR_ABX 8'h5E
 
`define NOP_IMP 8'hEA
 
`define ORA_IMM 8'h09
`define ORA_ZPG 8'h05
`define ORA_ZPX 8'h15
`define ORA_ABS 8'h0D
`define ORA_ABX 8'h1D
`define ORA_ABY 8'h19
`define ORA_IDX 8'h01
`define ORA_IDY 8'h11
 
`define PHA_IMP 8'h48
 
`define PHP_IMP 8'h08
 
`define PLA_IMP 8'h68
 
`define PLP_IMP 8'h28
 
`define ROL_ACC 8'h2A
`define ROL_ZPG 8'h26
`define ROL_ZPX 8'h36
`define ROL_ABS 8'h2E
`define ROL_ABX 8'h3E
 
`define ROR_ACC 8'h6A
`define ROR_ZPG 8'h66
`define ROR_ZPX 8'h76
`define ROR_ABS 8'h6E
`define ROR_ABX 8'h7E
 
`define RTI_IMP 8'h40
 
`define RTS_IMP 8'h60
 
`define SBC_IMM 8'hE9
`define SBC_ZPG 8'hE5
`define SBC_ZPX 8'hF5
`define SBC_ABS 8'hED
`define SBC_ABX 8'hFD
`define SBC_ABY 8'hF9
`define SBC_IDX 8'hE1
`define SBC_IDY 8'hF1
 
`define SEC_IMP 8'h38
 
`define SED_IMP 8'hF8
 
`define SEI_IMP 8'h78
 
`define STA_ZPG 8'h85
`define STA_ZPX 8'h95
`define STA_ABS 8'h8D
`define STA_ABX 8'h9D
`define STA_ABY 8'h99
`define STA_IDX 8'h81
`define STA_IDY 8'h91
 
`define STX_ZPG 8'h86
`define STX_ZPY 8'h96
`define STX_ABS 8'h8E
 
`define STY_ZPG 8'h84
`define STY_ZPX 8'h94
`define STY_ABS 8'h8C
 
`define TAX_IMP 8'hAA
 
`define TAY_IMP 8'hA8
 
`define TSX_IMP 8'hBA
 
`define TXA_IMP 8'h8A
 
`define TXS_IMP 8'h9A
 
`define TYA_IMP 8'h98
 
 
/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502.v
0,0 → 1,236
 
`include "./T6502_defines.v"
 
 
module `VARIANT #(
parameter ROM_WORDS = 4096, // Number of words
parameter ROM_ADD = 12, // Number of address bits
parameter RAM_WORDS = 4096, // Number of words
parameter RAM_ADD = 12, // Number of address bits
parameter ROM_FILE = "NONE", // Rom Data file
parameter NMI_MODE = "8'h00",
parameter IRQ_MODE = "8'h00",
parameter TX_FIFO = 0,
parameter TX_FIFO_SIZE = 3,
parameter TX_FIFO_WORDS= 8,
parameter RX_FIFO = 0,
parameter RX_FIFO_SIZE = 3,
parameter RX_FIFO_WORDS= 8,
parameter STARTUP = "NONE",
parameter FONT = "NONE",
parameter BOOT = 16'hf000
 
 
) (
 
input wire clk,
input wire reset,
input wire enable,
output wire [7:0] write_data,
output wire [15:0] addr_pin,
 
 
output wire txd_pad_out,
input wire rxd_pad_in,
input wire cts_pad_in,
output wire rts_pad_out,
 
 
output wire ps2_clk_oe,
input wire ps2_clk_in,
output wire ps2_data_oe,
input wire ps2_data_in,
 
 
output wire [7:0] gpio_0_out,
output wire [7:0] gpio_0_oe,
output wire [7:0] gpio_0_lat,
input wire [7:0] gpio_0_in,
output wire [7:0] gpio_1_out,
output wire [7:0] gpio_1_oe,
output wire [7:0] gpio_1_lat,
input wire [7:0] gpio_1_in,
input wire [3:0] ext_irq_in,
 
 
output wire [2:0] vgared_pad_out,
output wire [2:0] vgagreen_pad_out,
output wire [1:0] vgablue_pad_out,
 
output wire hsync_n_pad_out,
output wire vsync_n_pad_out
 
 
 
 
);
wire [15:0] pc;
wire [7:0] read_data;
wire [7:0] flash_data;
wire [7:0] sram_data;
wire [7:0] din;
wire dout_oe;
wire rd_pin;
wire [1:0] timer_irq;
wire we_pin;
assign rd_pin = !we_pin;
assign din = sram_data & flash_data & read_data;
 
 
 
reg CS;
reg CS0;
 
always@(*)
begin
if(addr_pin[15:12] == 4'b0000)
begin
CS0 = 1'b1;
CS = 1'b0;
end
else
if(addr_pin[15:12] == 4'b1111)
begin
CS0 = 1'b0;
CS = 1'b1;
end
else
begin
CS0 = 1'b0;
CS = 1'b0;
end
end
 
 
 
 
`VARIANT`CORE
#(.BOOT(BOOT))
core (
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.address ( addr_pin ),
.pc ( pc ),
.data_in ( din ),
.data_out ( write_data ),
.rw_mem ( we_pin )
 
);
 
 
 
`CDE`SRAM
#(.WIDTH (8),
.ADDR (ROM_ADD),
.WORDS (ROM_WORDS),
.DEFAULT (8'hff),
.INIT_FILE (ROM_FILE)
) core_rom (
.clk (clk),
.raddr (addr_pin[ROM_ADD-1:0]),
.waddr (addr_pin[ROM_ADD-1:0]),
.cs (CS),
.wr (1'b0),
.wdata (8'h00),
.rd (rd_pin),
.rdata (flash_data));
 
 
 
`CDE`SRAM
#(.WIDTH (8),
.ADDR (RAM_ADD),
.WORDS (RAM_WORDS),
.DEFAULT (8'hff)
) core_ram (
.clk (clk),
.raddr (addr_pin[RAM_ADD-1:0]),
.waddr (addr_pin[RAM_ADD-1:0]),
.rdata (sram_data),
.wdata (write_data),
.rd (rd_pin),
.cs (CS0),
.wr (we_pin)
);
 
 
 
`IO_MODULE
#(.NMI_MODE (NMI_MODE ),
.IRQ_MODE (IRQ_MODE ),
.TX_FIFO (TX_FIFO ),
.TX_FIFO_SIZE (TX_FIFO_SIZE ),
.TX_FIFO_WORDS (TX_FIFO_WORDS ),
.RX_FIFO (RX_FIFO ),
.RX_FIFO_SIZE (RX_FIFO_SIZE ),
.STARTUP (STARTUP ),
.FONT (FONT )
)
 
io_module(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.addr ( addr_pin[15:0] ),
.waddr ( addr_pin[7:0] ),
.rdata ( read_data ),
.wdata ( write_data ),
.rd ( rd_pin ),
.wr ( we_pin ),
.pic_irq ( irq_in ),
.pic_nmi ( nmi_in ),
.gpio_0_out ( gpio_0_out ),
.gpio_0_oe ( gpio_0_oe ),
.gpio_0_lat ( gpio_0_lat ),
.gpio_0_in ( gpio_0_in ),
.gpio_1_out ( gpio_1_out ),
.gpio_1_oe ( gpio_1_oe ),
.gpio_1_lat ( gpio_1_lat ),
.gpio_1_in ( gpio_1_in ),
.timer_irq ( timer_irq ),
.txd_pad_out ( txd_pad_out ),
.rxd_pad_in ( rxd_pad_in ),
.cts_pad_in ( cts_pad_in ),
.rts_pad_out ( rts_pad_out ),
.rx_irq ( rx_irq ),
.tx_irq ( tx_irq ),
.ps2_clk_pad_oe ( ps2_clk_oe ),
.ps2_clk_pad_in ( ps2_clk_in ),
.ps2_data_pad_oe ( ps2_data_oe ),
.ps2_data_pad_in ( ps2_data_in ),
.ps2_data_avail ( ps2_data_avail ),
.ext_irq_in ( {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq}),
 
 
.vgared_pad_out ( vgared_pad_out),
.vgagreen_pad_out ( vgagreen_pad_out),
.vgablue_pad_out ( vgablue_pad_out),
 
.hsync_n_pad_out ( hsync_n_pad_out),
.vsync_n_pad_out ( vsync_n_pad_out)
 
 
);
 
 
endmodule
 
 
 
 
 
 
/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_alu.v
0,0 → 1,464
 
`include "T6502_defines.v"
 
module
`VARIANT`ALU
 
(
 
 
input wire clk,
input wire reset,
input wire enable,
input wire alu_enable,
input wire [7:0] alu_opcode,
input wire [7:0] alu_a,
 
output reg [7:0] alu_result,
output reg [7:0] alu_status,
output reg [7:0] alu_x,
output reg [7:0] alu_y
 
);
 
 
 
 
 
localparam [3:0] BCD_HIGH_LIMIT = 4'd9;
localparam [3:0] BCD_FIX = 8'd6;
 
 
 
reg [7:0] A;
reg [7:0] STATUS;
reg [9:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
 
always @ (posedge clk )
begin
if (reset) begin
alu_result <= 10'd0;
alu_status[`C] <= 1'b0;
alu_status[`N] <= 1'b0;
alu_status[`V] <= 1'b0;
alu_status[5] <= 1'b1;
alu_status[`Z] <= 1'b1;
alu_status[`I] <= 1'b0;
alu_status[`B] <= 1'b0;
alu_status[`D] <= 1'b0;
A <= 8'd0;
alu_x <= 8'd0;
alu_y <= 8'd0;
end
 
else
if ( !enable ) begin
alu_result <= alu_result;
alu_status <= alu_status;
A <= A;
alu_x <= alu_x;
alu_y <= alu_y;
 
end
 
else
if ( alu_enable == 1'b1 ) begin
case (alu_opcode)
`ADC_IMM, `ADC_ZPG, `ADC_ZPX, `ADC_ABS, `ADC_ABX, `ADC_ABY,
`ADC_IDX, `ADC_IDY, `AND_IMM, `AND_ZPG, `AND_ZPX, `AND_ABS,
`AND_ABX, `AND_ABY, `AND_IDX, `AND_IDY, `ASL_ACC, `EOR_IMM,
`EOR_ZPG, `EOR_ZPX, `EOR_ABS, `EOR_ABX, `EOR_ABY, `EOR_IDX,
`EOR_IDY, `LSR_ACC, `ORA_IMM, `ORA_ZPG, `ORA_ZPX, `ORA_ABS,
`ORA_ABX, `ORA_ABY, `ORA_IDX, `ORA_IDY, `ROL_ACC, `ROR_ACC,
`SBC_IMM, `SBC_ZPG, `SBC_ZPX, `SBC_ABS, `SBC_ABX, `SBC_ABY,
`SBC_IDX, `SBC_IDY, `LDA_IMM, `LDA_ZPG, `LDA_ZPX, `LDA_ABS,
`LDA_ABX, `LDA_ABY, `LDA_IDX, `LDA_IDY, `PLA_IMP : begin
A <= result[7:0];
alu_result <= result[7:0];
alu_status <= STATUS;
end
`LDX_IMM, `LDX_ZPG, `LDX_ZPY, `LDX_ABS, `LDX_ABY, `TAX_IMP,
`TSX_IMP, `INX_IMP, `DEX_IMP : begin
alu_x <= result[7:0];
alu_status <= STATUS;
end
`TXS_IMP : begin
alu_x <= result[7:0];
end
`TXA_IMP, `TYA_IMP : begin
A <= result[7:0];
alu_status <= STATUS;
end
`LDY_IMM, `LDY_ZPG, `LDY_ZPX, `LDY_ABS, `LDY_ABX, `TAY_IMP,
`INY_IMP, `DEY_IMP : begin
alu_y <= result[7:0];
alu_status <= STATUS;
end
`CMP_IMM, `CMP_ZPG, `CMP_ZPX, `CMP_ABS, `CMP_ABX, `CMP_ABY,
`CMP_IDX, `CMP_IDY, `CPX_IMM, `CPX_ZPG, `CPX_ABS, `CPY_IMM,
`CPY_ZPG, `CPY_ABS : begin
alu_status <= STATUS;
end
`PHA_IMP, `STA_ZPG, `STA_ZPX, `STA_ABS, `STA_ABX, `STA_ABY,
`STA_IDX, `STA_IDY : begin
alu_result <= result[7:0];
end
`STX_ZPG, `STX_ZPY, `STX_ABS : begin
alu_x <= result[7:0];
end
`STY_ZPG, `STY_ZPX, `STY_ABS : begin
alu_y <= result[7:0];
end
`SEC_IMP : begin
alu_status[`C] <= 1'b1;
end
`SED_IMP : begin
alu_status[`D] <= 1'b1;
end
`SEI_IMP : begin
alu_status[`I] <= 1'b1;
end
`CLC_IMP : begin
alu_status[`C] <= 1'b0;
end
`CLD_IMP : begin
alu_status[`D] <= 1'b0;
end
`CLI_IMP : begin
alu_status[`I] <= 1'b0;
end
`CLV_IMP : begin
alu_status[`V] <= 1'b0;
end
`BRK_IMP : begin
alu_status[`B] <= 1'b1;
end
`PLP_IMP, `RTI_IMP : begin
alu_status[`C] <= alu_a[`C];
alu_status[`Z] <= alu_a[`Z];
alu_status[`I] <= alu_a[`I];
alu_status[`D] <= alu_a[`D];
alu_status[`B] <= alu_a[`B];
alu_status[`V] <= alu_a[`V];
alu_status[`N] <= alu_a[`N];
alu_status[5] <= 1'b1;
end
`BIT_ZPG, `BIT_ABS : begin
alu_status[`Z] <= STATUS[`Z];
alu_status[`V] <= alu_a[6];
alu_status[`N] <= alu_a[7];
end
`INC_ZPG, `INC_ZPX, `INC_ABS, `INC_ABX, `DEC_ZPG, `DEC_ZPX,
`DEC_ABS, `DEC_ABX, `ASL_ZPG, `ASL_ZPX, `ASL_ABS, `ASL_ABX,
`LSR_ZPG, `LSR_ZPX, `LSR_ABS, `LSR_ABX, `ROL_ZPG, `ROL_ZPX,
`ROL_ABS, `ROL_ABX, `ROR_ZPG, `ROR_ZPX, `ROR_ABS, `ROR_ABX :
begin
alu_result <= result[7:0];
alu_status <= STATUS;
end
default : begin
alu_result <= 8'hFF;
alu_status <= 8'hFF;
A <= 8'hFF;
alu_x <= 8'hFF;
alu_y <= 8'hFF;
end
endcase
end
end
 
always @ (*) begin
op1 = A;
op2 = alu_a;
result = {2'd0, A[7:0]};
result[9:8] = 2'b00;
STATUS[`N] = alu_status[`N];
STATUS[`C] = alu_status[`C];
STATUS[`V] = alu_status[`V];
STATUS[`B] = alu_status[`B];
STATUS[`I] = alu_status[`I];
STATUS[`D] = alu_status[`D];
STATUS[`Z] = alu_status[`Z];
STATUS[5] = 1'b1;
 
bcdl = 8'd0;
bcdh = 8'd0;
bcdh2 = 8'd0;
AL = 8'd0;
AH = 8'd0;
 
if (alu_enable == 1'b1) begin
case (alu_opcode)
// BIT - Bit Test
`BIT_ZPG, `BIT_ABS: begin
result[7:0] = A & alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// PLA - Pull Accumulator
`PLA_IMP : begin
result[7:0] = alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// TAX - Transfer Accumulator to X
// TAY - Transfer Accumulator to Y
// PHA - Push Accumulator
// STA - Store Accumulator
`TAX_IMP, `TAY_IMP, `PHA_IMP, `STA_ZPG, `STA_ZPX, `STA_ABS, `STA_ABX,
`STA_ABY, `STA_IDX, `STA_IDY : begin
result[7:0] = A;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// STX - Store X Register
// TXA - Transfer X to Accumulator
// TXS - Transfer X to Stack pointer
`STX_ZPG, `STX_ZPY, `STX_ABS, `TXA_IMP, `TXS_IMP : begin
result[7:0] = alu_x;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// STY - Store Y Register
// TYA - Transfer Y to Accumulator
`STY_ZPG, `STY_ZPX, `STY_ABS, `TYA_IMP : begin
result[7:0] = alu_y;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// INC - Increment memory
`INC_ZPG, `INC_ZPX, `INC_ABS, `INC_ABX : begin
result[7:0] = alu_a + 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// INX - Increment X Register
`INX_IMP: begin
result[7:0] = alu_x + 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// INY - Increment Y Register
`INY_IMP : begin
result[7:0] = alu_y + 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// DEC - Decrement memory
`DEC_ZPG, `DEC_ZPX, `DEC_ABS, `DEC_ABX : begin
result[7:0] = alu_a - 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// DEX - Decrement X register
`DEX_IMP: begin
result[7:0] = alu_x - 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// DEY - Decrement Y Register
`DEY_IMP: begin
result[7:0] = alu_y - 8'd1;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// ADC - Add with carry
`ADC_IMM, `ADC_ZPG, `ADC_ZPX, `ADC_ABS,
`ADC_ABX, `ADC_ABY, `ADC_IDX, `ADC_IDY : begin
if (!alu_status[`D]) begin
result = op1 + op2 + {7'd0, alu_status[`C]}; // this looks so ugly but the operands are all 8 bits now
STATUS[`N] = result[7];
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1'b1 : 1'b0;
STATUS[`C] = result[8];
end
else begin
AL = op1[3:0] + op2[3:0] + {7'd0, alu_status[`C]};
AH = op1[7:4] + op2[7:4];
STATUS[`Z] = (AL == 0 && AH == 0) ? 1'b1 : 1'b0;
if (AL > {4'd0,BCD_HIGH_LIMIT}) begin
bcdl = AL + {4'd0, BCD_FIX};
bcdh = AH + 8'd1;
end
else begin
bcdl = AL;
bcdh = AH;
end
STATUS[`N] = bcdh[3];
STATUS[`V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1'b1 : 1'b0;
if (bcdh > {4'd0, BCD_HIGH_LIMIT}) begin
bcdh2 = bcdh + {4'd0, BCD_FIX};
end
else begin
bcdh2 = bcdh;
end
STATUS[`C] = bcdh2[4] || bcdh2[5];
result[7:0] = {bcdh2[3:0], bcdl[3:0]};
end
end
// AND - Logical AND
`AND_IMM, `AND_ZPG, `AND_ZPX, `AND_ABS, `AND_ABX, `AND_ABY, `AND_IDX,
`AND_IDY : begin
result[7:0] = A & alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// CMP - Compare
`CMP_IMM, `CMP_ZPG, `CMP_ZPX, `CMP_ABS, `CMP_ABX, `CMP_ABY, `CMP_IDX,
`CMP_IDY : begin
result[7:0] = A - alu_a;
STATUS[`C] = (A >= alu_a) ? 1'b1 : 1'b0;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// EOR - Exclusive OR
`EOR_IMM, `EOR_ZPG, `EOR_ZPX, `EOR_ABS, `EOR_ABX, `EOR_ABY,
`EOR_IDX, `EOR_IDY : begin
result[7:0] = A ^ alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// LDA - Load Accumulator
// LDX - Load X Register
// LDY - Load Y Register
// TSX - Transfer Stack Pointer to X
`LDA_IMM, `LDA_ZPG, `LDA_ZPX, `LDA_ABS, `LDA_ABX, `LDA_ABY, `LDA_IDX,
`LDA_IDY, `LDX_IMM, `LDX_ZPG, `LDX_ZPY, `LDX_ABS, `LDX_ABY, `LDY_IMM,
`LDY_ZPG, `LDY_ZPX, `LDY_ABS, `LDY_ABX, `TSX_IMP : begin
result[7:0] = alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// ORA - Logical OR
`ORA_IMM, `ORA_ZPG, `ORA_ZPX, `ORA_ABS, `ORA_ABX, `ORA_ABY, `ORA_IDX,
`ORA_IDY : begin
result[7:0] = A | alu_a;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// SBC - Subtract with Carry
`SBC_IMM, `SBC_ZPG, `SBC_ZPX, `SBC_ABS, `SBC_ABX, `SBC_ABY, `SBC_IDX,
`SBC_IDY : begin
result = op1 - op2 - (1'b1 - alu_status[`C]);
STATUS[`N] = result[7];
STATUS[`V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1'b1 : 1'b0;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`C] = ~(result[8] || result[9]);
if (alu_status[`D]) begin
AL = op1[3:0] - op2[3:0] - (1'b1 - alu_status[`C]);
AH = op1[7:4] - op2[7:4];
if (AL[4]) begin
bcdl = AL - {4'd0, BCD_FIX};
bcdh = AH - 8'd1;
end
else begin
bcdl = AL;
bcdh = AH;
end
if (bcdh[4]) begin
bcdh2 = bcdh - {4'd0, BCD_FIX};
end
else begin
bcdh2 = bcdh;
end
result[7:0] = {bcdh2[3:0],bcdl[3:0]};
end
end
// ASL - Arithmetic Shift Left
`ASL_ACC : begin
{STATUS[`C],result[7:0]} = {A, 1'b0};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
`ASL_ZPG, `ASL_ZPX, `ASL_ABS, `ASL_ABX : begin
{STATUS[`C],result[7:0]} = {alu_a, 1'b0};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// LSR - Logical Shift Right
`LSR_ACC: begin
{result[7:0],STATUS[`C]} = {1'b0,A};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
`LSR_ZPG, `LSR_ZPX, `LSR_ABS, `LSR_ABX : begin
{result[7:0],STATUS[`C]} = {1'b0,alu_a};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// ROL - Rotate Left
`ROL_ACC : begin
{STATUS[`C],result[7:0]} = {A,alu_status[`C]};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
`ROL_ZPG, `ROL_ZPX, `ROL_ABS, `ROL_ABX : begin
{STATUS[`C],result[7:0]} = {alu_a,alu_status[`C]};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// ROR - Rotate Right
`ROR_ACC : begin
{result[7:0],STATUS[`C]} = {alu_status[`C],A};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
`ROR_ZPG, `ROR_ZPX, `ROR_ABS, `ROR_ABX : begin
{result[7:0], STATUS[`C]} = {alu_status[`C], alu_a};
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// CPX - Compare X Register
`CPX_IMM, `CPX_ZPG, `CPX_ABS : begin
result[7:0] = alu_x - alu_a;
STATUS[`C] = (alu_x >= alu_a) ? 1'b1 : 1'b0;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
// CPY - Compare Y Register
`CPY_IMM, `CPY_ZPG, `CPY_ABS : begin
result[7:0] = alu_y - alu_a;
STATUS[`C] = (alu_y >= alu_a) ? 1'b1 : 1'b0;
STATUS[`Z] = (result[7:0] == 0) ? 1'b1 : 1'b0;
STATUS[`N] = result[7];
end
default: begin
result = 10'h3FF;
STATUS = 8'hFF;
end
endcase
end
end
endmodule
/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_fsm.v
0,0 → 1,1387
 
`include "T6502_defines.v"
 
module `VARIANT`FSM
 
#(parameter BOOT= 16'hf000)
(
 
input wire clk,
input wire reset,
input wire enable,
input wire [7:0] alu_result, // result from alu operation
input wire [7:0] alu_status, // alu status register
input wire [7:0] data_in, // data that comes from the bus controller
input wire [7:0] alu_x, // alu x index register
input wire [7:0] alu_y, // alu y index register
 
output reg [15:0] address, // system bus address
output reg [15:0] pc, // program counter
output reg rw_mem, // read = 0, write = 1
output reg [7:0] data_out, // data that will be written somewhere else
output reg [7:0] alu_opcode, // current opcode
output reg [7:0] alu_a, // extra operand sent to the alu
output reg alu_enable // a flag that when high tells the alu when to perform the operations
 
 
 
 
);
 
 
 
 
 
// FSM states. If aiming for less power consumption try gray coding.
//localparam FETCH_OP_CALC = 5'b00001; this was never used
localparam FETCH_OP = 5'b00000;
localparam FETCH_LOW = 5'b00010;
localparam FETCH_HIGH = 5'b00011;
localparam READ_MEM = 5'b00100;
localparam DUMMY_WRT_CALC = 5'b00101;
localparam WRITE_MEM = 5'b00110;
localparam FETCH_OP_CALC_PARAM = 5'b00111;
localparam READ_MEM_CALC_INDEX = 5'b01000;
localparam FETCH_HIGH_CALC_INDEX = 5'b01001;
localparam READ_MEM_FIX_ADDR = 5'b01010;
localparam FETCH_OP_EVAL_BRANCH = 5'b01011;
localparam FETCH_OP_FIX_PC = 5'b01100;
localparam READ_FROM_POINTER = 5'b01101;
localparam READ_FROM_POINTER_X = 5'b01110;
localparam READ_FROM_POINTER_X1 = 5'b01111;
localparam PUSH_PCH = 5'b10000;
localparam PUSH_PCL = 5'b10001;
localparam PUSH_STATUS = 5'b10010;
localparam FETCH_PCL = 5'b10011;
localparam FETCH_PCH = 5'b10100;
localparam INCREMENT_SP = 5'b10101;
localparam PULL_STATUS = 5'b10110;
localparam PULL_PCL = 5'b10111;
localparam PULL_PCH = 5'b11000;
localparam INCREMENT_PC = 5'b11001;
localparam PUSH_REGISTER = 5'b11010;
localparam PULL_REGISTER = 5'b11011;
localparam DUMMY = 5'b11100;
localparam RESET = 5'b11111;
 
 
 
// rw_mem signals
localparam MEM_READ = 1'b0;
localparam MEM_WRITE = 1'b1;
 
 
reg [7:0] sp; // stack pointer. 9 bits wide.
reg [7:0] ir; // instruction register
reg [15:0] temp_addr; // temporary address
reg [7:0] temp_data; // temporary data
 
reg [4:0] state, next_state; // current and next state registers
 
// wiring that simplifies the FSM logic by simplifying the addressing modes
reg absolute;
reg absolute_indexed;
reg accumulator;
reg immediate;
reg implied;
reg indirectx;
reg indirecty;
reg relative;
reg zero_page;
reg zero_page_indexed;
reg [7:0] index; // will be assigned with either X or Y
 
// regs that store the type of operation. again, this simplifies the FSM a lot.
reg read;
reg read_modify_write;
reg write;
reg jump;
reg jump_indirect;
reg index_is_x;
reg index_is_branch;
 
// regs for the special instructions
reg brk;
reg rti;
reg rts;
reg pha;
reg php;
reg pla;
reg plp;
reg jsr;
reg tsx;
reg txs;
reg nop;
 
reg invalid;
 
wire [15:0] next_pc; // a simple logic to add one to the PC
assign next_pc = pc + 16'b0000000000000001;
 
wire [8:0] sp_plus_one; // simple adder and subtracter for the stack pointer
assign sp_plus_one = {1'b1, sp[7:0] + 8'b00000001};
 
wire [8:0] sp_minus_one;
assign sp_minus_one = {1'b1, sp[7:0] - 8'b00000001};
 
reg [15:0] address_plus_index; // this two registers are used when the instruction uses indexing.
reg page_crossed; // address_plus_index always adds index to address and page_crossed asserts when the sum creates a carry.
reg branch; // a simple reg that is asserted everytime a branch will be executed.
 
// this is the combinational logic related to indexed instructions
always @(*) begin
address_plus_index = 16'h0000;
page_crossed = 1'b0;
 
case (state)
READ_MEM_FIX_ADDR, FETCH_HIGH_CALC_INDEX: begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[15:8] = temp_addr[15:8] + page_crossed;
end
READ_FROM_POINTER_X1: begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[15:8] = data_in[7:0];
end
FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin
if (branch) begin address_plus_index = pc[15:0] + {{8{index[7]}},index}; // ???????????
// warning: pc might feed these lines twice and cause branch failure
end // solution: add a temp reg i guess
end
READ_FROM_POINTER: begin
if (indirectx) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index;
//address_plus_index[12:8] = 5'b00000; // already assigned earlier at this block
end
else if (jump_indirect) begin
address_plus_index[7:0] = temp_addr[7:0] + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
else begin // indirecty falls here
address_plus_index[7:0] = temp_data + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
end
READ_FROM_POINTER_X: begin
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
 
READ_MEM_CALC_INDEX: begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
//address_plus_index[12:8] = 5'b00000;
end
endcase
end
 
reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
 
always @ (posedge clk ) begin // sequencial always block
if (reset) begin
// all registers must assume default values
pc <= BOOT; // TODO: this is written somewhere. something about a reset vector. must be checked.
sp <= 9'b111111111; // the default is 'h1FF
ir <= 8'h00;
temp_addr <= 16'h0000;
temp_data <= 8'h00;
state <= RESET;
// registered outputs also receive default values
address <= BOOT;
rw_mem <= MEM_READ;
data_out <= 8'h00;
rst_counter <= 3'h0;
index <= 8'h00;
end // if (reset)
else if(!enable)
begin
pc <= pc;
sp <= sp;
ir <= ir;
temp_addr <= temp_addr;
temp_data <= temp_data;
state <= state ;
address <= address;
rw_mem <= rw_mem;
data_out <= data_out;
rst_counter <= rst_counter;
index <= index;
end
 
 
else begin
state <= next_state;
 
case (state)
RESET: begin // The processor was reset
rst_counter <= rst_counter + 3'b001;
//sp <= 9'b111111111; // this prevents flipflops with different drivers
//$write("under reset");
end
/*
FETCH_OP: executed when the processor was reset or the last instruction could not fetch.
FETCH_OP_CALC_PARAM: enables the alu with an argument (alu_a) and fetchs the next instruction opcode. (pipelining)
*/
FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
pc <= next_pc;
address <= next_pc;
rw_mem <= MEM_READ;
ir <= data_in;
end
/*
in this state the opcode is already known so truly execution begins.
all instructions execute this cycle.
*/
FETCH_LOW: begin
//$display("index_is_x = %b",index_is_x);
if (index_is_x == 1'b1) begin
index <= alu_x;
//$display("alu_x = %d",alu_x);
end
else begin
index <= alu_y;
//$display("alu_y = %d",alu_y);
end
if (index_is_branch) begin
index <= data_in; // ??????????????
end
if (accumulator || implied || txs || tsx) begin
pc <= pc; // is this better?
address <= pc;
rw_mem <= MEM_READ;
if (txs) begin
sp[7:0] <= alu_x;
end
//alu_a
end
else if (immediate || relative) begin
pc <= next_pc;
address <= next_pc;
rw_mem <= MEM_READ;
temp_data <= data_in; // the follow-up byte is saved in temp_data
end
else if (absolute || absolute_indexed || jump_indirect) begin
pc <= next_pc;
address <= next_pc;
rw_mem <= MEM_READ;
temp_addr <= {{5{1'b0}},data_in};
temp_data <= 8'h00;
end
else if (zero_page) begin
pc <= next_pc;
address <= {{8{1'b0}},data_in};
temp_addr <= {{8{1'b0}},data_in};
 
if (write) begin
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
else if (zero_page_indexed) begin
pc <= next_pc;
address <= {{8{1'b0}}, data_in};
temp_addr <= {{8{1'b0}}, data_in};
rw_mem <= MEM_READ;
end
else if (indirectx || indirecty) begin
pc <= next_pc;
address <= data_in;
temp_data <= data_in;
rw_mem <= MEM_READ;
end
else begin // the special instructions will fall here: BRK, RTI, RTS...
if (brk) begin
pc <= next_pc;
address <= sp;
data_out <= pc[15:8];
rw_mem <= MEM_WRITE;
end
else if (rti || rts) begin
address <= sp;
rw_mem <= MEM_READ;
end
else if (pha || php) begin
pc <= pc;
address <= sp;
data_out <= (pha) ? alu_result : alu_status;
rw_mem <= MEM_WRITE;
end
else if (pla || plp) begin
pc <= pc;
address <= sp;
rw_mem <= MEM_READ;
end
else if (invalid) begin
address <= pc;
rw_mem <= MEM_READ;
end
else begin // jsr
address <= sp;
rw_mem <= MEM_READ;
temp_addr <= {{8{1'b0}}, data_in};
pc <= next_pc;
end
end
end
FETCH_HIGH_CALC_INDEX: begin
pc <= next_pc;
temp_addr[15:8] <= data_in[7:0];
address <= {data_in[7:0], address_plus_index[7:0]};
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
// this cycle fetchs the next operand while still evaluating if a branch occurred.
FETCH_OP_EVAL_BRANCH: begin
if (branch) begin
pc <= address_plus_index[15:0]; // ???????????
address <= address_plus_index[15:0]; // ???????????????
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
else begin
pc <= next_pc;
address <= next_pc;
rw_mem <= MEM_READ;
data_out <= 8'h00;
ir <= data_in;
end
end
// sometimes when reading memory page crosses may occur. the pc register must be fixed, i.e., add 16'h0100
FETCH_OP_FIX_PC: begin
if (page_crossed) begin
pc[15:8] <= address_plus_index[15:8];
address[15:8] <= address_plus_index[15:8];
end
else begin
pc <= next_pc;
address <= next_pc;
rw_mem <= MEM_READ;
ir <= data_in;
end
end
// several instructions ocupy 3 bytes in memory. this cycle reads the third byte.
FETCH_HIGH: begin
if (jump) begin
pc <= {data_in[7:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
address <= {data_in[7:0], temp_addr[7:0]};
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
else begin
if (write) begin
pc <= next_pc;
temp_addr[15:8] <= data_in[7:0];
address <= {data_in[7:0],temp_addr[7:0]};
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin // read_modify_write or just read
pc <= next_pc;
temp_addr[15:8] <= data_in[7:0];
address <= {data_in[7:0],temp_addr[7:0]};
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
end
// read memory at address
READ_MEM: begin
if (read_modify_write) begin
pc <= pc;
address <= temp_addr;
rw_mem <= MEM_WRITE;
temp_data <= data_in;
data_out <= data_in; // writeback the same value
end
else begin
pc <= pc;
address <= pc;
temp_data <= data_in;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
READ_MEM_CALC_INDEX: begin
address <= address_plus_index;
temp_addr <= address_plus_index;
 
if (write) begin
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
 
end
READ_MEM_FIX_ADDR: begin
if (read) begin
rw_mem <= MEM_READ;
data_out <= 8'h00;
 
if (page_crossed) begin // fix address
address <= address_plus_index;
temp_addr <= address_plus_index;
end
else begin
address <= pc;
temp_data <= data_in;
end
end
else if (write) begin
rw_mem <= MEM_WRITE;
data_out <= alu_result;
address <= address_plus_index;
temp_addr <= address_plus_index;
 
end
else begin // read modify write
rw_mem <= MEM_READ;
data_out <= 8'h00;
address <= address_plus_index;
temp_addr <= address_plus_index;
end
end
// some instructions have a dummy write cycle. this is it.
DUMMY_WRT_CALC: begin
pc <= pc;
address <= temp_addr;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
WRITE_MEM: begin
pc <= pc;
address <= pc;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
READ_FROM_POINTER: begin
if (jump_indirect) begin
pc[7:0] <= data_in;
rw_mem <= MEM_READ;
address <= address_plus_index;
end
else begin
pc <= pc;
rw_mem <= MEM_READ;
if (indirectx) begin
address <= address_plus_index;
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr <= {{8{1'b0}}, data_in};
end
end
end
READ_FROM_POINTER_X: begin
pc <= pc;
address <= address_plus_index;
temp_addr[7:0] <= data_in;
rw_mem <= MEM_READ;
end
READ_FROM_POINTER_X1: begin
if (jump_indirect) begin
pc[15:8] <= data_in[7:0];
rw_mem <= MEM_READ;
address <= {data_in[7:0], pc[7:0]};
end
else if (indirectx) begin
address <= {data_in[7:0], temp_addr[7:0]};
if (write) begin
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
rw_mem <= MEM_READ;
end
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr[15:8] <= data_in;
rw_mem <= MEM_READ;
end
end
PUSH_PCH: begin // this is probably wrong
pc <= pc;
address <= sp_minus_one;
data_out <= pc[7:0];
rw_mem <= MEM_WRITE;
sp <= sp_minus_one;
end
PUSH_PCL: begin
if (jsr) begin
pc <= pc;
address <= pc;
rw_mem <= MEM_READ;
sp <= sp_minus_one;
end
else begin
pc <= pc;
address <= sp_minus_one;
data_out <= alu_status;
rw_mem <= MEM_WRITE;
sp <= sp_minus_one;
end
end
PUSH_STATUS: begin
address <= 13'h1FFE;
rw_mem <= MEM_READ;
sp <= sp_minus_one;
end
FETCH_PCL: begin
pc[7:0] <= data_in;
address <= 13'h1FFF;
rw_mem <= MEM_READ;
end
FETCH_PCH: begin
pc[15:8] <= data_in[7:0];
address <= {data_in[7:0], pc[7:0]};
rw_mem <= MEM_READ;
end
INCREMENT_SP: begin
sp <= sp_plus_one;
address <= sp_plus_one;
end
PULL_STATUS: begin
sp <= sp_plus_one;
address <= sp_plus_one;
temp_data <= data_in;
end
PULL_PCL: begin
sp <= sp_plus_one;
address <= sp_plus_one;
pc[7:0] <= data_in;
end
PULL_PCH: begin
pc[15:8] <= data_in[7:0];
address <= {data_in[7:0], pc[7:0]};
end
INCREMENT_PC: begin
pc <= next_pc;
address <= next_pc;
end
PUSH_REGISTER: begin
pc <= pc;
address <= pc;
sp <= sp_minus_one;
rw_mem <= MEM_READ;
temp_data <= data_in;
end
PULL_REGISTER: begin
pc <= pc;
address <= pc;
temp_data <= data_in;
end
DUMMY: begin
address <= {8'h01,sp};
rw_mem <= MEM_WRITE;
data_out <= pc[15:8];
end
default: begin
//$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
//$finish(0);
end
endcase
end
end
 
always @ (*) begin // this is the next_state logic and the combinational output logic always block
alu_opcode = 8'h00;
alu_a = 8'h00;
alu_enable = 1'b0;
next_state = RESET; // these lines prevents latches
 
if (invalid == 1'b1) begin
next_state = FETCH_OP;
end
else case (state)
RESET: begin
if (rst_counter == 3'd6) begin
next_state = FETCH_OP;
end
end
FETCH_OP: begin
next_state = FETCH_LOW;
end
FETCH_OP_CALC_PARAM: begin
next_state = FETCH_LOW;
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = temp_data;
end
FETCH_LOW: begin
if (accumulator || implied || txs) begin
if (!nop) begin
alu_opcode = ir;
alu_enable = 1'b1;
end
next_state = FETCH_OP;
end
else if (tsx) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = FETCH_OP;
alu_a = sp[7:0];
end
else if (immediate) begin
next_state = FETCH_OP_CALC_PARAM;
end
else if (zero_page) begin
if (read || read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
next_state = WRITE_MEM;
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = 8'h00;
end
else begin
//$write("unknown behavior");
//$finish(0);
end
end
else if (zero_page_indexed) begin
next_state = READ_MEM_CALC_INDEX;
end
else if (absolute || jump_indirect) begin
next_state = FETCH_HIGH;
if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = 8'h00;
end
end
else if (absolute_indexed) begin
next_state = FETCH_HIGH_CALC_INDEX;
end
else if (relative) begin
next_state = FETCH_OP_EVAL_BRANCH;
end
else if (indirectx || indirecty) begin
next_state = READ_FROM_POINTER;
end
else begin // all the special instructions will fall here
if (brk) begin
next_state = PUSH_PCH;
end
else if (rti || rts) begin
next_state = INCREMENT_SP;
end
else if (pha) begin
alu_opcode = ir;
alu_enable = 1'b1;
//alu_a = 8'h00;
next_state = PUSH_REGISTER;
end
else if (php) begin
next_state = PUSH_REGISTER;
end
else if (pla || plp) begin
next_state = INCREMENT_SP;
end
else begin // jsr
next_state = DUMMY;
end
end
end
READ_FROM_POINTER: begin
if (indirectx) begin
next_state = READ_FROM_POINTER_X;
end
else begin // indirecty and jump indirect falls here
next_state = READ_FROM_POINTER_X1;
end
end
READ_FROM_POINTER_X: begin
next_state = READ_FROM_POINTER_X1;
end
READ_FROM_POINTER_X1: begin
if (jump_indirect) begin
next_state = FETCH_OP;
end
else if (indirecty) begin
next_state = READ_MEM_FIX_ADDR;
end
else begin
if (read) begin // no instruction using pointers is from type read_modify_write
next_state = READ_MEM;
end
else if (write) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = WRITE_MEM;
end
end
end
FETCH_OP_EVAL_BRANCH: begin
if (branch) begin
next_state = FETCH_OP; //???????????
end
else begin
next_state = FETCH_LOW;
end
end
FETCH_OP_FIX_PC: begin
if (page_crossed) begin
next_state = FETCH_OP;
end
else begin
next_state = FETCH_LOW;
end
end
FETCH_HIGH_CALC_INDEX: begin
next_state = READ_MEM_FIX_ADDR;
end
READ_MEM_FIX_ADDR: begin
if (read) begin
if (page_crossed) begin
next_state = READ_MEM;
end
else begin
next_state = FETCH_OP_CALC_PARAM;
end
end
else if (read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
next_state = WRITE_MEM;
alu_enable = 1'b1;
alu_opcode = ir;
end
else begin
//$write("unknown behavior");
//$finish(0);
end
end
FETCH_HIGH: begin
if (jump_indirect) begin
next_state = READ_FROM_POINTER;
end
else if (jump) begin
next_state = FETCH_OP;
end
else if (read || read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
next_state = WRITE_MEM;
end
else begin
//$write("unknown behavior");
//$finish(0);
end
end
READ_MEM_CALC_INDEX: begin
if (read || read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = WRITE_MEM;
end
else begin
//$write("unknown behavior");
//$finish(0);
end
end
READ_MEM: begin
if (read) begin
next_state = FETCH_OP_CALC_PARAM;
end
else if (read_modify_write) begin
next_state = DUMMY_WRT_CALC;
end
end
DUMMY_WRT_CALC: begin
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = data_in;
next_state = WRITE_MEM;
end
WRITE_MEM: begin
next_state = FETCH_OP;
end
PUSH_PCH: begin
next_state = PUSH_PCL;
end
PUSH_PCL: begin
if (jsr) begin
next_state = FETCH_HIGH;
end
else begin
next_state = PUSH_STATUS;
end
end
PUSH_STATUS: begin
next_state = FETCH_PCL;
end
FETCH_PCL: begin
next_state = FETCH_PCH;
end
FETCH_PCH: begin
next_state = FETCH_OP;
end
INCREMENT_SP: begin
if (rti) begin
next_state = PULL_STATUS;
end
else if (pla || plp) begin
next_state = PULL_REGISTER;
end
else begin // rts
next_state = PULL_PCL;
end
end
PULL_STATUS: begin
next_state = PULL_PCL;
end
PULL_PCL: begin
next_state = PULL_PCH;
 
if (rti) begin
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = temp_data;
end
end
PULL_PCH: begin
if (rti) begin
next_state = FETCH_OP;
end
else begin // rts
next_state = INCREMENT_PC;
end
end
INCREMENT_PC: begin
next_state = FETCH_OP;
end
PUSH_REGISTER: begin
next_state = FETCH_OP;
end
PULL_REGISTER: begin
next_state = FETCH_OP_CALC_PARAM;
end
DUMMY: begin
next_state = PUSH_PCH;
end
default: begin
next_state = RESET;
end
endcase
end
 
// this always block is responsible for updating the address mode and the type of operation being done
always @ (*) begin //
absolute = 1'b0;
absolute_indexed = 1'b0;
accumulator = 1'b0;
immediate = 1'b0;
implied = 1'b0;
indirectx = 1'b0;
indirecty = 1'b0;
relative = 1'b0;
zero_page = 1'b0;
zero_page_indexed = 1'b0;
index_is_x = 1'b0;
index_is_branch = 1'b0;
//index = 8'h00;
 
read = 1'b0;
read_modify_write = 1'b0;
write = 1'b0;
jump = 1'b0;
jump_indirect = 1'b0;
branch = 1'b0;
 
brk = 1'b0;
rti = 1'b0;
rts = 1'b0;
pha = 1'b0;
php = 1'b0;
pla = 1'b0;
plp = 1'b0;
jsr = 1'b0;
tsx = 1'b0;
txs = 1'b0;
nop = 1'b0;
 
invalid = 1'b0;
 
case (ir)
`CLC_IMP, `CLD_IMP, `CLI_IMP, `CLV_IMP, `DEX_IMP, `DEY_IMP, `INX_IMP, `INY_IMP, `SEC_IMP, `SED_IMP, `SEI_IMP, `TAX_IMP,
`TAY_IMP, `TXA_IMP, `TYA_IMP: begin
implied = 1'b1;
end
`NOP_IMP: begin
implied = 1'b1;
nop = 1'b1;
end
`ASL_ACC, `LSR_ACC, `ROL_ACC, `ROR_ACC: begin
accumulator = 1'b1;
end
`ADC_IMM, `AND_IMM, `CMP_IMM, `CPX_IMM, `CPY_IMM, `EOR_IMM, `LDA_IMM, `LDX_IMM, `LDY_IMM, `ORA_IMM, `SBC_IMM: begin
immediate = 1'b1;
end
`ADC_ZPG, `AND_ZPG, `ASL_ZPG, `BIT_ZPG, `CMP_ZPG, `CPX_ZPG, `CPY_ZPG, `DEC_ZPG, `EOR_ZPG, `INC_ZPG, `LDA_ZPG, `LDX_ZPG, `LDY_ZPG,
`LSR_ZPG, `ORA_ZPG, `ROL_ZPG, `ROR_ZPG, `SBC_ZPG, `STA_ZPG, `STX_ZPG, `STY_ZPG: begin
zero_page = 1'b1;
end
`ADC_ZPX, `AND_ZPX, `ASL_ZPX, `CMP_ZPX, `DEC_ZPX, `EOR_ZPX, `INC_ZPX, `LDA_ZPX, `LDY_ZPX, `LSR_ZPX, `ORA_ZPX, `ROL_ZPX, `ROR_ZPX,
`SBC_ZPX, `STA_ZPX, `STY_ZPX: begin
zero_page_indexed = 1'b1;
index_is_x = 1'b1;
//index = alu_x;
end
`LDX_ZPY, `STX_ZPY: begin
zero_page_indexed = 1'b1;
index_is_x = 1'b0;
//index = alu_y;
end
`BCC_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[`C]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BCS_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
 
if (alu_status[`C]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BEQ_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[`Z]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BNE_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[`Z] == 1'b0) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BPL_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[`N]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BMI_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[`N]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BVC_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[`V]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`BVS_REL: begin
relative = 1'b1;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[`V]) begin
branch = 1'b1;
end
else begin
branch = 1'b0;
end
end
`ADC_ABS, `AND_ABS, `ASL_ABS, `BIT_ABS, `CMP_ABS, `CPX_ABS, `CPY_ABS, `DEC_ABS, `EOR_ABS, `INC_ABS, `LDA_ABS,
`LDX_ABS, `LDY_ABS, `LSR_ABS, `ORA_ABS, `ROL_ABS, `ROR_ABS, `SBC_ABS, `STA_ABS, `STX_ABS, `STY_ABS: begin
absolute = 1'b1;
end
`ADC_ABX, `AND_ABX, `ASL_ABX, `CMP_ABX, `DEC_ABX, `EOR_ABX, `INC_ABX, `LDA_ABX, `LDY_ABX, `LSR_ABX, `ORA_ABX, `ROL_ABX, `ROR_ABX,
`SBC_ABX, `STA_ABX: begin
absolute_indexed = 1'b1;
index_is_x = 1'b1;
end
`ADC_ABY, `AND_ABY, `CMP_ABY, `EOR_ABY, `LDA_ABY, `LDX_ABY, `ORA_ABY, `SBC_ABY, `STA_ABY: begin
absolute_indexed = 1'b1;
index_is_x = 1'b0;
end
`ADC_IDX, `AND_IDX, `CMP_IDX, `EOR_IDX, `LDA_IDX, `ORA_IDX, `SBC_IDX, `STA_IDX: begin
indirectx = 1'b1;
index_is_x = 1'b1;
end
`ADC_IDY, `AND_IDY, `CMP_IDY, `EOR_IDY, `LDA_IDY, `ORA_IDY, `SBC_IDY, `STA_IDY: begin
indirecty = 1'b1;
index_is_x = 1'b0;
end
`JMP_ABS: begin
absolute = 1'b1;
jump = 1'b1;
end
`JMP_IND: begin
jump_indirect = 1'b1;
end
`BRK_IMP: begin
brk = 1'b1;
end
`RTI_IMP: begin
rti = 1'b1;
end
`RTS_IMP: begin
rts = 1'b1;
end
`PHA_IMP: begin
pha = 1'b1;
end
`PHP_IMP: begin
php = 1'b1;
end
`PLA_IMP: begin
pla = 1'b1;
end
`PLP_IMP: begin
plp = 1'b1;
end
`JSR_ABS: begin
jsr = 1'b1;
jump = 1'b1;
end
`TSX_IMP: begin
tsx = 1'b1;
end
`TXS_IMP: begin
txs = 1'b1;
end
default: begin
index_is_x = 1'b1;
//$write("state : %b", state);
if (reset == 1'b0 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
invalid = 1'b1;
 
end
end
endcase
case (ir)
`ASL_ACC, `ASL_ZPG, `ASL_ZPX, `ASL_ABS, `ASL_ABX, `LSR_ACC, `LSR_ZPG, `LSR_ZPX, `LSR_ABS, `LSR_ABX, `ROL_ACC, `ROL_ZPG, `ROL_ZPX, `ROL_ABS,
`ROL_ABX, `ROR_ACC, `ROR_ZPG, `ROR_ZPX, `ROR_ABS, `ROR_ABX, `INC_ZPG, `INC_ZPX, `INC_ABS, `INC_ABX, `DEC_ZPG, `DEC_ZPX, `DEC_ABS,
`DEC_ABX: begin
read_modify_write = 1'b1;
end
`STA_ZPG, `STA_ZPX, `STA_ABS, `STA_ABX, `STA_ABY, `STA_IDX, `STA_IDY, `STX_ZPG, `STX_ZPY, `STX_ABS, `STY_ZPG, `STY_ZPX, `STY_ABS: begin
write = 1'b1;
end
default: begin // this should work fine since the previous case statement will detect the unknown/undocumented/unsupported opcodes
read = 1'b1;
end
endcase
end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
`ifndef SYNTHESIS
 
 
 
reg [21*8-1:0] state_string;
 
always @(*) begin
case (state)
FETCH_OP: state_string = "FETCH_OP ";
FETCH_LOW: state_string = "FETCH_LOW ";
FETCH_HIGH: state_string = "FETCH_HIGH ";
READ_MEM: state_string = "READ_MEM ";
DUMMY_WRT_CALC: state_string = "DUMMY_WRT_CALC ";
WRITE_MEM: state_string = "WRITE_MEM ";
FETCH_OP_CALC_PARAM: state_string = "FETCH_OP_CALC_PARAM ";
READ_MEM_CALC_INDEX: state_string = "READ_MEM_CALC_INDEX ";
FETCH_HIGH_CALC_INDEX: state_string = "FETCH_HIGH_CALC_INDEX";
READ_MEM_FIX_ADDR: state_string = "READ_MEM_FIX_ADDR ";
FETCH_OP_EVAL_BRANCH: state_string = "FETCH_OP_EVAL_BRANCH ";
FETCH_OP_FIX_PC: state_string = "FETCH_OP_FIX_PC ";
READ_FROM_POINTER: state_string = "READ_FROM_POINTER ";
READ_FROM_POINTER_X: state_string = "READ_FROM_POINTER_X ";
READ_FROM_POINTER_X1: state_string = "READ_FROM_POINTER_X1 ";
PUSH_PCH: state_string = "PUSH_PCH ";
PUSH_PCL: state_string = "PUSH_PCL ";
PUSH_STATUS: state_string = "PUSH_STATUS ";
FETCH_PCL: state_string = "FETCH_PCL ";
FETCH_PCH: state_string = "FETCH_PCH ";
INCREMENT_SP: state_string = "INCREMENT_SP ";
PULL_STATUS: state_string = "PULL_STATUS ";
PULL_PCL: state_string = "PULL_PCL ";
PULL_PCH: state_string = "PULL_PCH ";
INCREMENT_PC: state_string = "INCREMENT_PC ";
PUSH_REGISTER: state_string = "PUSH_REGISTER ";
PULL_REGISTER: state_string = "PULL_REGISTER ";
DUMMY: state_string = "DUMMY ";
RESET: state_string = "RESET ";
default: state_string = "-XXXXXX- ";
endcase
 
end
 
 
 
 
reg [7*8-1:0] instr_string;
 
always @(*) begin
case (ir)
`ADC_IMM: instr_string = "ADC_IMM";
`ADC_ZPG: instr_string = "ADC_ZPG";
`ADC_ZPX: instr_string = "ADC_ZPX";
`ADC_ABS: instr_string = "ADC_ABS";
`ADC_ABX: instr_string = "ADC_ABX";
`ADC_ABY: instr_string = "ADC_ABY";
`ADC_IDX: instr_string = "ADC_IDX";
`ADC_IDY: instr_string = "ADC_IDY";
`AND_IMM: instr_string = "AND_IMM";
`AND_ZPG: instr_string = "AND_ZPG";
`AND_ZPX: instr_string = "AND_ZPX";
`AND_ABS: instr_string = "AND_ABS";
`AND_ABX: instr_string = "AND_ABX";
`AND_ABY: instr_string = "AND_ABY";
`AND_IDX: instr_string = "AND_IDX";
`AND_IDY: instr_string = "AND_IDY";
`ASL_ACC: instr_string = "ASL_ACC";
`ASL_ZPG: instr_string = "ASL_ZPG";
`ASL_ZPX: instr_string = "ASL_ZPX";
`ASL_ABS: instr_string = "ASL_ABS";
`ASL_ABX: instr_string = "ASL_ABX";
`BCC_REL: instr_string = "BCC_REL";
`BCS_REL: instr_string = "BCS_REL";
`BEQ_REL: instr_string = "BEQ_REL";
`BIT_ZPG: instr_string = "BIT_ZPG";
`BIT_ABS: instr_string = "BIT_ABS";
`BMI_REL: instr_string = "BMI_REL";
`BNE_REL: instr_string = "BNE_REL";
`BPL_REL: instr_string = "BPL_REL";
`BRK_IMP: instr_string = "BRK_IMP";
`BVC_REL: instr_string = "BVC_REL";
`BVS_REL: instr_string = "BVS_REL";
`CLC_IMP: instr_string = "CLC_IMP";
`CLD_IMP: instr_string = "CLD_IMP";
`CLI_IMP: instr_string = "CLI_IMP";
`CLV_IMP: instr_string = "CLV_IMP";
`CMP_IMM: instr_string = "CMP_IMM";
`CMP_ZPG: instr_string = "CMP_ZPG";
`CMP_ZPX: instr_string = "CMP_ZPX";
`CMP_ABS: instr_string = "CMP_ABS";
`CMP_ABX: instr_string = "CMP_ABX";
`CMP_ABY: instr_string = "CMP_ABY";
`CMP_IDX: instr_string = "CMP_IDX";
`CMP_IDY: instr_string = "CMP_IDY";
`CPX_IMM: instr_string = "CPX_IMM";
`CPX_ZPG: instr_string = "CPX_ZPG";
`CPX_ABS: instr_string = "CPX_ABS";
`CPY_IMM: instr_string = "CPY_IMM";
`CPY_ZPG: instr_string = "CPY_ZPG";
`CPY_ABS: instr_string = "CPY_ABS";
`DEC_ZPG: instr_string = "DEC_ZPG";
`DEC_ZPX: instr_string = "DEC_ZPX";
`DEC_ABS: instr_string = "DEC_ABS";
`DEC_ABX: instr_string = "DEC_ABX";
`DEX_IMP: instr_string = "DEX_IMP";
`DEY_IMP: instr_string = "DEY_IMP";
`EOR_IMM: instr_string = "EOR_IMM";
`EOR_ZPG: instr_string = "EOR_ZPG";
`EOR_ZPX: instr_string = "EOR_ZPX";
`EOR_ABS: instr_string = "EOR_ABS";
`EOR_ABX: instr_string = "EOR_ABX";
`EOR_ABY: instr_string = "EOR_ABY";
`EOR_IDX: instr_string = "EOR_IDX";
`EOR_IDY: instr_string = "EOR_IDY";
`INC_ZPG: instr_string = "INC_ZPG";
`INC_ZPX: instr_string = "INC_ZPX";
`INC_ABS: instr_string = "INC_ABS";
`INC_ABX: instr_string = "INC_ABX";
`INX_IMP: instr_string = "INX_IMP";
`INY_IMP: instr_string = "INY_IMP";
`JMP_ABS: instr_string = "JMP_ABS";
`JMP_IND: instr_string = "JMP_IND";
`JSR_ABS: instr_string = "JSR_ABS";
`LDA_IMM: instr_string = "LDA_IMM";
`LDA_ZPG: instr_string = "LDA_ZPG";
`LDA_ZPX: instr_string = "LDA_ZPX";
`LDA_ABS: instr_string = "LDA_ABS";
`LDA_ABX: instr_string = "LDA_ABX";
`LDA_ABY: instr_string = "LDA_ABY";
`LDA_IDX: instr_string = "LDA_IDX";
`LDA_IDY: instr_string = "LDA_IDY";
`LDX_IMM: instr_string = "LDX_IMM";
`LDX_ZPG: instr_string = "LDX_ZPG";
`LDX_ZPY: instr_string = "LDX_ZPY";
`LDX_ABS: instr_string = "LDX_ABS";
`LDX_ABY: instr_string = "LDX_ABY";
`LDY_IMM: instr_string = "LDY_IMM";
`LDY_ZPG: instr_string = "LDY_ZPG";
`LDY_ZPX: instr_string = "LDY_ZPX";
`LDY_ABS: instr_string = "LDY_ABS";
`LDY_ABX: instr_string = "LDY_ABX";
`LSR_ACC: instr_string = "LSR_ACC";
`LSR_ZPG: instr_string = "LSR_ZPG";
`LSR_ZPX: instr_string = "LSR_ZPX";
`LSR_ABS: instr_string = "LSR_ABS";
`LSR_ABX: instr_string = "LSR_ABX";
`NOP_IMP: instr_string = "NOP_IMP";
`ORA_IMM: instr_string = "ORA_IMM";
`ORA_ZPG: instr_string = "ORA_ZPG";
`ORA_ZPX: instr_string = "ORA_ZPX";
`ORA_ABS: instr_string = "ORA_ABS";
`ORA_ABX: instr_string = "ORA_ABX";
`ORA_ABY: instr_string = "ORA_ABY";
`ORA_IDX: instr_string = "ORA_IDX";
`ORA_IDY: instr_string = "ORA_IDY";
`PHA_IMP: instr_string = "PHA_IMP";
`PHP_IMP: instr_string = "PHP_IMP";
`PLA_IMP: instr_string = "PLA_IMP";
`PLP_IMP: instr_string = "PLP_IMP";
`ROL_ACC: instr_string = "ROL_ACC";
`ROL_ZPG: instr_string = "ROL_ZPG";
`ROL_ZPX: instr_string = "ROL_ZPX";
`ROL_ABS: instr_string = "ROL_ABS";
`ROL_ABX: instr_string = "ROL_ABX";
`ROR_ACC: instr_string = "ROR_ACC";
`ROR_ZPG: instr_string = "ROR_ZPG";
`ROR_ZPX: instr_string = "ROR_ZPX";
`ROR_ABS: instr_string = "ROR_ABS";
`ROR_ABX: instr_string = "ROR_ABX";
`RTI_IMP: instr_string = "RTI_IMP";
`RTS_IMP: instr_string = "RTS_IMP";
`SBC_IMM: instr_string = "SBC_IMM";
`SBC_ZPG: instr_string = "SBC_ZPG";
`SBC_ZPX: instr_string = "SBC_ZPX";
`SBC_ABS: instr_string = "SBC_ABS";
`SBC_ABX: instr_string = "SBC_ABX";
`SBC_ABY: instr_string = "SBC_ABY";
`SBC_IDX: instr_string = "SBC_IDX";
`SBC_IDY: instr_string = "SBC_IDY";
`SEC_IMP: instr_string = "SEC_IMP";
`SED_IMP: instr_string = "SED_IMP";
`SEI_IMP: instr_string = "SEI_IMP";
`STA_ZPG: instr_string = "STA_ZPG";
`STA_ZPX: instr_string = "STA_ZPX";
`STA_ABS: instr_string = "STA_ABS";
`STA_ABX: instr_string = "STA_ABX";
`STA_ABY: instr_string = "STA_ABY";
`STA_IDX: instr_string = "STA_IDX";
`STA_IDY: instr_string = "STA_IDY";
`STX_ZPG: instr_string = "STX_ZPG";
`STX_ZPY: instr_string = "STX_ZPY";
`STX_ABS: instr_string = "STX_ABS";
`STY_ZPG: instr_string = "STY_ZPG";
`STY_ZPX: instr_string = "STY_ZPX";
`STY_ABS: instr_string = "STY_ABS";
`TAX_IMP: instr_string = "TAX_IMP";
`TAY_IMP: instr_string = "TAY_IMP";
`TSX_IMP: instr_string = "TSX_IMP";
`TXA_IMP: instr_string = "TXA_IMP";
`TXS_IMP: instr_string = "TXS_IMP";
`TYA_IMP: instr_string = "TYA_IMP";
default: instr_string = "XXX_XXX";
endcase
 
end
 
 
 
 
 
 
 
 
`endif
 
 
 
 
 
 
 
 
endmodule
 
 
 
/trunk/projects/Mos6502/ip/T6502/rtl/verilog/T6502_core.v
0,0 → 1,65
`include "T6502_defines.v"
 
 
module `VARIANT`CORE
#(parameter BOOT = 16'hf000)
(
 
input wire clk,
input wire reset,
input wire enable,
input wire [7:0] data_in,
 
output wire rw_mem,
output wire [7:0] data_out,
output wire [15:0] address,
output wire [15:0] pc
);
 
 
 
wire [7:0] alu_result;
wire [7:0] alu_status;
wire [7:0] alu_x;
wire [7:0] alu_y;
wire [7:0] alu_opcode;
wire [7:0] alu_a;
wire alu_enable;
 
 
`VARIANT`FSM
#(.BOOT(BOOT))
t6502_fsm(
.clk (clk),
.reset (reset),
.enable (enable),
.alu_result (alu_result),
.alu_status (alu_status),
.data_in (data_in),
.alu_x (alu_x),
.alu_y (alu_y),
.address (address),
.pc (pc),
.rw_mem (rw_mem),
.data_out (data_out),
.alu_opcode (alu_opcode),
.alu_a (alu_a),
.alu_enable (alu_enable)
);
 
`VARIANT`ALU t6502_alu (
.clk (clk),
.reset (reset),
.enable (enable),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
.alu_a (alu_a),
.alu_x (alu_x),
.alu_y (alu_y)
);
 
 
endmodule
/trunk/projects/Mos6502/ip/T6502/doc/spec.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/projects/Mos6502/ip/T6502/doc/spec.odt
trunk/projects/Mos6502/ip/T6502/doc/spec.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/projects/Mos6502/ip/T6502/doc/geda/drawing/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/doc/geda/drawing/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/doc/geda/drawing/filelist (revision 28) @@ -0,0 +1,6 @@ +`include "../../../rtl/gen/syn/T6502.v" +`include "../../lib/cde_sram/cde_sram.v" + + + + Index: trunk/projects/Mos6502/ip/T6502/doc/Readme.txt =================================================================== --- trunk/projects/Mos6502/ip/T6502/doc/Readme.txt (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/doc/Readme.txt (revision 28) @@ -0,0 +1,35 @@ + + + + +This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor. It had some documentation and a test suite that was somewhat working. + +I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made: + + + +1) Converted to a full 16 bit address bus. + + also hardcoded the 8 bit data bus. Hasn't changed in thirty five years. + +2) Converted parameters to `defines + +3) Converted reset to synchronous active high + +4) Converted test suite to socgen format + + Each test is in it's own subdirectory and any needed code is assembled and loaded into sram + +5) Design had no reset/interrupt vectors. Changed reset vector to a parameter. May add interupt(s) later. + +6) Added enable logic so that it could work with synchronous sram + +7) Design doesn't appear to be fully functional. + CLC followed by BCC missed the offset by one clock cycle. + JSR doesn't push high address on stack. puts wrong data in page 00 + Branch backwards doesn't work. + + +This appears to be a work in progress with numerous issues. I fixed enough of them so that I can +synthesize into an fpga and it runs the io_poll program on a Nexys2 Board. I will commit this as +a start but it is alpha code and will have bugs. Index: trunk/projects/Mos6502/ip/T6502/doc/copyright.v =================================================================== --- trunk/projects/Mos6502/ip/T6502/doc/copyright.v (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/doc/copyright.v (revision 28) @@ -0,0 +1,80 @@ +//////////////////////////////////////////////////////////////////// +// -------------- // +// / SOC \ // +// / GEN \ // +// / COMPONENT \ // +// ==================== // +// |digital done right| // +// |__________________| // +// // +// // +// // +// Copyright (C) <2010> // +// // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +//////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +//// //// +//// T6507LP IP Core //// +//// //// +//// This file is part of the T6507LP project //// +//// http://www.opencores.org/cores/t6507lp/ //// +//// //// +//// Description //// +//// Implementation of a 6507-compatible microprocessor //// +//// //// +//// To Do: //// +//// - Everything //// +//// //// +//// Author(s): //// +//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com //// +//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com //// +//// //// +//////////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +//////////////////////////////////////////////////////////////////////////// Index: trunk/projects/Mos6502/ip/T6502/bin/Makefile =================================================================== --- trunk/projects/Mos6502/ip/T6502/bin/Makefile (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/bin/Makefile (revision 28) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/liblist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/liblist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/liblist (revision 28) @@ -0,0 +1,6 @@ +`include "../../lib/cde_sram/cde_sram.v" +`include "../../lib/cde_divider/cde_divider.v" +`include "../../lib/cde_fifo/cde_fifo.v" +`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" +`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" +`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" \ No newline at end of file Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/TB.defs =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/TB.defs (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/TB.defs (revision 28) @@ -0,0 +1,8 @@ +`include "../../../rtl/variants/T6502/T6502_defines.v" + + + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/test_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/test_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/test_define (revision 28) @@ -0,0 +1,729 @@ +initial +begin +$display(" "); +$display(" ==================================================="); +$display(" Test Start"); +$display(" ==================================================="); +$display(" "); +cg.next(20); +cg.reset_off; +cg.next(90000); +cg.exit; +end + + +initial +begin + + + // Reset + + reset_n = 0; + @(negedge clk); + reset_n = 1; + alu_enable = 1; + alu_result_expected = 8'h00; + alu_status_expected = 8'b00100010; + alu_x_expected = 8'h00; + alu_y_expected = 8'h00; + + // LDA + alu_a = 0; + alu_opcode = `LDA_IMM; + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected = 8'b00100010; + check; + + // ADC + for (i = 0; i < 256; i = i + 1) + begin + alu_a = i; + alu_opcode = `LDA_IMM; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[`Z] = (alu_a == 0) ? 1 : 0; + alu_status_expected[`N] = alu_a[7]; + check; + for (j = 0; j < 256; j = j + 1) + begin + alu_opcode = `ADC_IMM; + alu_a = j; + @(negedge clk); + sign = alu_result_expected[7]; + {alu_status_expected[`C], alu_result_expected} = alu_result_expected + alu_a + alu_status_expected[`C]; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + alu_status_expected[`V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + end +/* + // SBC + for (i = 0; i < 256; i = i + 1) + begin + alu_a = i; + alu_opcode = `LDA_IMM; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[`Z] = (alu_a == 0) ? 1 : 0; + alu_status_expected[`N] = alu_a[7]; + check; + for (j = 0; j < 256; j = j + 1) + begin + alu_opcode = `SBC_IMM; + alu_a = j; + @(negedge clk); + sign = alu_result_expected[7]; + alu_result_expected = alu_result_expected - alu_a - (1 - alu_status_expected[`C]); + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + alu_status_expected[`V] = ((alu_a[7] == sign) && (alu_a[7] == alu_result_expected[7])); + alu_status_expected[`C] = ~alu_result_expected[7]; + check; + end + end +*/ + + + // CLC + alu_opcode = `CLC_IMP; + @(negedge clk); + alu_status_expected[`C] = 0; + check; + +/* + // SED + alu_opcode = `SED_IMP; + @(negedge clk); + alu_status_expected[`D] = 1; + check; + + // ADC + alu_opcode = `ADC_IMM; + alu_a = 8'h12; + @(negedge clk); + sign = alu_result_expected[7]; + AL = alu_a[3:0] + alu_result_expected[3:0] + alu_status_expected[`C]; + $display("AL = %b", AL); + AH = alu_a[7:4] + alu_result_expected[7:4] + AL[4]; + $display("AH = %b", AH); + if (AL > 9) begin + temp1 = AL - 6; + end + else begin + temp1 = AL; + end + $display("temp1 = %b", temp1); + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + alu_status_expected[`V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + if (AH > 9) begin + temp2 = AH - 6; + end + else begin + temp2 = AH; + end + $display("temp2 = %b", temp2); + alu_status_expected[`C] = (temp2 > 15) ? 1 : 0; + alu_result_expected = {temp2[3:0],temp1[3:0]}; + $display("A = %b PS = %b", alu_result_expected, alu_status_expected); + check; + + // CLD + alu_opcode = `CLD_IMP; + @(negedge clk); + alu_status_expected[`D] = 0; + check; +*/ +/* + // LDA + alu_a = 0; + alu_opcode = `LDA_IMM; + //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + //$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[`C], alu_status[`D], alu_status[`N], alu_status[`V], alu_result); + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[`N] = 0; + alu_status_expected[`Z] = 1; + check; + + // SED + alu_opcode = `SED_IMP; + //$display("A = %h B = %h X = %h Y = %h", alu_result, alu_a, alu_x, alu_y); + @(negedge clk); + alu_status_expected[`D] = 1; + check; + + // ADC + alu_opcode = `ADC_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = $random; + //$display("A = %h B = %h C = %b X = %h Y = %h", alu_result, alu_a, alu_status_expected[`C], alu_x, alu_y); + @(negedge clk); + AL = alu_result_expected[3:0] + alu_a[3:0] + alu_status_expected[`C]; + AH = alu_result_expected[7:4] + alu_a[7:4] + AL[4]; + if (AL > 9) AL = AL + 6; + if (AH > 9) AH = AH + 6; + alu_status_expected[`C] = AH[4]; + alu_result_expected = {AH[3:0],AL[3:0]}; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + alu_status_expected[`V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + //$stop; + // CLD + alu_opcode = `CLD_IMP; + @(negedge clk); + alu_status_expected[`D] = 0; + check; +*/ + // ASL + alu_opcode = `ASL_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_status_expected[`C], alu_result_expected} = {alu_a,1'b0}; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // ROL + alu_opcode = `ROL_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_status_expected[`C], alu_result_expected} = {alu_a,alu_status_expected[`C]}; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // ROR + alu_opcode = `ROR_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_result_expected, alu_status_expected[`C]} = {alu_status_expected[`C],alu_a}; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // LDA + alu_a = 137; + alu_opcode = `LDA_IMM; + @(negedge clk); + alu_result_expected = 8'd137; + // NV1BDIZC + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + + // EOR + alu_opcode = `EOR_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a ^ alu_result_expected; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + + + + + /* + // LDA + alu_a = 0; + alu_opcode = `LDA_IMM; + //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + //$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[`C], alu_status[`D], alu_status[`N], alu_status[`V], alu_result); + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + + // SBC + alu_opcode = `SBC_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = 1; // ??????? + @(negedge clk); + $display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + $display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y); + $display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[`C], alu_status[`D], alu_status[`N], alu_status[`V], alu_result); + sign = alu_result_expected[7]; + alu_result_expected = alu_result_expected - alu_a - ( 1 - alu_status_expected[`C]); + alu_status_expected[`C] = ~alu_result_expected[7]; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + $display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]); + alu_status_expected[`V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + */ + + + + + $display("XXX LDA_IMM"); + + // LDA + alu_opcode = `LDA_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + $display("XXX LDX_IMM"); + // LDX + alu_opcode = `LDX_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_a; + alu_status_expected[`Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_x_expected[7]; + check; + end + + $display("XXX LDY_IMM"); + + // LDY + alu_opcode = `LDY_IMM; + for (i = 0; i < 1001; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_a; + alu_status_expected[`Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_y_expected[7]; + check; + end + $display("XXX STA_ABS"); + + // STA + alu_opcode = `STA_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // STX + alu_opcode = `STX_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // STY + alu_opcode = `STY_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // CMP + alu_opcode = `CMP_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_result_expected - alu_a; + alu_status_expected[`Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[`N] = temp1[7]; + alu_status_expected[`C] = (alu_result_expected >= alu_a) ? 1 : 0; + check; + end + + // CPX + alu_opcode = `CPX_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_x_expected - alu_a; + alu_status_expected[`Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[`N] = temp1[7]; + alu_status_expected[`C] = (alu_x_expected >= alu_a) ? 1 : 0; + check; + end + + // CPY + alu_opcode = `CPY_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_y_expected - alu_a; + alu_status_expected[`Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[`N] = temp1[7]; + alu_status_expected[`C] = (alu_y_expected >= alu_a) ? 1 : 0; + check; + end + + + // AND + alu_opcode = `AND_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a & alu_result_expected; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // ASL + alu_opcode = `ASL_ACC; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[`C] = alu_result_expected[7]; + alu_result_expected[7:0] = alu_result_expected << 1; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // INC + alu_opcode = `INC_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a + 1; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // INX + alu_opcode = `INX_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_x_expected + 1; + alu_status_expected[`Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_x_expected[7]; + check; + end + + // INY + alu_opcode = `INY_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_y_expected + 1; + alu_status_expected[`Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_y_expected[7]; + check; + end + + // DEC + alu_opcode = `DEC_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a - 1; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + end + + // DEX + alu_opcode = `DEX_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_x_expected - 1; + alu_status_expected[`Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_x_expected[7]; + check; + end + + // DEY + alu_opcode = `DEY_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_y_expected - 1; + alu_status_expected[`Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_y_expected[7]; + check; + end + + + // LDA + alu_a = 0; + alu_opcode = `LDA_IMM; + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[`Z] = 1; + alu_status_expected[`N] = 0; + check; + + // BIT + alu_opcode = `BIT_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[`Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0; + alu_status_expected[`V] = alu_a[6]; + alu_status_expected[`N] = alu_a[7]; + check; + end + + // RTI + alu_opcode = `RTI_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[`C] = alu_a[`C]; + alu_status_expected[`Z] = alu_a[`Z]; + alu_status_expected[`N] = alu_a[`N]; + alu_status_expected[`V] = alu_a[`V]; + alu_status_expected[`B] = alu_a[`B]; + alu_status_expected[`D] = alu_a[`D]; + alu_status_expected[`I] = alu_a[`I]; + check; + end + + // PLP + alu_opcode = `PLP_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[`C] = alu_a[`C]; + alu_status_expected[`Z] = alu_a[`Z]; + alu_status_expected[`N] = alu_a[`N]; + alu_status_expected[`V] = alu_a[`V]; + alu_status_expected[`B] = alu_a[`B]; + alu_status_expected[`D] = alu_a[`D]; + alu_status_expected[`I] = alu_a[`I]; + check; + end + + // PHA + alu_opcode = `PHA_IMP; + @(negedge clk); + check; + + // PHP + alu_opcode = `PHP_IMP; + @(negedge clk); + check; + + // BRK + alu_opcode = `BRK_IMP; + @(negedge clk); + alu_status_expected[`B] = 1; + check; + + // SEC + alu_opcode = `SEC_IMP; + @(negedge clk); + alu_status_expected[`C] = 1; + check; + + // SED + alu_opcode = `SED_IMP; + @(negedge clk); + alu_status_expected[`D] = 1; + check; + + // SEI + alu_opcode = `SEI_IMP; + @(negedge clk); + alu_status_expected[`I] = 1; + check; + + // CLC + alu_opcode = `CLC_IMP; + @(negedge clk); + alu_status_expected[`C] = 0; + check; + + // CLD + alu_opcode = `CLD_IMP; + @(negedge clk); + alu_status_expected[`D] = 0; + check; + + // CLI + alu_opcode = `CLI_IMP; + @(negedge clk); + alu_status_expected[`I] = 0; + check; + + // CLV + alu_opcode = `CLV_IMP; + @(negedge clk); + alu_status_expected[`V] = 0; + check; + + // LDA + alu_opcode = `LDA_IMM; + alu_a = 8'h76; + @(negedge clk); + alu_result_expected = alu_a; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + + // TAX + alu_opcode = `TAX_IMP; + @(negedge clk); + alu_x_expected = alu_result_expected; + alu_status_expected[`Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_x_expected[7]; + check; + + // TAY + alu_opcode = `TAY_IMP; + @(negedge clk); + alu_y_expected = alu_result_expected; + alu_status_expected[`Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_y_expected[7]; + check; + + // TSX + alu_opcode = `TSX_IMP; + @(negedge clk); + alu_x_expected = alu_a; + //alu_result_expected = alu_a; + alu_status_expected[`Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_x_expected[7]; + check; + + // TXA + alu_opcode = `TXA_IMP; + @(negedge clk); + alu_result_expected = alu_x_expected; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + + // TXS + alu_opcode = `TXS_IMP; + @(negedge clk); + alu_result_expected = alu_x_expected; + check; + + // TYA + alu_opcode = `TYA_IMP; + @(negedge clk); + alu_result_expected = alu_y_expected; + alu_status_expected[`Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[`N] = alu_result_expected[7]; + check; + + // Nothing should happen + // BCC + alu_opcode = `BCC_REL; + @(negedge clk); + check; + + // BCS + alu_opcode = `BCS_REL; + @(negedge clk); + check; + + // BEQ + alu_opcode = `BEQ_REL; + @(negedge clk); + check; + + // BMI + alu_opcode = `BMI_REL; + @(negedge clk); + check; + + // BNE + alu_opcode = `BNE_REL; + @(negedge clk); + check; + + // BPL + alu_opcode = `BPL_REL; + @(negedge clk); + check; + + // BVC + alu_opcode = `BVC_REL; + @(negedge clk); + check; + + // BVS + alu_opcode = `BVS_REL; + @(negedge clk); + check; + + // JMP + alu_opcode = `JMP_ABS; + @(negedge clk); + check; + + // JMP + alu_opcode = `JMP_IND; + @(negedge clk); + check; + + // JSR + alu_opcode = `JSR_ABS; + @(negedge clk); + check; + + // NOP + alu_opcode = `NOP_IMP; + @(negedge clk); + check; + + // RTS + alu_opcode = `RTS_IMP; + @(negedge clk); + check; + + $display("TEST PASSED"); + $finish; +end + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dmp_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dmp_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dmp_define (revision 28) @@ -0,0 +1,7 @@ + $dumpfile ("TestBench.vcd"); + $dumpvars (0, TB); + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/t6507lp_alu_tb.v =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/t6507lp_alu_tb.v (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/t6507lp_alu_tb.v (revision 28) @@ -0,0 +1,775 @@ + +module t6507lp_alu_tb; + +`include "t6507lp_package.v" + +reg clk; +reg reset_n; +reg alu_enable; +wire [7:0] alu_result; +wire [7:0] alu_status; +reg [7:0] alu_opcode; +reg [7:0] alu_a; +wire [7:0] alu_x; +wire [7:0] alu_y; + +integer i, j; +integer ADC_RESULTS, SBC_RESULTS; + +reg [7:0] alu_result_expected; +reg [7:0] alu_status_expected; +reg [7:0] alu_x_expected; +reg [7:0] alu_y_expected; + +reg C_in; +reg C_temp; +reg sign; +reg [7:0] temp1; +reg [7:0] temp2; +reg [3:0] AL; +reg [3:0] AH; +reg [3:0] BL; +reg [3:0] BH; +reg [7:0] alu_result_expected_temp; + +t6507lp_alu DUT ( + .clk ( clk ), + .reset_n ( reset_n ), + .alu_enable (alu_enable), + .alu_result (alu_result), + .alu_status (alu_status), + .alu_opcode (alu_opcode), + .alu_a ( alu_a ), + .alu_x ( alu_x ), + .alu_y ( alu_y ) +); + + +localparam period = 10; + +task check; + begin + $display(" RESULTS EXPECTED"); + $display("alu_result %h %h ", alu_result, alu_result_expected); + $display("alu_status %b %b ", alu_status, alu_status_expected); + $display("alu_x %h %h ", alu_x, alu_x_expected ); + $display("alu_y %h %h ", alu_y, alu_y_expected ); + if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y)) + begin + $display("Instruction %h... OK!", alu_opcode); + end + else + begin + $display("ERROR at instruction %h",alu_opcode); + $finish; + end + end +endtask + + +always begin + #(period/2) clk = ~clk; +end + +initial +begin + //ADC_RESULT = fopen("ADC_RESULTS.txt"); + //SBC_RESULT = fopen("SBC_RESULTS.txt"); + + // Reset + clk = 0; + reset_n = 0; + @(negedge clk); + reset_n = 1; + alu_enable = 1; + alu_result_expected = 8'h00; + alu_status_expected = 8'b00100010; + alu_x_expected = 8'h00; + alu_y_expected = 8'h00; + + // LDA + alu_a = 0; + alu_opcode = LDA_IMM; + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected = 8'b00100010; + check; + + // ADC + for (i = 0; i < 256; i = i + 1) + begin + alu_a = i; + alu_opcode = LDA_IMM; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[Z] = (alu_a == 0) ? 1 : 0; + alu_status_expected[N] = alu_a[7]; + check; + for (j = 0; j < 256; j = j + 1) + begin + alu_opcode = ADC_IMM; + alu_a = j; + @(negedge clk); + sign = alu_result_expected[7]; + {alu_status_expected[C], alu_result_expected} = alu_result_expected + alu_a + alu_status_expected[C]; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + end + + // SBC + for (i = 0; i < 256; i = i + 1) + begin + alu_a = i; + alu_opcode = LDA_IMM; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[Z] = (alu_a == 0) ? 1 : 0; + alu_status_expected[N] = alu_a[7]; + check; + for (j = 0; j < 256; j = j + 1) + begin + alu_opcode = SBC_IMM; + alu_a = j; + @(negedge clk); + sign = alu_result_expected[7]; + alu_result_expected = alu_result_expected - alu_a - (1 - alu_status_expected[C]); + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] == alu_result_expected[7])); + alu_status_expected[C] = ~alu_result_expected[7]; + check; + end + end + + // CLC + alu_opcode = CLC_IMP; + @(negedge clk); + alu_status_expected[C] = 0; + check; + +/* + // SED + alu_opcode = SED_IMP; + @(negedge clk); + alu_status_expected[D] = 1; + check; + + // ADC + alu_opcode = ADC_IMM; + alu_a = 8'h12; + @(negedge clk); + sign = alu_result_expected[7]; + AL = alu_a[3:0] + alu_result_expected[3:0] + alu_status_expected[C]; + $display("AL = %b", AL); + AH = alu_a[7:4] + alu_result_expected[7:4] + AL[4]; + $display("AH = %b", AH); + if (AL > 9) begin + temp1 = AL - 6; + end + else begin + temp1 = AL; + end + $display("temp1 = %b", temp1); + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + if (AH > 9) begin + temp2 = AH - 6; + end + else begin + temp2 = AH; + end + $display("temp2 = %b", temp2); + alu_status_expected[C] = (temp2 > 15) ? 1 : 0; + alu_result_expected = {temp2[3:0],temp1[3:0]}; + $display("A = %b PS = %b", alu_result_expected, alu_status_expected); + check; + + // CLD + alu_opcode = CLD_IMP; + @(negedge clk); + alu_status_expected[D] = 0; + check; +*/ +/* + // LDA + alu_a = 0; + alu_opcode = LDA_IMM; + //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + //$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result); + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[N] = 0; + alu_status_expected[Z] = 1; + check; + + // SED + alu_opcode = SED_IMP; + //$display("A = %h B = %h X = %h Y = %h", alu_result, alu_a, alu_x, alu_y); + @(negedge clk); + alu_status_expected[D] = 1; + check; + + // ADC + alu_opcode = ADC_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = $random; + //$display("A = %h B = %h C = %b X = %h Y = %h", alu_result, alu_a, alu_status_expected[C], alu_x, alu_y); + @(negedge clk); + AL = alu_result_expected[3:0] + alu_a[3:0] + alu_status_expected[C]; + AH = alu_result_expected[7:4] + alu_a[7:4] + AL[4]; + if (AL > 9) AL = AL + 6; + if (AH > 9) AH = AH + 6; + alu_status_expected[C] = AH[4]; + alu_result_expected = {AH[3:0],AL[3:0]}; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + //$stop; + // CLD + alu_opcode = CLD_IMP; + @(negedge clk); + alu_status_expected[D] = 0; + check; +*/ + // ASL + alu_opcode = ASL_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_status_expected[C], alu_result_expected} = {alu_a,1'b0}; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // ROL + alu_opcode = ROL_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_status_expected[C], alu_result_expected} = {alu_a,alu_status_expected[C]}; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // ROR + alu_opcode = ROR_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + {alu_result_expected, alu_status_expected[C]} = {alu_status_expected[C],alu_a}; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // LDA + alu_a = 137; + alu_opcode = LDA_IMM; + @(negedge clk); + alu_result_expected = 8'd137; + // NV1BDIZC + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + + // EOR + alu_opcode = EOR_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a ^ alu_result_expected; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + /* + // LDA + alu_a = 0; + alu_opcode = LDA_IMM; + //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + //$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result); + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + + // SBC + alu_opcode = SBC_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = 1; + @(negedge clk); + //$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); + //$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y); + //$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result); + sign = alu_result_expected[7]; + alu_result_expected = alu_result_expected - alu_a - ( 1 - alu_status_expected[C]); + alu_status_expected[C] = ~alu_result_expected[7]; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + //$display("alu_a[7] = %b == sign = %b && alu_a[7] = %b != alu_result_expected[7] = %b", alu_a[7], sign, alu_a[7], alu_result_expected[7]); + alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7])); + check; + end + */ + + // LDA + alu_opcode = LDA_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = i; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // LDX + alu_opcode = LDX_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_a; + alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_x_expected[7]; + check; + end + + // LDY + alu_opcode = LDY_IMM; + for (i = 0; i < 1001; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_a; + alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_y_expected[7]; + check; + end + + // STA + alu_opcode = STA_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // STX + alu_opcode = STX_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // STY + alu_opcode = STY_ABS; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + check; + end + + // CMP + alu_opcode = CMP_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_result_expected - alu_a; + alu_status_expected[Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[N] = temp1[7]; + alu_status_expected[C] = (alu_result_expected >= alu_a) ? 1 : 0; + check; + end + + // CPX + alu_opcode = CPX_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_x_expected - alu_a; + alu_status_expected[Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[N] = temp1[7]; + alu_status_expected[C] = (alu_x_expected >= alu_a) ? 1 : 0; + check; + end + + // CPY + alu_opcode = CPY_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + temp1 = alu_y_expected - alu_a; + alu_status_expected[Z] = (temp1 == 0) ? 1 : 0; + alu_status_expected[N] = temp1[7]; + alu_status_expected[C] = (alu_y_expected >= alu_a) ? 1 : 0; + check; + end + + + // AND + alu_opcode = AND_IMM; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a & alu_result_expected; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // ASL + alu_opcode = ASL_ACC; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[C] = alu_result_expected[7]; + alu_result_expected[7:0] = alu_result_expected << 1; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // INC + alu_opcode = INC_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a + 1; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // INX + alu_opcode = INX_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_x_expected + 1; + alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_x_expected[7]; + check; + end + + // INY + alu_opcode = INY_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_y_expected + 1; + alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_y_expected[7]; + check; + end + + // DEC + alu_opcode = DEC_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_result_expected = alu_a - 1; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + end + + // DEX + alu_opcode = DEX_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_x_expected = alu_x_expected - 1; + alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_x_expected[7]; + check; + end + + // DEY + alu_opcode = DEY_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_y_expected = alu_y_expected - 1; + alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_y_expected[7]; + check; + end + + + // LDA + alu_a = 0; + alu_opcode = LDA_IMM; + @(negedge clk); + alu_result_expected = 8'h00; + // NV1BDIZC + alu_status_expected[Z] = 1; + alu_status_expected[N] = 0; + check; + + // BIT + alu_opcode = BIT_ZPG; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[Z] = ((alu_a & alu_result_expected) == 0) ? 1 : 0; + alu_status_expected[V] = alu_a[6]; + alu_status_expected[N] = alu_a[7]; + check; + end + + // RTI + alu_opcode = RTI_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[C] = alu_a[C]; + alu_status_expected[Z] = alu_a[Z]; + alu_status_expected[N] = alu_a[N]; + alu_status_expected[V] = alu_a[V]; + alu_status_expected[B] = alu_a[B]; + alu_status_expected[D] = alu_a[D]; + alu_status_expected[I] = alu_a[I]; + check; + end + + // PLP + alu_opcode = PLP_IMP; + for (i = 0; i < 1000; i = i + 1) + begin + alu_a = i; + @(negedge clk); + alu_status_expected[C] = alu_a[C]; + alu_status_expected[Z] = alu_a[Z]; + alu_status_expected[N] = alu_a[N]; + alu_status_expected[V] = alu_a[V]; + alu_status_expected[B] = alu_a[B]; + alu_status_expected[D] = alu_a[D]; + alu_status_expected[I] = alu_a[I]; + check; + end + + // PHA + alu_opcode = PHA_IMP; + @(negedge clk); + check; + + // PHP + alu_opcode = PHP_IMP; + @(negedge clk); + check; + + // BRK + alu_opcode = BRK_IMP; + @(negedge clk); + alu_status_expected[B] = 1; + check; + + // SEC + alu_opcode = SEC_IMP; + @(negedge clk); + alu_status_expected[C] = 1; + check; + + // SED + alu_opcode = SED_IMP; + @(negedge clk); + alu_status_expected[D] = 1; + check; + + // SEI + alu_opcode = SEI_IMP; + @(negedge clk); + alu_status_expected[I] = 1; + check; + + // CLC + alu_opcode = CLC_IMP; + @(negedge clk); + alu_status_expected[C] = 0; + check; + + // CLD + alu_opcode = CLD_IMP; + @(negedge clk); + alu_status_expected[D] = 0; + check; + + // CLI + alu_opcode = CLI_IMP; + @(negedge clk); + alu_status_expected[I] = 0; + check; + + // CLV + alu_opcode = CLV_IMP; + @(negedge clk); + alu_status_expected[V] = 0; + check; + + // LDA + alu_opcode = LDA_IMM; + alu_a = 8'h76; + @(negedge clk); + alu_result_expected = alu_a; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + + // TAX + alu_opcode = TAX_IMP; + @(negedge clk); + alu_x_expected = alu_result_expected; + alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_x_expected[7]; + check; + + // TAY + alu_opcode = TAY_IMP; + @(negedge clk); + alu_y_expected = alu_result_expected; + alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_y_expected[7]; + check; + + // TSX + alu_opcode = TSX_IMP; + @(negedge clk); + alu_x_expected = alu_a; + //alu_result_expected = alu_a; + alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_x_expected[7]; + check; + + // TXA + alu_opcode = TXA_IMP; + @(negedge clk); + alu_result_expected = alu_x_expected; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + + // TXS + alu_opcode = TXS_IMP; + @(negedge clk); + alu_result_expected = alu_x_expected; + check; + + // TYA + alu_opcode = TYA_IMP; + @(negedge clk); + alu_result_expected = alu_y_expected; + alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; + alu_status_expected[N] = alu_result_expected[7]; + check; + + // Nothing should happen + // BCC + alu_opcode = BCC_REL; + @(negedge clk); + check; + + // BCS + alu_opcode = BCS_REL; + @(negedge clk); + check; + + // BEQ + alu_opcode = BEQ_REL; + @(negedge clk); + check; + + // BMI + alu_opcode = BMI_REL; + @(negedge clk); + check; + + // BNE + alu_opcode = BNE_REL; + @(negedge clk); + check; + + // BPL + alu_opcode = BPL_REL; + @(negedge clk); + check; + + // BVC + alu_opcode = BVC_REL; + @(negedge clk); + check; + + // BVS + alu_opcode = BVS_REL; + @(negedge clk); + check; + + // JMP + alu_opcode = JMP_ABS; + @(negedge clk); + check; + + // JMP + alu_opcode = JMP_IND; + @(negedge clk); + check; + + // JSR + alu_opcode = JSR_ABS; + @(negedge clk); + check; + + // NOP + alu_opcode = NOP_IMP; + @(negedge clk); + check; + + // RTS + alu_opcode = RTS_IMP; + @(negedge clk); + check; + + $display("TEST PASSED"); + $finish; +end + +endmodule + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/filelist (revision 28) @@ -0,0 +1,6 @@ +`include "../../../rtl/gen/sim/T6502.v" +`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" +`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" +`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" +`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" +`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" \ No newline at end of file Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dut =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dut (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/dut (revision 28) @@ -0,0 +1,68 @@ + + + +reg reset_n; +reg alu_enable; +wire [7:0] alu_result; +wire [7:0] alu_status; +reg [7:0] alu_opcode; +reg [7:0] alu_a; +wire [7:0] alu_x; +wire [7:0] alu_y; + + + +integer i, j; +integer ADC_RESULTS, SBC_RESULTS; + +reg [7:0] alu_result_expected; +reg [7:0] alu_status_expected; +reg [7:0] alu_x_expected; +reg [7:0] alu_y_expected; + +reg C_in; +reg C_temp; +reg sign; +reg [7:0] temp1; +reg [7:0] temp2; +reg [3:0] AL; +reg [3:0] AH; +reg [3:0] BL; +reg [3:0] BH; +reg [7:0] alu_result_expected_temp; + +T6502_alu dut ( + .clk ( clk ), + .reset (!reset_n ), + .enable ( enable ), + .alu_enable ( alu_enable ), + .alu_result ( alu_result ), + .alu_status ( alu_status ), + .alu_opcode ( alu_opcode ), + .alu_a ( alu_a ), + .alu_x ( alu_x ), + .alu_y ( alu_y ) +); + + + +task check; + begin + $display(" RESULTS EXPECTED"); + $display("alu_result %h %h ", alu_result, alu_result_expected); + $display("alu_status %b %b ", alu_status, alu_status_expected); + $display("alu_x %h %h ", alu_x, alu_x_expected ); + $display("alu_y %h %h ", alu_y, alu_y_expected ); + if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y)) + begin + $display("Instruction %h... OK!", alu_opcode); + end + else + begin + $display("ERROR at instruction %h",alu_opcode); + $finish; + end + end +endtask + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/modellist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/modellist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/alu_test/modellist (revision 28) @@ -0,0 +1,2 @@ +`include "../../bench/verilog/models/clock_gen.v" + Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/t6507lp_fsm_tb.v =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/t6507lp_fsm_tb.v (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/t6507lp_fsm_tb.v (revision 28) @@ -0,0 +1,234 @@ +//////////////////////////////////////////////////////////////////////////// +//// //// +//// T6507LP IP Core //// +//// //// +//// This file is part of the T6507LP project //// +//// http://www.opencores.org/cores/t6507lp/ //// +//// //// +//// Description //// +//// 6507 FSM testbench //// +//// //// +//// Author(s): //// +//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com //// +//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com //// +//// //// +//////////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +//////////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module t6507lp_fsm_tb(); + // mem_rw signals + localparam MEM_READ = 1'b0; + localparam MEM_WRITE = 1'b1; + + reg clk; // regs are inputs + reg reset_n; + reg [7:0] alu_result; + reg [7:0] alu_status; + reg [7:0] data_in; + reg [7:0] alu_x; + reg [7:0] alu_y; + wire [12:0] address; // wires are outputs + wire mem_rw; + wire [7:0] data_out; + wire [7:0] alu_opcode; + wire [7:0] alu_a; + wire alu_enable; + + integer my_i; + + `include "t6507lp_package.v" + + t6507lp_fsm #(8,13) t6507lp_fsm( + .clk(clk), + .reset_n(reset_n), + .alu_result(alu_result), + .alu_status(alu_status), + .data_in(data_in), + .alu_x(alu_x), + .alu_y(alu_y), + .address(address), + .rw_mem(mem_rw), + .data_out(data_out), + .alu_opcode(alu_opcode), + .alu_a(alu_a), + .alu_enable(alu_enable) + ); + + always #10 clk = ~clk; + + reg[7:0] fake_mem[2**13-1:0]; + + initial begin + clk = 1'b0; + reset_n = 1'b0; + alu_result = 8'h01; + alu_status = 8'h00; + alu_x = 8'h07; + alu_y = 8'h03; + + for (my_i=0; my_i < 2**13; my_i= my_i+1) begin + $write("\n%d",my_i); + fake_mem[my_i]=8'h00; + end + + fake_mem[0] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed; + fake_mem[1] = 8'h00; + fake_mem[2] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed; + fake_mem[3] = 8'h04; + fake_mem[4] = 8'hFF; + + + /*fake_mem[0] = ASL_ACC; // testing ACC mode + fake_mem[1] = ADC_IMM; // testing IMM mode + fake_mem[2] = 8'h27; + fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type + fake_mem[4] = 8'h09;*/ + fake_mem[5] = 8'h00; + fake_mem[6] = ASL_ACC; // wont be executed + fake_mem[7] = ASL_ACC; // wont be executed + fake_mem[8] = ASL_ACC; // wont be executed + fake_mem[9] = ASL_ACC; // wont be executed + fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27) + fake_mem[11] = 8'h02; + fake_mem[12] = 8'h00; + fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC + fake_mem[14] = 8'h00; + fake_mem[15] = 8'h00; + fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1] + fake_mem[17] = 8'h01; + fake_mem[18] = 8'h00; + fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type + fake_mem[20] = 8'h00; + fake_mem[21] = ASL_ZPG; // testing ZPG mode, READ_MODIFY_WRITE type + fake_mem[22] = 8'h00; + fake_mem[23] = STA_ZPG; // testing ZPG mode, WRITE type + fake_mem[24] = 8'h00; + fake_mem[25] = LDA_ZPX; // testing ZPX mode, READ type. A = MEM[x+1] + fake_mem[26] = 8'h01; + fake_mem[27] = ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1; + fake_mem[28] = 8'h01; + fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A; + fake_mem[30] = 8'h02; + fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed. + fake_mem[32] = 8'h0a; + fake_mem[33] = 8'h00; + fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed. + fake_mem[35] = 8'hff; + fake_mem[36] = 8'h00; + fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed. + fake_mem[38] = 8'h01; + fake_mem[39] = 8'd35; + fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed. + fake_mem[41] = 8'hff; + fake_mem[42] = 8'h00; + fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed. + fake_mem[41] = 8'h04; + fake_mem[42] = 8'h00; + fake_mem[43] = STA_ABX; // testing ABX mode, WRITE TYPE. Page crossed. + fake_mem[44] = 8'hff; + fake_mem[45] = 8'h00; + fake_mem[46] = BNE_REL; // testing REL mode, taking a branch, no page crossed. + fake_mem[47] = 8'h0a; + fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed. + fake_mem[59] = 8'hff; + fake_mem[60] = 8'hff; + fake_mem[254] = 8'hff; + fake_mem[256] = 8'h55; // PCL fetched from here when executing RTS_IMP + fake_mem[257] = 8'h01; // PCH fetched from here when executing RTS_IMP + fake_mem[264] = 8'd340; + fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed. + fake_mem[316] = 8'hff; + fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed. + fake_mem[318] = 8'h00; + fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed; + fake_mem[320] = 8'h0a; + fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed; this will actually do A = MEM[6] because there is no carry + fake_mem[322] = 8'hff; + //fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE + //fake_mem[320] = 8'h0a; // all of read modify write instructions are not documented therefore will not be simulated + fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored + fake_mem[324] = 8'hff; + fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed; + fake_mem[326] = 8'h00; + fake_mem[327] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed; + fake_mem[328] = 8'h00; + fake_mem[329] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed. + fake_mem[330] = 8'hff; + /* testing IDY mode READ TYPE, page crossed. + address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs. + this is probably not an issue */ + fake_mem[331] = LDA_IDY; + fake_mem[332] = 8'hfe; + fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed; + fake_mem[334] = 8'h00; + fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed; + fake_mem[336] = 8'h0e; + fake_mem[337] = INX_IMP; + //fake_mem[338] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer. + //fake_mem[339] = 8'hff; + //fake_mem[340] = 8'h00; + //fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer. + //fake_mem[338] = 8'h3b; // these are commented cause they will actually jump + //fake_mem[339] = 8'h00; + //fake_mem[338] = BRK_IMP; + //fake_mem[339] = RTI_IMP; + //fake_mem[340] = RTS_IMP; + // 341 is skipped due to RTS internal functionality + //fake_mem[342] = PHA_IMP; + //fake_mem[343] = PHP_IMP; + //fake_mem[344] = PLA_IMP; + //fake_mem[345] = PLP_IMP; + fake_mem[338] = JSR_ABS; + fake_mem[339] = 8'h01; + fake_mem[340] = 8'h01; + + + + fake_mem[8190] = 8'h53; // this is the reset vector + fake_mem[8191] = 8'h01; + @(negedge clk) // will wait for next negative edge of the clock (t=20) + reset_n=1'b1; + + + #4000; + $finish; // to shut down the simulation + end //initial + + always @(clk) begin + if (mem_rw == MEM_READ) begin // MEM_READ + data_in <= fake_mem[address]; + $write("\nreading from mem position %h: %h", address, fake_mem[address]); + end + else begin // MEM_WRITE + fake_mem[address] <= data_out; + $write("\nreading from mem position %h: %h", address, fake_mem[address]); + end + end + +endmodule Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/liblist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/liblist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/liblist (revision 28) @@ -0,0 +1,6 @@ +`include "../../lib/cde_sram/cde_sram.v" +`include "../../lib/cde_divider/cde_divider.v" +`include "../../lib/cde_fifo/cde_fifo.v" +`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" +`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" +`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" \ No newline at end of file Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/TB.defs =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/TB.defs (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/TB.defs (revision 28) @@ -0,0 +1,8 @@ +`include "../../../rtl/variants/T6502/T6502_defines.v" + + + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/test_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/test_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/test_define (revision 28) @@ -0,0 +1,162 @@ +initial +begin +$display(" "); +$display(" ==================================================="); +$display(" Test Start"); +$display(" ==================================================="); +$display(" "); +cg.next(20); +cg.reset_off; +cg.next(9000); +cg.exit; +end + + + initial begin + + reset_n = 1'b0; + alu_result = 8'h01; + alu_status = 8'h00; + alu_x = 8'h07; + alu_y = 8'h03; + + for (my_i=0; my_i < 2**13; my_i= my_i+1) begin + $write("\n%d",my_i); + fake_mem[my_i]=8'h00; + end + + fake_mem[0] = `STA_IDY; // testing IDY mode WRITE TYPE, page crossed; + fake_mem[1] = 8'h00; + fake_mem[2] = `STA_IDY; // testing IDY mode WRITE TYPE, page not crossed; + fake_mem[3] = 8'h04; + fake_mem[4] = 8'hFF; + + + /*fake_mem[0] = `ASL_ACC; // testing ACC mode + fake_mem[1] = `ADC_IMM; // testing IMM mode + fake_mem[2] = 8'h27; + fake_mem[3] = `JMP_ABS; // testing ABS mode, JMP type + fake_mem[4] = 8'h09;*/ + fake_mem[5] = 8'h00; + fake_mem[6] = `ASL_ACC; // wont be executed + fake_mem[7] = `ASL_ACC; // wont be executed + fake_mem[8] = `ASL_ACC; // wont be executed + fake_mem[9] = `ASL_ACC; // wont be executed + fake_mem[10] = `LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27) + fake_mem[11] = 8'h02; + fake_mem[12] = 8'h00; + fake_mem[13] = `ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC + fake_mem[14] = 8'h00; + fake_mem[15] = 8'h00; + fake_mem[16] = `STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1] + fake_mem[17] = 8'h01; + fake_mem[18] = 8'h00; + fake_mem[19] = `LDA_ZPG; // testing ZPG mode, READ type + fake_mem[20] = 8'h00; + fake_mem[21] = `ASL_ZPG; // testing ZPG mode, READ_MODIFY_WRITE type + fake_mem[22] = 8'h00; + fake_mem[23] = `STA_ZPG; // testing ZPG mode, WRITE type + fake_mem[24] = 8'h00; + fake_mem[25] = `LDA_ZPX; // testing ZPX mode, READ type. A = MEM[x+1] + fake_mem[26] = 8'h01; + fake_mem[27] = `ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1; + fake_mem[28] = 8'h01; + fake_mem[29] = `STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A; + fake_mem[30] = 8'h02; + fake_mem[31] = `LDA_ABX; // testing ABX mode, READ TYPE. No page crossed. + fake_mem[32] = 8'h0a; + fake_mem[33] = 8'h00; + fake_mem[34] = `LDA_ABX; // testing ABX mode, READ TYPE. Page crossed. + fake_mem[35] = 8'hff; + fake_mem[36] = 8'h00; + fake_mem[37] = `ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed. + fake_mem[38] = 8'h01; + fake_mem[39] = 8'd35; + fake_mem[40] = `ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed. + fake_mem[41] = 8'hff; + fake_mem[42] = 8'h00; + fake_mem[40] = `STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed. + fake_mem[41] = 8'h04; + fake_mem[42] = 8'h00; + fake_mem[43] = `STA_ABX; // testing ABX mode, WRITE TYPE. Page crossed. + fake_mem[44] = 8'hff; + fake_mem[45] = 8'h00; + fake_mem[46] = `BNE_REL; // testing REL mode, taking a branch, no page crossed. + fake_mem[47] = 8'h0a; + fake_mem[58] = `BNE_REL; // testing REL mode, taking a branch, page crossed. + fake_mem[59] = 8'hff; + fake_mem[60] = 8'hff; + fake_mem[254] = 8'hff; + fake_mem[256] = 8'h55; // PCL fetched from here when executing RTS_IMP + fake_mem[257] = 8'h01; // PCH fetched from here when executing RTS_IMP + fake_mem[264] = 8'd340; + fake_mem[315] = `BEQ_REL; // testing REL mode, not taking a branch, page would have crossed. + fake_mem[316] = 8'hff; + fake_mem[317] = `BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed. + fake_mem[318] = 8'h00; + fake_mem[319] = `LDA_IDX; // testing IDX mode READ TYPE, no page crossed; + fake_mem[320] = 8'h0a; + fake_mem[321] = `LDA_IDX; // testing IDX mode READ TYPE, page crossed; this will actually do A = MEM[6] because there is no carry + fake_mem[322] = 8'hff; + //fake_mem[319] = `SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE + //fake_mem[320] = 8'h0a; // all of read modify write instructions are not documented therefore will not be simulated + fake_mem[323] = `STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored + fake_mem[324] = 8'hff; + fake_mem[325] = `STA_IDX; // testing IDX mode WRITE TYPE, page not crossed; + fake_mem[326] = 8'h00; + fake_mem[327] = `LDA_IDY; // testing IDY mode READ TYPE, page not crossed; + fake_mem[328] = 8'h00; + fake_mem[329] = `LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed. + fake_mem[330] = 8'hff; + /* testing IDY mode READ TYPE, page crossed. + address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs. + this is probably not an issue */ + fake_mem[331] = `LDA_IDY; + fake_mem[332] = 8'hfe; + fake_mem[333] = `STA_IDY; // testing IDY mode WRITE TYPE, page crossed; + fake_mem[334] = 8'h00; + fake_mem[335] = `STA_IDY; // testing IDY mode WRITE TYPE, page not crossed; + fake_mem[336] = 8'h0e; + fake_mem[337] = `INX_IMP; + //fake_mem[338] = `JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer. + //fake_mem[339] = 8'hff; + //fake_mem[340] = 8'h00; + //fake_mem[337] = `JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer. + //fake_mem[338] = 8'h3b; // these are commented cause they will actually jump + //fake_mem[339] = 8'h00; + //fake_mem[338] = `BRK_IMP; + //fake_mem[339] = `RTI_IMP; + //fake_mem[340] = `RTS_IMP; + // 341 is skipped due to RTS internal functionality + //fake_mem[342] = `PHA_IMP; + //fake_mem[343] = `PHP_IMP; + //fake_mem[344] = `PLA_IMP; + //fake_mem[345] = `PLP_IMP; + fake_mem[338] = `JSR_ABS; + fake_mem[339] = 8'h01; + fake_mem[340] = 8'h01; + + + + fake_mem[8190] = 8'h53; // this is the reset vector + fake_mem[8191] = 8'h01; + @(negedge clk) // will wait for next negative edge of the clock (t=20) + reset_n=1'b1; + + + #4000; + $finish; // to shut down the simulation + end //initial + + always @(clk) begin + if (mem_rw == MEM_READ) begin // MEM_READ + data_in <= fake_mem[address]; + $write("\nreading from mem position %h: %h", address, fake_mem[address]); + end + else begin // MEM_WRITE + fake_mem[address] <= data_out; + $write("\nreading from mem position %h: %h", address, fake_mem[address]); + end + end + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dmp_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dmp_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dmp_define (revision 28) @@ -0,0 +1,7 @@ + $dumpfile ("TestBench.vcd"); + $dumpvars (0, TB); + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/filelist (revision 28) @@ -0,0 +1,6 @@ +`include "../../../rtl/gen/sim/T6502.v" +`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" +`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" +`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" +`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" +`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" \ No newline at end of file Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/modellist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/modellist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/modellist (revision 28) @@ -0,0 +1,2 @@ +`include "../../bench/verilog/models/clock_gen.v" + Index: trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dut =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dut (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/fsm_test/dut (revision 28) @@ -0,0 +1,48 @@ + + // mem_rw signals + localparam MEM_READ = 1'b0; + localparam MEM_WRITE = 1'b1; + + + reg reset_n; + reg [7:0] alu_result; + reg [7:0] alu_status; + reg [7:0] data_in; + reg [7:0] alu_x; + reg [7:0] alu_y; + wire [15:0] address; + wire [15:0] pc; + wire mem_rw; + wire [7:0] data_out; + wire [7:0] alu_opcode; + wire [7:0] alu_a; + wire alu_enable; + + integer my_i; + + + + T6502_fsm t6507lp_fsm( + .clk ( clk ), + .reset (!reset_n ), + .enable ( enable ), + .alu_result ( alu_result ), + .alu_status ( alu_status ), + .data_in ( data_in ), + .alu_x ( alu_x ), + .alu_y ( alu_y ), + .address ( address ), + .pc ( pc ), + .rw_mem ( mem_rw ), + .data_out ( data_out ), + .alu_opcode ( alu_opcode ), + .alu_a ( alu_a ), + .alu_enable ( alu_enable ) + ); + + + + reg[7:0] fake_mem[2**13-1:0]; + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/liblist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/liblist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/liblist (revision 28) @@ -0,0 +1,8 @@ +`include "../../lib/cde_sram/cde_sram.v" +`include "../../lib/cde_divider/cde_divider.v" +`include "../../lib/cde_fifo/cde_fifo.v" +`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" +`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" +`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/TB.defs =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/TB.defs (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/TB.defs (revision 28) @@ -0,0 +1,7 @@ +`define TIMEOUT 800000 + +`define ROM_WORDS 4096 +`define ROM_ADD 12 +`define ROM_FILE "../../../../../../Mos6502/sw/Prog/Prog.abs" + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/test_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/test_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/test_define (revision 28) @@ -0,0 +1,15 @@ +initial +begin +$display(" "); +$display(" ==================================================="); +$display(" Test Start"); +$display(" ==================================================="); +$display(" "); +cg.next(20); +cg.reset_off; +cg.next(9000); +cg.exit; +end + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dmp_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dmp_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dmp_define (revision 28) @@ -0,0 +1,7 @@ + $dumpfile ("TestBench.vcd"); + $dumpvars (0, TB); + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/filelist (revision 28) @@ -0,0 +1,9 @@ +`include "../../../rtl/gen/sim/T6502.v" +`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" +`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" +`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" +`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" +`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dut =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dut (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/dut (revision 28) @@ -0,0 +1,125 @@ + +wire [15:0] addr; + + + +wire serial_txd; +wire serial_rxd; + + + + +wire [7:0] Status; + + +wire ps2_clk_in; +wire ps2_data_in; +wire ps2_clk_oe; +wire ps2_data_oe; + + +wire ps2_clk; +wire ps2_data; + + + + + +reg enable; + +always@(posedge clk) +if(reset) enable <= 1'b1; +else enable <= !enable; + + +T6502 + +#(.ROM_WORDS(`ROM_WORDS), + .ROM_ADD (`ROM_ADD), + .ROM_FILE (`ROM_FILE), + .BOOT (16'hf000) + + ) + +dut +( + .clk ( clk ), + .reset ( reset ), + .enable ( enable ), + + .gpio_0_out ( Status ), + .gpio_0_in ( Status ), + .gpio_0_oe ( ), + .gpio_0_lat ( ), + + .gpio_1_out ( ), + .gpio_1_in ( 8'h00 ), + .gpio_1_oe ( ), + .gpio_1_lat ( ), + + .ps2_clk_oe ( ps2_clk_oe ), + .ps2_clk_in ( ps2_clk_in ), + .ps2_data_oe ( ps2_data_oe ), + .ps2_data_in ( ps2_data_in ), + + .txd_pad_out ( serial_txd ), + .rxd_pad_in ( serial_rxd ), + .cts_pad_in ( loop ), + .rts_pad_out ( loop ) +); + + + + + + + +iobuftri +data_tri_buf + ( + .i ( 1'b0 ), + .oe ( ps2_data_oe ), + .o ( ps2_data_in ), + .pad ( ps2_data ) + ); + + +iobuftri +clk_tri_buf + ( + .i ( 1'b0 ), + .oe ( ps2_clk_oe ), + .o ( ps2_clk_in ), + .pad ( ps2_clk ) + ); + + + +pullup ua0(ps2_clk); +pullup ua1(ps2_data); + + +ps2_model +#(.CLKCNT(10'h177)) +ps2_model +( + .clk ( clk ), + .reset ( reset ), + .ps2_clk ( ps2_clk ), + .ps2_data ( ps2_data ) + + + +); + + + + + + uart_model #(.CLKCNT(4'hc)) + uart_model ( + .clk ( clk ), + .reset ( reset ), + .txd_in ( serial_txd ), + .rxd_out ( serial_rxd ) + ); Index: trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/modellist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/modellist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/prog_test/modellist (revision 28) @@ -0,0 +1,5 @@ +`include "../../bench/verilog/models/clock_gen.v" + +`include "../../bench/verilog/models/ps2_model.v" +`include "../../bench/verilog/models/iobuftri.v" +`include "../../bench/verilog/models/uart_model.v" Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/liblist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/liblist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/liblist (revision 28) @@ -0,0 +1,8 @@ +`include "../../lib/cde_sram/cde_sram.v" +`include "../../lib/cde_divider/cde_divider.v" +`include "../../lib/cde_fifo/cde_fifo.v" +`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v" +`include "../../lib/cde_serial_xmit/cde_serial_xmit.v" +`include "../../lib/cde_synchronizers/cde_sync_with_hysteresis.v" + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/TB.defs =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/TB.defs (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/TB.defs (revision 28) @@ -0,0 +1,5 @@ +`define TIMEOUT 800000 + +`define ROM_WORDS 2048 +`define ROM_ADD 11 +`define ROM_FILE "../../../../../../Mos6502/sw/io_poll/io_poll.abs" Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/test_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/test_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/test_define (revision 28) @@ -0,0 +1,20 @@ +initial +begin +$display(" "); +$display(" ==================================================="); +$display(" Test Start"); +$display(" ==================================================="); +$display(" "); +cg.next(20); +cg.reset_off; +uart_model.rcv_byte(8'h42); +uart_model.send_byte(8'h65); +uart_model.rcv_byte(8'h67); +uart_model.send_byte(8'h37); +uart_model.rcv_byte(8'h39); +cg.next(4000); +cg.exit; +end + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dmp_define =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dmp_define (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dmp_define (revision 28) @@ -0,0 +1,7 @@ + $dumpfile ("TestBench.vcd"); + $dumpvars (0, TB); + + + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/filelist (revision 28) @@ -0,0 +1,9 @@ +`include "../../../rtl/gen/sim/T6502.v" +`include "../../../../../children/logic/ip/io_module/rtl/gen/sim/io_module.v" +`include "../../../../../children/logic/ip/uart/rtl/gen/sim/uart.v" +`include "../../../../../children/logic/ip/serial_rcvr/rtl/gen/sim/serial_rcvr.v" +`include "../../../../../children/logic/ip/ps2_interface/rtl/gen/sim/ps2_interface.v" +`include "../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v" + + + Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dut =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dut (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/dut (revision 28) @@ -0,0 +1,125 @@ + +wire [15:0] addr; + + + +wire serial_txd; +wire serial_rxd; + + + + +wire [7:0] Status; + + +wire ps2_clk_in; +wire ps2_data_in; +wire ps2_clk_oe; +wire ps2_data_oe; + + +wire ps2_clk; +wire ps2_data; + + + + + +reg enable; + +always@(posedge clk) +if(reset) enable <= 1'b1; +else enable <= !enable; + + +T6502 + +#(.ROM_WORDS(`ROM_WORDS), + .ROM_ADD (`ROM_ADD), + .ROM_FILE (`ROM_FILE), + .BOOT (16'hf800) + + ) + +dut +( + .clk ( clk ), + .reset ( reset ), + .enable ( enable ), + + .gpio_0_out ( Status ), + .gpio_0_in ( Status ), + .gpio_0_oe ( ), + .gpio_0_lat ( ), + + .gpio_1_out ( ), + .gpio_1_in ( 8'h00 ), + .gpio_1_oe ( ), + .gpio_1_lat ( ), + + .ps2_clk_oe ( ps2_clk_oe ), + .ps2_clk_in ( ps2_clk_in ), + .ps2_data_oe ( ps2_data_oe ), + .ps2_data_in ( ps2_data_in ), + + .txd_pad_out ( serial_txd ), + .rxd_pad_in ( serial_rxd ), + .cts_pad_in ( loop ), + .rts_pad_out ( loop ) +); + + + + + + + +iobuftri +data_tri_buf + ( + .i ( 1'b0 ), + .oe ( ps2_data_oe ), + .o ( ps2_data_in ), + .pad ( ps2_data ) + ); + + +iobuftri +clk_tri_buf + ( + .i ( 1'b0 ), + .oe ( ps2_clk_oe ), + .o ( ps2_clk_in ), + .pad ( ps2_clk ) + ); + + + +pullup ua0(ps2_clk); +pullup ua1(ps2_data); + + +ps2_model +#(.CLKCNT(10'h177)) +ps2_model +( + .clk ( clk ), + .reset ( reset ), + .ps2_clk ( ps2_clk ), + .ps2_data ( ps2_data ) + + + +); + + + + + + uart_model #(.CLKCNT(4'hc)) + uart_model ( + .clk ( clk ), + .reset ( reset ), + .txd_in ( serial_txd ), + .rxd_out ( serial_rxd ) + ); Index: trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/modellist =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/modellist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/run/io_poll/modellist (revision 28) @@ -0,0 +1,5 @@ +`include "../../bench/verilog/models/clock_gen.v" + +`include "../../bench/verilog/models/ps2_model.v" +`include "../../bench/verilog/models/iobuftri.v" +`include "../../bench/verilog/models/uart_model.v" Index: trunk/projects/Mos6502/ip/T6502/sim/bin/Makefile =================================================================== --- trunk/projects/Mos6502/ip/T6502/sim/bin/Makefile (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/sim/bin/Makefile (revision 28) @@ -0,0 +1,3 @@ +include ../../../../bin/Makefile.root + + Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/bsdl/xc3s1200e_fg320_1532.bsd =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/bsdl/xc3s1200e_fg320_1532.bsd (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/bsdl/xc3s1200e_fg320_1532.bsd (revision 28) @@ -0,0 +1,1591 @@ +--$ XILINX$RCSfile: xc3s1200e_fg320_1532.bsd,v $ +--$ XILINX$Revision: 1.2.124.1 $ + +--################################################################### +-- WARNING !!!! .. This is a 1532 PROTOTYPE BDSL file. +--################################################################### +-- +-- It should not be be used in place of, or along side of 1149.1 bsdl files. +-- +-- This file conforms to the unapproved IEEE Standard 1532 BSDL draft +-- Standard. It may not function as expected with IEEE 1149.1 BSDL +-- and is subject to change pending the ratification of the 1532 Standard +-- by the IEEE. When denoted as FINAL, it has been verified +-- syntactically, and against hardware. +-- +-- Prototype 1532 BSDL file for device XC3S1200E, package FG320 +-- Xilinx, Inc. $State: Exp $ $Date: 2008/07/07 22:23:21 $ +-- +-- Generated by BSDLnet bsdlnet Version 1.40 +------------------------------------------------------------------------ +-- Modification History +-- | Generated on 05/28/08 +-- | CR # 471899 +-- | Details - Initial Release using BSDLnet. +-- | Added 'attribute COMPLIANCE_PATTERNS' & changed boundary +-- | register attribute to internal for PROG_B & PUDC_B. +------------------------------------------------------------------------ +-- +-- createBSDL template $RCSfile: xc3s1200e_fg320_1532.bsd,v $ $Revision: 1.2.124.1 $ $Date: 2008/07/07 22:23:21 $ +-- +--################################################################### +-- +-- +-- For technical support, contact Xilinx on the web at: +-- +-- http://support.xilinx.com +-- +-- Technical support can also take place via email or phone at: +-- +-- North America 1-800-255-7778 hotline@xilinx.com +-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com +-- France (33) 1 3463 0100 frhelp@xilinx.com +-- Germany (49) 89 991 54930 dlhelp@xilinx.com +-- Japan (81) 3-3297-9163 jhotline@xilinx.com +-- +-- +-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect +-- the post-configuration JTAG behavior (if any), edit this file as described +-- below. Many of these changes are demonstrated by commented-out template +-- lines preceeding the lines they would replace: +-- +-- 1. Set disable result of all pads as configured. +-- 2. Set safe state of boundary cells as necessary. +-- 3. Rename entity if necessary to avoid name collisions. +-- 4. Modify USERCODE value in USERCODE_REGISTER declaration. +-- +--###################################################################-- + +---------------------------------- + +-- BSDL File for 1532 Standard. + +---------------------------------- + +entity XC3S1200E_FG320 is + +-- Generic Parameter + +generic (PHYSICAL_PIN_MAP : string := "FG320" ); + +-- Logical Port Description + +port ( + A10: inout bit; -- PAD40 + A11: inout bit; -- PAD49 + A12: inout bit; -- PAD54 + A13: inout bit; -- PAD59 + A14: inout bit; -- PAD62 + A16: inout bit; -- PAD76 + A4: inout bit; -- PAD5 + A6: inout bit; -- PAD14 + A7: inout bit; -- PAD20 + A8: inout bit; -- PAD28 + B10: inout bit; -- PAD41 + B11: inout bit; -- PAD42 + B13: inout bit; -- PAD58 + B14: inout bit; -- PAD63 + B16: inout bit; -- PAD77 + B4: inout bit; -- PAD4 + B6: inout bit; -- PAD15 + C1: inout bit; -- PAD304 + C11: inout bit; -- PAD48 + C14: inout bit; -- PAD72 + C17: inout bit; -- PAD80 + C18: inout bit; -- PAD81 + C2: inout bit; -- PAD303 + C3: inout bit; -- PAD2 + C4: inout bit; -- PAD6 + C5: inout bit; -- PAD8 + C7: inout bit; -- PAD27 + C9: inout bit; -- PAD37 + D1: inout bit; -- PAD302 + D10: inout bit; -- PAD44 + D11: inout bit; -- PAD47 + D13: inout bit; -- PAD57 + D14: inout bit; -- PAD73 + D16: inout bit; -- PAD82 + D17: inout bit; -- PAD83 + D2: inout bit; -- PAD301 + D4: inout bit; -- PAD298 + D5: inout bit; -- PAD7 + D6: inout bit; -- PAD12 + D7: inout bit; -- PAD26 + D9: inout bit; -- PAD36 + DONE: inout bit; + E1: inout bit; -- PAD296 + E10: inout bit; -- PAD43 + E11: inout bit; -- PAD51 + E12: inout bit; -- PAD55 + E13: inout bit; -- PAD71 + E15: inout bit; -- PAD85 + E16: inout bit; -- PAD84 + E2: inout bit; -- PAD297 + E3: inout bit; -- PAD291 + E4: inout bit; -- PAD292 + E6: inout bit; -- PAD11 + E7: inout bit; -- PAD21 + E8: inout bit; -- PAD30 + E9: inout bit; -- PAD34 + F1: inout bit; -- PAD287 + F11: inout bit; -- PAD50 + F12: inout bit; -- PAD56 + F14: inout bit; -- PAD92 + F15: inout bit; -- PAD93 + F17: inout bit; -- PAD99 + F18: inout bit; -- PAD100 + F2: inout bit; -- PAD286 + F7: inout bit; -- PAD22 + F8: inout bit; -- PAD29 + F9: inout bit; -- PAD33 + G13: inout bit; -- PAD97 + G14: inout bit; -- PAD98 + G15: inout bit; -- PAD103 + G16: inout bit; -- PAD102 + G3: inout bit; -- PAD285 + G4: inout bit; -- PAD284 + G5: inout bit; -- PAD281 + G6: inout bit; -- PAD282 + G9: inout bit; -- PAD35 + GND: linkage bit_vector (1 to 28); + H1: inout bit; -- PAD274 + H14: inout bit; -- PAD105 + H15: inout bit; -- PAD104 + H16: inout bit; -- PAD108 + H17: inout bit; -- PAD107 + H2: inout bit; -- PAD275 + H3: inout bit; -- PAD276 + H4: inout bit; -- PAD277 + H5: inout bit; -- PAD279 + H6: inout bit; -- PAD280 + IPAD10: in bit; + IPAD101: in bit; + IPAD106: in bit; + IPAD111: in bit; + IPAD116: in bit; + IPAD121: in bit; + IPAD126: in bit; + IPAD131: in bit; + IPAD136: in bit; + IPAD141: in bit; + IPAD148: in bit; + IPAD155: in bit; + IPAD161: in bit; + IPAD162: in bit; + IPAD183: in bit; + IPAD184: in bit; + IPAD190: in bit; + IPAD191: in bit; + IPAD197: in bit; + IPAD198: in bit; + IPAD204: in bit; + IPAD205: in bit; + IPAD226: in bit; + IPAD227: in bit; + IPAD230: in bit; + IPAD231: in bit; + IPAD238: in bit; + IPAD243: in bit; + IPAD248: in bit; + IPAD253: in bit; + IPAD258: in bit; + IPAD263: in bit; + IPAD268: in bit; + IPAD273: in bit; + IPAD278: in bit; + IPAD283: in bit; + IPAD288: in bit; + IPAD293: in bit; + IPAD3: in bit; + IPAD300: in bit; + IPAD31: in bit; + IPAD32: in bit; + IPAD38: in bit; + IPAD39: in bit; + IPAD45: in bit; + IPAD46: in bit; + IPAD52: in bit; + IPAD53: in bit; + IPAD74: in bit; + IPAD75: in bit; + IPAD78: in bit; + IPAD79: in bit; + IPAD86: in bit; + IPAD9: in bit; + IPAD91: in bit; + IPAD96: in bit; + J1: inout bit; -- PAD270 + J12: inout bit; -- PAD110 + J13: inout bit; -- PAD109 + J14: inout bit; -- PAD112 + J15: inout bit; -- PAD113 + J16: inout bit; -- PAD114 + J17: inout bit; -- PAD115 + J2: inout bit; -- PAD269 + J4: inout bit; -- PAD271 + J5: inout bit; -- PAD272 + K12: inout bit; -- PAD119 + K13: inout bit; -- PAD120 + K14: inout bit; -- PAD117 + K15: inout bit; -- PAD118 + K3: inout bit; -- PAD267 + K4: inout bit; -- PAD266 + K5: inout bit; -- PAD264 + K6: inout bit; -- PAD265 + L1: inout bit; -- PAD262 + L15: inout bit; -- PAD124 + L16: inout bit; -- PAD125 + L17: inout bit; -- PAD122 + L18: inout bit; -- PAD123 + L2: inout bit; -- PAD261 + L3: inout bit; -- PAD260 + L4: inout bit; -- PAD259 + L5: inout bit; -- PAD256 + L6: inout bit; -- PAD257 + M10: inout bit; -- PAD186 + M13: inout bit; -- PAD134 + M14: inout bit; -- PAD135 + M15: inout bit; -- PAD130 + M16: inout bit; -- PAD129 + M18: inout bit; -- PAD127 + M3: inout bit; -- PAD254 + M4: inout bit; -- PAD255 + M5: inout bit; -- PAD252 + M6: inout bit; -- PAD251 + M9: inout bit; -- PAD195 + N10: inout bit; -- PAD185 + N11: inout bit; -- PAD181 + N12: inout bit; -- PAD171 + N14: inout bit; -- PAD139 + N15: inout bit; -- PAD140 + N18: inout bit; -- PAD128 + N4: inout bit; -- PAD250 + N5: inout bit; -- PAD249 + N7: inout bit; -- PAD208 + N8: inout bit; -- PAD202 + N9: inout bit; -- PAD196 + P1: inout bit; -- PAD244 + P10: inout bit; -- PAD188 + P11: inout bit; -- PAD182 + P12: inout bit; -- PAD170 + P13: inout bit; -- PAD167 + P16: inout bit; -- PAD142 + P17: inout bit; -- PAD133 + P18: inout bit; -- PAD132 + P2: inout bit; -- PAD245 + P3: inout bit; -- PAD242 + P4: inout bit; -- PAD241 + P6: inout bit; -- PAD214 + P7: inout bit; -- PAD207 + P8: inout bit; -- PAD203 + P9: inout bit; -- PAD201 + PROG_B: in bit; + PUDC_B: in bit; -- PAD1 + R10: inout bit; -- PAD189 + R11: inout bit; -- PAD180 + R12: inout bit; -- PAD173 + R13: inout bit; -- PAD166 + R14: inout bit; -- PAD159 + R15: inout bit; -- PAD147 + R16: inout bit; -- PAD146 + R18: inout bit; -- PAD150 + R2: inout bit; -- PAD234 + R3: inout bit; -- PAD235 + R5: inout bit; -- PAD222 + R6: inout bit; -- PAD215 + R8: inout bit; -- PAD200 + R9: inout bit; -- PAD194 + T1: inout bit; -- PAD232 + T12: inout bit; -- PAD174 + T14: inout bit; -- PAD160 + T15: inout bit; -- PAD158 + T16: inout bit; -- PAD154 + T17: inout bit; -- PAD151 + T18: inout bit; -- PAD149 + T2: inout bit; -- PAD233 + T3: inout bit; -- PAD228 + T4: inout bit; -- PAD224 + T5: inout bit; -- PAD221 + T8: inout bit; -- PAD199 + TCK: in bit; + TDI: in bit; + TDO: out bit; + TMS: in bit; + U13: inout bit; -- PAD172 + U15: inout bit; -- PAD156 + U16: inout bit; -- PAD153 + U18: inout bit; -- PAD152 + U3: inout bit; -- PAD229 + U4: inout bit; -- PAD225 + U5: inout bit; -- PAD223 + U6: inout bit; -- PAD209 + U9: inout bit; -- PAD193 + V11: inout bit; -- PAD187 + V12: inout bit; -- PAD179 + V13: inout bit; -- PAD178 + V15: inout bit; -- PAD157 + V5: inout bit; -- PAD211 + V6: inout bit; -- PAD210 + V7: inout bit; -- PAD206 + V9: inout bit; -- PAD192 + VCCAUX: linkage bit_vector (1 to 8); + VCCINT: linkage bit_vector (1 to 8); + VCCO_0: linkage bit_vector (1 to 5); + VCCO_1: linkage bit_vector (1 to 5); + VCCO_2: linkage bit_vector (1 to 5); + VCCO_3: linkage bit_vector (1 to 5) +); --end port list + +-- Use Statements + +use STD_1149_1_2001.all; +use STD_1532_2002.all; + +-- Component Conformance Statement(s) + +attribute COMPONENT_CONFORMANCE of XC3S1200E_FG320 : entity is + "STD_1149_1_2001"; + +-- Device Package Pin Mappings + +attribute PIN_MAP of XC3S1200E_FG320 : entity is PHYSICAL_PIN_MAP; + +constant FG320: PIN_MAP_STRING:= + "A10:A10," & + "A11:A11," & + "A12:A12," & + "A13:A13," & + "A14:A14," & + "A16:A16," & + "A4:A4," & + "A6:A6," & + "A7:A7," & + "A8:A8," & + "B10:B10," & + "B11:B11," & + "B13:B13," & + "B14:B14," & + "B16:B16," & + "B4:B4," & + "B6:B6," & + "C1:C1," & + "C11:C11," & + "C14:C14," & + "C17:C17," & + "C18:C18," & + "C2:C2," & + "C3:C3," & + "C4:C4," & + "C5:C5," & + "C7:C7," & + "C9:C9," & + "D1:D1," & + "D10:D10," & + "D11:D11," & + "D13:D13," & + "D14:D14," & + "D16:D16," & + "D17:D17," & + "D2:D2," & + "D4:D4," & + "D5:D5," & + "D6:D6," & + "D7:D7," & + "D9:D9," & + "DONE:V17," & + "E1:E1," & + "E10:E10," & + "E11:E11," & + "E12:E12," & + "E13:E13," & + "E15:E15," & + "E16:E16," & + "E2:E2," & + "E3:E3," & + "E4:E4," & + "E6:E6," & + "E7:E7," & + "E8:E8," & + "E9:E9," & + "F1:F1," & + "F11:F11," & + "F12:F12," & + "F14:F14," & + "F15:F15," & + "F17:F17," & + "F18:F18," & + "F2:F2," & + "F7:F7," & + "F8:F8," & + "F9:F9," & + "G13:G13," & + "G14:G14," & + "G15:G15," & + "G16:G16," & + "G3:G3," & + "G4:G4," & + "G5:G5," & + "G6:G6," & + "G9:G9," & + "GND:(A1,A18,B2,B17,C10,G7,G12,H8,H9,H10," & + "H11,J3,J8,J11,K8,K11,K16,L8,L9,L10," & + "L11,M7,M12,T9,U2,U17,V1,V18)," & + "H1:H1," & + "H14:H14," & + "H15:H15," & + "H16:H16," & + "H17:H17," & + "H2:H2," & + "H3:H3," & + "H4:H4," & + "H5:H5," & + "H6:H6," & + "IPAD10:A5," & + "IPAD101:H13," & + "IPAD106:G18," & + "IPAD111:H18," & + "IPAD116:K18," & + "IPAD121:K17," & + "IPAD126:L13," & + "IPAD131:L14," & + "IPAD136:N17," & + "IPAD141:P15," & + "IPAD148:R17," & + "IPAD155:V16," & + "IPAD161:U14," & + "IPAD162:V14," & + "IPAD183:U11," & + "IPAD184:T11," & + "IPAD190:T10," & + "IPAD191:U10," & + "IPAD197:V8," & + "IPAD198:U8," & + "IPAD204:R7," & + "IPAD205:T7," & + "IPAD226:V3," & + "IPAD227:V4," & + "IPAD230:V2," & + "IPAD231:U1," & + "IPAD238:R1," & + "IPAD243:R4," & + "IPAD248:N2," & + "IPAD253:N1," & + "IPAD258:M1," & + "IPAD263:K7," & + "IPAD268:K2," & + "IPAD273:J6," & + "IPAD278:J7," & + "IPAD283:G1," & + "IPAD288:F5," & + "IPAD293:F4," & + "IPAD3:A3," & + "IPAD300:D3," & + "IPAD31:D8," & + "IPAD32:C8," & + "IPAD38:B9," & + "IPAD39:B8," & + "IPAD45:G10," & + "IPAD46:F10," & + "IPAD52:D12," & + "IPAD53:C12," & + "IPAD74:A15," & + "IPAD75:B15," & + "IPAD78:C15," & + "IPAD79:B18," & + "IPAD86:D18," & + "IPAD9:B5," & + "IPAD91:E17," & + "IPAD96:E18," & + "J1:J1," & + "J12:J12," & + "J13:J13," & + "J14:J14," & + "J15:J15," & + "J16:J16," & + "J17:J17," & + "J2:J2," & + "J4:J4," & + "J5:J5," & + "K12:K12," & + "K13:K13," & + "K14:K14," & + "K15:K15," & + "K3:K3," & + "K4:K4," & + "K5:K5," & + "K6:K6," & + "L1:L1," & + "L15:L15," & + "L16:L16," & + "L17:L17," & + "L18:L18," & + "L2:L2," & + "L3:L3," & + "L4:L4," & + "L5:L5," & + "L6:L6," & + "M10:M10," & + "M13:M13," & + "M14:M14," & + "M15:M15," & + "M16:M16," & + "M18:M18," & + "M3:M3," & + "M4:M4," & + "M5:M5," & + "M6:M6," & + "M9:M9," & + "N10:N10," & + "N11:N11," & + "N12:N12," & + "N14:N14," & + "N15:N15," & + "N18:N18," & + "N4:N4," & + "N5:N5," & + "N7:N7," & + "N8:N8," & + "N9:N9," & + "P1:P1," & + "P10:P10," & + "P11:P11," & + "P12:P12," & + "P13:P13," & + "P16:P16," & + "P17:P17," & + "P18:P18," & + "P2:P2," & + "P3:P3," & + "P4:P4," & + "P6:P6," & + "P7:P7," & + "P8:P8," & + "P9:P9," & + "PROG_B:B1," & + "PUDC_B:B3," & + "R10:R10," & + "R11:R11," & + "R12:R12," & + "R13:R13," & + "R14:R14," & + "R15:R15," & + "R16:R16," & + "R18:R18," & + "R2:R2," & + "R3:R3," & + "R5:R5," & + "R6:R6," & + "R8:R8," & + "R9:R9," & + "T1:T1," & + "T12:T12," & + "T14:T14," & + "T15:T15," & + "T16:T16," & + "T17:T17," & + "T18:T18," & + "T2:T2," & + "T3:T3," & + "T4:T4," & + "T5:T5," & + "T8:T8," & + "TCK:A17," & + "TDI:A2," & + "TDO:C16," & + "TMS:D15," & + "U13:U13," & + "U15:U15," & + "U16:U16," & + "U18:U18," & + "U3:U3," & + "U4:U4," & + "U5:U5," & + "U6:U6," & + "U9:U9," & + "V11:V11," & + "V12:V12," & + "V13:V13," & + "V15:V15," & + "V5:V5," & + "V6:V6," & + "V7:V7," & + "V9:V9," & + "VCCAUX:(B7,B12,G2,G17,M2,M17,U7,U12)," & + "VCCINT:(E5,E14,F6,F13,N6,N13,P5,P14)," & + "VCCO_0:(A9,C6,C13,G8,G11)," & + "VCCO_1:(F16,H12,J18,L12,N16)," & + "VCCO_2:(M8,M11,T6,T13,V10)," & + "VCCO_3:(F3,H7,K1,L7,N3)"; + + +-- Scan Port Identification + +attribute TAP_SCAN_OUT of TDO : signal is true; +attribute TAP_SCAN_IN of TDI : signal is true; +attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both); +attribute TAP_SCAN_MODE of TMS : signal is true; + +-- Compliance-Enable Description + +attribute COMPLIANCE_PATTERNS of XC3S1200E_FG320 : entity is + "(PROG_B, PUDC_B) (10)"; + +-- Instruction Register Description + +attribute INSTRUCTION_LENGTH of XC3S1200E_FG320 : entity is 6; + +attribute INSTRUCTION_OPCODE of XC3S1200E_FG320 : entity is + + "EXTEST (001111)," & + "SAMPLE (000001)," & + "PRELOAD (000001)," & -- Same as SAMPLE + "USER1 (000010)," & -- Not available until after configuration + "USER2 (000011)," & -- Not available until after configuration + "CFG_OUT (000100)," & -- Not available during configuration with another mode. + "CFG_IN (000101)," & -- Not available during configuration with another mode. + "INTEST (000111)," & + "USERCODE (001000)," & + "IDCODE (001001)," & + "HIGHZ (001010)," & + "JPROGRAM (001011)," & -- Not available during configuration with another mode. + "JSTART (001100)," & -- Not available during configuration with another mode. + "JSHUTDOWN (001101)," & -- Not available during configuration with another mode. + "BYPASS (111111)," & + "ISC_ENABLE (010000)," & + "ISC_PROGRAM (010001)," & + "ISC_NOOP (010100)," & + "ISC_READ (010101)," & + "ISC_DISABLE (010110)"; + +attribute INSTRUCTION_CAPTURE of XC3S1200E_FG320 : entity is +-- Bit 5 is 1 when DONE is released (part of startup sequence) +-- Bit 4 is 1 if house-cleaning is complete +-- Bit 3 is ISC_Enabled +-- Bit 2 is ISC_Done + "XXXX01" ; + +attribute INSTRUCTION_PRIVATE of XC3S1200E_FG320 : entity is + "USER1," & + "USER2," & + "CFG_OUT," & + "CFG_IN," & + "JPROGRAM," & + "JSTART," & + "JSHUTDOWN," & + "ISC_ENABLE," & + "ISC_PROGRAM," & + "ISC_NOOP," & + "ISC_READ," & + "ISC_DISABLE"; + +-- Optional Register Description + +attribute IDCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXX" & -- version + "0001110" & -- family + "000101110" & -- array size + "00001001001" & -- manufacturer + "1"; -- required by 1149.1 + + +attribute USERCODE_REGISTER of XC3S1200E_FG320 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + +-- Register Access Description + +attribute REGISTER_ACCESS of XC3S1200E_FG320 : entity is + "TEST1[8] (USER1)," & + "TEST2[16] (USER2)," & + "DEVICE_ID (USERCODE,IDCODE)," & + "BYPASS (BYPASS,HIGHZ,JPROGRAM,JSTART,JSHUTDOWN)," & + "CFG_DATA[3838752] (CFG_IN)," & + "ISC_PDATA[16] (ISC_PROGRAM),"& + "ISC_RDATA[16] (ISC_READ),"& + "ISC_DEFAULT[5] (ISC_NOOP)," & + "ISC_CONFIG[5] (ISC_ENABLE,ISC_DISABLE)," & + "BOUNDARY (EXTEST, SAMPLE, PRELOAD, INTEST)"; + +-- Boundary-Scan Register Description + +attribute BOUNDARY_LENGTH of XC3S1200E_FG320 : entity is 772; + +attribute BOUNDARY_REGISTER of XC3S1200E_FG320 : entity is +-- cellnum (type, port, function, safe[, ccell, disval, disrslt]) + " 771 (BC_2, IPAD79, input, X)," & + " 770 (BC_2, C17, input, X)," & -- PAD80 + " 769 (BC_2, C17, output3, X, 768, 1, PULL1)," & -- PAD80 + " 768 (BC_2, *, controlr, 1)," & + " 767 (BC_2, C18, input, X)," & -- PAD81 + " 766 (BC_2, C18, output3, X, 765, 1, PULL1)," & -- PAD81 + " 765 (BC_2, *, controlr, 1)," & + " 764 (BC_2, D16, input, X)," & -- PAD82 + " 763 (BC_2, D16, output3, X, 762, 1, PULL1)," & -- PAD82 + " 762 (BC_2, *, controlr, 1)," & + " 761 (BC_2, D17, input, X)," & -- PAD83 + " 760 (BC_2, D17, output3, X, 759, 1, PULL1)," & -- PAD83 + " 759 (BC_2, *, controlr, 1)," & + " 758 (BC_2, E16, input, X)," & -- PAD84 + " 757 (BC_2, E16, output3, X, 756, 1, PULL1)," & -- PAD84 + " 756 (BC_2, *, controlr, 1)," & + " 755 (BC_2, E15, input, X)," & -- PAD85 + " 754 (BC_2, E15, output3, X, 753, 1, PULL1)," & -- PAD85 + " 753 (BC_2, *, controlr, 1)," & + " 752 (BC_2, IPAD86, input, X)," & + " 751 (BC_2, *, internal, X)," & -- PAD87.I + " 750 (BC_2, *, internal, X)," & -- PAD87.O + " 749 (BC_2, *, internal, 1)," & -- PAD87.T + " 748 (BC_2, *, internal, X)," & -- PAD88.I + " 747 (BC_2, *, internal, X)," & -- PAD88.O + " 746 (BC_2, *, internal, 1)," & -- PAD88.T + " 745 (BC_2, *, internal, X)," & -- PAD89.I + " 744 (BC_2, *, internal, X)," & -- PAD89.O + " 743 (BC_2, *, internal, 1)," & -- PAD89.T + " 742 (BC_2, *, internal, X)," & -- PAD90.I + " 741 (BC_2, *, internal, X)," & -- PAD90.O + " 740 (BC_2, *, internal, 1)," & -- PAD90.T + " 739 (BC_2, IPAD91, input, X)," & + " 738 (BC_2, F14, input, X)," & -- PAD92 + " 737 (BC_2, F14, output3, X, 736, 1, PULL1)," & -- PAD92 + " 736 (BC_2, *, controlr, 1)," & + " 735 (BC_2, F15, input, X)," & -- PAD93 + " 734 (BC_2, F15, output3, X, 733, 1, PULL1)," & -- PAD93 + " 733 (BC_2, *, controlr, 1)," & + " 732 (BC_2, *, internal, X)," & -- PAD94.I + " 731 (BC_2, *, internal, X)," & -- PAD94.O + " 730 (BC_2, *, internal, 1)," & -- PAD94.T + " 729 (BC_2, *, internal, X)," & -- PAD95.I + " 728 (BC_2, *, internal, X)," & -- PAD95.O + " 727 (BC_2, *, internal, 1)," & -- PAD95.T + " 726 (BC_2, IPAD96, input, X)," & + " 725 (BC_2, G13, input, X)," & -- PAD97 + " 724 (BC_2, G13, output3, X, 723, 1, PULL1)," & -- PAD97 + " 723 (BC_2, *, controlr, 1)," & + " 722 (BC_2, G14, input, X)," & -- PAD98 + " 721 (BC_2, G14, output3, X, 720, 1, PULL1)," & -- PAD98 + " 720 (BC_2, *, controlr, 1)," & + " 719 (BC_2, F17, input, X)," & -- PAD99 + " 718 (BC_2, F17, output3, X, 717, 1, PULL1)," & -- PAD99 + " 717 (BC_2, *, controlr, 1)," & + " 716 (BC_2, F18, input, X)," & -- PAD100 + " 715 (BC_2, F18, output3, X, 714, 1, PULL1)," & -- PAD100 + " 714 (BC_2, *, controlr, 1)," & + " 713 (BC_2, IPAD101, input, X)," & + " 712 (BC_2, G16, input, X)," & -- PAD102 + " 711 (BC_2, G16, output3, X, 710, 1, PULL1)," & -- PAD102 + " 710 (BC_2, *, controlr, 1)," & + " 709 (BC_2, G15, input, X)," & -- PAD103 + " 708 (BC_2, G15, output3, X, 707, 1, PULL1)," & -- PAD103 + " 707 (BC_2, *, controlr, 1)," & + " 706 (BC_2, H15, input, X)," & -- PAD104 + " 705 (BC_2, H15, output3, X, 704, 1, PULL1)," & -- PAD104 + " 704 (BC_2, *, controlr, 1)," & + " 703 (BC_2, H14, input, X)," & -- PAD105 + " 702 (BC_2, H14, output3, X, 701, 1, PULL1)," & -- PAD105 + " 701 (BC_2, *, controlr, 1)," & + " 700 (BC_2, IPAD106, input, X)," & + " 699 (BC_2, H17, input, X)," & -- PAD107 + " 698 (BC_2, H17, output3, X, 697, 1, PULL1)," & -- PAD107 + " 697 (BC_2, *, controlr, 1)," & + " 696 (BC_2, H16, input, X)," & -- PAD108 + " 695 (BC_2, H16, output3, X, 694, 1, PULL1)," & -- PAD108 + " 694 (BC_2, *, controlr, 1)," & + " 693 (BC_2, J13, input, X)," & -- PAD109 + " 692 (BC_2, J13, output3, X, 691, 1, PULL1)," & -- PAD109 + " 691 (BC_2, *, controlr, 1)," & + " 690 (BC_2, J12, input, X)," & -- PAD110 + " 689 (BC_2, J12, output3, X, 688, 1, PULL1)," & -- PAD110 + " 688 (BC_2, *, controlr, 1)," & + " 687 (BC_2, IPAD111, input, X)," & + " 686 (BC_2, J14, input, X)," & -- PAD112 + " 685 (BC_2, J14, output3, X, 684, 1, PULL1)," & -- PAD112 + " 684 (BC_2, *, controlr, 1)," & + " 683 (BC_2, J15, input, X)," & -- PAD113 + " 682 (BC_2, J15, output3, X, 681, 1, PULL1)," & -- PAD113 + " 681 (BC_2, *, controlr, 1)," & + " 680 (BC_2, J16, input, X)," & -- PAD114 + " 679 (BC_2, J16, output3, X, 678, 1, PULL1)," & -- PAD114 + " 678 (BC_2, *, controlr, 1)," & + " 677 (BC_2, J17, input, X)," & -- PAD115 + " 676 (BC_2, J17, output3, X, 675, 1, PULL1)," & -- PAD115 + " 675 (BC_2, *, controlr, 1)," & + " 674 (BC_2, IPAD116, input, X)," & + " 673 (BC_2, K14, input, X)," & -- PAD117 + " 672 (BC_2, K14, output3, X, 671, 1, PULL1)," & -- PAD117 + " 671 (BC_2, *, controlr, 1)," & + " 670 (BC_2, K15, input, X)," & -- PAD118 + " 669 (BC_2, K15, output3, X, 668, 1, PULL1)," & -- PAD118 + " 668 (BC_2, *, controlr, 1)," & + " 667 (BC_2, K12, input, X)," & -- PAD119 + " 666 (BC_2, K12, output3, X, 665, 1, PULL1)," & -- PAD119 + " 665 (BC_2, *, controlr, 1)," & + " 664 (BC_2, K13, input, X)," & -- PAD120 + " 663 (BC_2, K13, output3, X, 662, 1, PULL1)," & -- PAD120 + " 662 (BC_2, *, controlr, 1)," & + " 661 (BC_2, IPAD121, input, X)," & + " 660 (BC_2, L17, input, X)," & -- PAD122 + " 659 (BC_2, L17, output3, X, 658, 1, PULL1)," & -- PAD122 + " 658 (BC_2, *, controlr, 1)," & + " 657 (BC_2, L18, input, X)," & -- PAD123 + " 656 (BC_2, L18, output3, X, 655, 1, PULL1)," & -- PAD123 + " 655 (BC_2, *, controlr, 1)," & + " 654 (BC_2, L15, input, X)," & -- PAD124 + " 653 (BC_2, L15, output3, X, 652, 1, PULL1)," & -- PAD124 + " 652 (BC_2, *, controlr, 1)," & + " 651 (BC_2, L16, input, X)," & -- PAD125 + " 650 (BC_2, L16, output3, X, 649, 1, PULL1)," & -- PAD125 + " 649 (BC_2, *, controlr, 1)," & + " 648 (BC_2, IPAD126, input, X)," & + " 647 (BC_2, M18, input, X)," & -- PAD127 + " 646 (BC_2, M18, output3, X, 645, 1, PULL1)," & -- PAD127 + " 645 (BC_2, *, controlr, 1)," & + " 644 (BC_2, N18, input, X)," & -- PAD128 + " 643 (BC_2, N18, output3, X, 642, 1, PULL1)," & -- PAD128 + " 642 (BC_2, *, controlr, 1)," & + " 641 (BC_2, M16, input, X)," & -- PAD129 + " 640 (BC_2, M16, output3, X, 639, 1, PULL1)," & -- PAD129 + " 639 (BC_2, *, controlr, 1)," & + " 638 (BC_2, M15, input, X)," & -- PAD130 + " 637 (BC_2, M15, output3, X, 636, 1, PULL1)," & -- PAD130 + " 636 (BC_2, *, controlr, 1)," & + " 635 (BC_2, IPAD131, input, X)," & + " 634 (BC_2, P18, input, X)," & -- PAD132 + " 633 (BC_2, P18, output3, X, 632, 1, PULL1)," & -- PAD132 + " 632 (BC_2, *, controlr, 1)," & + " 631 (BC_2, P17, input, X)," & -- PAD133 + " 630 (BC_2, P17, output3, X, 629, 1, PULL1)," & -- PAD133 + " 629 (BC_2, *, controlr, 1)," & + " 628 (BC_2, M13, input, X)," & -- PAD134 + " 627 (BC_2, M13, output3, X, 626, 1, PULL1)," & -- PAD134 + " 626 (BC_2, *, controlr, 1)," & + " 625 (BC_2, M14, input, X)," & -- PAD135 + " 624 (BC_2, M14, output3, X, 623, 1, PULL1)," & -- PAD135 + " 623 (BC_2, *, controlr, 1)," & + " 622 (BC_2, IPAD136, input, X)," & + " 621 (BC_2, *, internal, X)," & -- PAD137.I + " 620 (BC_2, *, internal, X)," & -- PAD137.O + " 619 (BC_2, *, internal, 1)," & -- PAD137.T + " 618 (BC_2, *, internal, X)," & -- PAD138.I + " 617 (BC_2, *, internal, X)," & -- PAD138.O + " 616 (BC_2, *, internal, 1)," & -- PAD138.T + " 615 (BC_2, N14, input, X)," & -- PAD139 + " 614 (BC_2, N14, output3, X, 613, 1, PULL1)," & -- PAD139 + " 613 (BC_2, *, controlr, 1)," & + " 612 (BC_2, N15, input, X)," & -- PAD140 + " 611 (BC_2, N15, output3, X, 610, 1, PULL1)," & -- PAD140 + " 610 (BC_2, *, controlr, 1)," & + " 609 (BC_2, IPAD141, input, X)," & + " 608 (BC_2, P16, input, X)," & -- PAD142 + " 607 (BC_2, P16, output3, X, 606, 1, PULL1)," & -- PAD142 + " 606 (BC_2, *, controlr, 1)," & + " 605 (BC_2, *, internal, X)," & -- PAD143.I + " 604 (BC_2, *, internal, X)," & -- PAD143.O + " 603 (BC_2, *, internal, 1)," & -- PAD143.T + " 602 (BC_2, *, internal, X)," & -- PAD144.I + " 601 (BC_2, *, internal, X)," & -- PAD144.O + " 600 (BC_2, *, internal, 1)," & -- PAD144.T + " 599 (BC_2, *, internal, X)," & -- PAD145.I + " 598 (BC_2, *, internal, X)," & -- PAD145.O + " 597 (BC_2, *, internal, 1)," & -- PAD145.T + " 596 (BC_2, R16, input, X)," & -- PAD146 + " 595 (BC_2, R16, output3, X, 594, 1, PULL1)," & -- PAD146 + " 594 (BC_2, *, controlr, 1)," & + " 593 (BC_2, R15, input, X)," & -- PAD147 + " 592 (BC_2, R15, output3, X, 591, 1, PULL1)," & -- PAD147 + " 591 (BC_2, *, controlr, 1)," & + " 590 (BC_2, IPAD148, input, X)," & + " 589 (BC_2, T18, input, X)," & -- PAD149 + " 588 (BC_2, T18, output3, X, 587, 1, PULL1)," & -- PAD149 + " 587 (BC_2, *, controlr, 1)," & + " 586 (BC_2, R18, input, X)," & -- PAD150 + " 585 (BC_2, R18, output3, X, 584, 1, PULL1)," & -- PAD150 + " 584 (BC_2, *, controlr, 1)," & + " 583 (BC_2, T17, input, X)," & -- PAD151 + " 582 (BC_2, T17, output3, X, 581, 1, PULL1)," & -- PAD151 + " 581 (BC_2, *, controlr, 1)," & + " 580 (BC_2, U18, input, X)," & -- PAD152 + " 579 (BC_2, U18, output3, X, 578, 1, PULL1)," & -- PAD152 + " 578 (BC_2, *, controlr, 1)," & + " 577 (BC_2, DONE, input, X)," & + " 576 (BC_2, DONE, output3, X, 575, 1, PULL1)," & + " 575 (BC_2, *, controlr, 1)," & + " 574 (BC_2, U16, input, X)," & -- PAD153 + " 573 (BC_2, U16, output3, X, 572, 1, PULL1)," & -- PAD153 + " 572 (BC_2, *, controlr, 1)," & + " 571 (BC_2, T16, input, X)," & -- PAD154 + " 570 (BC_2, T16, output3, X, 569, 1, PULL1)," & -- PAD154 + " 569 (BC_2, *, controlr, 1)," & + " 568 (BC_2, IPAD155, input, X)," & + " 567 (BC_2, U15, input, X)," & -- PAD156 + " 566 (BC_2, U15, output3, X, 565, 1, PULL1)," & -- PAD156 + " 565 (BC_2, *, controlr, 1)," & + " 564 (BC_2, V15, input, X)," & -- PAD157 + " 563 (BC_2, V15, output3, X, 562, 1, PULL1)," & -- PAD157 + " 562 (BC_2, *, controlr, 1)," & + " 561 (BC_2, T15, input, X)," & -- PAD158 + " 560 (BC_2, T15, output3, X, 559, 1, PULL1)," & -- PAD158 + " 559 (BC_2, *, controlr, 1)," & + " 558 (BC_2, R14, input, X)," & -- PAD159 + " 557 (BC_2, R14, output3, X, 556, 1, PULL1)," & -- PAD159 + " 556 (BC_2, *, controlr, 1)," & + " 555 (BC_2, T14, input, X)," & -- PAD160 + " 554 (BC_2, T14, output3, X, 553, 1, PULL1)," & -- PAD160 + " 553 (BC_2, *, controlr, 1)," & + " 552 (BC_2, IPAD161, input, X)," & + " 551 (BC_2, IPAD162, input, X)," & + " 550 (BC_2, *, internal, X)," & -- PAD163.I + " 549 (BC_2, *, internal, X)," & -- PAD163.O + " 548 (BC_2, *, internal, 1)," & -- PAD163.T + " 547 (BC_2, *, internal, X)," & -- PAD164.I + " 546 (BC_2, *, internal, X)," & -- PAD164.O + " 545 (BC_2, *, internal, 1)," & -- PAD164.T + " 544 (BC_2, *, internal, X)," & -- PAD165.I + " 543 (BC_2, *, internal, X)," & -- PAD165.O + " 542 (BC_2, *, internal, 1)," & -- PAD165.T + " 541 (BC_2, R13, input, X)," & -- PAD166 + " 540 (BC_2, R13, output3, X, 539, 1, PULL1)," & -- PAD166 + " 539 (BC_2, *, controlr, 1)," & + " 538 (BC_2, P13, input, X)," & -- PAD167 + " 537 (BC_2, P13, output3, X, 536, 1, PULL1)," & -- PAD167 + " 536 (BC_2, *, controlr, 1)," & + " 535 (BC_2, *, internal, X)," & -- IPAD168 + " 534 (BC_2, *, internal, X)," & -- IPAD169 + " 533 (BC_2, P12, input, X)," & -- PAD170 + " 532 (BC_2, P12, output3, X, 531, 1, PULL1)," & -- PAD170 + " 531 (BC_2, *, controlr, 1)," & + " 530 (BC_2, N12, input, X)," & -- PAD171 + " 529 (BC_2, N12, output3, X, 528, 1, PULL1)," & -- PAD171 + " 528 (BC_2, *, controlr, 1)," & + " 527 (BC_2, U13, input, X)," & -- PAD172 + " 526 (BC_2, U13, output3, X, 525, 1, PULL1)," & -- PAD172 + " 525 (BC_2, *, controlr, 1)," & + " 524 (BC_2, R12, input, X)," & -- PAD173 + " 523 (BC_2, R12, output3, X, 522, 1, PULL1)," & -- PAD173 + " 522 (BC_2, *, controlr, 1)," & + " 521 (BC_2, T12, input, X)," & -- PAD174 + " 520 (BC_2, T12, output3, X, 519, 1, PULL1)," & -- PAD174 + " 519 (BC_2, *, controlr, 1)," & + " 518 (BC_2, *, internal, X)," & -- IPAD175 + " 517 (BC_2, *, internal, X)," & -- IPAD176 + " 516 (BC_2, *, internal, X)," & -- PAD177.I + " 515 (BC_2, *, internal, X)," & -- PAD177.O + " 514 (BC_2, *, internal, 1)," & -- PAD177.T + " 513 (BC_2, V13, input, X)," & -- PAD178 + " 512 (BC_2, V13, output3, X, 511, 1, PULL1)," & -- PAD178 + " 511 (BC_2, *, controlr, 1)," & + " 510 (BC_2, V12, input, X)," & -- PAD179 + " 509 (BC_2, V12, output3, X, 508, 1, PULL1)," & -- PAD179 + " 508 (BC_2, *, controlr, 1)," & + " 507 (BC_2, R11, input, X)," & -- PAD180 + " 506 (BC_2, R11, output3, X, 505, 1, PULL1)," & -- PAD180 + " 505 (BC_2, *, controlr, 1)," & + " 504 (BC_2, N11, input, X)," & -- PAD181 + " 503 (BC_2, N11, output3, X, 502, 1, PULL1)," & -- PAD181 + " 502 (BC_2, *, controlr, 1)," & + " 501 (BC_2, P11, input, X)," & -- PAD182 + " 500 (BC_2, P11, output3, X, 499, 1, PULL1)," & -- PAD182 + " 499 (BC_2, *, controlr, 1)," & + " 498 (BC_2, IPAD183, input, X)," & + " 497 (BC_2, IPAD184, input, X)," & + " 496 (BC_2, N10, input, X)," & -- PAD185 + " 495 (BC_2, N10, output3, X, 494, 1, PULL1)," & -- PAD185 + " 494 (BC_2, *, controlr, 1)," & + " 493 (BC_2, M10, input, X)," & -- PAD186 + " 492 (BC_2, M10, output3, X, 491, 1, PULL1)," & -- PAD186 + " 491 (BC_2, *, controlr, 1)," & + " 490 (BC_2, V11, input, X)," & -- PAD187 + " 489 (BC_2, V11, output3, X, 488, 1, PULL1)," & -- PAD187 + " 488 (BC_2, *, controlr, 1)," & + " 487 (BC_2, P10, input, X)," & -- PAD188 + " 486 (BC_2, P10, output3, X, 485, 1, PULL1)," & -- PAD188 + " 485 (BC_2, *, controlr, 1)," & + " 484 (BC_2, R10, input, X)," & -- PAD189 + " 483 (BC_2, R10, output3, X, 482, 1, PULL1)," & -- PAD189 + " 482 (BC_2, *, controlr, 1)," & + " 481 (BC_2, IPAD190, input, X)," & + " 480 (BC_2, IPAD191, input, X)," & + " 479 (BC_2, V9, input, X)," & -- PAD192 + " 478 (BC_2, V9, output3, X, 477, 1, PULL1)," & -- PAD192 + " 477 (BC_2, *, controlr, 1)," & + " 476 (BC_2, U9, input, X)," & -- PAD193 + " 475 (BC_2, U9, output3, X, 474, 1, PULL1)," & -- PAD193 + " 474 (BC_2, *, controlr, 1)," & + " 473 (BC_2, R9, input, X)," & -- PAD194 + " 472 (BC_2, R9, output3, X, 471, 1, PULL1)," & -- PAD194 + " 471 (BC_2, *, controlr, 1)," & + " 470 (BC_2, M9, input, X)," & -- PAD195 + " 469 (BC_2, M9, output3, X, 468, 1, PULL1)," & -- PAD195 + " 468 (BC_2, *, controlr, 1)," & + " 467 (BC_2, N9, input, X)," & -- PAD196 + " 466 (BC_2, N9, output3, X, 465, 1, PULL1)," & -- PAD196 + " 465 (BC_2, *, controlr, 1)," & + " 464 (BC_2, IPAD197, input, X)," & + " 463 (BC_2, IPAD198, input, X)," & + " 462 (BC_2, T8, input, X)," & -- PAD199 + " 461 (BC_2, T8, output3, X, 460, 1, PULL1)," & -- PAD199 + " 460 (BC_2, *, controlr, 1)," & + " 459 (BC_2, R8, input, X)," & -- PAD200 + " 458 (BC_2, R8, output3, X, 457, 1, PULL1)," & -- PAD200 + " 457 (BC_2, *, controlr, 1)," & + " 456 (BC_2, P9, input, X)," & -- PAD201 + " 455 (BC_2, P9, output3, X, 454, 1, PULL1)," & -- PAD201 + " 454 (BC_2, *, controlr, 1)," & + " 453 (BC_2, N8, input, X)," & -- PAD202 + " 452 (BC_2, N8, output3, X, 451, 1, PULL1)," & -- PAD202 + " 451 (BC_2, *, controlr, 1)," & + " 450 (BC_2, P8, input, X)," & -- PAD203 + " 449 (BC_2, P8, output3, X, 448, 1, PULL1)," & -- PAD203 + " 448 (BC_2, *, controlr, 1)," & + " 447 (BC_2, IPAD204, input, X)," & + " 446 (BC_2, IPAD205, input, X)," & + " 445 (BC_2, V7, input, X)," & -- PAD206 + " 444 (BC_2, V7, output3, X, 443, 1, PULL1)," & -- PAD206 + " 443 (BC_2, *, controlr, 1)," & + " 442 (BC_2, P7, input, X)," & -- PAD207 + " 441 (BC_2, P7, output3, X, 440, 1, PULL1)," & -- PAD207 + " 440 (BC_2, *, controlr, 1)," & + " 439 (BC_2, N7, input, X)," & -- PAD208 + " 438 (BC_2, N7, output3, X, 437, 1, PULL1)," & -- PAD208 + " 437 (BC_2, *, controlr, 1)," & + " 436 (BC_2, U6, input, X)," & -- PAD209 + " 435 (BC_2, U6, output3, X, 434, 1, PULL1)," & -- PAD209 + " 434 (BC_2, *, controlr, 1)," & + " 433 (BC_2, V6, input, X)," & -- PAD210 + " 432 (BC_2, V6, output3, X, 431, 1, PULL1)," & -- PAD210 + " 431 (BC_2, *, controlr, 1)," & + " 430 (BC_2, V5, input, X)," & -- PAD211 + " 429 (BC_2, V5, output3, X, 428, 1, PULL1)," & -- PAD211 + " 428 (BC_2, *, controlr, 1)," & + " 427 (BC_2, *, internal, X)," & -- IPAD212 + " 426 (BC_2, *, internal, X)," & -- IPAD213 + " 425 (BC_2, P6, input, X)," & -- PAD214 + " 424 (BC_2, P6, output3, X, 423, 1, PULL1)," & -- PAD214 + " 423 (BC_2, *, controlr, 1)," & + " 422 (BC_2, R6, input, X)," & -- PAD215 + " 421 (BC_2, R6, output3, X, 420, 1, PULL1)," & -- PAD215 + " 420 (BC_2, *, controlr, 1)," & + " 419 (BC_2, *, internal, X)," & -- PAD216.I + " 418 (BC_2, *, internal, X)," & -- PAD216.O + " 417 (BC_2, *, internal, 1)," & -- PAD216.T + " 416 (BC_2, *, internal, X)," & -- PAD217.I + " 415 (BC_2, *, internal, X)," & -- PAD217.O + " 414 (BC_2, *, internal, 1)," & -- PAD217.T + " 413 (BC_2, *, internal, X)," & -- PAD218.I + " 412 (BC_2, *, internal, X)," & -- PAD218.O + " 411 (BC_2, *, internal, 1)," & -- PAD218.T + " 410 (BC_2, *, internal, X)," & -- IPAD219 + " 409 (BC_2, *, internal, X)," & -- IPAD220 + " 408 (BC_2, T5, input, X)," & -- PAD221 + " 407 (BC_2, T5, output3, X, 406, 1, PULL1)," & -- PAD221 + " 406 (BC_2, *, controlr, 1)," & + " 405 (BC_2, R5, input, X)," & -- PAD222 + " 404 (BC_2, R5, output3, X, 403, 1, PULL1)," & -- PAD222 + " 403 (BC_2, *, controlr, 1)," & + " 402 (BC_2, U5, input, X)," & -- PAD223 + " 401 (BC_2, U5, output3, X, 400, 1, PULL1)," & -- PAD223 + " 400 (BC_2, *, controlr, 1)," & + " 399 (BC_2, T4, input, X)," & -- PAD224 + " 398 (BC_2, T4, output3, X, 397, 1, PULL1)," & -- PAD224 + " 397 (BC_2, *, controlr, 1)," & + " 396 (BC_2, U4, input, X)," & -- PAD225 + " 395 (BC_2, U4, output3, X, 394, 1, PULL1)," & -- PAD225 + " 394 (BC_2, *, controlr, 1)," & + " 393 (BC_2, IPAD226, input, X)," & + " 392 (BC_2, IPAD227, input, X)," & + " 391 (BC_2, T3, input, X)," & -- PAD228 + " 390 (BC_2, T3, output3, X, 389, 1, PULL1)," & -- PAD228 + " 389 (BC_2, *, controlr, 1)," & + " 388 (BC_2, U3, input, X)," & -- PAD229 + " 387 (BC_2, U3, output3, X, 386, 1, PULL1)," & -- PAD229 + " 386 (BC_2, *, controlr, 1)," & + " 385 (BC_2, IPAD230, input, X)," & + " 384 (BC_2, IPAD231, input, X)," & + " 383 (BC_2, T1, input, X)," & -- PAD232 + " 382 (BC_2, T1, output3, X, 381, 1, PULL1)," & -- PAD232 + " 381 (BC_2, *, controlr, 1)," & + " 380 (BC_2, T2, input, X)," & -- PAD233 + " 379 (BC_2, T2, output3, X, 378, 1, PULL1)," & -- PAD233 + " 378 (BC_2, *, controlr, 1)," & + " 377 (BC_2, R2, input, X)," & -- PAD234 + " 376 (BC_2, R2, output3, X, 375, 1, PULL1)," & -- PAD234 + " 375 (BC_2, *, controlr, 1)," & + " 374 (BC_2, R3, input, X)," & -- PAD235 + " 373 (BC_2, R3, output3, X, 372, 1, PULL1)," & -- PAD235 + " 372 (BC_2, *, controlr, 1)," & + " 371 (BC_2, *, internal, X)," & -- PAD236.I + " 370 (BC_2, *, internal, X)," & -- PAD236.O + " 369 (BC_2, *, internal, 1)," & -- PAD236.T + " 368 (BC_2, *, internal, X)," & -- PAD237.I + " 367 (BC_2, *, internal, X)," & -- PAD237.O + " 366 (BC_2, *, internal, 1)," & -- PAD237.T + " 365 (BC_2, IPAD238, input, X)," & + " 364 (BC_2, *, internal, X)," & -- PAD239.I + " 363 (BC_2, *, internal, X)," & -- PAD239.O + " 362 (BC_2, *, internal, 1)," & -- PAD239.T + " 361 (BC_2, *, internal, X)," & -- PAD240.I + " 360 (BC_2, *, internal, X)," & -- PAD240.O + " 359 (BC_2, *, internal, 1)," & -- PAD240.T + " 358 (BC_2, P4, input, X)," & -- PAD241 + " 357 (BC_2, P4, output3, X, 356, 1, PULL1)," & -- PAD241 + " 356 (BC_2, *, controlr, 1)," & + " 355 (BC_2, P3, input, X)," & -- PAD242 + " 354 (BC_2, P3, output3, X, 353, 1, PULL1)," & -- PAD242 + " 353 (BC_2, *, controlr, 1)," & + " 352 (BC_2, IPAD243, input, X)," & + " 351 (BC_2, P1, input, X)," & -- PAD244 + " 350 (BC_2, P1, output3, X, 349, 1, PULL1)," & -- PAD244 + " 349 (BC_2, *, controlr, 1)," & + " 348 (BC_2, P2, input, X)," & -- PAD245 + " 347 (BC_2, P2, output3, X, 346, 1, PULL1)," & -- PAD245 + " 346 (BC_2, *, controlr, 1)," & + " 345 (BC_2, *, internal, X)," & -- PAD246.I + " 344 (BC_2, *, internal, X)," & -- PAD246.O + " 343 (BC_2, *, internal, 1)," & -- PAD246.T + " 342 (BC_2, *, internal, X)," & -- PAD247.I + " 341 (BC_2, *, internal, X)," & -- PAD247.O + " 340 (BC_2, *, internal, 1)," & -- PAD247.T + " 339 (BC_2, IPAD248, input, X)," & + " 338 (BC_2, N5, input, X)," & -- PAD249 + " 337 (BC_2, N5, output3, X, 336, 1, PULL1)," & -- PAD249 + " 336 (BC_2, *, controlr, 1)," & + " 335 (BC_2, N4, input, X)," & -- PAD250 + " 334 (BC_2, N4, output3, X, 333, 1, PULL1)," & -- PAD250 + " 333 (BC_2, *, controlr, 1)," & + " 332 (BC_2, M6, input, X)," & -- PAD251 + " 331 (BC_2, M6, output3, X, 330, 1, PULL1)," & -- PAD251 + " 330 (BC_2, *, controlr, 1)," & + " 329 (BC_2, M5, input, X)," & -- PAD252 + " 328 (BC_2, M5, output3, X, 327, 1, PULL1)," & -- PAD252 + " 327 (BC_2, *, controlr, 1)," & + " 326 (BC_2, IPAD253, input, X)," & + " 325 (BC_2, M3, input, X)," & -- PAD254 + " 324 (BC_2, M3, output3, X, 323, 1, PULL1)," & -- PAD254 + " 323 (BC_2, *, controlr, 1)," & + " 322 (BC_2, M4, input, X)," & -- PAD255 + " 321 (BC_2, M4, output3, X, 320, 1, PULL1)," & -- PAD255 + " 320 (BC_2, *, controlr, 1)," & + " 319 (BC_2, L5, input, X)," & -- PAD256 + " 318 (BC_2, L5, output3, X, 317, 1, PULL1)," & -- PAD256 + " 317 (BC_2, *, controlr, 1)," & + " 316 (BC_2, L6, input, X)," & -- PAD257 + " 315 (BC_2, L6, output3, X, 314, 1, PULL1)," & -- PAD257 + " 314 (BC_2, *, controlr, 1)," & + " 313 (BC_2, IPAD258, input, X)," & + " 312 (BC_2, L4, input, X)," & -- PAD259 + " 311 (BC_2, L4, output3, X, 310, 1, PULL1)," & -- PAD259 + " 310 (BC_2, *, controlr, 1)," & + " 309 (BC_2, L3, input, X)," & -- PAD260 + " 308 (BC_2, L3, output3, X, 307, 1, PULL1)," & -- PAD260 + " 307 (BC_2, *, controlr, 1)," & + " 306 (BC_2, L2, input, X)," & -- PAD261 + " 305 (BC_2, L2, output3, X, 304, 1, PULL1)," & -- PAD261 + " 304 (BC_2, *, controlr, 1)," & + " 303 (BC_2, L1, input, X)," & -- PAD262 + " 302 (BC_2, L1, output3, X, 301, 1, PULL1)," & -- PAD262 + " 301 (BC_2, *, controlr, 1)," & + " 300 (BC_2, IPAD263, input, X)," & + " 299 (BC_2, K5, input, X)," & -- PAD264 + " 298 (BC_2, K5, output3, X, 297, 1, PULL1)," & -- PAD264 + " 297 (BC_2, *, controlr, 1)," & + " 296 (BC_2, K6, input, X)," & -- PAD265 + " 295 (BC_2, K6, output3, X, 294, 1, PULL1)," & -- PAD265 + " 294 (BC_2, *, controlr, 1)," & + " 293 (BC_2, K4, input, X)," & -- PAD266 + " 292 (BC_2, K4, output3, X, 291, 1, PULL1)," & -- PAD266 + " 291 (BC_2, *, controlr, 1)," & + " 290 (BC_2, K3, input, X)," & -- PAD267 + " 289 (BC_2, K3, output3, X, 288, 1, PULL1)," & -- PAD267 + " 288 (BC_2, *, controlr, 1)," & + " 287 (BC_2, IPAD268, input, X)," & + " 286 (BC_2, J2, input, X)," & -- PAD269 + " 285 (BC_2, J2, output3, X, 284, 1, PULL1)," & -- PAD269 + " 284 (BC_2, *, controlr, 1)," & + " 283 (BC_2, J1, input, X)," & -- PAD270 + " 282 (BC_2, J1, output3, X, 281, 1, PULL1)," & -- PAD270 + " 281 (BC_2, *, controlr, 1)," & + " 280 (BC_2, J4, input, X)," & -- PAD271 + " 279 (BC_2, J4, output3, X, 278, 1, PULL1)," & -- PAD271 + " 278 (BC_2, *, controlr, 1)," & + " 277 (BC_2, J5, input, X)," & -- PAD272 + " 276 (BC_2, J5, output3, X, 275, 1, PULL1)," & -- PAD272 + " 275 (BC_2, *, controlr, 1)," & + " 274 (BC_2, IPAD273, input, X)," & + " 273 (BC_2, H1, input, X)," & -- PAD274 + " 272 (BC_2, H1, output3, X, 271, 1, PULL1)," & -- PAD274 + " 271 (BC_2, *, controlr, 1)," & + " 270 (BC_2, H2, input, X)," & -- PAD275 + " 269 (BC_2, H2, output3, X, 268, 1, PULL1)," & -- PAD275 + " 268 (BC_2, *, controlr, 1)," & + " 267 (BC_2, H3, input, X)," & -- PAD276 + " 266 (BC_2, H3, output3, X, 265, 1, PULL1)," & -- PAD276 + " 265 (BC_2, *, controlr, 1)," & + " 264 (BC_2, H4, input, X)," & -- PAD277 + " 263 (BC_2, H4, output3, X, 262, 1, PULL1)," & -- PAD277 + " 262 (BC_2, *, controlr, 1)," & + " 261 (BC_2, IPAD278, input, X)," & + " 260 (BC_2, H5, input, X)," & -- PAD279 + " 259 (BC_2, H5, output3, X, 258, 1, PULL1)," & -- PAD279 + " 258 (BC_2, *, controlr, 1)," & + " 257 (BC_2, H6, input, X)," & -- PAD280 + " 256 (BC_2, H6, output3, X, 255, 1, PULL1)," & -- PAD280 + " 255 (BC_2, *, controlr, 1)," & + " 254 (BC_2, G5, input, X)," & -- PAD281 + " 253 (BC_2, G5, output3, X, 252, 1, PULL1)," & -- PAD281 + " 252 (BC_2, *, controlr, 1)," & + " 251 (BC_2, G6, input, X)," & -- PAD282 + " 250 (BC_2, G6, output3, X, 249, 1, PULL1)," & -- PAD282 + " 249 (BC_2, *, controlr, 1)," & + " 248 (BC_2, IPAD283, input, X)," & + " 247 (BC_2, G4, input, X)," & -- PAD284 + " 246 (BC_2, G4, output3, X, 245, 1, PULL1)," & -- PAD284 + " 245 (BC_2, *, controlr, 1)," & + " 244 (BC_2, G3, input, X)," & -- PAD285 + " 243 (BC_2, G3, output3, X, 242, 1, PULL1)," & -- PAD285 + " 242 (BC_2, *, controlr, 1)," & + " 241 (BC_2, F2, input, X)," & -- PAD286 + " 240 (BC_2, F2, output3, X, 239, 1, PULL1)," & -- PAD286 + " 239 (BC_2, *, controlr, 1)," & + " 238 (BC_2, F1, input, X)," & -- PAD287 + " 237 (BC_2, F1, output3, X, 236, 1, PULL1)," & -- PAD287 + " 236 (BC_2, *, controlr, 1)," & + " 235 (BC_2, IPAD288, input, X)," & + " 234 (BC_2, *, internal, X)," & -- PAD289.I + " 233 (BC_2, *, internal, X)," & -- PAD289.O + " 232 (BC_2, *, internal, 1)," & -- PAD289.T + " 231 (BC_2, *, internal, X)," & -- PAD290.I + " 230 (BC_2, *, internal, X)," & -- PAD290.O + " 229 (BC_2, *, internal, 1)," & -- PAD290.T + " 228 (BC_2, E3, input, X)," & -- PAD291 + " 227 (BC_2, E3, output3, X, 226, 1, PULL1)," & -- PAD291 + " 226 (BC_2, *, controlr, 1)," & + " 225 (BC_2, E4, input, X)," & -- PAD292 + " 224 (BC_2, E4, output3, X, 223, 1, PULL1)," & -- PAD292 + " 223 (BC_2, *, controlr, 1)," & + " 222 (BC_2, IPAD293, input, X)," & + " 221 (BC_2, *, internal, X)," & -- PAD294.I + " 220 (BC_2, *, internal, X)," & -- PAD294.O + " 219 (BC_2, *, internal, 1)," & -- PAD294.T + " 218 (BC_2, *, internal, X)," & -- PAD295.I + " 217 (BC_2, *, internal, X)," & -- PAD295.O + " 216 (BC_2, *, internal, 1)," & -- PAD295.T + " 215 (BC_2, E1, input, X)," & -- PAD296 + " 214 (BC_2, E1, output3, X, 213, 1, PULL1)," & -- PAD296 + " 213 (BC_2, *, controlr, 1)," & + " 212 (BC_2, E2, input, X)," & -- PAD297 + " 211 (BC_2, E2, output3, X, 210, 1, PULL1)," & -- PAD297 + " 210 (BC_2, *, controlr, 1)," & + " 209 (BC_2, D4, input, X)," & -- PAD298 + " 208 (BC_2, D4, output3, X, 207, 1, PULL1)," & -- PAD298 + " 207 (BC_2, *, controlr, 1)," & + " 206 (BC_2, *, internal, X)," & -- PAD299.I + " 205 (BC_2, *, internal, X)," & -- PAD299.O + " 204 (BC_2, *, internal, 1)," & -- PAD299.T + " 203 (BC_2, IPAD300, input, X)," & + " 202 (BC_2, D2, input, X)," & -- PAD301 + " 201 (BC_2, D2, output3, X, 200, 1, PULL1)," & -- PAD301 + " 200 (BC_2, *, controlr, 1)," & + " 199 (BC_2, D1, input, X)," & -- PAD302 + " 198 (BC_2, D1, output3, X, 197, 1, PULL1)," & -- PAD302 + " 197 (BC_2, *, controlr, 1)," & + " 196 (BC_2, C2, input, X)," & -- PAD303 + " 195 (BC_2, C2, output3, X, 194, 1, PULL1)," & -- PAD303 + " 194 (BC_2, *, controlr, 1)," & + " 193 (BC_2, C1, input, X)," & -- PAD304 + " 192 (BC_2, C1, output3, X, 191, 1, PULL1)," & -- PAD304 + " 191 (BC_2, *, controlr, 1)," & + " 190 (BC_2, *, internal, 1)," & -- PROG_B + " 189 (BC_2, *, internal, 1)," & -- PUDC_B + " 188 (BC_2, *, internal, 1)," & -- PUDC_B + " 187 (BC_2, *, internal, 1)," & -- PUDC_B + " 186 (BC_2, C3, input, X)," & -- PAD2 + " 185 (BC_2, C3, output3, X, 184, 1, PULL1)," & -- PAD2 + " 184 (BC_2, *, controlr, 1)," & + " 183 (BC_2, IPAD3, input, X)," & + " 182 (BC_2, B4, input, X)," & -- PAD4 + " 181 (BC_2, B4, output3, X, 180, 1, PULL1)," & -- PAD4 + " 180 (BC_2, *, controlr, 1)," & + " 179 (BC_2, A4, input, X)," & -- PAD5 + " 178 (BC_2, A4, output3, X, 177, 1, PULL1)," & -- PAD5 + " 177 (BC_2, *, controlr, 1)," & + " 176 (BC_2, C4, input, X)," & -- PAD6 + " 175 (BC_2, C4, output3, X, 174, 1, PULL1)," & -- PAD6 + " 174 (BC_2, *, controlr, 1)," & + " 173 (BC_2, D5, input, X)," & -- PAD7 + " 172 (BC_2, D5, output3, X, 171, 1, PULL1)," & -- PAD7 + " 171 (BC_2, *, controlr, 1)," & + " 170 (BC_2, C5, input, X)," & -- PAD8 + " 169 (BC_2, C5, output3, X, 168, 1, PULL1)," & -- PAD8 + " 168 (BC_2, *, controlr, 1)," & + " 167 (BC_2, IPAD9, input, X)," & + " 166 (BC_2, IPAD10, input, X)," & + " 165 (BC_2, E6, input, X)," & -- PAD11 + " 164 (BC_2, E6, output3, X, 163, 1, PULL1)," & -- PAD11 + " 163 (BC_2, *, controlr, 1)," & + " 162 (BC_2, D6, input, X)," & -- PAD12 + " 161 (BC_2, D6, output3, X, 160, 1, PULL1)," & -- PAD12 + " 160 (BC_2, *, controlr, 1)," & + " 159 (BC_2, *, internal, X)," & -- PAD13.I + " 158 (BC_2, *, internal, X)," & -- PAD13.O + " 157 (BC_2, *, internal, 1)," & -- PAD13.T + " 156 (BC_2, A6, input, X)," & -- PAD14 + " 155 (BC_2, A6, output3, X, 154, 1, PULL1)," & -- PAD14 + " 154 (BC_2, *, controlr, 1)," & + " 153 (BC_2, B6, input, X)," & -- PAD15 + " 152 (BC_2, B6, output3, X, 151, 1, PULL1)," & -- PAD15 + " 151 (BC_2, *, controlr, 1)," & + " 150 (BC_2, *, internal, X)," & -- IPAD16 + " 149 (BC_2, *, internal, X)," & -- IPAD17 + " 148 (BC_2, *, internal, X)," & -- PAD18.I + " 147 (BC_2, *, internal, X)," & -- PAD18.O + " 146 (BC_2, *, internal, 1)," & -- PAD18.T + " 145 (BC_2, *, internal, X)," & -- PAD19.I + " 144 (BC_2, *, internal, X)," & -- PAD19.O + " 143 (BC_2, *, internal, 1)," & -- PAD19.T + " 142 (BC_2, A7, input, X)," & -- PAD20 + " 141 (BC_2, A7, output3, X, 140, 1, PULL1)," & -- PAD20 + " 140 (BC_2, *, controlr, 1)," & + " 139 (BC_2, E7, input, X)," & -- PAD21 + " 138 (BC_2, E7, output3, X, 137, 1, PULL1)," & -- PAD21 + " 137 (BC_2, *, controlr, 1)," & + " 136 (BC_2, F7, input, X)," & -- PAD22 + " 135 (BC_2, F7, output3, X, 134, 1, PULL1)," & -- PAD22 + " 134 (BC_2, *, controlr, 1)," & + " 133 (BC_2, *, internal, X)," & -- IPAD23 + " 132 (BC_2, *, internal, X)," & -- IPAD24 + " 131 (BC_2, *, internal, X)," & -- PAD25.I + " 130 (BC_2, *, internal, X)," & -- PAD25.O + " 129 (BC_2, *, internal, 1)," & -- PAD25.T + " 128 (BC_2, D7, input, X)," & -- PAD26 + " 127 (BC_2, D7, output3, X, 126, 1, PULL1)," & -- PAD26 + " 126 (BC_2, *, controlr, 1)," & + " 125 (BC_2, C7, input, X)," & -- PAD27 + " 124 (BC_2, C7, output3, X, 123, 1, PULL1)," & -- PAD27 + " 123 (BC_2, *, controlr, 1)," & + " 122 (BC_2, A8, input, X)," & -- PAD28 + " 121 (BC_2, A8, output3, X, 120, 1, PULL1)," & -- PAD28 + " 120 (BC_2, *, controlr, 1)," & + " 119 (BC_2, F8, input, X)," & -- PAD29 + " 118 (BC_2, F8, output3, X, 117, 1, PULL1)," & -- PAD29 + " 117 (BC_2, *, controlr, 1)," & + " 116 (BC_2, E8, input, X)," & -- PAD30 + " 115 (BC_2, E8, output3, X, 114, 1, PULL1)," & -- PAD30 + " 114 (BC_2, *, controlr, 1)," & + " 113 (BC_2, IPAD31, input, X)," & + " 112 (BC_2, IPAD32, input, X)," & + " 111 (BC_2, F9, input, X)," & -- PAD33 + " 110 (BC_2, F9, output3, X, 109, 1, PULL1)," & -- PAD33 + " 109 (BC_2, *, controlr, 1)," & + " 108 (BC_2, E9, input, X)," & -- PAD34 + " 107 (BC_2, E9, output3, X, 106, 1, PULL1)," & -- PAD34 + " 106 (BC_2, *, controlr, 1)," & + " 105 (BC_2, G9, input, X)," & -- PAD35 + " 104 (BC_2, G9, output3, X, 103, 1, PULL1)," & -- PAD35 + " 103 (BC_2, *, controlr, 1)," & + " 102 (BC_2, D9, input, X)," & -- PAD36 + " 101 (BC_2, D9, output3, X, 100, 1, PULL1)," & -- PAD36 + " 100 (BC_2, *, controlr, 1)," & + " 99 (BC_2, C9, input, X)," & -- PAD37 + " 98 (BC_2, C9, output3, X, 97, 1, PULL1)," & -- PAD37 + " 97 (BC_2, *, controlr, 1)," & + " 96 (BC_2, IPAD38, input, X)," & + " 95 (BC_2, IPAD39, input, X)," & + " 94 (BC_2, A10, input, X)," & -- PAD40 + " 93 (BC_2, A10, output3, X, 92, 1, PULL1)," & -- PAD40 + " 92 (BC_2, *, controlr, 1)," & + " 91 (BC_2, B10, input, X)," & -- PAD41 + " 90 (BC_2, B10, output3, X, 89, 1, PULL1)," & -- PAD41 + " 89 (BC_2, *, controlr, 1)," & + " 88 (BC_2, B11, input, X)," & -- PAD42 + " 87 (BC_2, B11, output3, X, 86, 1, PULL1)," & -- PAD42 + " 86 (BC_2, *, controlr, 1)," & + " 85 (BC_2, E10, input, X)," & -- PAD43 + " 84 (BC_2, E10, output3, X, 83, 1, PULL1)," & -- PAD43 + " 83 (BC_2, *, controlr, 1)," & + " 82 (BC_2, D10, input, X)," & -- PAD44 + " 81 (BC_2, D10, output3, X, 80, 1, PULL1)," & -- PAD44 + " 80 (BC_2, *, controlr, 1)," & + " 79 (BC_2, IPAD45, input, X)," & + " 78 (BC_2, IPAD46, input, X)," & + " 77 (BC_2, D11, input, X)," & -- PAD47 + " 76 (BC_2, D11, output3, X, 75, 1, PULL1)," & -- PAD47 + " 75 (BC_2, *, controlr, 1)," & + " 74 (BC_2, C11, input, X)," & -- PAD48 + " 73 (BC_2, C11, output3, X, 72, 1, PULL1)," & -- PAD48 + " 72 (BC_2, *, controlr, 1)," & + " 71 (BC_2, A11, input, X)," & -- PAD49 + " 70 (BC_2, A11, output3, X, 69, 1, PULL1)," & -- PAD49 + " 69 (BC_2, *, controlr, 1)," & + " 68 (BC_2, F11, input, X)," & -- PAD50 + " 67 (BC_2, F11, output3, X, 66, 1, PULL1)," & -- PAD50 + " 66 (BC_2, *, controlr, 1)," & + " 65 (BC_2, E11, input, X)," & -- PAD51 + " 64 (BC_2, E11, output3, X, 63, 1, PULL1)," & -- PAD51 + " 63 (BC_2, *, controlr, 1)," & + " 62 (BC_2, IPAD52, input, X)," & + " 61 (BC_2, IPAD53, input, X)," & + " 60 (BC_2, A12, input, X)," & -- PAD54 + " 59 (BC_2, A12, output3, X, 58, 1, PULL1)," & -- PAD54 + " 58 (BC_2, *, controlr, 1)," & + " 57 (BC_2, E12, input, X)," & -- PAD55 + " 56 (BC_2, E12, output3, X, 55, 1, PULL1)," & -- PAD55 + " 55 (BC_2, *, controlr, 1)," & + " 54 (BC_2, F12, input, X)," & -- PAD56 + " 53 (BC_2, F12, output3, X, 52, 1, PULL1)," & -- PAD56 + " 52 (BC_2, *, controlr, 1)," & + " 51 (BC_2, D13, input, X)," & -- PAD57 + " 50 (BC_2, D13, output3, X, 49, 1, PULL1)," & -- PAD57 + " 49 (BC_2, *, controlr, 1)," & + " 48 (BC_2, B13, input, X)," & -- PAD58 + " 47 (BC_2, B13, output3, X, 46, 1, PULL1)," & -- PAD58 + " 46 (BC_2, *, controlr, 1)," & + " 45 (BC_2, A13, input, X)," & -- PAD59 + " 44 (BC_2, A13, output3, X, 43, 1, PULL1)," & -- PAD59 + " 43 (BC_2, *, controlr, 1)," & + " 42 (BC_2, *, internal, X)," & -- IPAD60 + " 41 (BC_2, *, internal, X)," & -- IPAD61 + " 40 (BC_2, A14, input, X)," & -- PAD62 + " 39 (BC_2, A14, output3, X, 38, 1, PULL1)," & -- PAD62 + " 38 (BC_2, *, controlr, 1)," & + " 37 (BC_2, B14, input, X)," & -- PAD63 + " 36 (BC_2, B14, output3, X, 35, 1, PULL1)," & -- PAD63 + " 35 (BC_2, *, controlr, 1)," & + " 34 (BC_2, *, internal, X)," & -- PAD64.I + " 33 (BC_2, *, internal, X)," & -- PAD64.O + " 32 (BC_2, *, internal, 1)," & -- PAD64.T + " 31 (BC_2, *, internal, X)," & -- PAD65.I + " 30 (BC_2, *, internal, X)," & -- PAD65.O + " 29 (BC_2, *, internal, 1)," & -- PAD65.T + " 28 (BC_2, *, internal, X)," & -- PAD66.I + " 27 (BC_2, *, internal, X)," & -- PAD66.O + " 26 (BC_2, *, internal, 1)," & -- PAD66.T + " 25 (BC_2, *, internal, X)," & -- IPAD67 + " 24 (BC_2, *, internal, X)," & -- IPAD68 + " 23 (BC_2, *, internal, X)," & -- PAD69.I + " 22 (BC_2, *, internal, X)," & -- PAD69.O + " 21 (BC_2, *, internal, 1)," & -- PAD69.T + " 20 (BC_2, *, internal, X)," & -- PAD70.I + " 19 (BC_2, *, internal, X)," & -- PAD70.O + " 18 (BC_2, *, internal, 1)," & -- PAD70.T + " 17 (BC_2, E13, input, X)," & -- PAD71 + " 16 (BC_2, E13, output3, X, 15, 1, PULL1)," & -- PAD71 + " 15 (BC_2, *, controlr, 1)," & + " 14 (BC_2, C14, input, X)," & -- PAD72 + " 13 (BC_2, C14, output3, X, 12, 1, PULL1)," & -- PAD72 + " 12 (BC_2, *, controlr, 1)," & + " 11 (BC_2, D14, input, X)," & -- PAD73 + " 10 (BC_2, D14, output3, X, 9, 1, PULL1)," & -- PAD73 + " 9 (BC_2, *, controlr, 1)," & + " 8 (BC_2, IPAD74, input, X)," & + " 7 (BC_2, IPAD75, input, X)," & + " 6 (BC_2, A16, input, X)," & -- PAD76 + " 5 (BC_2, A16, output3, X, 4, 1, PULL1)," & -- PAD76 + " 4 (BC_2, *, controlr, 1)," & + " 3 (BC_2, B16, input, X)," & -- PAD77 + " 2 (BC_2, B16, output3, X, 1, 1, PULL1)," & -- PAD77 + " 1 (BC_2, *, controlr, 1)," & + " 0 (BC_2, IPAD78, input, X)"; + + +attribute ISC_PIN_BEHAVIOR of XC3S1200E_FG320 : entity is + "HIGHZ" ; -- clamp behavior + -- no status + +attribute ISC_STATUS of XC3S1200E_FG320 : entity is + "NOT IMPLEMENTED" ; + +attribute ISC_BLANK_USERCODE of XC3S1200E_FG320 : entity is + "00000000000000000000000000000000"; + +attribute ISC_FLOW of XC3S1200E_FG320 : entity is + -- Enable program + "flow_enable " & + "initialize " & + " (ISC_ENABLE 5:00 wait TCK 16)," & + + "flow_disable " & + "initialize " & + " (ISC_DISABLE wait TCK 16)" & + " (BYPASS 1:0 wait TCK 1)," & + + "flow_program(array) " & + "Repeat 239922 " & + " (ISC_PROGRAM 16:? wait TCK 1 )," & + + "flow_program(legacy) " & + "Initialize " & + " (JSHUTDOWN wait TCK 16)" & + " (CFG_IN 3838752:? wait TCK 1)" & + " (JSTART wait TCK 32)" & + " (BYPASS 1:0 wait TCK 1)," & + + "flow_verify(idcode) " & + "initialize " & + " (IDCODE wait TCK 1 32:01C2E093*0FFFFFFF)," & + + "flow_read(usercode) " & + "initialize " & + " (USERCODE wait TCK 1 32:!)," & + + "flow_read(idcode) " & + "initialize " & + " (IDCODE wait TCK 1 32:!)," & + + "flow_program_done " & + "initialize " & + " (BYPASS wait TCK 1)," & + + "flow_error_exit " & + "initialize " & + " (BYPASS wait TCK 1)"; + +attribute ISC_PROCEDURE of XC3S1200E_FG320 : entity is + "proc_enable = (flow_enable)," & + "proc_disable = (flow_disable)," & + "proc_program = (flow_program(array))," & + "proc_program(legacy) = (flow_program(legacy))," & + "proc_verify(idcode) = (flow_verify(idcode))," & + "proc_read(idcode) = (flow_read(idcode))," & + "proc_read(usercode) = (flow_read(usercode))," & + "proc_program_done = (flow_program_done)," & + "proc_error_exit = (flow_error_exit)"; + +attribute ISC_ACTION of XC3S1200E_FG320 : entity is + "program = (proc_verify(idcode) recommended," & + " proc_enable, proc_program," & + " proc_disable)," & + "program(lgcy) = (proc_verify(idcode) recommended," & + " proc_enable, proc_program(legacy)," & + " proc_disable)," & + "verify(idcode) = (proc_verify(idcode))," & + "read(idcode) = (proc_read(idcode))," & + "read(usercode) = (proc_read(usercode))"; + +-- Design Warning Section + +attribute DESIGN_WARNING of XC3S1200E_FG320 : entity is + "This is a preliminary BSDL file which has not been verified." & + "This BSDL file must be modified by the FPGA designer in order to" & + "reflect post-configuration behavior (if any)." & + "To avoid losing the current configuration, the PROG_B should be" & + "kept high. If the PROG_B pin goes low by any means," & + "the configuration will be cleared." & + "PROG_B can only be captured, not updated." & + "The value at the pin is always used by the device." & + "PUDC_B can be captured and updated." & + "The value at the pin is always used by the device" & + "before configuration is done." & + "During pre-configuration, the disable result of a 3-stated" & + "I/O in this file corresponds to PUDC_B being low" & + "or during EXTEST instruction." & + "When PUDC_B is high AND during SAMPLE instruction, change" & + "all PULL1s to PULL0s." & + "After configuration, the disable result only depends on" & + "the individual IO configuration setting." & + "In EXTEST, output and tristate values are not captured in the" & + "Capture-DR state - those register cells are unchanged." & + "In INTEST, the pin input values are not captured in the" & + "Capture-DR state - those register cells are unchanged." & + "The output and tristate capture values are not valid until after" & + "the device is configured." & + "The tristate control value is not captured properly when" & + "GTS is activated."; + +end XC3S1200E_FG320; + Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/impact_bat =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/impact_bat (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/impact_bat (revision 28) @@ -0,0 +1,6 @@ +setMode -bs +setCable -port svf -file ../debug/bitstream.svf +addDevice -p 1 -file Board_Design_jtag.bit +program -p 1 +closeCable +quit Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/fpga_load =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/fpga_load (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/debug/fpga_load (revision 28) @@ -0,0 +1,6 @@ +bsdl path ../bsdl;../target/bsdl; +cable usbblaster +detect +part 1 +svf bitstream.svf + Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/filelist =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/filelist (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/filelist (revision 28) @@ -0,0 +1,28 @@ +verilog work ./target/Pad_Ring.v + + +verilog work ../../../../../ip/T6502/rtl/gen/syn/T6502.v +verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v +verilog work ../../../../../children/logic/ip/io_module/rtl/gen/syn/io_module.v + + + +verilog work ../../../../../children/logic/ip/vga_char_ctrl/rtl/gen/syn/vga_char_ctrl.v +verilog work ../../../../../children/logic/ip/ps2_interface/rtl/gen/syn/ps2_interface.v +verilog work ../../../../../children/logic/ip/uart/rtl/gen/syn/uart.v +verilog work ../../../../../children/logic/ip/serial_rcvr/rtl/gen/syn/serial_rcvr.v + + +verilog work ./target/lib/syn/cde_pads/cde_pad_se_dig.v +verilog work ./target/lib/syn/cde_clock_sys/cde_clock_sys.v +verilog work ./target/lib/syn/cde_jtag/cde_jtag.v +verilog work ./target/lib/syn/cde_jtag/cde_jtag_rpc_reg.v +verilog work ./target/lib/syn/cde_sram/cde_sram.v +verilog work ./target/lib/syn/cde_fifo/cde_fifo.v +verilog work ./target/lib/syn/cde_synchronizers/cde_sync_with_hysteresis.v +verilog work ./target/lib/syn/cde_divider/cde_divider.v +verilog work ./target/lib/syn/cde_serial_rcvr/cde_serial_rcvr.v +verilog work ./target/lib/syn/cde_serial_xmit/cde_serial_xmit.v + + + Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/core.v =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/core.v (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/core.v (revision 28) @@ -0,0 +1,163 @@ + + + + + + + // Declare I/O Port connections + + +wire clk = ck25MHz; + +wire [7:0] rx_data; +wire read; + + + + +wire sync; +wire rd; +wire wr; + +wire [7:0] write_data; + + + +wire [7:0] data; +wire baud_clk; + +reg enable; +wire [15:0] add_mon; +wire [7:0] gpio_0_out; +wire [7:0] gpio_1_out; + + +assign rs_tx_pad_out = rs_rx_pad_in; + + + + +assign jtag_user1_cap = jtag_user1_upd; +assign jtag_user2_cap = add_mon; + +assign PosD = {gpio_0_out,gpio_1_out}; +assign PosL = 8'h12; + + + +assign ja_1_pad_out = 1'b0; +assign ja_2_pad_out = reset; +assign ja_3_pad_out = one_usec; +assign ja_4_pad_out = 1'b0 ; + +assign ja_7_pad_out = 1'b0; +assign ja_8_pad_out = 1'b0; +assign ja_9_pad_out = 1'b0; +assign ja_10_pad_out = 1'b0; + + + +assign jb_1_pad_out = 1'b0; +assign jb_2_pad_out = 1'b0; +assign jb_3_pad_out = 1'b0; +assign jb_4_pad_out = 1'b0; + + +assign jb_7_pad_out = 1'b0; +assign jb_8_pad_out = 1'b0; +assign jb_9_pad_out = 1'b0; +assign jb_10_pad_out = 1'b0; + + +assign jc_1_pad_out = 1'b1; +assign jc_2_pad_out = 1'b0; +assign jc_3_pad_out = 1'b1; +assign jc_4_pad_out = 1'b0; + +assign jc_7_pad_out = 1'b1; +assign jc_8_pad_out = 1'b0; +assign jc_9_pad_out = 1'b1; +assign jc_10_pad_out = 1'b0; + + + + + +wire [9:0] xpos; + + + + + + + + + + +always@(posedge ck25MHz) +if(reset) enable <= 1'b1; +else enable <= !enable; + + + + +T6502 #( + .ROM_WORDS (`ROM_WORDS), + .ROM_ADD (`ROM_ADD), + .RAM_WORDS (4096), + .ROM_FILE (`ROM_FILE), + .STARTUP (`STARTUP), + .FONT (`FONT) + + ) + cpu ( + .clk ( ck25MHz ), + .reset ( reset ), + .enable ( enable ), + + + .ext_irq_in ( 4'h0 ), + + .gpio_0_out ( gpio_0_out ), + .gpio_0_in ( 8'h00 ), + .gpio_0_oe ( ), + .gpio_0_lat ( ), + + .gpio_1_out ( gpio_1_out ), + .gpio_1_in ( 8'h00 ), + .gpio_1_oe ( ), + .gpio_1_lat ( ), + + + .ps2_data_oe ( ps2_data_pad_oe ), + .ps2_data_in ( ps2_data_pad_in ), + .ps2_clk_oe ( ps2_clk_pad_oe ), + .ps2_clk_in ( ps2_clk_pad_in ), + + + + .txd_pad_out ( txd_pad_out ), + .rxd_pad_in ( rxd_pad_in ), + .cts_pad_in ( cts_pad_in ), + .rts_pad_out ( rts_pad_out ), + + .vgared_pad_out ( vgared_pad_out[2:0] ), + .vgagreen_pad_out ( vgagreen_pad_out[2:0] ), + .vgablue_pad_out ( vgablue_pad_out[1:0] ), + + .hsync_n_pad_out ( hsync_pad_out ), + .vsync_n_pad_out ( vsync_pad_out ) + + + + +); + + + + + + + + + \ No newline at end of file Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/Makefile =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/Makefile (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/Makefile (revision 28) @@ -0,0 +1,4 @@ +include ../../../../bin/Makefile.root +include ./target/Makefile.brd +Design=M6502_io_poll + Index: trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/def_file =================================================================== --- trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/def_file (nonexistent) +++ trunk/projects/Mos6502/ip/T6502/syn/Nexys2_io_poll/def_file (revision 28) @@ -0,0 +1,18 @@ +`define SYNTHESIS +`define ROM_FILE "../../../../../../../projects/Mos6502/sw/io_poll/io_poll.abs" +`define ROM_WORDS 2048 +`define ROM_ADD 11 +`define MODULE_NAME Nexys2_M6502_io_poll + +`define STARTUP "../../../../../../../projects/pic_micro/sw/vga_startup_screen/vga_startup_screen.abs" + +`define FONT "../../../../../../../projects/pic_micro/sw/vga_font/vga_font.abs" + + + +`define JTAG_USER1_WIDTH 8 +`define JTAG_USER1_RESET 8'h12 + +`define JTAG_USER2_WIDTH 16 +`define JTAG_USER2_RESET 16'h0000 + Index: trunk/projects/Mos6502/sw/vga_font/vga_font.asm =================================================================== --- trunk/projects/Mos6502/sw/vga_font/vga_font.asm (nonexistent) +++ trunk/projects/Mos6502/sw/vga_font/vga_font.asm (revision 28) @@ -0,0 +1,313 @@ + + + cpu 6502 + output HEX + + * = $0000 ; assemble at $0000 + code +;------------------------------------------- +; ; +;Code 00h defines a solid block ; +;Codes 01h-04h define block graphics ; +;Codes 05h-1Fh define line graphics ; +;Codes 20h-7Eh define the ASCII characters ; +;Code 7Fh defines a hash pattern ; +;Codes 80h-FFh user defined characters ; +;------------------------------------------- ; +;//// Solid Block //// + ;// 00h: solid block address 000 + db $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF; +;// Block graphics //// + ; 01h: Left block up, right block down address 008 + db $F0,$F0,$F0,$F0,$0F,$0F,$0F,$0F; + ; 02h: Left block down, right block up address 010 + db $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0; + ; 03h: Both blocks down address 018 + db $00,$00,$00,$00,$FF,$FF,$FF,$FF; + ; 04h: Both blocks up address 020 + db $FF,$FF,$FF,$FF,$00,$00,$00,$00; +;// Line Graphics //// + ; 05h: corner upper left address 028 + db $FF,$80,$80,$80,$80,$80,$80,$80; + ; 06h: corner upper right address 030 + db $FF,$01,$01,$01,$01,$01,$01,$01; + ; 07h: corner lower left address 038 + db $80,$80,$80,$80,$80,$80,$80,$FF; + ; 08h: corner lower right address 040 + db $01,$01,$01,$01,$01,$01,$01,$FF; + ; 09h: cross junction address 048 + db $10,$10,$10,$FF,$10,$10,$10,$10; + ; 0Ah: "T" junction address 050 + db $FF,$10,$10,$10,$10,$10,$10,$10; + ; 0Bh: "T" juntion rotated 90 clockwise address 058 + db $01,$01,$01,$FF,$01,$01,$01,$01; + ; 0Ch: "T" juntion rotated 180 address 060 + db $10,$10,$10,$10,$10,$10,$10,$FF; + ; 0Dh: "T" junction rotated 270 clockwise address 068 + db $80,$80,$80,$FF,$80,$80,$80,$80; + ; 0Eh: arrow pointing right address 070 + db $08,$04,$02,$FF,$02,$04,$08,$00; + ; 0Fh: arrow pointing left address 078 + db $10,$20,$40,$FF,$40,$20,$10,$00; + ; 10h: first (top) horizontal line address 080 + db $FF,$00,$00,$00,$00,$00,$00,$00; + ; 11h: second horizontal line address 088 + db $00,$FF,$00,$00,$00,$00,$00,$00; + ; 12h: third horizontal line address 090 + db $00,$00,$FF,$00,$00,$00,$00,$00; + ; 13h: fourth horizontal line address 098 + db $00,$00,$00,$FF,$00,$00,$00,$00; + ; 14h: fifth horizontal line address 0A0 + db $00,$00,$00,$00,$FF,$00,$00; + ; 15h: sixth horizontal line address 0A7 + db $00,$00,$00,$00,$00,$00,$FF,$00,$00; + ; 16h: seventh horizontal line address 0B0 + db $00,$00,$00,$00,$00,$00,$FF,$00; + ; 17h: eighth (bottom) horizontal line address 0B8 + db $00,$00,$00,$00,$00,$00,$00,$FF; + ; 18h: first (left) vertical line address 0C0 + db $80,$80,$80,$80,$80,$80,$80,$80; + ; 19h: second vertical line address 0C8 + db $40,$40,$40,$40,$40,$40,$40,$40; + ; 1Ah: third vertical line address 0D0 + db $20,$20,$20,$20,$20,$20,$20,$20; + ; 1Bh: fourth vertical line address 0D8 + db $10,$10,$10,$10,$10,$10,$10,$10; + ; 1Ch: fifth vertical line address 0E0 + db $08,$08,$08,$08,$08,$08,$08,$08; + ; 1Dh: sixth vertical line address 0E8 + db $04,$04,$04,$04,$04,$04,$04,$04; + ; 1Eh: seventh vertical line address 0F0 + db $02,$02,$02,$02,$02,$02,$02,$02; + ; 1Fh: eighth (right) vertical line address 0F8 + db $01,$01,$01,$01,$01,$01,$01,$01; +;// ASCII Characters //// + ; 20h: space address 100 + db $00,$00,$00,$00,$00,$00,$00,$00; + ; 21h: ! address 108 + db $10,$10,$10,$10,$00,$00,$10,$00; + ; 22h: " address 110 + db $28,$28,$28,$00,$00,$00,$00,$00; + ; 23h: # address 118 + db $28,$28,$7C,$28,$7C,$28,$28,$00; + ; 24h: $ address 120 + db $10,$3C,$50,$38,$14,$78,$10,$00; + ; 25h: % address 128 + db $60,$64,$08,$10,$20,$46,$06,$00; + ; 26h: & address 130 + db $30,$48,$50,$20,$54,$48,$34,$00; + ; 27h: ' address 138 + db $30,$10,$20,$00,$00,$00,$00,$00; + ; 28h: ( address 140 + db $08,$10,$20,$20,$20,$10,$08,$00; + ; 29h: ) address 148 + db $20,$10,$08,$08,$08,$10,$20,$00; + ; 2Ah: * address 150 + db $00,$10,$54,$38,$54,$10,$00,$00; + ; 2Bh: + address 158 + db $00,$10,$10,$7C,$10,$10,$00,$00; + ; 2Ch: , address 160 + db $00,$00,$00,$00,$00,$30,$10,$20; + ; 2Dh: - address 168 + db $00,$00,$00,$7C,$00,$00,$00,$00; + ; 2Eh: . address 170 + db $00,$00,$00,$00,$00,$30,$30,$00; + ; 2Fh: / address 178 + db $00,$04,$08,$10,$20,$40,$00,$00; + ; 30h: 0 address 180 + db $38,$44,$4C,$54,$64,$44,$38,$00; + ; 31h: 1 address 188 + db $10,$30,$10,$10,$10,$10,$38,$00; + ; 32h: 2 address 190 + db $38,$44,$04,$08,$10,$20,$7C,$00; + ; 33h: 3 address 198 + db $7C,$08,$10,$08,$04,$44,$38,$00; + ; 34h: 4 address 1A0 + db $08,$18,$28,$48,$7C,$08,$08,$00; + ; 35h: 5 address 1A8 + db $7C,$40,$78,$04,$04,$44,$38,$00; + ; 36h: 6 address 1B0 + db $18,$20,$40,$78,$44,$44,$38,$00; + ; 37h: 7 address 1B8 + db $7C,$04,$08,$10,$20,$20,$20,$00; + ; 38h: 8 address 1C0 + db $38,$44,$44,$38,$44,$44,$38,$00; + ; 39h: 9 address 1C8 + db $38,$44,$44,$3C,$04,$08,$30,$00; + ; 3Ah: : address 1D0 + db $00,$30,$30,$00,$00,$30,$30,$00; + ; 3Bh: ; address 1D8 + db $00,$30,$30,$00,$00,$30,$10,$20; + ; 3Ch: < address 1E0 + db $08,$10,$20,$40,$20,$10,$08,$00; + ; 3Dh: = address 1E8 + db $00,$00,$7C,$00,$7C,$00,$00,$00; + ; 3Eh: > address 1F0 + db $20,$10,$08,$04,$08,$10,$20,$00; + ; 3Fh: ? address 1F8 + db $38,$44,$04,$08,$10,$00,$10,$00; + ; 40h: @ address 200 + db $38,$44,$04,$34,$54,$54,$38,$00; + ; 41h: A address 208 + db $38,$44,$44,$44,$7C,$44,$44,$00; + ; 42h: B address 210 + db $78,$44,$44,$78,$44,$44,$78,$00; + ; 43h: C address 218 + db $38,$44,$40,$40,$40,$44,$38,$00; + ; 44h: D address 220 + db $70,$48,$44,$44,$44,$48,$70,$00; + ; 45h: E address 228 + db $7C,$40,$40,$78,$40,$40,$7C,$00; + ; 46h: F address 230 + db $7C,$40,$40,$78,$40,$40,$40,$00; + ; 47h: G address 238 + db $38,$44,$40,$5C,$44,$44,$3C,$00; + ; 48h: H address 240 + db $44,$44,$44,$7C,$44,$44,$44,$00; + ; 49h: I address 248 + db $38,$10,$10,$10,$10,$10,$38,$00; + ; 4Ah: J address 250 + db $1C,$08,$08,$08,$08,$48,$30,$00; + ; 4Bh: K address 258 + db $44,$48,$50,$60,$50,$48,$44,$00; + ; 4Ch: L address 260 + db $40,$40,$40,$40,$40,$40,$7C,$00; + ; 4Dh: M address 268 + db $44,$6C,$54,$54,$44,$44,$44,$00; + ; 4Eh: N address 270 + db $44,$44,$64,$54,$4C,$44,$44,$00; + ; 4Fh: O address 278 + db $38,$44,$44,$44,$44,$44,$38,$00; + ; 50h: P address 280 + db $78,$44,$44,$78,$40,$40,$40,$00; + ; 51h: Q address 288 + db $38,$44,$44,$44,$54,$48,$34,$00; + ; 52h: R address 290 + db $78,$44,$44,$78,$50,$48,$44,$00; + ; 53h: S address 298 + db $3C,$40,$40,$38,$04,$04,$78,$00; + ; 54h: T address 2A0 + db $7C,$10,$10,$10,$10,$10,$10,$00; + ; 55h: U address 2A8 + db $44,$44,$44,$44,$44,$44,$38,$00; + ; 56h: V address 2B0 + db $44,$44,$44,$44,$44,$28,$10,$00; + ; 57h: W address 2B8 + db $44,$44,$44,$54,$54,$54,$28,$00; + ; 58h: X address 2C0 + db $44,$44,$28,$10,$28,$44,$44,$00; + ; 59h: Y address 2C8 + db $44,$44,$44,$28,$10,$10,$10,$00; + ; 5Ah: Z address 2D0 + db $7C,$04,$08,$10,$20,$40,$7C,$00; + ; 5Bh: [ address 2D8 + db $38,$20,$20,$20,$20,$20,$38,$00; + ; 5Ch: \ address 2E0 + db $00,$40,$20,$10,$08,$04,$00,$00; + ; 5Dh: ] address 2E8 + db $38,$08,$08,$08,$08,$08,$38,$00; + ; 5Eh: ^ address 2F0 + db $10,$28,$44,$00,$00,$00,$00,$00; + ; 5Fh: _ address 2F8 + db $00,$00,$00,$00,$00,$00,$7C,$00; + ; 60h: ` address 300 + db $20,$10,$08,$00,$00,$00,$00,$00; + ; 61h: a address 308 + db $00,$00,$38,$04,$3C,$44,$3C,$00; + ; 62h: b address 310 + db $40,$40,$58,$64,$44,$44,$78,$00; + ; 63h: c address 318 + db $00,$00,$38,$40,$40,$44,$38,$00; + ; 64h: d address 320 + db $04,$04,$34,$4C,$44,$44,$3C,$00; + ; 65h: e address 328 + db $00,$00,$38,$44,$7C,$40,$38,$00; + ; 66h: f address 330 + db $18,$24,$20,$70,$20,$20,$20,$00; + ; 67h: g address 338 + db $00,$00,$3C,$44,$44,$3C,$04,$38; + ; 68h: h address 340 + db $40,$40,$58,$64,$44,$44,$44,$00; + ; 69h: i address 348 + db $10,$10,$30,$10,$10,$10,$38,$00; + ; 6Ah: j address 350 + db $00,$08,$00,$18,$08,$08,$48,$30; + ; 6Bh: k address 358 + db $40,$40,$48,$50,$60,$50,$48,$00; + ; 6Ch: l address 360 + db $30,$10,$10,$10,$10,$10,$38,$00; + ; 6Dh: m address 368 + db $00,$00,$68,$54,$54,$44,$44,$00; + ; 6Eh: n address 370 + db $00,$00,$58,$64,$44,$44,$44,$00; + ; 6Fh: o address 378 + db $00,$00,$38,$44,$44,$44,$38,$00; + ; 70h: p address 380 + db $00,$00,$78,$44,$78,$40,$40,$40; + ; 71h: q address 388 + db $00,$00,$00,$34,$4C,$3C,$04,$04; + ; 72h: r address 390 + db $00,$00,$58,$64,$40,$40,$40,$00; + ; 73h: s address 398 + db $00,$00,$38,$40,$38,$04,$78,$00; + ; 74h: t address 3A0 + db $00,$20,$20,$70,$20,$20,$24,$18; + ; 75h: u address 3A8 + db $00,$00,$44,$44,$44,$4C,$34,$00; + ; 76h: v address 3B0 + db $00,$00,$44,$44,$44,$28,$10,$00; + ; 77h: w address 3B8 + db $00,$00,$44,$44,$54,$54,$28,$00; + ; 78h: x address 3C0 + db $00,$00,$44,$28,$10,$28,$44,$00; + ; 79h: y address 3C8 + db $00,$00,$00,$44,$44,$3C,$04,$38; + ; 7Ah: z address 3D0 + db $00,$00,$7C,$08,$10,$20,$7C,$00; + ; 7Bh: { address 3D8 + db $08,$10,$10,$20,$10,$10,$08,$00; + ; 7Ch: | address 3E0 + db $10,$10,$10,$10,$10,$10,$10,$00; + ; 7Dh: } address 3E8 + db $20,$10,$10,$08,$10,$10,$20,$00; + ; 7Eh: ~ address 3F0 + db $00,$00,$60,$92,$0C,$00,$00,$00; +;// Hash Pattern //// + ; 7Fh: hash pattern address 3F8 + db $55,$AA,$55,$AA,$55,$AA,$55,$AA; +;// User Defined Characters //// + ; 80h: vertical to the left address 400 + db $F0,$F0,$F0,$F0,$F0,$F0,$F0,$F0; + ; 81h: vertical to the right address 408 + db $0F,$0F,$0F,$0F,$0F,$0F,$0F,$0F; + ; 82h: circle address 410 + db $00,$18,$3C,$7E,$7E,$3C,$18,$00; + ; 83h: Upper left block only address 418 + db $F0,$F0,$F0,$F0,$00,$00,$00,$00; + ; 84h: Upper right block only address 420 + db $0F,$0F,$0F,$0F,$00,$00,$00,$00; + ; 85h: Lower left block only address 428 + db $00,$00,$00,$00,$F0,$F0,$F0,$F0; + ; 86h: Lower right block only address 430 + db $00,$00,$00,$00,$0F,$0F,$0F,$0F; + ; 87h: One horizontal line address 438 + db $00,$00,$00,$00,$00,$00,$00,$FF; + ; 88h: Two horizontal lines address 440 + db $00,$00,$00,$00,$00,$00,$FF,$FF; + ; 89h: Three horizontal lines address 448 + db $00,$00,$00,$00,$00,$FF,$FF,$FF; + ; 8Ah: Four horizontal lines address 450 + db $00,$00,$00,$00,$FF,$FF,$FF,$FF; + ; 8Bh: Five horizontal lines address 458 + db $00,$00,$00,$FF,$FF,$FF,$FF,$FF; + ; 8Ch: Six horizontal lines address 460 + db $00,$00,$FF,$FF,$FF,$FF,$FF,$FF; + ; 8Dh: Seven horizontal lines address 468 + db $00,$FF,$FF,$FF,$FF,$FF,$FF,$FF; + ; 8Eh: One vertical line address 470 + db $80,$80,$80,$80,$80,$80,$80,$80; + ; 8Fh: Two vertical lines address 478 + db $c0,$c0,$c0,$c0,$c0,$c0,$c0,$c0; + + + code \ No newline at end of file Index: trunk/projects/Mos6502/sw/vga_font/Makefile =================================================================== --- trunk/projects/Mos6502/sw/vga_font/Makefile (nonexistent) +++ trunk/projects/Mos6502/sw/vga_font/Makefile (revision 28) @@ -0,0 +1,5 @@ +include ../../bin/Makefile.root +code=vga_font + + +all: asm_6502 \ No newline at end of file Index: trunk/projects/Mos6502/sw/Prog/Prog.asm =================================================================== --- trunk/projects/Mos6502/sw/Prog/Prog.asm (nonexistent) +++ trunk/projects/Mos6502/sw/Prog/Prog.asm (revision 28) @@ -0,0 +1,1514 @@ + + + cpu 6502 + output HEX +io_base = $8000 ; +io_stat = $2 ; +io_tim0_start = $10 ; +io_tim0_end = $12 ; +io_tim1_start = $20 ; +io_tim1_end = $22 ; + + + * = $f000 ; assemble at $f000 + code + +.start nop + lda #$00 + sta $04 + sta $05 + sta $06 + sta $07 + lda #$00 + sta io_base+io_stat + lda io_base+io_stat + lda #$01 + sta io_base+io_stat + lda io_base+io_stat + jmp .lab_00 + lda #$00 + jmp .lab_100 +.lab_00 lda #$01 + sta io_base+io_stat + lda io_base+io_stat + lda #$02 + sta io_base+io_stat + lda io_base+io_stat + clc + bcc .lab_01 + lda #$01 + jmp .lab_100 +.lab_01 lda #$03 + sta io_base+io_stat + lda io_base+io_stat + sec + bcc .lab_02 + jmp .lab_025 +.lab_02 lda #$02 + jmp .lab_100 +.lab_025 lda #$04 + sta io_base+io_stat + lda io_base+io_stat + sec + bcs .lab_03 + lda #$01 + jmp .lab_100 + +.lab_03 clc + bcs .lab_04 + jmp .lab_045 +.lab_04 lda #$02 + jmp .lab_100 +.lab_045 lda #$05 + sta io_base+io_stat + lda #$05 + cmp #$04 + beq .lab_05 + cmp #$05 + beq .lab_06 +.lab_05 lda #$03 + jmp .lab_100 +.lab_06 lda #$06 + sta io_base+io_stat + lda #$c4 + cmp #$e4 + bne .lab_07 + lda #$04 + jmp .lab_100 +.lab_07 cmp #$C4 + bne .lab_08 + jmp .lab_085 +.lab_08 lda #$05 + jmp .lab_100 +.lab_085 lda #$07 + sta io_base+io_stat + ldx #$42 + cpx #$32 + beq .lab_09 + cpx #$42 + beq .lab_10 +.lab_09 lda #$06 + jmp .lab_100 +.lab_10 lda #$08 + sta io_base+io_stat + ldy #$C3 + cpy #$D3 + beq .lab_11 + cpy #$C3 + beq .lab_12 +.lab_11 lda #$07 + jmp .lab_100 +.lab_12 lda #$09 + sta io_base+io_stat + ldx #$00 + dex + cpx #$FF + beq .lab_13 + lda #$08 + jmp .lab_100 +.lab_13 lda #$0A + sta io_base+io_stat + ldy #$00 + dey + cpy #$FF + beq .lab_14 + lda #$09 + jmp .lab_100 +.lab_14 lda #$0B + sta io_base+io_stat + ldx #$0F + inx + cpx #$10 + beq .lab_15 + lda #$10 + jmp .lab_100 +.lab_15 lda #$0C + sta io_base+io_stat + ldy #$7F + iny + cpy #$80 + beq .lab_16 + lda #$11 + jmp .lab_100 +.lab_16 lda #$0D + sta io_base+io_stat + lda #$ED + jsr .lab_165 + cmp #$42 + beq .lab_17 + lda #$12 + jmp .lab_100 +.lab_165 lda #$42 + rts +.lab_17 lda #$0E + sta io_base+io_stat + lda #$35 + tax + cpx #$35 + beq .lab_18 + lda #$12 + jmp .lab_100 +.lab_18 lda #$0F + sta io_base+io_stat + lda #$76 + tay + cpy #$76 + beq .lab_19 + lda #$13 + jmp .lab_100 +.lab_19 lda #$10 + sta io_base+io_stat + ldx #$52 + txa + cmp #$52 + beq .lab_20 + lda #$14 + jmp .lab_100 +.lab_20 lda #$11 + sta io_base+io_stat + ldy #$52 + tya + cmp #$52 + beq .lab_21 + lda #$15 + jmp .lab_100 +.lab_21 lda #$12 + sta io_base+io_stat + clc + lda #$23 + adc #$45 + cmp #$68 + beq .lab_22 + lda #$16 + jmp .lab_100 +.lab_22 sec + lda #$42 + adc #$63 + cmp #$A6 + beq .lab_23 + lda #$17 + jmp .lab_100 +.lab_23 lda #$13 + sta io_base+io_stat + lda #$36 + and #$f0 + cmp #$30 + beq .lab_24 + lda #$18 + jmp .lab_100 +.lab_24 lda #$14 + sta io_base+io_stat + clc + lda #$36 + asl a + cmp #$6C + beq .lab_25 + lda #$19 + jmp .lab_100 +.lab_25 lda #$15 + sta io_base+io_stat + lda #$89 + eor #$96 + cmp #$1F + beq .lab_26 + lda #$20 + jmp .lab_100 +.lab_26 lda #$16 + sta io_base+io_stat + clc + lda #$52 + lsr a + cmp #$29 + beq .lab_27 + lda #$21 + jmp .lab_100 +.lab_27 lda #$17 + sta io_base+io_stat + lda #$B6 + ora #$4D + cmp #$FF + beq .lab_28 + lda #$22 + jmp .lab_100 +.lab_28 lda #$18 + sta io_base+io_stat + clc + lda #$23 + rol a + cmp #$46 + beq .lab_29 + lda #$23 + jmp .lab_100 +.lab_29 sec + lda #$42 + rol a + cmp #$85 + beq .lab_30 + lda #$24 + jmp .lab_100 +.lab_30 lda #$19 + sta io_base+io_stat + clc + lda #$23 + ror a + cmp #$11 + beq .lab_31 + lda #$25 + jmp .lab_100 +.lab_31 sec + lda #$42 + ror a + cmp #$A1 + beq .lab_32 + lda #$26 + jmp .lab_100 +.lab_32 lda #$20 + sta io_base+io_stat + sec + lda #$86 + sbc #$45 + cmp #$41 + beq .lab_33 + lda #$27 + jmp .lab_100 +.lab_33 clc + lda #$89 + sbc #$23 + cmp #$65 + beq .lab_34 + lda #$28 + jmp .lab_100 +.lab_34 lda #$21 + sta io_base+io_stat + lda #$42 + sta $0200 + lda #$9F + sta $0201 + lda $0200 + cmp #$42 + beq .lab_35 + lda #$29 + jmp .lab_100 +.lab_35 lda $0201 + cmp #$9F + beq .lab_36 + lda #$30 + jmp .lab_100 +.lab_36 lda #$22 + sta io_base+io_stat + lda #$94 + sta $0201 + lda #$41 + sta $0200 + lda #$53 + clc + adc $0200 + cmp $0201 + beq .lab_37 + lda #$31 + jmp .lab_100 +.lab_37 lda #$8D + sta $0201 + lda #$98 + sta $0200 + lda #$F4 + sec + adc $0200 + cmp $0201 + beq .lab_38 + lda #$32 + jmp .lab_100 +.lab_38 lda #$23 + sta io_base+io_stat + ldy #$84 + sty $0201 + ldx #$B4 + stx $0200 + lda #$86 + and $0200 + cmp $0201 + beq .lab_39 + lda #$33 + jmp .lab_100 +.lab_39 lda #$24 + sta io_base+io_stat + ldx #$55 + stx $0200 + asl $0200 + lda $0200 + cmp #$AA + beq .lab_40 + lda #$34 + jmp .lab_100 +.lab_40 lda #$25 + sta io_base+io_stat + lda #$53 + sta $0200 + lda #$00 + ldx #$53 + cpx $0200 + beq .lab_41 + lda #$35 + jmp .lab_100 +.lab_41 lda #$26 + sta io_base+io_stat + lda #$45 + sta $0200 + lda #$00 + ldy #$45 + cpy $0200 + beq .lab_42 + lda #$36 + jmp .lab_100 +.lab_42 lda #$27 + sta io_base+io_stat + lda #$EF + sta $0200 + dec $0200 + lda #$EE + cmp $0200 + beq .lab_43 + lda #$37 + jmp .lab_100 +.lab_43 lda #$01 + sta $0200 + dec $0200 + beq .lab_44 + lda #$38 + jmp .lab_100 +.lab_44 lda #$28 + sta io_base+io_stat + lda #$EF + sta $0200 + inc $0200 + lda #$F0 + cmp $0200 + beq .lab_45 + lda #$39 + jmp .lab_100 +.lab_45 lda #$FF + sta $0200 + inc $0200 + beq .lab_46 + lda #$40 + jmp .lab_100 +.lab_46 lda #$29 + sta io_base+io_stat + ldy #$32 + sty $0201 + ldx #$B4 + stx $0200 + lda #$86 + eor $0200 + cmp $0201 + beq .lab_47 + lda #$41 + jmp .lab_100 +.lab_47 lda #$2A + sta io_base+io_stat + ldy #$B6 + sty $0201 + ldx #$B4 + stx $0200 + lda #$86 + ora $0200 + cmp $0201 + beq .lab_48 + lda #$42 + jmp .lab_100 +.lab_48 lda #$2B + sta io_base+io_stat + clc + ldx #$AA + stx $0200 + rol $0200 + bcs .lab_49 + lda #$43 + jmp .lab_100 +.lab_49 lda $0200 + cmp #$54 + beq .lab_50 + lda #$44 + jmp .lab_100 +.lab_50 lda #$2C + sta io_base+io_stat + clc + ldx #$55 + stx $0200 + ror $0200 + bcs .lab_51 + lda #$45 + jmp .lab_100 +.lab_51 lda $0200 + cmp #$2A + beq .lab_52 + lda #$46 + jmp .lab_100 +.lab_52 lda #$2D + sta io_base+io_stat + ldx #$96 + stx $0200 + lsr $0200 + lda $0200 + cmp #$4B + beq .lab_53 + lda #$47 + jmp .lab_100 +.lab_53 lda #$2E + sta io_base+io_stat + ldx #$42 + stx $0200 + ldx #$9F + stx $0201 + ldx $0200 + cpx #$42 + beq .lab_54 + lda #$48 + jmp .lab_100 +.lab_54 ldx $0201 + cpx #$9F + beq .lab_55 + lda #$49 + jmp .lab_100 +.lab_55 lda #$2F + sta io_base+io_stat + ldy #$34 + sty $0200 + ldy #$75 + sty $0201 + ldy $0200 + cpy #$34 + beq .lab_56 + lda #$4A + jmp .lab_100 +.lab_56 ldy $0201 + cpy #$75 + beq .lab_57 + lda #$4B + jmp .lab_100 +.lab_57 lda #$30 + sta io_base+io_stat + lda #$12 + sta $0201 + lda #$41 + sta $0200 + lda #$53 + sec + sbc $0200 + cmp $0201 + beq .lab_58 + lda #$4C + jmp .lab_100 +.lab_58 lda #$5B + sta $0201 + lda #$98 + sta $0200 + lda #$F4 + clc + sbc $0200 + cmp $0201 + beq .lab_59 + lda #$4D + jmp .lab_100 +.lab_59 lda #$31 + sta io_base+io_stat + lda #$42 + pha + lda #$ED + pha + lda #$BE + pha + lda #$00 + pla + cmp #$BE + bne .lab_60 + pla + cmp #$ED + bne .lab_60 + pla + cmp #$42 + bne .lab_60 + jmp .lab_605 +.lab_60 lda #$4E + jmp .lab_100 +.lab_605 lda #$32 + sta io_base+io_stat + ldx #$00 + clc + lda #$03 + sta $0200,X + adc #$07 + inx + sta $0200,X + adc #$07 + inx + sta $0200,X + adc #$07 + inx + sta $0200,X + adc #$07 + inx + sta $0200,X + adc #$07 + inx + sta $0200,X + adc #$07 + inx + sta $0200,X + ldx #$00 + clc + lda $0200,X + cmp #$03 + bne .lab_61 + inx + lda $0200,X + cmp #$0A + bne .lab_61 + inx + lda $0200,X + cmp #$11 + bne .lab_61 + inx + lda $0200,X + cmp #$18 + bne .lab_61 + inx + lda $0200,X + cmp #$1F + bne .lab_61 + inx + lda $0200,X + cmp #$26 + bne .lab_61 + inx + lda $0200,X + cmp #$2D + bne .lab_61 + jmp .lab_615 +.lab_61 lda #$4F + jmp .lab_100 +.lab_615 lda #$33 + sta io_base+io_stat + ldy #$00 + clc + lda #$03 + sta $0200,Y + adc #$07 + iny + sta $0200,Y + adc #$07 + iny + sta $0200,Y + adc #$07 + iny + sta $0200,Y + adc #$07 + iny + sta $0200,Y + adc #$07 + iny + sta $0200,Y + adc #$07 + iny + sta $0200,Y + ldy #$00 + clc + lda $0200,Y + cmp #$03 + bne .lab_62 + iny + lda $0200,Y + cmp #$0A + bne .lab_62 + iny + lda $0200,Y + cmp #$11 + bne .lab_62 + iny + lda $0200,Y + cmp #$18 + bne .lab_62 + iny + lda $0200,Y + cmp #$1F + bne .lab_62 + iny + lda $0200,Y + cmp #$26 + bne .lab_62 + iny + lda $0200,Y + cmp #$2D + bne .lab_62 + jmp .lab_625 +.lab_62 lda #$50 + jmp .lab_100 +.lab_625 lda #$34 + sta io_base+io_stat + lda #$52 + sta $0200 + lda #$24 + sta $0201 + lda #$78 + sta $0202 + lda #$00 + ldx #$00 + clc + adc $0200,X + clc + inx + adc $0200,X + clc + inx + adc $0200,X + cmp #$EE + beq .lab_63 + lda #$51 + jmp .lab_100 +.lab_63 lda #$35 + sta io_base+io_stat + lda #$68 + sta $0200 + lda #$13 + sta $0201 + lda #$95 + sta $0202 + lda #$00 + ldy #$00 + clc + adc $0200,Y + clc + iny + adc $0200,Y + clc + iny + adc $0200,Y + cmp #$10 + beq .lab_64 + lda #$52 + jmp .lab_100 +.lab_64 lda #$36 + sta io_base+io_stat + lda #$34 + sta $0200 + lda #$54 + sta $0201 + lda #$97 + sta $0202 + lda #$FF + ldy #$00 + and $0200,Y + iny + and $0200,Y + iny + and $0200,Y + cmp #$14 + beq .lab_65 + lda #$53 + jmp .lab_100 +.lab_65 lda #$37 + sta io_base+io_stat + lda #$34 + sta $0200 + lda #$54 + sta $0201 + lda #$97 + sta $0202 + lda #$FF + ldx #$00 + and $0200,X + inx + and $0200,X + inx + and $0200,X + cmp #$14 + beq .lab_66 + lda #$54 + jmp .lab_100 +.lab_66 lda #$38 + sta io_base+io_stat + lda #$64 + sta $00 + lda #$39 + clc + adc $00 + cmp #$9D + beq .lab_67 + lda #$55 + jmp .lab_100 +.lab_67 lda #$39 + sta io_base+io_stat + lda #$95 + sta $00 + lda #$76 + sta $01 + lda #$45 + sta $02 + ldx #$00 + lda #$00 + clc + adc $00,X + inx + clc + adc $00,X + inx + clc + adc $00,X + cmp #$50 + beq .lab_68 + lda #$56 + jmp .lab_100 +.lab_68 lda #$3A + sta io_base+io_stat + lda #$64 + sta $00 + lda #$39 + and $00 + cmp #$20 + beq .lab_69 + lda #$57 + jmp .lab_100 +.lab_69 lda #$3B + sta io_base+io_stat + lda #$95 + sta $00 + lda #$76 + sta $01 + lda #$45 + sta $02 + ldx #$00 + lda #$FF + and $00,X + inx + and $00,X + inx + and $00,X + cmp #$04 + beq .lab_70 + lda #$58 + jmp .lab_100 +.lab_70 lda #$3C + sta io_base+io_stat + lda #$97 + sta $0200 + lda #$78 + sta $0201 + lda #$45 + sta $0202 + ldx #$00 + lda #$97 + cmp $0200,X + bne .lab_71 + lda #$78 + inx + cmp $0200,X + bne .lab_71 + lda #$45 + inx + cmp $0200,X + bne .lab_71 + jmp .lab_715 +.lab_71 lda #$59 + jmp .lab_100 +.lab_715 lda #$3D + sta io_base+io_stat + lda #$97 + sta $0200 + lda #$78 + sta $0201 + lda #$45 + sta $0202 + ldy #$00 + lda #$97 + cmp $0200,Y + bne .lab_72 + lda #$78 + iny + cmp $0200,Y + bne .lab_72 + lda #$45 + iny + cmp $0200,Y + bne .lab_72 + jmp .lab_725 +.lab_72 lda #$5A + jmp .lab_100 +.lab_725 lda #$3E + sta io_base+io_stat + lda #$97 + sta $0200 + lda #$78 + sta $0201 + lda #$45 + sta $0202 + ldx #$00 + lda #$97 + cmp $0200,X + bne .lab_73 + lda #$78 + inx + cmp $0200,X + bne .lab_73 + lda #$45 + inx + cmp $0200,X + bne .lab_73 + jmp .lab_735 +.lab_73 lda #$5B + jmp .lab_100 +.lab_735 lda #$3F + sta io_base+io_stat + lda #$95 + sta $02 + lda #$00 + lda #$95 + cmp $02 + beq .lab_74 + lda #$5C + jmp .lab_100 +.lab_74 lda #$75 + sta $02 + lda #$67 + cmp $02 + bne .lab_75 + lda #$5D + jmp .lab_100 +.lab_75 lda #$40 + sta io_base+io_stat + lda #$36 + sta $02 + lda #$00 + ldx #$36 + cpx $02 + beq .lab_76 + lda #$5E + jmp .lab_100 +.lab_76 lda #$57 + sta $02 + ldx #$39 + cpx $02 + bne .lab_77 + lda #$5F + jmp .lab_100 +.lab_77 lda #$41 + sta io_base+io_stat + lda #$75 + sta $02 + lda #$00 + ldy #$75 + cpy $02 + beq .lab_78 + lda #$60 + jmp .lab_100 +.lab_78 lda #$43 + sta $02 + ldy #$24 + cpy $02 + bne .lab_79 + lda #$61 + jmp .lab_100 +.lab_79 lda #$42 + sta io_base+io_stat + nop ; was cli + lda #$00 + sta $05 + lda #$01 + sta $04 + lda #$10 + + + sta io_base+io_tim0_end + sta io_base+io_tim0_start + ldx #$00 + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + cpx #$10 + beq .lab_80 + lda #$62 + jmp .lab_100 +.lab_80 lda $05 + cmp #$00 ; was 1 if int serviced + beq .lab_81 + lda #$63 + jmp .lab_100 +.lab_81 nop ; was sei to disable interrupt + lda #$00 + sta $05 + lda #$01 + sta $04 + lda #$10 + sta io_base+io_tim0_end + sta io_base+io_tim0_start + ldx #$00 + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + cpx #$10 + beq .lab_82 + lda #$62 + jmp .lab_100 +.lab_82 lda $05 + cmp #$00 + beq .lab_83 + lda #$63 + jmp .lab_100 +.lab_83 lda #$00 + sta $04 + sta io_base+io_tim0_end + lda #$43 + sta io_base+io_stat + lda #$00 + sta $07 + lda #$01 + sta $06 + lda #$10 + sta io_base+io_tim0_end ; change to tim1 for nmi + sta io_base+io_tim0_start ; change to tim1 for nmi + ldx #$00 + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + inx + cpx #$10 + beq .lab_84 + lda #$64 + jmp .lab_100 +.lab_84 lda $07 + cmp #$00 ; change to 1 if nmi serviced + beq .lab_85 + lda #$65 + jmp .lab_100 +.lab_85 lda #$00 + sta $06 + sta io_base+io_tim1_end + lda #$44 + sta io_base+io_stat + jmp .lab_865 +.lab_86 jmp .lab_866 +.lab_865 sec + bcs .lab_86 + nop + nop + nop + lda #$66 + jmp .lab_100 +.lab_866 lda #$45 + sta io_base+io_stat + sec + lda #$34 + sbc #$75 + bcc .lab_87 + lda #$67 + jmp .lab_100 +.lab_87 lda #$46 + sta io_base+io_stat + tsx + stx $00 + lda #$42 + pha + lda #$00 + tsx + inx + lda $0100,X + cmp #$42 + beq .lab_88 + lda #$68 + jmp .lab_100 +.lab_88 lda #$69 + sta $0112 + lda #$00 + ldx #$11 + txs + pla + cmp #$69 + beq .lab_89 + lda #$69 + jmp .lab_100 +.lab_89 ldx $00 + txs + lda #$47 + sta io_base+io_stat + lda #$04 ; keep int disabled + pha + plp + stx $08 + lda #$00 + sta $05 + lda #$01 + sta $04 + ldx #$59 + nop ; was brk + inx + lda #$00 + sta $04 + lda $05 + cmp #$00 ; was 1 if brk taken + beq .lab_90 + lda #$70 + jmp .lab_100 +.lab_90 lda $08 + and #$10 + bne .lab_91 + lda #$71 + jmp .lab_100 +.lab_91 cpx #$59 + bne .lab_92 ; was beq + lda #$72 + jmp .lab_100 +.lab_92 lda #$48 + sta io_base+io_stat + lda #$53 + sta $30 + lda #$00 + ldx #$40 + lda $F0,X + cmp #$53 + beq .lab_93 + lda #$73 + jmp .lab_100 +.lab_93 lda #$49 + sta io_base+io_stat + clc + lda #$FF + adc #$01 + bcs .lab_94 + lda #$74 + jmp .lab_100 +.lab_94 lda #$4A + sta io_base+io_stat + sec + lda #$7F + sbc #$7E + bvc .lab_95 + lda #$75 + jmp .lab_100 +.lab_95 lda #$4B + sta io_base+io_stat + lda #$FF + pha + plp + php + pla + cmp #$FF + beq .lab_96 + lda #$76 + jmp .lab_100 +.lab_96 lda #$4C + sta io_base+io_stat + lda #$40 + ldx #$00 + sta $0200,X + inx + lsr a + sta $0200,X + inx + lsr a + sta $0200,X + inx + lsr a + sta $0200,X + inx + lsr a + sta $0200,X + inx + lsr a + sta $0200,X + inx + lsr a + sta $0200,X + ldx #$00 + asl $0200,X + inx + asl $0200,X + inx + asl $0200,X + inx + asl $0200,X + inx + asl $0200,X + inx + asl $0200,X + inx + asl $0200,X + lda #$00 + clc + adc $0200 + adc $0201 + adc $0202 + adc $0203 + adc $0204 + adc $0205 + adc $0206 + cmp #$FE + beq .lab_97 + lda #$77 + jmp .lab_100 +.lab_97 lda #$4D + sta io_base+io_stat + ldx #$42 + ldy #$00 + stx $0200 + ldx #$9F + stx $0201 + ldx $0200,Y + cpx #$42 + beq .lab_98 + lda #$48 + jmp .lab_100 +.lab_98 ldx $0201,Y + cpx #$9F + beq .lab_99 + lda #$78 + jmp .lab_100 +.lab_99 sei + lda #$FF + sta io_base+io_stat + lda io_base+io_stat + lda #$F0 + sta io_base + lda io_base + jmp .lab_99 +.lab_100 sei + sta io_base + lda io_base + jmp .lab_100 +.lab_10X pha + txa + pha + tya + pha + tsx + inx + inx + inx + inx + lda $0100,X + sta $08 + lda $04 + cmp #$00 + bne .lab_101 + lda #$E0 + jmp .lab_100 +.lab_101 sta io_base+io_tim0_end + inc $05 + pla + tay + pla + tax + pla + rti +.lab_10Y pha + txa + pha + tya + pha + lda $06 + cmp #$00 + bne .lab_102 + lda #$E0 + jmp .lab_100 +.lab_102 sta io_base+io_tim1_end + inc $07 + pla + tay + pla + tax + pla + rti + jmp .lab_10X + jmp .lab_10Y + + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00,$00,$00,$00,$00,$00; + db $00; + + dw .lab_10X ; + dw .start ; + dw .lab_10Y ; + + code + + + + + + Index: trunk/projects/Mos6502/sw/Prog/Makefile =================================================================== --- trunk/projects/Mos6502/sw/Prog/Makefile (nonexistent) +++ trunk/projects/Mos6502/sw/Prog/Makefile (revision 28) @@ -0,0 +1,7 @@ +include ../../bin/Makefile.root +code=Prog + +all:asm_6502 + + + Index: trunk/projects/Mos6502/sw/tim_1/ok_no_jsr =================================================================== --- trunk/projects/Mos6502/sw/tim_1/ok_no_jsr (nonexistent) +++ trunk/projects/Mos6502/sw/tim_1/ok_no_jsr (revision 28) @@ -0,0 +1,411 @@ + + + cpu 6502 + output HEX + dummy + +io_base = $8000 ; + +io_gpio_0 = $02 ; +io_gpio_1 = $06 ; + +io_tim0_start = $10 ; +io_tim0_end = $12 ; + +io_tim1_start = $20 ; +io_tim1_end = $22 ; + +io_uart_xmt = $30 ; +io_uart_rcv = $32 ; +io_uart_cnt = $34 ; +io_uart_stat = $36 ; + + +io_pic_int = $40 ; +io_pic_irq_en = $42 ; +io_pic_nmi_en = $44 ; +io_pic_irq_ac = $46 ; +io_pic_nmi_ac = $48 ; + +io_ps2_xmit = $50 ; +io_ps2_rcv = $52 ; +io_ps2_stat = $54 ; +io_ps2_cntrl = $56 ; +io_ps2_xpos = $58 ; +io_ps2_ypos = $5a ; + +address = $00 + + + + * = $f800 ; assemble start + code + +.str_1 ASC "Mem " ; + DB $00 ; + +.put_c pha +.put_cl lda io_base+io_pic_int + and #$08 + beq .put_cl + pla + sta io_base+io_uart_xmt + rts + +.prtbyt pha + lsr a + lsr a + lsr a + lsr a + jsr .hexta + pla + +.hexta and #$0f + cmp #$0a + clc + bmi .hexta1 + adc #$07 +.hexta1 adc #$30 + jmp .put_c + + +.delay lda #$ff + clc + adc #$01 + bne .delay + rts + + + + + +.start lda #$ff + sta io_base+io_ps2_xmit + +.loop_f0 lda io_base+io_ps2_stat + and #$40 + beq .loop_f0 + lda io_base+io_ps2_rcv + nop + jsr .delay + +.loop_aa lda io_base+io_ps2_stat + and #$40 + beq .loop_aa + lda io_base+io_ps2_rcv + nop + jsr .delay + +.loop_00 lda io_base+io_ps2_stat + and #$40 + beq .loop_00 + lda io_base+io_ps2_rcv + jsr .delay + + + lda #$f3 + sta io_base+io_ps2_xmit + +.loop_f1 lda io_base+io_ps2_stat + and #$40 + beq .loop_f1 + lda io_base+io_ps2_rcv + nop + + jsr .delay + + + lda #$c8 + + sta io_base+io_ps2_xmit + +.loop_f2 lda io_base+io_ps2_stat + and #$40 + beq .loop_f2 + lda io_base+io_ps2_rcv + nop + + + + + jsr .delay + + + + lda #$f3 + + sta io_base+io_ps2_xmit + +.loop_f3 lda io_base+io_ps2_stat + and #$40 + beq .loop_f3 + lda io_base+io_ps2_rcv + nop + + + + + jsr .delay + + + + lda #$64 + + sta io_base+io_ps2_xmit + +.loop_f4 lda io_base+io_ps2_stat + and #$40 + beq .loop_f4 + lda io_base+io_ps2_rcv + nop + + + + jsr .delay + + + + + lda #$f3 + + sta io_base+io_ps2_xmit + +.loop_f5 lda io_base+io_ps2_stat + and #$40 + beq .loop_f5 + lda io_base+io_ps2_rcv + nop + + + + + jsr .delay + + + + lda #$50 + + + + sta io_base+io_ps2_xmit + +.loop_f6 lda io_base+io_ps2_stat + and #$40 + beq .loop_f6 + lda io_base+io_ps2_rcv + nop + + + + + jsr .delay + + + lda #$f2 + + + + + sta io_base+io_ps2_xmit + +.loop_f7 lda io_base+io_ps2_stat + and #$40 + beq .loop_f7 + lda io_base+io_ps2_rcv + nop + + + + jsr .delay + + + + + +.loop_fa8 lda io_base+io_ps2_stat + and #$40 + beq .loop_fa8 + lda io_base+io_ps2_rcv + jsr .delay + + + + lda #$e8 + + + + sta io_base+io_ps2_xmit + +.loop_f9 lda io_base+io_ps2_stat + and #$40 + beq .loop_f9 + lda io_base+io_ps2_rcv + nop + + + + + + jsr .delay + + + lda #$03 + + sta io_base+io_ps2_xmit + +.loop_fa lda io_base+io_ps2_stat + and #$40 + beq .loop_fa + lda io_base+io_ps2_rcv + nop + + + + + + jsr .delay + + + lda #$f3 + + sta io_base+io_ps2_xmit + +.loop_fb lda io_base+io_ps2_stat + and #$40 + beq .loop_fb + lda io_base+io_ps2_rcv + nop + + + + + + jsr .delay + + + + lda #$28 + + + + sta io_base+io_ps2_xmit + +.loop_fc lda io_base+io_ps2_stat + and #$40 + beq .loop_fc + lda io_base+io_ps2_rcv + nop + + + + + jsr .delay + + + lda #$f4 + + + sta io_base+io_ps2_xmit + +.loop_fd lda io_base+io_ps2_stat + and #$40 + beq .loop_fd + lda io_base+io_ps2_rcv + nop + + + + nop + + + nop + nop + nop + nop + nop + lda #$01 + + sta io_base+io_ps2_cntrl + + + + lda #$c0 + sta io_base+io_uart_cnt + ldx #$00 + ldy #$00 + lda #$fa + sta address + lda #$ff + sta address+1 + +.prn_add ldy #$00 + lda address+1 + jsr .prtbyt + lda address + jsr .prtbyt + lda #$20 + jsr .put_c + + + ldy #$00 + lda (address),y + jsr .prtbyt + lda #$20 + jsr .put_c + + ldx #$00 + +.lab_01 lda .str_1,X ; + beq .lab_80 + jsr .put_c + inx + bne .lab_01 ; +.lab_80 lda #$0d + jsr .put_c + lda #$0a + jsr .put_c + +.lab_81 lda io_base+io_ps2_xpos + sta io_base+io_gpio_0 + lda io_base+io_ps2_ypos + sta io_base+io_gpio_1 + + + lda io_base+io_pic_int + + and #$04 + beq .lab_81 + lda io_base+io_uart_rcv + inc address + bne .prn_add + inc address+1 + jmp .prn_add + + + + +.irq_vec pha + txa + tax + pla + rti + +.nmi_vec pha + pla + rti + + + * = $fffa ; vectors + + + dw .nmi_vec ; + dw .start ; + dw .irq_vec ; + + code + + + + + + Index: trunk/projects/Mos6502/sw/tim_1/tim_1.asm =================================================================== --- trunk/projects/Mos6502/sw/tim_1/tim_1.asm (nonexistent) +++ trunk/projects/Mos6502/sw/tim_1/tim_1.asm (revision 28) @@ -0,0 +1,267 @@ + + + cpu 6502 + output HEX + dummy + +io_base = $8000 ; + +io_gpio_0 = $02 ; +io_gpio_1 = $06 ; + +io_tim0_start = $10 ; +io_tim0_count = $12 ; +io_tim0_end = $14 ; + +io_tim1_start = $18 ; +io_tim0_count = $1A ; +io_tim1_end = $1C ; + +io_uart_xmt = $20 ; +io_uart_rcv = $22 ; +io_uart_cnt = $24 ; +io_uart_stat = $26 ; + + +io_pic_int = $30 ; +io_pic_irq_en = $32 ; +io_pic_nmi_en = $34 ; +io_pic_irq_ac = $36 ; +io_pic_nmi_ac = $38 ; + +io_ps2_data = $40 ; +io_ps2_stat = $42 ; +io_ps2_cntrl = $44 ; +io_ps2_xpos = $46 ; +io_ps2_ypos = $48 ; + + +io_utim_lat = $50 ; +io_utim_cnt = $52 ; + +io_vga_ascii = $60 ; +io_vga_addl = $62 ; +io_vga_addh = $64 ; +io_vga_cntrl = $66 ; + + +address = $00 + + + + * = $fc00 ; assemble start + code + +.str_1 ASC "Mem " ; + DB $00 ; + +.put_c pha +.put_cl lda io_base+io_pic_int + and #$08 + beq .put_cl + pla + sta io_base+io_uart_xmt + rts + +.prtbyt pha + lsr a + lsr a + lsr a + lsr a + jsr .hexta + pla + +.hexta and #$0f + cmp #$0a + clc + bmi .hexta1 + adc #$07 +.hexta1 adc #$30 + jmp .put_c + + +.delay lda #$ff + clc + adc #$01 + bne .delay + rts + + +.send_ps sta io_base+io_ps2_data + lda #$64 + sta io_base+io_utim_cnt + lda #$02 + sta io_base+io_ps2_cntrl +.lp_100 lda io_base+io_utim_cnt + bne .lp_100 + lda #$00 + sta io_base+io_ps2_cntrl + +.rcv_ps lda io_base+io_ps2_stat + and #$40 + beq .rcv_ps + lda io_base+io_ps2_data + nop + rts + + +.start lda #$ff + jsr .send_ps + jsr .rcv_ps + jsr .rcv_ps + + jsr .delay + jsr .delay + jsr .delay + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$c8 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$64 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$50 + jsr .send_ps + jsr .delay + + + lda #$f2 + jsr .send_ps + jsr .delay + + jsr .rcv_ps + jsr .delay + + lda #$e8 + jsr .send_ps + jsr .delay + + lda #$03 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$28 + jsr .send_ps + jsr .delay + + lda #$f4 + jsr .send_ps + + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + lda #$01 + sta io_base+io_ps2_cntrl + + + + lda #$c0 + sta io_base+io_uart_cnt + ldx #$00 + ldy #$00 + lda #$fa + sta address + lda #$ff + sta address+1 + +.prn_add ldy #$00 + lda address+1 + jsr .prtbyt + lda address + jsr .prtbyt + lda #$20 + jsr .put_c + + + ldy #$00 + lda (address),y + jsr .prtbyt + lda #$20 + jsr .put_c + + ldx #$00 + +.lab_01 lda .str_1,X ; + beq .lab_80 + jsr .put_c + inx + bne .lab_01 ; +.lab_80 lda #$0d + jsr .put_c + lda #$0a + jsr .put_c + +.lab_81 lda io_base+io_ps2_xpos + sta io_base+io_gpio_0 + lda io_base+io_ps2_ypos + sta io_base+io_gpio_1 + + lda io_base+io_pic_int + + and #$04 + beq .lab_81 + lda io_base+io_uart_rcv + sta io_base+io_vga_ascii + inc address + bne .prn_add + inc address+1 + jmp .prn_add + + + + +.irq_vec pha + txa + tax + pla + rti + +.nmi_vec pha + pla + rti + + + * = $fffa ; vectors + + + dw .nmi_vec ; + dw .start ; + dw .irq_vec ; + + code + + + + + + Index: trunk/projects/Mos6502/sw/tim_1/Makefile =================================================================== --- trunk/projects/Mos6502/sw/tim_1/Makefile (nonexistent) +++ trunk/projects/Mos6502/sw/tim_1/Makefile (revision 28) @@ -0,0 +1,4 @@ +include ../../bin/Makefile.root +code=tim_1 + +all: asm_6502 Index: trunk/projects/Mos6502/sw/tim_1/tim_1.asm.xxx =================================================================== --- trunk/projects/Mos6502/sw/tim_1/tim_1.asm.xxx (nonexistent) +++ trunk/projects/Mos6502/sw/tim_1/tim_1.asm.xxx (revision 28) @@ -0,0 +1,261 @@ + + + cpu 6502 + output HEX + dummy + +io_base = $8000 ; + +io_gpio_0 = $02 ; +io_gpio_1 = $06 ; + +io_tim0_start = $10 ; +io_tim0_count = $12 ; +io_tim0_end = $14 ; + +io_tim1_start = $18 ; +io_tim0_count = $1A ; +io_tim1_end = $1C ; + +io_uart_xmt = $20 ; +io_uart_rcv = $22 ; +io_uart_cnt = $24 ; +io_uart_stat = $26 ; + + +io_pic_int = $30 ; +io_pic_irq_en = $32 ; +io_pic_nmi_en = $34 ; +io_pic_irq_ac = $36 ; +io_pic_nmi_ac = $38 ; + +io_ps2_data = $40 ; +io_ps2_stat = $42 ; +io_ps2_cntrl = $44 ; +io_ps2_xpos = $46 ; +io_ps2_ypos = $48 ; + + +io_utim_lat = $50 ; +io_utim_cnt = $52 ; + +address = $00 + + + + * = $fc00 ; assemble start + code + +.str_1 ASC "Mem " ; + DB $00 ; + +.put_c pha +.put_cl lda io_base+io_pic_int + and #$08 + beq .put_cl + pla + sta io_base+io_uart_xmt + rts + +.prtbyt pha + lsr a + lsr a + lsr a + lsr a + jsr .hexta + pla + +.hexta and #$0f + cmp #$0a + clc + bmi .hexta1 + adc #$07 +.hexta1 adc #$30 + jmp .put_c + + +.delay lda #$ff + clc + adc #$01 + bne .delay + rts + + +.send_ps sta io_base+io_ps2_data + lda #$64 + sta io_base+io_utim_cnt + lda #$02 + sta io_base+io_ps2_cntrl +.lp_100 lda io_base+io_utim_cnt + bne .lp_100 + lda #$00 + sta io_base+io_ps2_cntrl + +.rcv_ps lda io_base+io_ps2_stat + and #$40 + beq .rcv_ps + lda io_base+io_ps2_data + nop + rts + + +.start lda #$ff + jsr .send_ps + jsr .rcv_ps + jsr .rcv_ps + + jsr .delay + jsr .delay + jsr .delay + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$c8 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$64 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$50 + jsr .send_ps + jsr .delay + + + lda #$f2 + jsr .send_ps + jsr .delay + + jsr .rcv_ps + jsr .delay + + lda #$e8 + jsr .send_ps + jsr .delay + + lda #$03 + jsr .send_ps + jsr .delay + + lda #$f3 + jsr .send_ps + jsr .delay + + lda #$28 + jsr .send_ps + jsr .delay + + lda #$f4 + jsr .send_ps + + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + lda #$01 + sta io_base+io_ps2_cntrl + + + + lda #$c0 + sta io_base+io_uart_cnt + ldx #$00 + ldy #$00 + lda #$fa + sta address + lda #$ff + sta address+1 + +.prn_add ldy #$00 + lda address+1 + jsr .prtbyt + lda address + jsr .prtbyt + lda #$20 + jsr .put_c + + + ldy #$00 + lda (address),y + jsr .prtbyt + lda #$20 + jsr .put_c + + ldx #$00 + +.lab_01 lda .str_1,X ; + beq .lab_80 + jsr .put_c + inx + bne .lab_01 ; +.lab_80 lda #$0d + jsr .put_c + lda #$0a + jsr .put_c + +.lab_81 lda io_base+io_ps2_xpos + sta io_base+io_gpio_0 + lda io_base+io_ps2_ypos + sta io_base+io_gpio_1 + + + lda io_base+io_pic_int + + and #$04 + beq .lab_81 + lda io_base+io_uart_rcv + inc address + bne .prn_add + inc address+1 + jmp .prn_add + + + + +.irq_vec pha + txa + tax + pla + rti + +.nmi_vec pha + pla + rti + + + * = $fffa ; vectors + + + dw .nmi_vec ; + dw .start ; + dw .irq_vec ; + + code + + + + + + Index: trunk/projects/Mos6502/sw/io_poll/io_poll.asm =================================================================== --- trunk/projects/Mos6502/sw/io_poll/io_poll.asm (nonexistent) +++ trunk/projects/Mos6502/sw/io_poll/io_poll.asm (revision 28) @@ -0,0 +1,83 @@ + + + cpu 6502 + output HEX +io_base = $8000 ; +io_gpio_0 = $02 ; +io_gpio_1 = $06 ; +io_tim0_start = $10 ; +io_tim0_end = $14 ; +io_tim1_start = $18 ; +io_tim1_end = $1C ; + +io_uart_xmt = $20 ; +io_uart_rcv = $22 ; +io_uart_cnt = $24 ; +io_uart_stat = $26 ; + + +io_pic_irq = $30 ; + + + + * = $f800 ; assemble start + code + +.start nop + ldx #00 + ldy #00 + lda io_base+io_gpio_0 + sec + adc #00 + sta io_base+io_gpio_0 + lda io_base+io_gpio_0 + sec + adc #00 + sta io_base+io_gpio_0 + + + + + lda #$c0 + sta io_base+io_uart_cnt + lda #$42 + sta io_base+io_uart_xmt + +.lab_80 lda io_base+io_pic_irq + sta io_base+io_gpio_1 + and #$04 + beq .lab_80 + lda io_base+io_uart_rcv + sec + adc #01 + sta io_base+io_uart_xmt + inc io_base+io_gpio_0 + jmp .lab_80 + + + + +.irq_vec pha + txa + tax + pla + rti + +.nmi_vec pha + pla + rti + + * = $fffa ; vectors + + + dw .nmi_vec ; + dw .start ; + dw .irq_vec ; + + code + + + + + + Index: trunk/projects/Mos6502/sw/io_poll/Makefile =================================================================== --- trunk/projects/Mos6502/sw/io_poll/Makefile (nonexistent) +++ trunk/projects/Mos6502/sw/io_poll/Makefile (revision 28) @@ -0,0 +1,5 @@ +include ../../bin/Makefile.root +code=io_poll + +all: asm_6502 + Index: trunk/projects/Mos6502/sw/vga_startup_screen/Makefile =================================================================== --- trunk/projects/Mos6502/sw/vga_startup_screen/Makefile (nonexistent) +++ trunk/projects/Mos6502/sw/vga_startup_screen/Makefile (revision 28) @@ -0,0 +1,5 @@ +include ../../bin/Makefile.root +code=vga_startup_screen + + +all: asm_6502 \ No newline at end of file Index: trunk/projects/Mos6502/sw/vga_startup_screen/vga_startup_screen.asm =================================================================== --- trunk/projects/Mos6502/sw/vga_startup_screen/vga_startup_screen.asm (nonexistent) +++ trunk/projects/Mos6502/sw/vga_startup_screen/vga_startup_screen.asm (revision 28) @@ -0,0 +1,69 @@ + + + cpu 6502 + output HEX + + * = $0000 ; + code + ASC "+------------------------------------------------------------------------------+"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| SOCGEN Project |"; + ASC "| M6502 |"; + ASC "| |"; + ASC "| abcdefghijklmnopqrstuvwxyz |"; + ASC "| |"; + ASC "| ABCDEFGHIJKLMNOPQRSTUVWXYZ |"; + ASC "| |"; + ASC "| 1234567890 |"; + ASC "| |"; + ASC "| `~!@#$%^&*()-_=+[{]}|;:,<.>? |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| dddddddddddddddddddddddddddddddddddddddddddddddddddd |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "| |"; + ASC "+------------------------------------------------------------------------------+"; + + code \ No newline at end of file Index: trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v =================================================================== --- trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v (revision 27) +++ trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v (revision 28) @@ -271,8 +271,8 @@ .reset ( reset ), .edge_enable ( ( load_tx_data && force_startbit) || ps2_clk_fall ), // one pulse per bit time for data rate timing .parity_enable (1'b1 ), // 0 = no parity bit sent, 1= parity bit sent - .two_stop_enable (1'b0 ), // 0 = 1 stop bit, 1 = 2 stop bits - .parity_type (2'b00 ), // 00= odd,01=even,10=force a 0,11= force a 1 + .parity_type (1'b0 ), // 0= odd + .parity_force (1'b0 ), // no force .load ( load_tx_data && force_startbit ), // start transmiting data .start_value (1'b1 ), // value out at start bit time .stop_value (1'b0 ), // value out for stop bit also used for break @@ -290,7 +290,8 @@ .reset ( reset ||(ps2_clk_s && ps2_data_s && !busy) ), .edge_enable ( ps2_clk_fall ), // one pulse per bit time for 16 x data rate timing .parity_enable (1'b1 ), // 0 = no parity bit sent, 1= parity bit sent - .parity_type (2'b01 ), // 00= odd,01=even,10=force a 0,11= force a 1 + .parity_type (1'b1 ), // 1= odd,0=even + .parity_force (1'b0 ), // don't force .stop_value (1'b1 ), // value out for stop bit .ser_in ( ps2_data_s ), // from pad_ring .shift_buffer ( x_shift_buffer ), Index: trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v =================================================================== --- trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v (revision 27) +++ trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v (revision 28) @@ -2,7 +2,10 @@ `include "ps2_interface_defines.v" + module `VARIANT`FSM + + #(parameter NUMBITS=11) (
/trunk/projects/logic/ip/disp_io/sim/run/default/TB.defs
1,2 → 1,2
`define PERIOD 20.00000
`define PERIOD 40.00000
 
/trunk/projects/logic/ip/disp_io/sim/run/default/dut
16,6 → 16,9
wire [3:0] PosB;
 
 
wire clk_tgen;
wire out_tgen;
wire in_tgen;
 
 
disp_io
37,5 → 40,98
 
 
 
reg [3:0] test_cnt;
wire [3:0] test_cnt_src;
 
reg [3:0] test_tar;
 
always@(posedge clk)
if(reset ) test_cnt <= 4'h0;
else test_cnt <= test_cnt+4'b0001;
 
always@(posedge clk)
if(reset ) test_tar <= 4'h0;
else test_tar <= test_tar+4'b0011;
 
 
 
timing_gen
#(.DELAY(10),
.WIDTH(20))
clk_tgenx
( .clk (clk),
.reset (reset),
.tgen (clk_tgen));
 
 
timing_gen
#(.DELAY(5),
.WIDTH(35))
out_tgenx
( .clk (clk),
.reset (reset),
.tgen (out_tgen));
 
 
 
timing_gen
#(.DELAY(15),
.WIDTH(25))
in_tgenx
( .clk (clk),
.reset (reset),
.tgen (in_tgen));
 
 
 
 
ic_test_probe
clk_timer ( .signal ( clk_src ),
.assert_value ( 1'b1 ),
.drive_value ( 1'b1 ),
.clk ( clk ),
.tgen_out ( clk_tgen ),
.probe_type (2'b10 )
);
 
 
 
/*
 
ic_test_probe
#(.SIGNAL_WIDTH(4))
test_cnt_timer
(.signal ( test_cnt_src ),
.assert_value ( 1'b1 ),
.drive_value ( test_cnt ),
.clk ( clk ),
.tgen_out ( out_tgen ),
.probe_type (2'b00 )
);
 
*/
 
timed_driver
#(.WIDTH(4),
.PROBE_TYPE(2'b00))
test_cnt_timer (
.clk ( clk ),
.signal ( test_cnt_src ),
.drive_value ( test_cnt ),
.tgen ( out_tgen )
);
 
 
timed_tester
#(.WIDTH(4))
tx
(
.clk ( clk ),
.expected_value ( test_tar ),
.mask (4'b1001 ),
.tgen ( in_tgen ),
.signal ( test_cnt_src ),
.filtered_value ( ),
.fail ( )
 
);
/trunk/projects/logic/ip/disp_io/sim/run/default/modellist
1,3 → 1,4
`include "../../bench/verilog/models/clock_gen.v"
 
 
`include "../../bench/verilog/models/timing_gen.v"
`include "../../bench/verilog/models/timed_driver.v"
`include "../../bench/verilog/models/timed_tester.v"
/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/serial_rcvr.v
41,51 → 41,52
 
module
`VARIANT
#(parameter WIDTH=8, // Number of data bits
parameter SIZE=4, // binary size of shift_cnt, must be able to hold WIDTH + 4 states
parameter SAMPLE=4'b0111 // point at which the sample is taken in the data stream
)
 
 
(
#(parameter WIDTH=8, // Number of data bits
parameter SIZE=4, // binary size of shift_cnt, must be able to hold WIDTH + 4 states
parameter SAMPLE=4'b0111, // point at which the sample is taken in the data stream
parameter RX_FIFO=0,
parameter RX_FIFO_SIZE=4,
parameter RX_FIFO_WORDS=16
)(
input wire clk,
input wire reset,
input wire edge_enable, // one pulse per bit time for 16 x data rate timing
input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent
input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1
 
input wire parity_type, // 1= odd,0=even
input wire parity_force, // 1=force to parity_type
input wire start_value, // value out at start bit time
input wire stop_value, // value out for stop bit also used for break
input wire pad_in, // from pad_ring
input wire rcv_stb, // byte taken
 
output reg start_detect,
output reg [WIDTH-1:0] shift_buffer,
output reg parity_calc,
output reg parity_samp,
output reg parity_error,
output reg frame_err,
output reg frame_rdy
 
output wire [WIDTH-1:0] data_out,
output wire parity_error,
output wire stop_error,
output wire data_avail
);
 
 
wire baud_enable;
wire stop_cnt;
wire last_cnt;
wire [WIDTH-1:0] next_shift_buffer;
wire next_parity_calc;
wire next_parity_samp;
wire next_frame_err;
wire baud_enable;
wire stop_cnt;
wire last_cnt;
wire [WIDTH-1:0] next_shift_buffer;
wire next_parity_calc;
wire next_parity_samp;
wire next_frame_error;
reg parity_calc;
reg parity_samp;
reg frame_rdy;
reg start_detect;
reg rxd_pad_sig;
reg [1:0] rdy_del;
 
//
// watch for start bit
//
 
 
reg rxd_pad_sig;
reg [1:0] rdy_del;
reg [WIDTH-1:0] shift_buffer;
reg frame_parity_error;
reg frame_error;
reg frame_avail;
always@(posedge clk)
if(reset) rxd_pad_sig <= 1'b1;
129,6 → 130,7
.edge_enable ( baud_enable ),
.parity_enable ( parity_enable ),
.parity_type ( parity_type ),
.parity_force ( parity_force ),
.stop_cnt ( stop_cnt ),
.last_cnt ( last_cnt ),
.stop_value ( stop_value ),
136,7 → 138,7
.shift_buffer ( next_shift_buffer ),
.parity_calc ( next_parity_calc ),
.parity_samp ( next_parity_samp ),
.frame_err ( next_frame_err )
.frame_err ( next_frame_error )
);
cde_divider
155,6 → 157,17
);
 
 
 
always@(posedge clk)
if (reset) frame_avail <= 1'b0;
else
if(frame_rdy) frame_avail <= 1'b1;
else
if(rcv_stb) frame_avail <= 1'b0;
else frame_avail <= frame_avail;
 
 
always@(posedge clk)
if(reset)
begin
161,8 → 174,8
shift_buffer <= 8'h00;
parity_calc <= 1'b0;
parity_samp <= 1'b0;
parity_error <= 1'b0;
frame_err <= 1'b0;
frame_parity_error <= 1'b0;
frame_error <= 1'b0;
end
else
if(last_cnt )
170,8 → 183,8
shift_buffer <= next_shift_buffer;
parity_calc <= next_parity_calc;
parity_samp <= next_parity_samp;
parity_error <= next_parity_samp ^ next_parity_calc;
frame_err <= next_frame_err;
frame_parity_error <= (next_parity_samp ^ next_parity_calc) && parity_enable;
frame_error <= next_frame_error;
end
else
begin
178,11 → 191,78
shift_buffer <= shift_buffer;
parity_calc <= parity_calc;
parity_samp <= parity_samp;
parity_error <= parity_error;
frame_err <= frame_err;
frame_parity_error <= frame_parity_error;
frame_error <= frame_error;
end
 
 
generate
 
if(RX_FIFO == 0)
begin
 
 
 
assign data_out = shift_buffer;
assign parity_error = frame_parity_error;
assign stop_error = frame_error;
assign data_avail = frame_avail ;
 
 
 
end
else
begin
 
 
 
wire fifo_full;
wire fifo_empty;
wire fifo_over_run;
wire fifo_under_run;
cde_fifo
#(.WIDTH(WIDTH+2),
.SIZE(RX_FIFO_SIZE),
.WORDS(RX_FIFO_WORDS)
)
fifo
(
.clk ( clk ),
.reset ( reset ),
.push ( last_cnt ),
.din ( {next_frame_error, (next_parity_samp ^ next_parity_calc) && parity_enable ,next_shift_buffer} ),
.pop ( rcv_stb ),
.dout ( { stop_error, parity_error , data_out } ),
.full ( fifo_full ),
.empty ( fifo_empty ),
.over_run ( fifo_over_run ),
.under_run ( fifo_under_run )
);
 
assign data_avail = !fifo_empty ;
 
 
 
end // else: !if(RX_FIFO == 0)
 
endgenerate
 
 
 
 
 
 
 
endmodule
 
 
/trunk/projects/logic/ip/serial_rcvr/sim/run/default/liblist
1,2 → 1,5
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_divider/cde_divider.v"
`include "../../lib/cde_fifo/cde_fifo.v"
`include "../../lib/cde_sram/cde_sram.v"
 
/trunk/projects/logic/ip/serial_rcvr/sim/run/default/test_define
24,10 → 24,12
 
edge_enable = 1'b0;
parity_enable = 1'b1;
parity_type = 2'b00;
parity_type = 1'b0;
parity_force = 1'b0;
start_value = 1'b0;
stop_value = 1'b1;
pad_in = 1'b1;
rcv_stb = 1'b0;
 
cg.next(12);
cg.reset_off;
34,7 → 36,6
cg.next(88);
 
$display("%t Test enabled ",$realtime );
parity_type = 2'b00;
parity_enable = 1'b1;
pad_in = 1'b0;
cg.next(1800);
/trunk/projects/logic/ip/serial_rcvr/sim/run/default/dut
1,22 → 1,24
 
reg edge_enable;
reg parity_enable;
reg [1:0] parity_type;
reg parity_type;
reg parity_force;
reg start_value;
reg stop_value;
 
reg rcv_stb;
reg pad_in;
 
wire start_detect;
wire [7:0] shift_buffer;
 
wire parity_calc;
wire parity_samp;
wire frame_err;
wire frame_rdy;
wire [7:0] data_out;
 
wire data_avail;
wire parity_error;
wire stop_error;
 
 
 
 
serial_rcvr
dut(
.clk ( clk ),
24,18 → 26,16
.edge_enable ( edge_enable ),
.parity_enable ( parity_enable ),
.parity_type ( parity_type ),
 
.parity_force ( parity_force ),
.start_value ( start_value ),
.stop_value ( stop_value ),
.pad_in ( pad_in ),
 
.start_detect ( start_detect ),
.shift_buffer ( shift_buffer ),
.parity_calc ( parity_calc ),
.parity_samp ( parity_samp ),
.frame_err ( frame_err ),
.frame_rdy ( frame_rdy )
.rcv_stb ( rcv_stb ),
.data_out ( data_out ),
.parity_error ( parity_error ),
.stop_error ( stop_error ),
.data_avail ( data_avail )
);
 
 
/trunk/projects/logic/ip/uart/rtl/verilog/uart.v
38,82 → 38,63
#(parameter PRESCALE=5'b01100,
parameter PRE_SIZE=5,
parameter SIZE=8,
parameter DIV_SIZE=4
parameter DIV=0,
parameter DIV_SIZE=4,
parameter TX_FIFO=0,
parameter TX_FIFO_SIZE=3,
parameter TX_FIFO_WORDS=8,
parameter RX_FIFO=0,
parameter RX_FIFO_SIZE=3,
parameter RX_FIFO_WORDS=8
 
 
)
 
 
(
input wire clk,
input wire reset,
input wire parity_enable,
`ifdef DIV
 
input wire clk,
input wire reset,
input wire parity_enable,
input wire [DIV_SIZE-1:0] divider_in,
input wire cts_pad_in,
output reg rts_pad_out,
output wire txd_pad_out,
input wire rxd_pad_in,
output reg cts_out,
input wire rts_in,
 
input wire txd_parity,
input wire txd_force_parity,
input wire txd_load,
input wire txd_break,
input wire [SIZE-1:0] txd_data_in,
output wire txd_buffer_empty,
 
`endif
 
input wire rxd_data_avail_stb,
output wire rxd_data_avail,
 
input wire cts_pad_in,
output reg rts_pad_out,
output wire txd_pad_out,
input wire rxd_pad_in,
output reg cts_out,
input wire rts_in,
 
input wire txd_parity,
input wire txd_force_parity,
input wire txd_load,
input wire txd_break,
input wire [SIZE-1:0] txd_data_in,
output wire txd_buffer_empty,
 
 
input wire rxd_parity,
input wire rxd_force_parity,
output wire [SIZE-1:0] rxd_data_out,
output wire rxd_buffer_full,
output wire rxd_parity_error,
output wire rxd_stop_error
input wire rxd_parity,
input wire rxd_force_parity,
output wire [SIZE-1:0] rxd_data_out,
output wire rxd_parity_error,
output wire rxd_stop_error
);
 
 
wire baud_clk;
wire baud_clk_div;
wire [7:0] fifo_data_out;
wire fifo_full;
wire fifo_empty;
wire fifo_over_run;
wire fifo_under_run;
wire cde_buffer_empty;
reg xmit_start;
 
`ifdef SYNTHESIS
 
`else
always@(posedge rxd_buffer_full)
begin
 
 
$display("%t %m Received %h stop error %b parity error %b",
$realtime,rxd_data_out, rxd_stop_error,rxd_parity_error );
end
 
always@(negedge txd_load)
begin
 
if(!reset)
begin
$display("%t %m Sending %h parity %b ",
$realtime,txd_data_in,txd_parity );
end
 
end
 
`endif
 
 
 
always@(posedge clk)
if(reset) rts_pad_out <= 1'b0;
else rts_pad_out <= rts_in;
135,10 → 116,14
);
 
 
generate
 
`ifdef DIV
 
if(DIV == 0)
begin
assign baud_clk_div = baud_clk;
end
else
begin
cde_divider
#(.SIZE(DIV_SIZE))
baud_divider (
148,21 → 133,11
.enable ( baud_clk ),
.divider_out ( baud_clk_div )
);
end
 
endgenerate
 
`else
 
 
assign baud_clk_div = baud_clk;
 
`endif
 
 
 
 
cde_divider
#(.SIZE(4))
x_divider (
175,49 → 150,134
 
 
 
 
generate
 
if(TX_FIFO == 0)
begin
 
always@(*) xmit_start = txd_load;
assign fifo_data_out = txd_data_in;
assign txd_buffer_empty = cde_buffer_empty;
end
else
begin
 
 
always@(posedge clk)
if(reset)
begin
xmit_start <= 1'b0;
end
else
if( !fifo_empty && cde_buffer_empty && !xmit_start )
begin
xmit_start <= 1'b1;
end
else
begin
xmit_start <= 1'b0;
end
 
 
 
cde_fifo
#(.WIDTH(SIZE),
.SIZE(TX_FIFO_SIZE),
.WORDS(TX_FIFO_WORDS))
fifo
(
.clk ( clk ),
.reset ( reset ),
.push ( txd_load ),
.din ( txd_data_in ),
.pop ( !fifo_empty && cde_buffer_empty && ! xmit_start ),
.dout ( fifo_data_out ),
.full ( fifo_full ),
.empty ( fifo_empty ),
.over_run ( fifo_over_run ),
.under_run ( fifo_under_run )
);
 
 
assign txd_buffer_empty = !fifo_full;
end
 
endgenerate
 
cde_serial_xmit
cde_serial_xmit (
.clk ( clk ),
.reset ( reset ),
.edge_enable ( xmit_enable ),
.parity_enable ( parity_enable ),
.two_stop_enable ( 1'b0 ),
.parity_type ( {txd_force_parity, txd_parity } ),
.load ( txd_load ),
.start_value ( 1'b0 ),
.stop_value (!txd_break ),
.data ( txd_data_in ),
.buffer_empty ( txd_buffer_empty ),
.ser_out ( txd_pad_out )
.clk ( clk ),
.reset ( reset ),
.edge_enable ( xmit_enable ),
.parity_enable ( parity_enable ),
.parity_force ( txd_force_parity ),
.parity_type ( txd_parity ),
.load ( xmit_start ),
.start_value ( 1'b0 ),
.stop_value (!txd_break ),
.data ( fifo_data_out ),
.buffer_empty ( cde_buffer_empty ),
.ser_out ( txd_pad_out )
);
 
 
serial_rcvr
#(.RX_FIFO(RX_FIFO),
.RX_FIFO_SIZE(RX_FIFO_SIZE),
.RX_FIFO_WORDS(RX_FIFO_WORDS))
serial_rcvr(
.clk ( clk ),
.reset ( reset ),
.edge_enable ( baud_clk_div ),
.parity_enable ( parity_enable ),
.parity_type ({rxd_force_parity,rxd_parity} ),
.start_value ( 1'b0 ),
.stop_value ( 1'b1 ),
.pad_in ( rxd_pad_in ),
.start_detect ( rxd_busy ),
.shift_buffer ( rxd_data_out ),
.parity_calc ( rxd_parity_calc ),
.parity_samp ( rxd_parity_samp ),
.frame_err ( rxd_stop_error ),
.frame_rdy ( rxd_buffer_full )
.clk ( clk ),
.reset ( reset ),
.edge_enable ( baud_clk_div ),
.parity_enable ( parity_enable ),
.parity_type ( rxd_parity ),
.parity_force ( rxd_force_parity ),
.start_value ( 1'b0 ),
.stop_value ( 1'b1 ),
.pad_in ( rxd_pad_in ),
.rcv_stb ( rxd_data_avail_stb ),
.data_out ( rxd_data_out ),
.parity_error ( rxd_parity_error ),
.stop_error ( rxd_stop_error ),
.data_avail ( rxd_data_avail )
);
 
 
 
assign rxd_parity_error = (rxd_parity_calc ^ rxd_parity_samp) && parity_enable;
 
 
`ifdef SYNTHESIS
 
`else
always@(posedge serial_rcvr.frame_rdy)
begin
$display("%t %m Received %h stop error %b parity error %b",
$realtime,serial_rcvr.shift_buffer, serial_rcvr.frame_error,serial_rcvr.frame_parity_error );
end
 
always@(negedge xmit_start)
begin
if(!reset)
begin
$display("%t %m Sending %h",
$realtime,fifo_data_out );
end
end
 
`endif
 
 
 
 
 
endmodule
 
 
/trunk/projects/logic/ip/uart/sim/run/default/liblist
1,5 → 1,8
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_divider/cde_divider.v"
`include "../../lib/cde_fifo/cde_fifo.v"
`include "../../lib/cde_sram/cde_sram.v"
 
 
 
/trunk/projects/logic/ip/uart/sim/run/default/test_define
37,7 → 37,9
uart_host.send_byte(8'h12);
cg.next(30);
uart_host.send_byte(8'h34);
cg.next(100);
 
 
cg.next(40000);
uart_host.rcv_byte(8'h66);
cg.next(100);
 
49,6 → 51,12
 
uart_host.rcv_byte(8'h56);
cg.next(100);
uart_host.rcv_byte(8'h78);
cg.next(100);
uart_host.rcv_byte(8'h9a);
cg.next(100);
uart_host.rcv_byte(8'hbc);
cg.next(100);
 
end
 
79,14 → 87,26
uart_model.rcv_byte(8'h12);
cg.next(10);
uart_model.rcv_byte(8'h34);
cg.next(100);
cg.next(10);
uart_model.send_byte(8'h66);
cg.next(100);
cg.next(10);
uart_model.send_byte(8'h12);
cg.next(100);
cg.next(10);
uart_model.send_byte(8'h34);
cg.next(100);
cg.next(10);
uart_model.send_byte(8'h56);
cg.next(10);
uart_model.send_byte(8'h78);
cg.next(10);
uart_model.send_byte(8'h9a);
cg.next(10);
uart_model.send_byte(8'hbc);
 
 
 
 
 
 
end
 
join
/trunk/projects/logic/ip/uart/sim/run/default/dut
1,78 → 1,82
 
wire host_parity_enable ;
wire host_parity_enable ;
 
wire host_txd_parity ;
wire host_txd_force_parity ;
wire [7:0] host_txd_data_in ;
wire host_txd_buffer_empty ;
wire host_txd_load ;
wire host_txd_break ;
wire host_txd_parity ;
wire host_txd_force_parity ;
wire [7:0] host_txd_data_in ;
wire host_txd_buffer_empty ;
wire host_txd_load ;
wire host_txd_break ;
 
wire host_rxd_parity ;
wire host_rxd_force_parity ;
wire [7:0] host_rxd_data_out ;
wire host_rxd_buffer_full ;
wire host_rxd_stop_error ;
wire host_rxd_parity_error ;
wire host_rxd_parity ;
wire host_rxd_force_parity ;
wire [7:0] host_rxd_data_out ;
wire host_rxd_data_avail ;
wire host_rxd_data_avail_stb ;
wire host_rxd_stop_error ;
wire host_rxd_parity_error ;
wire host_rx_data_avail ;
 
 
 
uart
#(
.RX_FIFO(1),
.RX_FIFO_SIZE(4),
.RX_FIFO_WORDS(16),
.TX_FIFO(1),
.TX_FIFO_SIZE(3),
.TX_FIFO_WORDS(8))
dut(
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_buffer_full ( host_rxd_buffer_full ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error ),
.txd_pad_out ( serial_txd ),
.rxd_pad_in ( serial_rxd ),
.cts_pad_in ( 1'b0 ),
.rts_pad_out ( ),
.cts_out ( ),
.rts_in ( 1'b0 )
 
 
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.divider_in ( 4'b0000 ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error ),
.rxd_data_avail ( host_rxd_data_avail ),
.rxd_data_avail_stb ( host_rxd_data_avail_stb ),
.txd_pad_out ( serial_txd ),
.rxd_pad_in ( serial_rxd ),
.cts_pad_in ( 1'b0 ),
.rts_pad_out ( ),
.cts_out ( ),
.rts_in ( 1'b0 )
);
 
 
 
 
uart_host
uart_host(
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_buffer_full ( host_rxd_buffer_full ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error )
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_data_avail ( host_rxd_data_avail ),
.rxd_data_avail_stb ( host_rxd_data_avail_stb ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error )
);
 
 
 
 
 
 
uart_model #(.CLKCNT(4'hc))
uart_model (
uart_model #(.CLKCNT(4'hc))
uart_model (
.clk ( clk ),
.reset ( reset ),
.txd_in ( serial_txd ),
/trunk/projects/logic/ip/uart/sim/run/divide/liblist
1,4 → 1,6
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_divider/cde_divider.v"
`include "../../lib/cde_fifo/cde_fifo.v"
`include "../../lib/cde_sram/cde_sram.v"
 
/trunk/projects/logic/ip/uart/sim/run/divide/filelist
1,5 → 1,5
 
`include "../../../rtl/gen/sim/uart_div.v"
`include "../../../rtl/gen/sim/uart.v"
`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
 
 
/trunk/projects/logic/ip/uart/sim/run/divide/dut
11,36 → 11,39
wire host_rxd_parity ;
wire host_rxd_force_parity ;
wire [7:0] host_rxd_data_out ;
wire host_rxd_buffer_full ;
wire host_rxd_data_avail ;
wire host_rxd_data_avail_stb ;
wire host_rxd_stop_error ;
wire host_rxd_parity_error ;
 
 
uart_div
#(.DIV_SIZE(4))
uart
#(.DIV_SIZE(4),
.DIV(1))
dut(
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.divider_in ( 4'b1101 ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_buffer_full ( host_rxd_buffer_full ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error ),
.txd_pad_out ( serial_txd ),
.rxd_pad_in ( serial_rxd ),
.cts_pad_in ( 1'b0 ),
.rts_pad_out ( ),
.cts_out ( ),
.rts_in ( 1'b0 )
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.divider_in ( 4'b1101 ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_data_avail ( host_rxd_data_avail ),
.rxd_data_avail_stb ( host_rxd_data_avail_stb ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error ),
.txd_pad_out ( serial_txd ),
.rxd_pad_in ( serial_rxd ),
.cts_pad_in ( 1'b0 ),
.rts_pad_out ( ),
.cts_out ( ),
.rts_in ( 1'b0 )
 
 
);
50,21 → 53,22
 
uart_host
uart_host(
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_buffer_full ( host_rxd_buffer_full ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error )
.clk ( clk ),
.reset ( reset ),
.parity_enable ( host_parity_enable ),
.txd_parity ( host_txd_parity ),
.txd_force_parity ( host_txd_force_parity ),
.txd_data_in ( host_txd_data_in ),
.txd_buffer_empty ( host_txd_buffer_empty ),
.txd_load ( host_txd_load ),
.txd_break ( host_txd_break ),
.rxd_parity ( host_rxd_parity ),
.rxd_force_parity ( host_rxd_force_parity ),
.rxd_data_out ( host_rxd_data_out ),
.rxd_data_avail ( host_rxd_data_avail ),
.rxd_data_avail_stb ( host_rxd_data_avail_stb ),
.rxd_stop_error ( host_rxd_stop_error ),
.rxd_parity_error ( host_rxd_parity_error )
);
 
 
72,9 → 76,9
 
 
 
uart_model #(.CLKCNT(8'hbb),
uart_model #(.CLKCNT(8'hbb),
.SIZE (8))
uart_model (
uart_model (
.clk ( clk ),
.reset ( reset ),
.txd_in ( serial_txd ),
/trunk/projects/logic/ip/io_module/rtl/variants/io_module_mouse/io_module_defines.v
1,9 → 1,17
`define VARIANT io_module_mouse
 
`define UART _uart
`define PS2 _ps2
`define UTIMER _utimer
`define PIC _pic
 
`define TIMER _timer
`define TIMER_MICRO_REG _timer_micro_reg
`define GPIO _gpio
`define GPIO_MICRO_REG _gpio_micro_reg
`define UART _uart
`define UART_MICRO_REG _uart_micro_reg
`define PS2 _ps2
`define PS2_MICRO_REG _ps2_micro_reg
`define UTIMER _utimer
`define UTIMER_MICRO_REG _utimer_micro_reg
`define PIC _pic
`define PIC_MICRO_REG _pic_micro_reg
 
`define CDE cde
/trunk/projects/logic/ip/io_module/rtl/variants/io_module/io_module_defines.v
1,10 → 1,19
 
`define VARIANT io_module
`define TIMER _timer
`define GPIO _gpio
`define UART _uart
`define PIC _pic
`define PS2 _ps2
`define UTIMER _utimer
`define TIMER _timer
`define TIMER_MICRO_REG _timer_micro_reg
`define GPIO _gpio
`define GPIO_MICRO_REG _gpio_micro_reg
`define UART _uart
`define UART_MICRO_REG _uart_micro_reg
`define PIC _pic
`define PIC_MICRO_REG _pic_micro_reg
`define PS2 _ps2
`define PS2_MICRO_REG _ps2_micro_reg
`define UTIMER _utimer
`define UTIMER_MICRO_REG _utimer_micro_reg
`define VGA _vga
`define VGA_MICRO_REG _vga_micro_reg
 
 
`define CDE cde
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module.v
7,7 → 7,15
parameter BASE_WIDTH = 8,
parameter ADDR_WIDTH = 16,
parameter NMI_MODE = 8'h00,
parameter IRQ_MODE = 8'h00
parameter IRQ_MODE = 8'h00,
parameter TX_FIFO = 0,
parameter TX_FIFO_SIZE = 3,
parameter TX_FIFO_WORDS = 8,
parameter RX_FIFO = 0,
parameter RX_FIFO_SIZE = 3,
parameter RX_FIFO_WORDS = 8,
parameter STARTUP = "NONE",
parameter FONT = "NONE"
)
(
 
88,8 → 96,20
 
`endif
 
 
,
output wire [2:0] vgared_pad_out,
output wire [2:0] vgagreen_pad_out,
output wire [1:0] vgablue_pad_out,
 
output wire hsync_n_pad_out,
output wire vsync_n_pad_out
 
 
);
 
 
114,7 → 134,7
wire [7:0] pic_rdata;
wire [7:0] ps2_rdata;
wire [7:0] utim_rdata;
 
wire [7:0] vga_rdata;
wire [7:0] out_data;
130,7 → 150,7
 
`ifdef GPIO
 
`VARIANT`GPIO
`VARIANT`GPIO_MICRO_REG
#(.BASE_ADDR(4'h0),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
137,24 → 157,33
)
gpio
(
.clk ( clk ),
.reset ( reset ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( gpio_rdata ),
.gpio_0_out ( gpio_0_out ),
.gpio_0_oe ( gpio_0_oe ),
.gpio_0_lat ( gpio_0_lat ),
.gpio_0_in ( gpio_0_in ),
.gpio_1_out ( gpio_1_out ),
.gpio_1_oe ( gpio_1_oe ),
.gpio_1_lat ( gpio_1_lat ),
.gpio_1_in ( gpio_1_in )
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( gpio_rdata ),
.gpio_0_out ( gpio_0_out ),
.next_gpio_0_out ( gpio_0_out ),
.gpio_0_oe ( gpio_0_oe ),
.next_gpio_0_oe ( gpio_0_oe ),
.gpio_0_lat ( gpio_0_lat ),
.gpio_0_in ( gpio_0_in ),
 
.gpio_1_out ( gpio_1_out ),
.next_gpio_1_out ( gpio_1_out ),
.gpio_1_oe ( gpio_1_oe ),
.next_gpio_1_oe ( gpio_1_oe ),
 
.gpio_1_lat ( gpio_1_lat ),
.gpio_1_in ( gpio_1_in )
 
);
 
`else
175,6 → 204,7
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
196,17 → 226,23
`ifdef UART
 
 
`VARIANT`UART
#(.BASE_ADDR(4'h2),
.BASE_WIDTH(4),
.ADDR_WIDTH(8)
#(.BASE_ADDR (4'h2),
.BASE_WIDTH (4),
.ADDR_WIDTH (8),
.TX_FIFO (TX_FIFO),
.TX_FIFO_SIZE (TX_FIFO_SIZE),
.TX_FIFO_WORDS (TX_FIFO_WORDS),
.RX_FIFO (RX_FIFO),
.RX_FIFO_SIZE (RX_FIFO_SIZE),
.RX_FIFO_WORDS (RX_FIFO_WORDS)
)
uart
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
247,6 → 283,7
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
280,6 → 317,7
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs && enable ),
.wr ( wr ),
.rd ( rd ),
323,6 → 361,7
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
340,9 → 379,61
 
`endif
 
 
 
 
 
`ifdef VGA
 
 
`VARIANT`VGA
#(.BASE_ADDR(4'h6),
.BASE_WIDTH(4),
.ADDR_WIDTH(8),
.STARTUP(STARTUP),
.FONT(FONT)
)
vga
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr && enable ),
.rd ( rd ),
.waddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.raddr ( addr[ADDR_WIDTH-BASE_WIDTH-1:0] ),
.wdata ( wdata ),
.rdata ( vga_rdata ),
 
.vgared_pad_out (vgared_pad_out),
.vgagreen_pad_out (vgagreen_pad_out),
.vgablue_pad_out (vgablue_pad_out),
 
.hsync_n_pad_out (hsync_n_pad_out),
.vsync_n_pad_out (vsync_n_pad_out)
 
);
 
 
`else
 
assign vga_rdata = 8'hff;
 
assign vgared_pad_out= 3'b000;
assign vgagreen_pad_out= 3'b000;
assign vgablue_pad_out= 2'b00;
 
assign hsync_n_pad_out= 1'b1;
assign vsync_n_pad_out= 1'b1;
 
`endif
 
 
endmodule
 
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_timer.v
12,6 → 12,7
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
28,6 → 29,8
 
 
 
parameter TIMER_0_START = 4'h0;
parameter TIMER_0_COUNT = 4'h2;
parameter TIMER_0_END = 4'h4;
66,9 → 69,9
if(rd && cs && ras)
begin
case(raddr[3:0])
TIMER_0_START: rdata = {4'h0,irq,state_0[2:0]};
TIMER_0_START: rdata = {4'h0,irq[0],state_0[2:0]};
TIMER_0_COUNT: rdata = count_0[7:0];
TIMER_1_START: rdata = {4'h0,irq,state_1[2:0]};
TIMER_1_START: rdata = {4'h0,irq[1],state_1[2:0]};
TIMER_1_COUNT: rdata = count_1[7:0];
default: rdata = 8'h00;
endcase
81,6 → 84,34
 
 
`VARIANT`TIMER_MICRO_REG
#(.BASE_ADDR (BASE_ADDR),
.BASE_WIDTH (BASE_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH)
)
io_module_timer_micro_reg
(
.clk ( clk ),
.reset ( reset ),
.cs ( cs ),
.wr ( wr ),
.rd ( rd ),
.waddr ( waddr ),
.raddr ( raddr ),
.wdata ( wdata ),
.rdata ( ),
.start_0 ({4'h0,irq[0],state_0[2:0]} ),
.count_0 ( count_0 ),
.start_1 ({4'h0,irq[1],state_1[2:0]} ),
.count_1 ( count_1 )
);
 
 
 
 
 
 
always@(posedge clk)
if(reset)
begin
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_pic_micro_reg.v
0,0 → 1,149
`include "io_module_defines"
 
`ifdef PIC
 
module `VARIANT`PIC_MICRO_REG
 
#(
parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8,
parameter IRQ_MODE = 8'h00,
parameter NMI_MODE = 8'h00
)
 
(
 
input wire clk,
input wire reset,
 
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
 
output reg [7:0] irq_enable,
output reg [7:0] nmi_enable,
output reg [7:0] irq_act,
output reg [7:0] nmi_act,
input wire [7:0] int_in,
input wire [7:0] next_irq_enable,
input wire [7:0] next_nmi_enable,
input wire [7:0] irq_act_in,
input wire [7:0] nmi_act_in
 
);
 
 
parameter INT_IN = 4'h0;
parameter IRQ_ENABLE = 4'h1;
parameter NMI_ENABLE = 4'h2;
parameter IRQ_ACT = 4'h3;
parameter NMI_ACT = 4'h4;
 
 
reg was;
reg ras;
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
INT_IN: rdata = int_in;
IRQ_ENABLE: rdata = irq_enable;
NMI_ENABLE: rdata = nmi_enable;
IRQ_ACT: rdata = irq_act;
NMI_ACT: rdata = nmi_act;
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
irq_enable <= IRQ_MODE;
end
else
if(wr && was && cs && waddr[3:0] == IRQ_ENABLE)
begin
irq_enable <= wdata;
end
else
begin
irq_enable <= next_irq_enable;
end
 
 
always@(posedge clk)
if (reset)
begin
nmi_enable <= NMI_MODE;
end
else
if(wr && was && cs && waddr[3:0] == NMI_ENABLE)
begin
nmi_enable <= wdata;
end
else
begin
nmi_enable <= next_nmi_enable;
end
 
 
always@(posedge clk)
if (reset)
begin
irq_act <= 8'h00;
end
else
if(rd && ras && cs && raddr[3:0] == IRQ_ACT)
begin
irq_act <= irq_act;
end
else
begin
irq_act <= irq_act_in;
end
 
 
always@(posedge clk)
if (reset)
begin
nmi_act <= 8'h00;
end
else
if(rd && ras && cs && raddr[3:0] == NMI_ACT)
begin
nmi_act <= nmi_act;
end
else
begin
nmi_act <= nmi_act_in;
end
 
 
 
endmodule
 
`endif // `ifdef PIC
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_uart_micro_reg.v
0,0 → 1,104
`include "io_module_defines"
 
`ifdef UART
 
module `VARIANT`UART_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)
 
(
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
output reg [7:0] lat_wdata,
input wire [7:0] rcv_data,
input wire [7:0] status,
 
output reg [7:0] cntrl,
output reg txd_load,
output reg load,
output reg rxd_data_avail_stb
 
);
 
 
 
 
parameter XMIT_DATA = 4'h0;
parameter RCV_DATA = 4'h2;
parameter CNTRL = 4'h4;
parameter STATUS = 4'h6;
reg was;
reg ras;
always@(posedge clk)
if (reset) lat_wdata <= 8'h00;
else lat_wdata <= wdata;
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
RCV_DATA: rdata = rcv_data;
CNTRL: rdata = cntrl;
STATUS: rdata = {status[7:0]};
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
cntrl <= 8'h00;
end
else
if(wr && was && cs && waddr[3:0] == CNTRL)
begin
cntrl <= wdata;
end
else
begin
cntrl <= cntrl;
end
 
 
always@(posedge clk)
if (reset)
begin
load <= 1'b0;
txd_load <= 1'b0;
rxd_data_avail_stb <= 1'b0;
end
else
begin
load <= txd_load;
txd_load <= (enable && wr && was && cs && (waddr[3:0] == XMIT_DATA));
rxd_data_avail_stb <= (enable && rd && was && cs && (waddr[3:0] == RCV_DATA ));
end
 
endmodule
 
 
`endif // `ifdef UART
 
 
 
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_vga_micro_reg.v
0,0 → 1,163
`include "io_module_defines"
 
`ifdef VGA
 
module `VARIANT`VGA_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)
 
(
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
input wire [15:0] vga_address,
 
output reg [7:0] rdata,
output reg [7:0] lat_wdata,
output reg [7:0] cntrl,
output reg [7:0] char_color,
output reg [7:0] back_color,
output reg [7:0] cursor_color,
output reg ascii_load,
output reg add_l_load,
output reg add_h_load
 
);
 
 
 
 
parameter ASCII_DATA = 4'h0;
parameter ADD_L = 4'h2;
parameter ADD_H = 4'h4;
parameter CNTRL = 4'h6;
parameter CHAR_COLOR = 4'h8;
parameter BACK_COLOR = 4'ha;
parameter CURSOR_COLOR = 4'hc;
reg was;
reg ras;
always@(posedge clk)
if (reset) lat_wdata <= 8'h00;
else lat_wdata <= wdata;
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
CNTRL: rdata = cntrl;
ADD_L: rdata = vga_address[7:0];
ADD_H: rdata = vga_address[15:8];
CHAR_COLOR: rdata = char_color;
BACK_COLOR: rdata = back_color;
CURSOR_COLOR: rdata = cursor_color;
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
cntrl <= 8'h00;
end
else
if(wr && was && cs && waddr[3:0] == CNTRL)
begin
cntrl <= wdata;
end
else
begin
cntrl <= cntrl;
end
 
always@(posedge clk)
if (reset)
begin
char_color <= 8'h1c;
end
else
if(wr && was && cs && waddr[3:0] == CHAR_COLOR)
begin
char_color <= wdata;
end
else
begin
char_color <= char_color;
end
 
always@(posedge clk)
if (reset)
begin
back_color <= 8'h01;
end
else
if(wr && was && cs && waddr[3:0] == BACK_COLOR)
begin
back_color <= wdata;
end
else
begin
back_color <= back_color;
end
 
always@(posedge clk)
if (reset)
begin
cursor_color <= 8'he0;
end
else
if(wr && was && cs && waddr[3:0] == CURSOR_COLOR)
begin
cursor_color <= wdata;
end
else
begin
cursor_color <= cursor_color;
end
 
 
 
 
 
always@(posedge clk)
if (reset)
begin
ascii_load <= 1'b0;
add_l_load <= 1'b0;
add_h_load <= 1'b0;
end
else
begin
ascii_load <= (enable && wr && was && cs && (waddr[3:0] == ASCII_DATA));
add_l_load <= (enable && wr && was && cs && (waddr[3:0] == ADD_L));
add_h_load <= (enable && wr && was && cs && (waddr[3:0] == ADD_H));
end
 
endmodule
 
 
`endif // `ifdef VGA
 
 
 
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2.v
12,6 → 12,7
(
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_gpio_micro_reg.v
0,0 → 1,203
`include "io_module_defines"
 
 
`ifdef GPIO
 
module `VARIANT`GPIO_MICRO_REG
 
#(
parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)
 
(
 
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
output reg [7:0] gpio_0_out,
input wire [7:0] next_gpio_0_out,
 
output reg [7:0] gpio_0_oe,
input wire [7:0] next_gpio_0_oe,
 
output reg [7:0] gpio_0_lat,
input wire [7:0] gpio_0_in,
 
output reg [7:0] gpio_1_out,
input wire [7:0] next_gpio_1_out,
 
output reg [7:0] gpio_1_oe,
input wire [7:0] next_gpio_1_oe,
 
output reg [7:0] gpio_1_lat,
input wire [7:0] gpio_1_in
 
);
 
 
parameter GPIO_0_IN = 4'h0;
parameter GPIO_0_OE = 4'h1;
parameter GPIO_0_OUT = 4'h2;
 
parameter GPIO_1_IN = 4'h4;
parameter GPIO_1_OE = 4'h5;
parameter GPIO_1_OUT = 4'h6;
 
 
 
reg ras;
reg was;
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
GPIO_0_OUT: rdata = gpio_0_out;
GPIO_0_OE: rdata = gpio_0_oe;
GPIO_0_IN: rdata = gpio_0_lat;
GPIO_1_OUT: rdata = gpio_1_out;
GPIO_1_OE: rdata = gpio_1_oe;
GPIO_1_IN: rdata = gpio_1_lat;
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
gpio_0_out <= 8'h00;
end
else
if(enable &&wr && was && cs && (waddr[3:0] == GPIO_0_OUT))
begin
gpio_0_out <= wdata;
end
else
begin
gpio_0_out <= next_gpio_0_out;
end
 
 
 
always@(posedge clk)
if (reset)
begin
gpio_0_oe <= 8'h00;
end
else
if(enable && wr && was && cs && (waddr[3:0] == GPIO_0_OE))
begin
gpio_0_oe <= wdata;
end
else
begin
gpio_0_oe <= next_gpio_0_oe;
end
 
 
 
always@(posedge clk)
if (reset)
begin
gpio_1_out <= 8'h00;
end
else
if(enable && wr && was && cs && (waddr[3:0] == GPIO_1_OUT))
begin
gpio_1_out <= wdata;
end
else
begin
gpio_1_out <= next_gpio_1_out;
end
 
 
 
always@(posedge clk)
if (reset)
begin
gpio_1_oe <= 8'h00;
end
else
if(enable && wr && was && cs && (waddr[3:0] == GPIO_1_OE))
begin
gpio_1_oe <= wdata;
end
else
begin
gpio_1_oe <= next_gpio_1_oe;
end
 
 
 
always@(posedge clk)
if (reset)
begin
gpio_0_lat <= 8'h00;
end
else
if(enable && rd && ras && cs && (raddr[3:0] == GPIO_0_IN))
begin
gpio_0_lat <= gpio_0_lat;
end
else
begin
gpio_0_lat <= gpio_0_in;
end
 
 
always@(posedge clk)
if (reset)
begin
gpio_1_lat <= 8'h00;
end
else
if(enable && rd && ras && cs && (raddr[3:0] == GPIO_1_IN))
begin
gpio_1_lat <= gpio_1_lat;
end
else
begin
gpio_1_lat <= gpio_1_in;
end
 
 
 
 
 
 
 
 
 
endmodule
 
`endif
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_utimer.v
14,7 → 14,7
input wire clk,
input wire reset,
 
input wire enable,
input wire cs,
input wire wr,
input wire rd,
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_timer_micro_reg.v
0,0 → 1,76
`include "io_module_defines"
 
`ifdef TIMER
 
 
module `VARIANT`TIMER_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)(
input wire clk,
input wire reset,
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
input wire [7:0] count_0,
input wire [7:0] start_0,
 
input wire [7:0] count_1,
input wire [7:0] start_1
 
 
);
parameter TIMER_0_START = 4'h0;
parameter TIMER_0_COUNT = 4'h2;
parameter TIMER_0_END = 4'h4;
 
parameter TIMER_1_START = 4'h8;
parameter TIMER_1_COUNT = 4'hA;
parameter TIMER_1_END = 4'hC;
reg was;
reg ras;
 
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
 
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
TIMER_0_START: rdata = start_0;
TIMER_0_COUNT: rdata = count_0;
TIMER_1_START: rdata = start_1;
TIMER_1_COUNT: rdata = count_1;
default: rdata = 8'h00;
endcase
end
else
begin
rdata = 8'hFF;
end
 
 
 
 
 
endmodule
 
`endif // `ifdef TIMER
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2_micro_reg.v
0,0 → 1,117
`include "io_module_defines"
 
`ifdef PS2
 
module `VARIANT`PS2_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)
 
(
input wire clk,
input wire reset,
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
input wire [7:0] rcv_data,
input wire [7:0] status,
input wire [7:0] x_pos,
input wire [7:0] y_pos,
 
output reg [7:0] cntrl,
output reg [7:0] wdata_buf,
output reg ps2_data_read_stb
 
);
 
 
parameter PS2_DATA = 4'h0;
parameter STATUS = 4'h2;
parameter CNTRL = 4'h4;
parameter X_POS = 4'h6;
parameter Y_POS = 4'h8;
 
reg was;
reg ras;
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
PS2_DATA: rdata = rcv_data;
STATUS: rdata = status;
CNTRL: rdata = cntrl;
X_POS: rdata = x_pos[7:0];
Y_POS: rdata = y_pos[7:0];
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
wdata_buf <= 8'h00;
end
else
if(wr && was && cs && waddr[3:0] == PS2_DATA)
begin
wdata_buf <= wdata;
end
else
begin
wdata_buf <= wdata_buf;
end
 
 
always@(posedge clk)
if (reset)
begin
cntrl <= 8'h00;
end
else
if(wr && was && cs && waddr[3:0] == CNTRL)
begin
cntrl <= wdata;
end
else
begin
cntrl <= cntrl;
end
 
 
 
 
 
 
always@(posedge clk)
if (reset)
begin
ps2_data_read_stb <= 1'b0;
end
else
begin
ps2_data_read_stb <= ( rd && ras && cs && (raddr[3:0] == PS2_DATA ));
end
 
endmodule
 
 
`endif // `ifdef PS2
 
 
 
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_pic.v
16,7 → 16,7
 
input wire clk,
input wire reset,
 
input wire enable,
input wire cs,
input wire wr,
input wire rd,
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_uart.v
5,12 → 5,19
module `VARIANT`UART
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
parameter ADDR_WIDTH = 8,
parameter TX_FIFO = 0,
parameter TX_FIFO_SIZE = 3,
parameter TX_FIFO_WORDS = 8,
parameter RX_FIFO = 0,
parameter RX_FIFO_SIZE = 3,
parameter RX_FIFO_WORDS = 8
)
 
(
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
17,7 → 24,7
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
output wire [7:0] rdata,
output wire txd_pad_out,
input wire rxd_pad_in,
input wire cts_pad_in,
28,116 → 35,100
 
 
 
wire [7:0] status;
wire [7:0] rcv_data;
wire [7:0] cntrl;
wire [7:0] lat_wdata;
wire txd_load;
wire rxd_data_avail_stb;
wire rxd_data_avail;
 
 
`VARIANT`UART_MICRO_REG
 
parameter XMIT_DATA = 4'h0;
parameter RCV_DATA = 4'h2;
parameter CNTRL = 4'h4;
parameter STATUS = 4'h6;
#(.BASE_ADDR(BASE_ADDR ),
.BASE_WIDTH(BASE_WIDTH ),
.ADDR_WIDTH(ADDR_WIDTH )
)
uart_micro_reg
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr ),
.rd ( rd ),
.waddr ( waddr ),
.raddr ( raddr ),
.wdata ( wdata ),
.rdata ( rdata ),
.lat_wdata ( lat_wdata ),
.rcv_data ( rcv_data ),
.status ( status ),
.cntrl ( cntrl ),
.txd_load ( txd_load ),
.rxd_data_avail_stb ( rxd_data_avail_stb )
);
 
reg was;
reg ras;
wire [7:0] rcv_data;
reg [7:0] cntrl;
reg load;
wire [7:0] status;
reg rx_data_avail;
wire rxd_buffer_full;
 
 
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
RCV_DATA: rdata = rcv_data;
CNTRL: rdata = cntrl;
STATUS: rdata = {status[7:1],rx_data_avail};
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
always@(posedge clk)
if (reset)
begin
cntrl <= 8'h00;
load <= 1'b0;
end
else
if(wr && was && cs && waddr[3:0] == CNTRL)
begin
cntrl <= wdata;
end
else
if(wr && was && cs && waddr[3:0] == XMIT_DATA)
begin
load <= 1'b1;
end
else
begin
cntrl <= cntrl;
load <= 1'b0;
end
// TX_IRQ_EN,RX_IRQ_EN,0,0,RTS,TX_BREAK,FORCE_PARITY,PARITY
// cntrl
 
 
always@(posedge clk)
if (reset) rx_data_avail <= 1'b0;
else
if(rxd_buffer_full) rx_data_avail <= 1'b1;
else
if(rd && was && cs && (waddr[3:0] == RCV_DATA)) rx_data_avail <= 1'b0;
else rx_data_avail <= rx_data_avail;
 
 
 
always@(posedge clk)
if (reset) rx_irq <= 1'b0;
else rx_irq <= cntrl[6] && rx_data_avail;
if (reset) rx_irq <= 1'b0;
else rx_irq <= cntrl[6] && rxd_data_avail;
 
always@(posedge clk)
if (reset) tx_irq <= 1'b0;
else tx_irq <= cntrl[7] && status[5];
if (reset) tx_irq <= 1'b0;
else tx_irq <= cntrl[7] && status[5];
 
 
assign status[2] = 1'b0;
 
assign status[0] = rxd_data_avail;
uart
#(
.TX_FIFO (TX_FIFO),
.TX_FIFO_SIZE (TX_FIFO_SIZE),
.TX_FIFO_WORDS (TX_FIFO_WORDS),
.RX_FIFO (RX_FIFO),
.RX_FIFO_SIZE (RX_FIFO_SIZE),
.RX_FIFO_WORDS (RX_FIFO_WORDS)
)
uart(
.clk ( clk ),
.reset ( reset ),
.txd_parity ( cntrl[0] ),
.txd_force_parity ( cntrl[1] ),
.txd_break ( cntrl[2] ),
.rts_in ( cntrl[3] ),
.parity_enable ( cntrl[4] ),
.txd_data_in ( wdata ),
.txd_load ( load ),
.rxd_data_out ( rcv_data ),
.rxd_parity ( cntrl[0] ),
.rxd_force_parity ( cntrl[1] ),
.rxd_buffer_full ( rxd_buffer_full ),
.rxd_stop_error ( status[1] ),
.rxd_parity_error ( status[3] ),
.cts_out ( status[4] ),
.txd_buffer_empty ( status[5] ),
.txd_pad_out ( txd_pad_out ),
.rxd_pad_in ( rxd_pad_in ),
.cts_pad_in ( cts_pad_in ),
.rts_pad_out ( rts_pad_out )
.clk ( clk ),
.reset ( reset ),
.txd_parity ( cntrl[0] ),
.txd_force_parity ( cntrl[1] ),
.txd_break ( cntrl[2] ),
.rts_in ( cntrl[3] ),
.parity_enable ( cntrl[4] ),
.txd_data_in ( lat_wdata ),
.txd_load ( txd_load ),
.rxd_data_out ( rcv_data ),
.rxd_parity ( cntrl[0] ),
.rxd_force_parity ( cntrl[1] ),
.rxd_stop_error ( status[1] ),
.rxd_parity_error ( status[3] ),
.rxd_data_avail_stb ( rxd_data_avail_stb ),
.rxd_data_avail ( rxd_data_avail ),
.cts_out ( status[4] ),
.txd_buffer_empty ( status[5] ),
.txd_pad_out ( txd_pad_out ),
.rxd_pad_in ( rxd_pad_in ),
.cts_pad_in ( cts_pad_in ),
.rts_pad_out ( rts_pad_out )
);
 
 
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_utimer_micro_reg.v
0,0 → 1,85
`include "io_module_defines"
 
`ifdef UTIMER
 
 
 
module `VARIANT`UTIMER_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)(
input wire clk,
input wire reset,
 
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
 
output reg [7:0] count,
output reg [7:0] latch,
 
input wire [7:0] next_count,
input wire [7:0] next_latch
 
);
 
parameter TIMER_LATCH = 4'h0;
parameter TIMER_COUNT = 4'h2;
 
reg ras;
reg was;
 
 
 
 
 
always@(waddr) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(raddr) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
 
 
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
TIMER_LATCH: rdata = latch[7:0];
TIMER_COUNT: rdata = count[7:0];
default: rdata = 8'h00;
endcase
end
else rdata = 8'hFF;
 
 
 
 
always@(posedge clk)
if (reset) latch <= 8'h00;
else
if(wr && was && cs && waddr[3:0] == TIMER_LATCH) latch <= wdata;
else latch <= next_latch;
 
 
 
always@(posedge clk)
if (reset) count <= 8'h00;
else
if(wr && was && cs && waddr[3:0] == TIMER_COUNT) count <= wdata;
else count <= next_count;
 
 
 
 
endmodule
 
`endif // `ifdef UTIMER
/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_vga.v
0,0 → 1,119
`include "io_module_defines"
 
`ifdef VGA
 
module `VARIANT`VGA
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8,
parameter STARTUP="NONE",
parameter FONT="NONE"
)
 
(
input wire clk,
input wire reset,
input wire enable,
input wire cs,
input wire wr,
input wire rd,
input wire [7:0] waddr,
input wire [7:0] raddr,
input wire [7:0] wdata,
output wire [7:0] rdata,
 
output wire [2:0] vgared_pad_out,
output wire [2:0] vgagreen_pad_out,
output wire [1:0] vgablue_pad_out,
 
output wire hsync_n_pad_out,
output wire vsync_n_pad_out
);
 
 
 
wire [7:0] cntrl;
wire [7:0] char_color;
wire [7:0] back_color;
wire [7:0] cursor_color;
 
wire [15:0] vga_address;
wire ascii_load;
wire add_l_load;
wire add_h_load;
 
 
`VARIANT`VGA_MICRO_REG
 
#(.BASE_ADDR(BASE_ADDR ),
.BASE_WIDTH(BASE_WIDTH ),
.ADDR_WIDTH(ADDR_WIDTH )
)
vga_micro_reg
(
.clk ( clk ),
.reset ( reset ),
.enable ( enable ),
.cs ( cs ),
.wr ( wr ),
.rd ( rd ),
.waddr ( waddr ),
.raddr ( raddr ),
.wdata ( wdata ),
.rdata ( rdata ),
.lat_wdata ( ),
.cntrl ( cntrl ),
.char_color ( char_color ),
.back_color ( back_color ),
.cursor_color ( cursor_color ),
.vga_address ( vga_address ),
 
 
.ascii_load ( ascii_load ),
.add_l_load ( add_l_load ),
.add_h_load ( add_h_load )
 
);
 
 
 
vga_char_ctrl
#(.STARTUP(STARTUP),
.FONT(FONT)
)
vga_char_ctrl
(
.clk ( clk ),
.reset ( reset ),
.ascii_load ( ascii_load ),
.add_l_load ( add_l_load ),
.add_h_load ( add_h_load ),
 
.wdata ( wdata ),
.address ( vga_address[13:0] ),
.char_color ( char_color ),
.back_color ( back_color ),
.cursor_color ( cursor_color ),
 
.vga_red_pad_out ( vgared_pad_out ),
.vga_green_pad_out ( vgagreen_pad_out ),
.vga_blue_pad_out ( vgablue_pad_out ),
 
.hsync_n_pad_out ( hsync_n_pad_out ),
.vsync_n_pad_out ( vsync_n_pad_out )
);
 
 
 
 
 
endmodule
 
`endif // `ifdef VGA
/trunk/projects/logic/ip/io_module/sim/run/default/liblist
2,3 → 2,5
`include "../../lib/cde_divider/cde_divider.v"
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
`include "../../lib/cde_fifo/cde_fifo.v"
`include "../../lib/cde_sram/cde_sram.v"
/trunk/projects/logic/ip/io_module/sim/run/default/filelist
2,4 → 2,5
`include "../../../rtl/gen/sim/io_module.v"
`include "../../../../uart/rtl/gen/sim/uart.v"
`include "../../../../ps2_interface/rtl/gen/sim/ps2_interface.v"
`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
`include "../../../../vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
/trunk/projects/logic/ip/io_module/sim/run/mouse/liblist
2,3 → 2,5
`include "../../lib/cde_divider/cde_divider.v"
`include "../../lib/cde_serial_rcvr/cde_serial_rcvr.v"
`include "../../lib/cde_serial_xmit/cde_serial_xmit.v"
`include "../../lib/cde_fifo/cde_fifo.v"
`include "../../lib/cde_sram/cde_sram.v"
/trunk/projects/logic/ip/io_module/sim/run/mouse/filelist
2,4 → 2,5
`include "../../../rtl/gen/sim/io_module.v"
`include "../../../../uart/rtl/gen/sim/uart.v"
`include "../../../../ps2_interface/rtl/gen/sim/ps2_interface.v"
`include "../../../../vga_char_ctrl/rtl/gen/sim/vga_char_ctrl.v"
`include "../../../../serial_rcvr/rtl/gen/sim/serial_rcvr.v"
/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl_600x432/vga_char_ctrl_defines.v
0,0 → 1,24
 
`define VARIANT vga_char_ctrl_600x432
`define CDE cde
`define CHAR_DISPLAY _char_display
`define CHAR_GEN _char_gen
`define SVGA_TIMING_GENERATION _svga_timing_generation
`define VIDEO_OUT _video_out
`define SRAM _sram
 
 
// 600 X 432 @ 60Hz with a 25.175MHz pixel clock
`define H_ACTIVE 600 // pixels
`define H_FRONT_PORCH 16 // pixels
`define H_SYNCH 96 // pixels
`define H_BACK_PORCH 48 // pixels
`define H_TOTAL 800 // pixels
 
`define V_ACTIVE 432 // lines
`define V_FRONT_PORCH 11 // lines
`define V_SYNCH 2 // lines
`define V_BACK_PORCH 31 // lines
`define V_TOTAL 524 // lines
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/variants/vga_char_ctrl/vga_char_ctrl_defines.v
0,0 → 1,25
 
`define VARIANT vga_char_ctrl
`define CDE cde
`define CHAR_DISPLAY _char_display
`define CHAR_GEN _char_gen
`define SVGA_TIMING_GENERATION _svga_timing_generation
`define VIDEO_OUT _video_out
`define SRAM _sram
 
 
// 640 X 480 @ 60Hz with a 25.175MHz pixel clock
`define H_ACTIVE 640 // pixels
`define H_FRONT_PORCH 16 // pixels
`define H_SYNCH 96 // pixels
`define H_BACK_PORCH 48 // pixels
`define H_TOTAL 800 // pixels
 
`define V_ACTIVE 480 // lines
`define V_FRONT_PORCH 11 // lines
`define V_SYNCH 2 // lines
`define V_BACK_PORCH 31 // lines
`define V_TOTAL 524 // lines
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_video_out.v
0,0 → 1,100
`include "vga_char_ctrl_defines.v"
 
 
module `VARIANT`VIDEO_OUT
(
 
 
input wire clk,
input wire reset,
input wire h_synch,
input wire v_synch,
input wire blank,
input wire pixel_on,
input wire cursor_on,
input wire [7:0] char_color,
input wire [7:0] cursor_color,
input wire [7:0] back_color,
output reg hsync_n_pad_out,
output reg vsync_n_pad_out,
output reg [2:0] vga_red_pad_out,
output reg [2:0] vga_green_pad_out,
output reg [1:0] vga_blue_pad_out
 
);
 
 
 
// make the external video connections
always @ (posedge clk ) begin
if (reset) begin
// shut down the video output during reset
hsync_n_pad_out <= 1'b1;
vsync_n_pad_out <= 1'b1;
end
else begin
// output color data otherwise
hsync_n_pad_out <= !h_synch;
vsync_n_pad_out <= !v_synch;
end
end
 
 
 
 
// make the external video connections
always @ (posedge clk )
begin
if (reset)
begin
// shut down the video output during reset
vga_red_pad_out <= 3'b000;
vga_green_pad_out <= 3'b000;
vga_blue_pad_out <= 2'b00;
end
else
if (blank)
begin
// output black during the blank signal
vga_red_pad_out <= 3'b000;
vga_green_pad_out <= 3'b000;
vga_blue_pad_out <= 2'b00;
end
 
else
if (cursor_on)
begin
// output black during the blank signal
vga_red_pad_out <= cursor_color[7:5];
vga_green_pad_out <= cursor_color[4:2];
vga_blue_pad_out <= cursor_color[1:0];
end
 
else
if (pixel_on)
begin
// output black during the blank signal
vga_red_pad_out <= char_color[7:5];
vga_green_pad_out <= char_color[4:2];
vga_blue_pad_out <= char_color[1:0];
end
else
begin
// output black during the blank signal
vga_red_pad_out <= back_color[7:5];
vga_green_pad_out <= back_color[4:2];
vga_blue_pad_out <= back_color[1:0];
end
end
 
 
endmodule // VIDEO_OUT
/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl.v
0,0 → 1,146
`include "vga_char_ctrl_defines.v"
 
//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//----------------------------------------------------------------------------
 
module `VARIANT
#(parameter STARTUP="NONE",
parameter FONT="NONE",
parameter CHARACTER_DECODE_DELAY=4
)
(
 
input wire clk, // 25MHz CLOCK
input wire reset,
 
input wire ascii_load,
input wire add_l_load,
input wire add_h_load,
 
input wire [7:0] wdata,
output reg [13:0] address,
 
input wire [7:0] char_color,
input wire [7:0] back_color,
input wire [7:0] cursor_color,
output wire [2:0] vga_red_pad_out,
output wire [2:0] vga_green_pad_out,
output wire [1:0] vga_blue_pad_out,
 
output wire hsync_n_pad_out,
output wire vsync_n_pad_out
);
 
 
// internal video timing signals
wire h_synch; // horizontal synch for VGA connector
wire v_synch; // vertical synch for VGA connector
wire blank; // composite blanking
wire [10:0] pixel_count; // bit mapped pixel position within the lin
wire [9:0] line_count; // bit mapped line number in a frame lines within the frame
wire [2:0] subchar_pixel;// pixel position within the character
wire [2:0] subchar_line; // identifies the line number within a character block
wire [6:0] char_column; // character number on the current line
wire [6:0] char_line; // line number on the screen
 
wire pixel_on;
wire cursor_on;
 
 
 
always@(posedge clk)
if(reset) address <= 14'b00000000000000;
else
if(add_l_load) address[7:0] <= wdata;
else
if(add_h_load) address[13:8] <= wdata[5:0];
else
if(ascii_load) address <= address+ 14'b0000000000001;
else address <= address;
 
 
// instantiate the character generator
`VARIANT`CHAR_DISPLAY
#(.STARTUP(STARTUP),
.FONT(FONT))
CHAR_DISPLAY
(
.clk ( clk ),
.reset ( reset ),
.char_column ( char_column ),
.char_line ( char_line ),
.subchar_line ( subchar_line ),
.subchar_pixel ( subchar_pixel ),
.pixel_on ( pixel_on ),
.cursor_on ( cursor_on ),
.char_write_addr ( address ),
.char_write_data ( wdata ),
.char_write_enable ( ascii_load )
);
 
// instantiate the video timing generator
`VARIANT`SVGA_TIMING_GENERATION
#(.CHARACTER_DECODE_DELAY(CHARACTER_DECODE_DELAY))
SVGA_TIMING_GENERATION
(
.clk ( clk ),
.reset ( reset ),
.h_synch ( h_synch ),
.v_synch ( v_synch ),
.blank ( blank ),
.pixel_count ( pixel_count ),
.line_count ( line_count ),
.subchar_pixel ( subchar_pixel),
.subchar_line ( subchar_line ),
.char_column ( char_column ),
.char_line ( char_line )
);
 
// instantiate the video output mux
`VARIANT`VIDEO_OUT
VIDEO_OUT
(
.clk ( clk ),
.reset ( reset ),
.h_synch ( h_synch ),
.v_synch ( v_synch ),
.blank ( blank ),
.char_color ( char_color ),
.back_color ( back_color ),
.cursor_color ( cursor_color ),
.pixel_on ( pixel_on ),
.cursor_on ( cursor_on ),
.hsync_n_pad_out ( hsync_n_pad_out ),
.vsync_n_pad_out ( vsync_n_pad_out ),
.vga_red_pad_out ( vga_red_pad_out ),
.vga_green_pad_out ( vga_green_pad_out ),
.vga_blue_pad_out ( vga_blue_pad_out )
);
 
 
 
endmodule // MAIN
/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_char_display.v
0,0 → 1,60
`include "vga_char_ctrl_defines.v"
 
module `VARIANT`CHAR_DISPLAY
#(parameter STARTUP="NONE",
parameter FONT="NONE")
 
(
input wire clk,
input wire reset,
input wire [6:0] char_column, // character number on the current line
input wire [6:0] char_line, // line number on the screen
input wire [2:0] subchar_line, // the line number within a character block 0-8
input wire [2:0] subchar_pixel, // the pixel number within a character block 0-8
 
 
output wire cursor_on,
output wire pixel_on,
input wire [13:0] char_write_addr,
input wire [7:0] char_write_data,
input wire char_write_enable
 
);
 
 
reg [13:0] char_read_addr;
 
 
always @ (*)
begin
char_read_addr = (char_line[6:0] * `H_ACTIVE / 8 ) + char_column[6:0];
end
 
 
 
 
// the character generator block includes the character RAM
// and the character generator ROM
`VARIANT`CHAR_GEN
#(.STARTUP(STARTUP),
.FONT(FONT))
 
CHAR_GEN
(
.clk ( clk ),
.reset ( reset ), // reset signal
.char_write_addr ( char_write_addr ), // write address
.char_write_data ( char_write_data ), // write data
.char_write_enable ( char_write_enable ), // write enable
.char_read_addr ( char_read_addr ), // read address of current character
.subchar_line ( subchar_line ), // current line of pixels within current character
.subchar_pixel ( subchar_pixel ), // current column of pixels withing current character
.cursor_on ( cursor_on ), //
.pixel_on ( pixel_on ) //
);
 
endmodule //CHAR_DISPLAY
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_svga_timing_generation.v
0,0 → 1,271
`include "vga_char_ctrl_defines.v"
 
//---------------------------------------------------
 
module `VARIANT`SVGA_TIMING_GENERATION
#(parameter CHARACTER_DECODE_DELAY=4)
(
 
input clk, // pixel clock
input reset, // reset
output reg h_synch, // horizontal synch for VGA connector
output reg v_synch, // vertical synch for VGA connector
output reg blank, // composite blanking
output reg [10:0] pixel_count, // counts the pixels in a line
output reg [9:0] line_count, // counts the display lines
output reg [2:0] subchar_pixel, // pixel position within the character
output reg [2:0] subchar_line, // identifies the line number within a character block
output reg [6:0] char_column, // character number on the current line
output reg [6:0] char_line // line number on the screen
 
);
 
 
reg h_blank; // horizontal blanking
reg v_blank; // vertical blanking
 
 
 
reg [9:0] char_column_count; // a counter used to define the character column number
reg [9:0] char_line_count; // a counter used to define the character line number
reg reset_char_line; // flag to reset the character line during VBI
reg reset_char_column; // flag to reset the character column during HBI
 
 
 
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
always @ (posedge clk) begin
if (reset)
// on reset set pixel counter to 0
pixel_count <= 11'd0;
else if (pixel_count == (`H_TOTAL - 1))
// last pixel in the line, so reset pixel counter
pixel_count <= 11'd0;
else
pixel_count <= pixel_count + 1;
end
 
// CREATE THE HORIZONTAL SYNCH PULSE
always @ (posedge clk ) begin
if (reset)
// on reset remove h_synch
h_synch <= 1'b0;
else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
// start of h_synch
h_synch <= 1'b1;
else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
// end of h_synch
h_synch <= 1'b0;
end
 
// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge clk ) begin
if (reset)
// on reset set line counter to 0
line_count <= 10'd0;
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'd0;
else if ((pixel_count == (`H_TOTAL - 1)))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
 
// CREATE THE VERTICAL SYNCH PULSE
always @ (posedge clk ) begin
if (reset)
// on reset remove v_synch
v_synch = 1'b0;
 
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
(pixel_count == `H_TOTAL - 1)))
// start of v_synch
v_synch = 1'b1;
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
(pixel_count == (`H_TOTAL - 1)))
// end of v_synch
v_synch = 1'b0;
end
 
 
// CREATE THE HORIZONTAL BLANKING SIGNAL
// the "-2" is used instead of "-1" because of the extra register delay
// for the composite blanking signal
always @ (posedge clk ) begin
if (reset)
// on reset remove the h_blank
h_blank <= 1'b0;
 
else if (pixel_count == (`H_ACTIVE -2))
// start of HBI
h_blank <= 1'b1;
else if (pixel_count == (`H_TOTAL -2))
// end of HBI
h_blank <= 1'b0;
end
 
 
// CREATE THE VERTICAL BLANKING SIGNAL
// the "-2" is used instead of "-1" in the horizontal factor because of the extra
// register delay for the composite blanking signal
always @ (posedge clk ) begin
if (reset)
// on reset remove v_blank
v_blank <= 1'b0;
 
else if ((line_count == (`V_ACTIVE - 1) &
(pixel_count == `H_TOTAL - 2)))
// start of VBI
v_blank <= 1'b1;
else if ((line_count == (`V_TOTAL - 1)) &
(pixel_count == (`H_TOTAL - 2)))
// end of VBI
v_blank <= 1'b0;
end
 
 
// CREATE THE COMPOSITE BANKING SIGNAL
always @ (posedge clk ) begin
if (reset)
// on reset remove blank
blank <= 1'b0;
 
// blank during HBI or VBI
else if (h_blank || v_blank)
blank <= 1'b1;
else
// active video do not blank
blank <= 1'b0;
end
 
 
/*
CREATE THE CHARACTER COUNTER.
CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
 
A 640 x 480 video mode will display 80 characters on 60 lines.
A 800 x 600 video mode will display 100 characters on 75 lines.
A 1024 x 768 video mode will display 128 characters on 96 lines.
 
"subchar_line" identifies the row in the 8 x 8 block.
"subchar_pixel" identifies the column in the 8 x 8 block.
*/
 
// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge clk ) begin
if (reset)
// on reset set line counter to 0
subchar_line <= 3'b000;
 
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
// reset line counter
subchar_line <= 3'b000;
 
else if (pixel_count == (`H_TOTAL - 1) - CHARACTER_DECODE_DELAY)
// increment line counter
subchar_line <= line_count + 1;
end
 
// subchar_pixel defines the pixel within the character line
always @ (posedge clk ) begin
if (reset)
// reset to 5 so that the first character data can be latched
subchar_pixel <= 3'b101;
else if (pixel_count == ((`H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
// reset to 5 so that the first character data can be latched
subchar_pixel <= 3'b101;
else
subchar_pixel <= subchar_pixel + 1;
end
 
 
wire [9:0] char_column_count_iter = char_column_count + 1;
 
always @ (posedge clk ) begin
if (reset) begin
char_column_count <= 10'd0;
char_column <= 7'd0;
end
else if (reset_char_column) begin
// reset the char column count during the HBI
char_column_count <= 10'd0;
char_column <= 7'd0;
end
else begin
char_column_count <= char_column_count_iter;
char_column <= char_column_count_iter[9:3];
end
end
 
wire [9:0] char_line_count_iter = char_line_count + 1;
 
always @ (posedge clk ) begin
if (reset) begin
char_line_count <= 10'd0;
char_line <= 7'd0;
end
else if (reset_char_line) begin
// reset the char line count during the VBI
char_line_count <= 10'd0;
char_line <= 7'd0;
end
else if (pixel_count == ((`H_TOTAL - 1) - CHARACTER_DECODE_DELAY)) begin
// last pixel but not last line, so increment line counter
char_line_count <= char_line_count_iter;
char_line <= char_line_count_iter[9:3];
end
end
 
// CREATE THE CONTROL SIGNALS FOR THE CHARACTER ADDRESS COUNTERS
/*
The HOLD and RESET signals are advanced from the beginning and end
of HBI and VBI to compensate for the internal character generation
pipeline.
*/
always @ (posedge clk ) begin
if (reset)
reset_char_column <= 1'b0;
 
else if (pixel_count == ((`H_ACTIVE - 2) - CHARACTER_DECODE_DELAY))
// start of HBI
reset_char_column <= 1'b1;
else if (pixel_count == ((`H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
// end of HBI
reset_char_column <= 1'b0;
end
 
always @ (posedge clk ) begin
if (reset)
reset_char_line <= 1'b0;
 
else if ((line_count == (`V_ACTIVE - 1)) &
(pixel_count == ((`H_ACTIVE - 1) - CHARACTER_DECODE_DELAY)))
// start of VBI
reset_char_line <= 1'b1;
else if ((line_count == (`V_TOTAL - 1)) &
(pixel_count == ((`H_TOTAL - 1) - CHARACTER_DECODE_DELAY)))
// end of VBI
reset_char_line <= 1'b0;
end
endmodule //SVGA_TIMING_GENERATION
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/verilog/vga_char_ctrl_char_gen.v
0,0 → 1,187
`include "vga_char_ctrl_defines.v"
 
module `VARIANT`CHAR_GEN
#(parameter STARTUP="NONE",
parameter FONT="NONE")
(
 
input wire clk,
input wire reset,
input wire [13:0] char_write_addr,
input wire [7:0] char_write_data,
input wire char_write_enable,
input wire [13:0] char_read_addr, // character address "0" is upper left character
input wire [2:0] subchar_line, // line number within 8 line block
 
input wire [2:0] subchar_pixel, // pixel position within 8 pixel block
 
output reg pixel_on,
output reg cursor_on
);
 
reg latch_data;
reg latch_low_data;
reg shift_high;
reg shift_low;
reg [3:0] latched_low_char_data;
reg [7:0] latched_char_data;
 
 
wire [7:0] ascii_code;
wire [10:0] chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]};
wire [7:0] char_gen_rom_data;
 
 
 
 
always @ (posedge clk )
if (reset) cursor_on <= 1'b0;
else cursor_on <= (char_read_addr == char_write_addr) ;
 
cde_sram #(
.ADDR (13),
.WIDTH (8),
.WORDS (4800),
.INIT_FILE (STARTUP)
)
char_ram
(
.clk ( clk ),
.cs (1'b1 ),
.waddr ( char_write_addr[12:0]),
.raddr ( char_read_addr[12:0] ),
.wr ( char_write_enable ),
.rd (1'b1 ),
.wdata ( char_write_data ),
.rdata ( ascii_code[7:0] )
);
 
 
 
 
// instantiate the character generator ROM
 
cde_sram #(
.ADDR (11),
.WIDTH (8),
.WORDS (1152),
.INIT_FILE (FONT)
)
char_gen_rom
(
.clk ( clk ),
.cs (1'b1 ),
.waddr (11'b00000000000 ),
.raddr ( chargen_rom_address),
.wr (1'b0 ),
.rd (1'b1 ),
.wdata (8'h00 ),
.rdata ( char_gen_rom_data[7:0] )
);
 
 
 
 
// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM
always @ (posedge clk )begin
if (reset) begin
latch_data <= 1'b0;
end
else if (subchar_pixel == 3'b110) begin
latch_data <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
latch_data <= 1'b0;
end
end
 
always @ (posedge clk )begin
if (reset) begin
latch_low_data <= 1'b0;
end
else if (subchar_pixel == 3'b010) begin
latch_low_data <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
latch_low_data <= 1'b0;
end
end
 
always @ (posedge clk )begin
if (reset) begin
shift_high <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
shift_high <= 1'b0;
end
else if (subchar_pixel == 3'b111) begin
shift_high <= 1'b1;
end
end
 
always @ (posedge clk )begin
if (reset) begin
shift_low <= 1'b0;
end
else if (subchar_pixel == 3'b011) begin
shift_low <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
shift_low <= 1'b0;
end
end
 
// serialize the CHARACTER MODE data
always @ (posedge clk ) begin
if (reset)
begin
pixel_on = 1'b0;
latched_low_char_data = 4'h0;
latched_char_data = 8'h00;
end
 
else if (shift_high)
begin
pixel_on = latched_char_data [7];
latched_char_data [7] = latched_char_data [6];
latched_char_data [6] = latched_char_data [5];
latched_char_data [5] = latched_char_data [4];
latched_char_data [4] = latched_char_data [7];
if(latch_low_data) begin
latched_low_char_data [3:0] = latched_char_data [3:0];
end
else begin
latched_low_char_data [3:0] = latched_low_char_data [3:0];
end
end
 
else if (shift_low)
begin
pixel_on = latched_low_char_data [3];
latched_low_char_data [3] = latched_low_char_data [2];
latched_low_char_data [2] = latched_low_char_data [1];
latched_low_char_data [1] = latched_low_char_data [0];
latched_low_char_data [0] = latched_low_char_data [3];
if (latch_data) begin
latched_char_data [7:0] = char_gen_rom_data[7:0];
end
else begin
latched_char_data [7:0] = latched_char_data [7:0];
end
end
else
begin
latched_low_char_data [3:0] = latched_low_char_data [3:0];
latched_char_data [7:0] = latched_char_data [7:0];
pixel_on = pixel_on;
end
end
 
endmodule //CHAR_GEN
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_char_display.v
0,0 → 1,120
`include "vga_char_interface_defines.v"
 
 
module `VARIANT`CHAR_DISPLAY
(
char_column,
char_line,
subchar_line,
subchar_pixel,
pixel_clock,
reset,
vga_red_data,
vga_green_data,
vga_blue_data,
address,
character,
loadit
);
 
input [6:0] char_column; // character number on the current line
input [6:0] char_line; // line number on the screen
input [2:0] subchar_line; // the line number within a character block 0-8
input [2:0] subchar_pixel; // the pixel number within a character block 0-8
input pixel_clock;
input reset;
output vga_red_data;
output vga_green_data;
output vga_blue_data;
 
input [13:0] address;
input [11:0] character;
input loadit;
 
//// Label Definitions ////
 
// Note: all labels must match their defined length--shorter labels will be padded with solid blocks,
// and longer labels will be truncated
 
wire write_enable; // character memory is written to on a clock rise when high
assign write_enable = loadit;
 
// The character write address
reg [13:0] char_addr;
 
//wire [13:0] my_char_read_addr = {char_line[6:0], char_column[6:0]};
//wire [13:0] my_char_read_addr = {char_line[6:0], char_column[5:0]};
wire [13:0] my_char_read_addr = (char_line[6:0] * 75) + char_column[6:0];
 
wire pixel_on; // high => output foreground color, low => output background color
reg [13:0] char_write_data; // the data that will be written to character memory at the clock rise
reg char_addr_is_0;
 
reg [3:0] hex; // the 4 bit value to be converted into ASCII
wire [7:0] ascii; // the result of the conversion to ASCII
integer i, ii; // iterators
 
wire fore_red;
wire fore_green;
wire fore_blue;
wire back_red;
wire back_green;
wire back_blue;
 
// write the appropriate character data to memory
always @ (char_line or char_column) begin
char_write_data <= character;
char_addr <= address[13:0];
end
 
 
wire background_red; // the red component of the background color
wire background_green; // the green component of the background color
wire background_blue; // the blue component of the background color
wire foreground_red; // the red component of the foreground color
wire foreground_green; // the green component of the foreground color
wire foreground_blue; // the blue component of the foreground color
 
// use the result of the character generator module to choose between the foreground and background color
assign vga_red_data = (pixel_on) ? foreground_red : background_red;
assign vga_green_data = (pixel_on) ? foreground_green : background_green;
assign vga_blue_data = (pixel_on) ? foreground_blue : background_blue;
 
assign foreground_red = (back_red) ? 0 : fore_red; // If the invert signal is 1, then foreground is 0
assign foreground_green = (back_red) ? 0 : fore_green;
assign foreground_blue = (back_red) ? 0 : fore_blue;
 
assign background_red = (back_red) ? fore_red : 0; // If invert is 1, then the background is the values passed
assign background_green = (back_red) ? fore_green : 0;
assign background_blue = (back_red) ? fore_blue : 0;
 
// the character generator block includes the character RAM
// and the character generator ROM
`VARIANT`CHAR_GEN CHAR_GEN
(
reset, // reset signal
char_addr, // write address
char_write_data, // write data
write_enable, // write enable
pixel_clock, // write clock
my_char_read_addr,// read address of current character
subchar_line, // current line of pixels within current character
subchar_pixel, // current column of pixels withing current character
pixel_clock, // read clock
pixel_on, // read data
fore_red,
fore_green,
fore_blue,
back_red,
back_green,
back_blue
);
 
endmodule //CHAR_DISPLAY
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_char_gen_rom.v
0,0 → 1,1356
`include "vga_char_interface_defines.v"
 
module `VARIANT`CHAR_GEN_ROM
(
pixel_clock,
address,
data
);
 
input pixel_clock;
input [10:0] address;
output reg [7:0] data;
 
always @(posedge pixel_clock) begin
case(address)
//// Solid Block ////
// 00h: solid block
11'h000: data <= 8'hFF;
11'h001: data <= 8'hFF;
11'h002: data <= 8'hFF;
11'h003: data <= 8'hFF;
11'h004: data <= 8'hFF;
11'h005: data <= 8'hFF;
11'h006: data <= 8'hFF;
11'h007: data <= 8'hFF;
//// Block graphics ////
// 01h: Left block up, right block down
11'h008: data <= 8'hF0;
11'h009: data <= 8'hF0;
11'h00A: data <= 8'hF0;
11'h00B: data <= 8'hF0;
11'h00C: data <= 8'h0F;
11'h00D: data <= 8'h0F;
11'h00E: data <= 8'h0F;
11'h00F: data <= 8'h0F;
// 02h: Left block down, right block up
11'h010: data <= 8'h0F;
11'h011: data <= 8'h0F;
11'h012: data <= 8'h0F;
11'h013: data <= 8'h0F;
11'h014: data <= 8'hF0;
11'h015: data <= 8'hF0;
11'h016: data <= 8'hF0;
11'h017: data <= 8'hF0;
// 03h: Both blocks down
11'h018: data <= 8'h00;
11'h019: data <= 8'h00;
11'h01A: data <= 8'h00;
11'h01B: data <= 8'h00;
11'h01C: data <= 8'hFF;
11'h01D: data <= 8'hFF;
11'h01E: data <= 8'hFF;
11'h01F: data <= 8'hFF;
// 04h: Both blocks up
11'h020: data <= 8'hFF;
11'h021: data <= 8'hFF;
11'h022: data <= 8'hFF;
11'h023: data <= 8'hFF;
11'h024: data <= 8'h00;
11'h025: data <= 8'h00;
11'h026: data <= 8'h00;
11'h027: data <= 8'h00;
//// Line Graphics ////
// 05h: corner upper left
11'h028: data <= 8'hFF;
11'h029: data <= 8'h80;
11'h02A: data <= 8'h80;
11'h02B: data <= 8'h80;
11'h02C: data <= 8'h80;
11'h02D: data <= 8'h80;
11'h02E: data <= 8'h80;
11'h02F: data <= 8'h80;
// 06h: corner upper right
11'h030: data <= 8'hFF;
11'h031: data <= 8'h01;
11'h032: data <= 8'h01;
11'h033: data <= 8'h01;
11'h034: data <= 8'h01;
11'h035: data <= 8'h01;
11'h036: data <= 8'h01;
11'h037: data <= 8'h01;
// 07h: corner lower left
11'h038: data <= 8'h80;
11'h039: data <= 8'h80;
11'h03A: data <= 8'h80;
11'h03B: data <= 8'h80;
11'h03C: data <= 8'h80;
11'h03D: data <= 8'h80;
11'h03E: data <= 8'h80;
11'h03F: data <= 8'hFF;
// 08h: corner lower right
11'h040: data <= 8'h01;
11'h041: data <= 8'h01;
11'h042: data <= 8'h01;
11'h043: data <= 8'h01;
11'h044: data <= 8'h01;
11'h045: data <= 8'h01;
11'h046: data <= 8'h01;
11'h047: data <= 8'hFF;
// 09h: cross junction
11'h048: data <= 8'h10;
11'h049: data <= 8'h10;
11'h04A: data <= 8'h10;
11'h04B: data <= 8'hFF;
11'h04C: data <= 8'h10;
11'h04D: data <= 8'h10;
11'h04E: data <= 8'h10;
11'h04F: data <= 8'h10;
// 0Ah: "T" junction
11'h050: data <= 8'hFF;
11'h051: data <= 8'h10;
11'h052: data <= 8'h10;
11'h053: data <= 8'h10;
11'h054: data <= 8'h10;
11'h055: data <= 8'h10;
11'h056: data <= 8'h10;
11'h057: data <= 8'h10;
// 0Bh: "T" juntion rotated 90 clockwise
11'h058: data <= 8'h01;
11'h059: data <= 8'h01;
11'h05A: data <= 8'h01;
11'h05B: data <= 8'hFF;
11'h05C: data <= 8'h01;
11'h05D: data <= 8'h01;
11'h05E: data <= 8'h01;
11'h05F: data <= 8'h01;
// 0Ch: "T" juntion rotated 180
11'h060: data <= 8'h10;
11'h061: data <= 8'h10;
11'h062: data <= 8'h10;
11'h063: data <= 8'h10;
11'h064: data <= 8'h10;
11'h065: data <= 8'h10;
11'h066: data <= 8'h10;
11'h067: data <= 8'hFF;
// 0Dh: "T" junction rotated 270 clockwise
11'h068: data <= 8'h80;
11'h069: data <= 8'h80;
11'h06A: data <= 8'h80;
11'h06B: data <= 8'hFF;
11'h06C: data <= 8'h80;
11'h06D: data <= 8'h80;
11'h06E: data <= 8'h80;
11'h06F: data <= 8'h80;
// 0Eh: arrow pointing right
11'h070: data <= 8'h08;
11'h071: data <= 8'h04;
11'h072: data <= 8'h02;
11'h073: data <= 8'hFF;
11'h074: data <= 8'h02;
11'h075: data <= 8'h04;
11'h076: data <= 8'h08;
11'h077: data <= 8'h00;
// 0Fh: arrow pointing left
11'h078: data <= 8'h10;
11'h079: data <= 8'h20;
11'h07A: data <= 8'h40;
11'h07B: data <= 8'hFF;
11'h07C: data <= 8'h40;
11'h07D: data <= 8'h20;
11'h07E: data <= 8'h10;
11'h07F: data <= 8'h00;
// 10h: first (top) horizontal line
11'h080: data <= 8'hFF;
11'h081: data <= 8'h00;
11'h082: data <= 8'h00;
11'h083: data <= 8'h00;
11'h084: data <= 8'h00;
11'h085: data <= 8'h00;
11'h086: data <= 8'h00;
11'h087: data <= 8'h00;
// 11h: second horizontal line
11'h088: data <= 8'h00;
11'h089: data <= 8'hFF;
11'h08A: data <= 8'h00;
11'h08B: data <= 8'h00;
11'h08C: data <= 8'h00;
11'h08D: data <= 8'h00;
11'h08E: data <= 8'h00;
11'h08F: data <= 8'h00;
// 12h: third horizontal line
11'h090: data <= 8'h00;
11'h091: data <= 8'h00;
11'h092: data <= 8'hFF;
11'h093: data <= 8'h00;
11'h094: data <= 8'h00;
11'h095: data <= 8'h00;
11'h096: data <= 8'h00;
11'h097: data <= 8'h00;
// 13h: fourth horizontal line
11'h098: data <= 8'h00;
11'h099: data <= 8'h00;
11'h09A: data <= 8'h00;
11'h09B: data <= 8'hFF;
11'h09C: data <= 8'h00;
11'h09D: data <= 8'h00;
11'h09E: data <= 8'h00;
11'h09F: data <= 8'h00;
// 14h: fifth horizontal line
11'h0A0: data <= 8'h00;
11'h0A1: data <= 8'h00;
11'h0A2: data <= 8'h00;
11'h0A3: data <= 8'h00;
11'h0A4: data <= 8'hFF;
11'h0A5: data <= 8'h00;
11'h0A6: data <= 8'h00;
// 15h: sixth horizontal line
11'h0A7: data <= 8'h00;
11'h0A8: data <= 8'h00;
11'h0A9: data <= 8'h00;
11'h0AA: data <= 8'h00;
11'h0AB: data <= 8'h00;
11'h0AC: data <= 8'h00;
11'h0AD: data <= 8'hFF;
11'h0AE: data <= 8'h00;
11'h0AF: data <= 8'h00;
// 16h: seventh horizontal line
11'h0B0: data <= 8'h00;
11'h0B1: data <= 8'h00;
11'h0B2: data <= 8'h00;
11'h0B3: data <= 8'h00;
11'h0B4: data <= 8'h00;
11'h0B5: data <= 8'h00;
11'h0B6: data <= 8'hFF;
11'h0B7: data <= 8'h00;
// 17h: eighth (bottom) horizontal line
11'h0B8: data <= 8'h00;
11'h0B9: data <= 8'h00;
11'h0BA: data <= 8'h00;
11'h0BB: data <= 8'h00;
11'h0BC: data <= 8'h00;
11'h0BD: data <= 8'h00;
11'h0BE: data <= 8'h00;
11'h0BF: data <= 8'hFF;
// 18h: first (left) vertical line
11'h0C0: data <= 8'h80;
11'h0C1: data <= 8'h80;
11'h0C2: data <= 8'h80;
11'h0C3: data <= 8'h80;
11'h0C4: data <= 8'h80;
11'h0C5: data <= 8'h80;
11'h0C6: data <= 8'h80;
11'h0C7: data <= 8'h80;
// 19h: second vertical line
11'h0C8: data <= 8'h40;
11'h0C9: data <= 8'h40;
11'h0CA: data <= 8'h40;
11'h0CB: data <= 8'h40;
11'h0CC: data <= 8'h40;
11'h0CD: data <= 8'h40;
11'h0CE: data <= 8'h40;
11'h0CF: data <= 8'h40;
// 1Ah: third vertical line
11'h0D0: data <= 8'h20;
11'h0D1: data <= 8'h20;
11'h0D2: data <= 8'h20;
11'h0D3: data <= 8'h20;
11'h0D4: data <= 8'h20;
11'h0D5: data <= 8'h20;
11'h0D6: data <= 8'h20;
11'h0D7: data <= 8'h20;
// 1Bh: fourth vertical line
11'h0D8: data <= 8'h10;
11'h0D9: data <= 8'h10;
11'h0DA: data <= 8'h10;
11'h0DB: data <= 8'h10;
11'h0DC: data <= 8'h10;
11'h0DD: data <= 8'h10;
11'h0DE: data <= 8'h10;
11'h0DF: data <= 8'h10;
// 1Ch: fifth vertical line
11'h0E0: data <= 8'h08;
11'h0E1: data <= 8'h08;
11'h0E2: data <= 8'h08;
11'h0E3: data <= 8'h08;
11'h0E4: data <= 8'h08;
11'h0E5: data <= 8'h08;
11'h0E6: data <= 8'h08;
11'h0E7: data <= 8'h08;
// 1Dh: sixth vertical line
11'h0E8: data <= 8'h04;
11'h0E9: data <= 8'h04;
11'h0EA: data <= 8'h04;
11'h0EB: data <= 8'h04;
11'h0EC: data <= 8'h04;
11'h0ED: data <= 8'h04;
11'h0EE: data <= 8'h04;
11'h0EF: data <= 8'h04;
// 1Eh: seventh vertical line
11'h0F0: data <= 8'h02;
11'h0F1: data <= 8'h02;
11'h0F2: data <= 8'h02;
11'h0F3: data <= 8'h02;
11'h0F4: data <= 8'h02;
11'h0F5: data <= 8'h02;
11'h0F6: data <= 8'h02;
11'h0F7: data <= 8'h02;
// 1Fh: eighth (right) vertical line
11'h0F8: data <= 8'h01;
11'h0F9: data <= 8'h01;
11'h0FA: data <= 8'h01;
11'h0FB: data <= 8'h01;
11'h0FC: data <= 8'h01;
11'h0FD: data <= 8'h01;
11'h0FE: data <= 8'h01;
11'h0FF: data <= 8'h01;
//// ASCII Characters ////
// 20h: space
11'h100: data <= 8'h00;
11'h101: data <= 8'h00;
11'h102: data <= 8'h00;
11'h103: data <= 8'h00;
11'h104: data <= 8'h00;
11'h105: data <= 8'h00;
11'h106: data <= 8'h00;
11'h107: data <= 8'h00;
// 21h: !
11'h108: data <= 8'h10;
11'h109: data <= 8'h10;
11'h10A: data <= 8'h10;
11'h10B: data <= 8'h10;
11'h10C: data <= 8'h00;
11'h10D: data <= 8'h00;
11'h10E: data <= 8'h10;
11'h10F: data <= 8'h00;
// 22h: "
11'h110: data <= 8'h28;
11'h111: data <= 8'h28;
11'h112: data <= 8'h28;
11'h113: data <= 8'h00;
11'h114: data <= 8'h00;
11'h115: data <= 8'h00;
11'h116: data <= 8'h00;
11'h117: data <= 8'h00;
// 23h: #
11'h118: data <= 8'h28;
11'h119: data <= 8'h28;
11'h11A: data <= 8'h7C;
11'h11B: data <= 8'h28;
11'h11C: data <= 8'h7C;
11'h11D: data <= 8'h28;
11'h11E: data <= 8'h28;
11'h11F: data <= 8'h00;
// 24h: $
11'h120: data <= 8'h10;
11'h121: data <= 8'h3C;
11'h122: data <= 8'h50;
11'h123: data <= 8'h38;
11'h124: data <= 8'h14;
11'h125: data <= 8'h78;
11'h126: data <= 8'h10;
11'h127: data <= 8'h00;
// 25h: %
11'h128: data <= 8'h60;
11'h129: data <= 8'h64;
11'h12A: data <= 8'h08;
11'h12B: data <= 8'h10;
11'h12C: data <= 8'h20;
11'h12D: data <= 8'h46;
11'h12E: data <= 8'h06;
11'h12F: data <= 8'h00;
// 26h: &
11'h130: data <= 8'h30;
11'h131: data <= 8'h48;
11'h132: data <= 8'h50;
11'h133: data <= 8'h20;
11'h134: data <= 8'h54;
11'h135: data <= 8'h48;
11'h136: data <= 8'h34;
11'h137: data <= 8'h00;
// 27h: '
11'h138: data <= 8'h30;
11'h139: data <= 8'h10;
11'h13A: data <= 8'h20;
11'h13B: data <= 8'h00;
11'h13C: data <= 8'h00;
11'h13D: data <= 8'h00;
11'h13E: data <= 8'h00;
11'h13F: data <= 8'h00;
// 28h: (
11'h140: data <= 8'h08;
11'h141: data <= 8'h10;
11'h142: data <= 8'h20;
11'h143: data <= 8'h20;
11'h144: data <= 8'h20;
11'h145: data <= 8'h10;
11'h146: data <= 8'h08;
11'h147: data <= 8'h00;
// 29h: )
11'h148: data <= 8'h20;
11'h149: data <= 8'h10;
11'h14A: data <= 8'h08;
11'h14B: data <= 8'h08;
11'h14C: data <= 8'h08;
11'h14D: data <= 8'h10;
11'h14E: data <= 8'h20;
11'h14F: data <= 8'h00;
// 2Ah: *
11'h150: data <= 8'h00;
11'h151: data <= 8'h10;
11'h152: data <= 8'h54;
11'h153: data <= 8'h38;
11'h154: data <= 8'h54;
11'h155: data <= 8'h10;
11'h156: data <= 8'h00;
11'h157: data <= 8'h00;
// 2Bh: +
11'h158: data <= 8'h00;
11'h159: data <= 8'h10;
11'h15A: data <= 8'h10;
11'h15B: data <= 8'h7C;
11'h15C: data <= 8'h10;
11'h15D: data <= 8'h10;
11'h15E: data <= 8'h00;
11'h15F: data <= 8'h00;
// 2Ch: ,
11'h160: data <= 8'h00;
11'h161: data <= 8'h00;
11'h162: data <= 8'h00;
11'h163: data <= 8'h00;
11'h164: data <= 8'h00;
11'h165: data <= 8'h30;
11'h166: data <= 8'h10;
11'h167: data <= 8'h20;
// 2Dh: -
11'h168: data <= 8'h00;
11'h169: data <= 8'h00;
11'h16A: data <= 8'h00;
11'h16B: data <= 8'h7C;
11'h16C: data <= 8'h00;
11'h16D: data <= 8'h00;
11'h16E: data <= 8'h00;
11'h16F: data <= 8'h00;
// 2Eh: .
11'h170: data <= 8'h00;
11'h171: data <= 8'h00;
11'h172: data <= 8'h00;
11'h173: data <= 8'h00;
11'h174: data <= 8'h00;
11'h175: data <= 8'h30;
11'h176: data <= 8'h30;
11'h177: data <= 8'h00;
// 2Fh: /
11'h178: data <= 8'h00;
11'h179: data <= 8'h04;
11'h17A: data <= 8'h08;
11'h17B: data <= 8'h10;
11'h17C: data <= 8'h20;
11'h17D: data <= 8'h40;
11'h17E: data <= 8'h00;
11'h17F: data <= 8'h00;
// 30h: 0
11'h180: data <= 8'h38;
11'h181: data <= 8'h44;
11'h182: data <= 8'h4C;
11'h183: data <= 8'h54;
11'h184: data <= 8'h64;
11'h185: data <= 8'h44;
11'h186: data <= 8'h38;
11'h187: data <= 8'h00;
// 31h: 1
11'h188: data <= 8'h10;
11'h189: data <= 8'h30;
11'h18A: data <= 8'h10;
11'h18B: data <= 8'h10;
11'h18C: data <= 8'h10;
11'h18D: data <= 8'h10;
11'h18E: data <= 8'h38;
11'h18F: data <= 8'h00;
// 32h: 2
11'h190: data <= 8'h38;
11'h191: data <= 8'h44;
11'h192: data <= 8'h04;
11'h193: data <= 8'h08;
11'h194: data <= 8'h10;
11'h195: data <= 8'h20;
11'h196: data <= 8'h7C;
11'h197: data <= 8'h00;
// 33h: 3
11'h198: data <= 8'h7C;
11'h199: data <= 8'h08;
11'h19A: data <= 8'h10;
11'h19B: data <= 8'h08;
11'h19C: data <= 8'h04;
11'h19D: data <= 8'h44;
11'h19E: data <= 8'h38;
11'h19F: data <= 8'h00;
// 34h: 4
11'h1A0: data <= 8'h08;
11'h1A1: data <= 8'h18;
11'h1A2: data <= 8'h28;
11'h1A3: data <= 8'h48;
11'h1A4: data <= 8'h7C;
11'h1A5: data <= 8'h08;
11'h1A6: data <= 8'h08;
11'h1A7: data <= 8'h00;
// 35h: 5
11'h1A8: data <= 8'h7C;
11'h1A9: data <= 8'h40;
11'h1AA: data <= 8'h78;
11'h1AB: data <= 8'h04;
11'h1AC: data <= 8'h04;
11'h1AD: data <= 8'h44;
11'h1AE: data <= 8'h38;
11'h1AF: data <= 8'h00;
// 36h: 6
11'h1B0: data <= 8'h18;
11'h1B1: data <= 8'h20;
11'h1B2: data <= 8'h40;
11'h1B3: data <= 8'h78;
11'h1B4: data <= 8'h44;
11'h1B5: data <= 8'h44;
11'h1B6: data <= 8'h38;
11'h1B7: data <= 8'h00;
// 37h: 7
11'h1B8: data <= 8'h7C;
11'h1B9: data <= 8'h04;
11'h1BA: data <= 8'h08;
11'h1BB: data <= 8'h10;
11'h1BC: data <= 8'h20;
11'h1BD: data <= 8'h20;
11'h1BE: data <= 8'h20;
11'h1BF: data <= 8'h00;
// 38h: 8
11'h1C0: data <= 8'h38;
11'h1C1: data <= 8'h44;
11'h1C2: data <= 8'h44;
11'h1C3: data <= 8'h38;
11'h1C4: data <= 8'h44;
11'h1C5: data <= 8'h44;
11'h1C6: data <= 8'h38;
11'h1C7: data <= 8'h00;
// 39h: 9
11'h1C8: data <= 8'h38;
11'h1C9: data <= 8'h44;
11'h1CA: data <= 8'h44;
11'h1CB: data <= 8'h3C;
11'h1CC: data <= 8'h04;
11'h1CD: data <= 8'h08;
11'h1CE: data <= 8'h30;
11'h1CF: data <= 8'h00;
// 3Ah: :
11'h1D0: data <= 8'h00;
11'h1D1: data <= 8'h30;
11'h1D2: data <= 8'h30;
11'h1D3: data <= 8'h00;
11'h1D4: data <= 8'h00;
11'h1D5: data <= 8'h30;
11'h1D6: data <= 8'h30;
11'h1D7: data <= 8'h00;
// 3Bh: ;
11'h1D8: data <= 8'h00;
11'h1D9: data <= 8'h30;
11'h1DA: data <= 8'h30;
11'h1DB: data <= 8'h00;
11'h1DC: data <= 8'h00;
11'h1DD: data <= 8'h30;
11'h1DE: data <= 8'h10;
11'h1DF: data <= 8'h20;
// 3Ch: <
11'h1E0: data <= 8'h08;
11'h1E1: data <= 8'h10;
11'h1E2: data <= 8'h20;
11'h1E3: data <= 8'h40;
11'h1E4: data <= 8'h20;
11'h1E5: data <= 8'h10;
11'h1E6: data <= 8'h08;
11'h1E7: data <= 8'h00;
// 3Dh: =
11'h1E8: data <= 8'h00;
11'h1E9: data <= 8'h00;
11'h1EA: data <= 8'h7C;
11'h1EB: data <= 8'h00;
11'h1EC: data <= 8'h7C;
11'h1ED: data <= 8'h00;
11'h1EE: data <= 8'h00;
11'h1EF: data <= 8'h00;
// 3Eh: >
11'h1F0: data <= 8'h20;
11'h1F1: data <= 8'h10;
11'h1F2: data <= 8'h08;
11'h1F3: data <= 8'h04;
11'h1F4: data <= 8'h08;
11'h1F5: data <= 8'h10;
11'h1F6: data <= 8'h20;
11'h1F7: data <= 8'h00;
// 3Fh: ?
11'h1F8: data <= 8'h38;
11'h1F9: data <= 8'h44;
11'h1FA: data <= 8'h04;
11'h1FB: data <= 8'h08;
11'h1FC: data <= 8'h10;
11'h1FD: data <= 8'h00;
11'h1FE: data <= 8'h10;
11'h1FF: data <= 8'h00;
// 40h: @
11'h200: data <= 8'h38;
11'h201: data <= 8'h44;
11'h202: data <= 8'h04;
11'h203: data <= 8'h34;
11'h204: data <= 8'h54;
11'h205: data <= 8'h54;
11'h206: data <= 8'h38;
11'h207: data <= 8'h00;
// 41h: A
11'h208: data <= 8'h38;
11'h209: data <= 8'h44;
11'h20A: data <= 8'h44;
11'h20B: data <= 8'h44;
11'h20C: data <= 8'h7C;
11'h20D: data <= 8'h44;
11'h20E: data <= 8'h44;
11'h20F: data <= 8'h00;
// 42h: B
11'h210: data <= 8'h78;
11'h211: data <= 8'h44;
11'h212: data <= 8'h44;
11'h213: data <= 8'h78;
11'h214: data <= 8'h44;
11'h215: data <= 8'h44;
11'h216: data <= 8'h78;
11'h217: data <= 8'h00;
// 43h: C
11'h218: data <= 8'h38;
11'h219: data <= 8'h44;
11'h21A: data <= 8'h40;
11'h21B: data <= 8'h40;
11'h21C: data <= 8'h40;
11'h21D: data <= 8'h44;
11'h21E: data <= 8'h38;
11'h21F: data <= 8'h00;
// 44h: D
11'h220: data <= 8'h70;
11'h221: data <= 8'h48;
11'h222: data <= 8'h44;
11'h223: data <= 8'h44;
11'h224: data <= 8'h44;
11'h225: data <= 8'h48;
11'h226: data <= 8'h70;
11'h227: data <= 8'h00;
// 45h: E
11'h228: data <= 8'h7C;
11'h229: data <= 8'h40;
11'h22A: data <= 8'h40;
11'h22B: data <= 8'h78;
11'h22C: data <= 8'h40;
11'h22D: data <= 8'h40;
11'h22E: data <= 8'h7C;
11'h22F: data <= 8'h00;
// 46h: F
11'h230: data <= 8'h7C;
11'h231: data <= 8'h40;
11'h232: data <= 8'h40;
11'h233: data <= 8'h78;
11'h234: data <= 8'h40;
11'h235: data <= 8'h40;
11'h236: data <= 8'h40;
11'h237: data <= 8'h00;
// 47h: G
11'h238: data <= 8'h38;
11'h239: data <= 8'h44;
11'h23A: data <= 8'h40;
11'h23B: data <= 8'h5C;
11'h23C: data <= 8'h44;
11'h23D: data <= 8'h44;
11'h23E: data <= 8'h3C;
11'h23F: data <= 8'h00;
// 48h: H
11'h240: data <= 8'h44;
11'h241: data <= 8'h44;
11'h242: data <= 8'h44;
11'h243: data <= 8'h7C;
11'h244: data <= 8'h44;
11'h245: data <= 8'h44;
11'h246: data <= 8'h44;
11'h247: data <= 8'h00;
// 49h: I
11'h248: data <= 8'h38;
11'h249: data <= 8'h10;
11'h24A: data <= 8'h10;
11'h24B: data <= 8'h10;
11'h24C: data <= 8'h10;
11'h24D: data <= 8'h10;
11'h24E: data <= 8'h38;
11'h24F: data <= 8'h00;
// 4Ah: J
11'h250: data <= 8'h1C;
11'h251: data <= 8'h08;
11'h252: data <= 8'h08;
11'h253: data <= 8'h08;
11'h254: data <= 8'h08;
11'h255: data <= 8'h48;
11'h256: data <= 8'h30;
11'h257: data <= 8'h00;
// 4Bh: K
11'h258: data <= 8'h44;
11'h259: data <= 8'h48;
11'h25A: data <= 8'h50;
11'h25B: data <= 8'h60;
11'h25C: data <= 8'h50;
11'h25D: data <= 8'h48;
11'h25E: data <= 8'h44;
11'h25F: data <= 8'h00;
// 4Ch: L
11'h260: data <= 8'h40;
11'h261: data <= 8'h40;
11'h262: data <= 8'h40;
11'h263: data <= 8'h40;
11'h264: data <= 8'h40;
11'h265: data <= 8'h40;
11'h266: data <= 8'h7C;
11'h267: data <= 8'h00;
// 4Dh: M
11'h268: data <= 8'h44;
11'h269: data <= 8'h6C;
11'h26A: data <= 8'h54;
11'h26B: data <= 8'h54;
11'h26C: data <= 8'h44;
11'h26D: data <= 8'h44;
11'h26E: data <= 8'h44;
11'h26F: data <= 8'h00;
// 4Eh: N
11'h270: data <= 8'h44;
11'h271: data <= 8'h44;
11'h272: data <= 8'h64;
11'h273: data <= 8'h54;
11'h274: data <= 8'h4C;
11'h275: data <= 8'h44;
11'h276: data <= 8'h44;
11'h277: data <= 8'h00;
// 4Fh: O
11'h278: data <= 8'h38;
11'h279: data <= 8'h44;
11'h27A: data <= 8'h44;
11'h27B: data <= 8'h44;
11'h27C: data <= 8'h44;
11'h27D: data <= 8'h44;
11'h27E: data <= 8'h38;
11'h27F: data <= 8'h00;
// 50h: P
11'h280: data <= 8'h78;
11'h281: data <= 8'h44;
11'h282: data <= 8'h44;
11'h283: data <= 8'h78;
11'h284: data <= 8'h40;
11'h285: data <= 8'h40;
11'h286: data <= 8'h40;
11'h287: data <= 8'h00;
// 51h: Q
11'h288: data <= 8'h38;
11'h289: data <= 8'h44;
11'h28A: data <= 8'h44;
11'h28B: data <= 8'h44;
11'h28C: data <= 8'h54;
11'h28D: data <= 8'h48;
11'h28E: data <= 8'h34;
11'h28F: data <= 8'h00;
// 52h: R
11'h290: data <= 8'h78;
11'h291: data <= 8'h44;
11'h292: data <= 8'h44;
11'h293: data <= 8'h78;
11'h294: data <= 8'h50;
11'h295: data <= 8'h48;
11'h296: data <= 8'h44;
11'h297: data <= 8'h00;
// 53h: S
11'h298: data <= 8'h3C;
11'h299: data <= 8'h40;
11'h29A: data <= 8'h40;
11'h29B: data <= 8'h38;
11'h29C: data <= 8'h04;
11'h29D: data <= 8'h04;
11'h29E: data <= 8'h78;
11'h29F: data <= 8'h00;
// 54h: T
11'h2A0: data <= 8'h7C;
11'h2A1: data <= 8'h10;
11'h2A2: data <= 8'h10;
11'h2A3: data <= 8'h10;
11'h2A4: data <= 8'h10;
11'h2A5: data <= 8'h10;
11'h2A6: data <= 8'h10;
11'h2A7: data <= 8'h00;
// 55h: U
11'h2A8: data <= 8'h44;
11'h2A9: data <= 8'h44;
11'h2AA: data <= 8'h44;
11'h2AB: data <= 8'h44;
11'h2AC: data <= 8'h44;
11'h2AD: data <= 8'h44;
11'h2AE: data <= 8'h38;
11'h2AF: data <= 8'h00;
// 56h: V
11'h2B0: data <= 8'h44;
11'h2B1: data <= 8'h44;
11'h2B2: data <= 8'h44;
11'h2B3: data <= 8'h44;
11'h2B4: data <= 8'h44;
11'h2B5: data <= 8'h28;
11'h2B6: data <= 8'h10;
11'h2B7: data <= 8'h00;
// 57h: W
11'h2B8: data <= 8'h44;
11'h2B9: data <= 8'h44;
11'h2BA: data <= 8'h44;
11'h2BB: data <= 8'h54;
11'h2BC: data <= 8'h54;
11'h2BD: data <= 8'h54;
11'h2BE: data <= 8'h28;
11'h2BF: data <= 8'h00;
// 58h: X
11'h2C0: data <= 8'h44;
11'h2C1: data <= 8'h44;
11'h2C2: data <= 8'h28;
11'h2C3: data <= 8'h10;
11'h2C4: data <= 8'h28;
11'h2C5: data <= 8'h44;
11'h2C6: data <= 8'h44;
11'h2C7: data <= 8'h00;
// 59h: Y
11'h2C8: data <= 8'h44;
11'h2C9: data <= 8'h44;
11'h2CA: data <= 8'h44;
11'h2CB: data <= 8'h28;
11'h2CC: data <= 8'h10;
11'h2CD: data <= 8'h10;
11'h2CE: data <= 8'h10;
11'h2CF: data <= 8'h00;
// 5Ah: Z
11'h2D0: data <= 8'h7C;
11'h2D1: data <= 8'h04;
11'h2D2: data <= 8'h08;
11'h2D3: data <= 8'h10;
11'h2D4: data <= 8'h20;
11'h2D5: data <= 8'h40;
11'h2D6: data <= 8'h7C;
11'h2D7: data <= 8'h00;
// 5Bh: [
11'h2D8: data <= 8'h38;
11'h2D9: data <= 8'h20;
11'h2DA: data <= 8'h20;
11'h2DB: data <= 8'h20;
11'h2DC: data <= 8'h20;
11'h2DD: data <= 8'h20;
11'h2DE: data <= 8'h38;
11'h2DF: data <= 8'h00;
// 5Ch: \
11'h2E0: data <= 8'h00;
11'h2E1: data <= 8'h40;
11'h2E2: data <= 8'h20;
11'h2E3: data <= 8'h10;
11'h2E4: data <= 8'h08;
11'h2E5: data <= 8'h04;
11'h2E6: data <= 8'h00;
11'h2E7: data <= 8'h00;
// 5Dh: ]
11'h2E8: data <= 8'h38;
11'h2E9: data <= 8'h08;
11'h2EA: data <= 8'h08;
11'h2EB: data <= 8'h08;
11'h2EC: data <= 8'h08;
11'h2ED: data <= 8'h08;
11'h2EE: data <= 8'h38;
11'h2EF: data <= 8'h00;
// 5Eh: ^
11'h2F0: data <= 8'h10;
11'h2F1: data <= 8'h28;
11'h2F2: data <= 8'h44;
11'h2F3: data <= 8'h00;
11'h2F4: data <= 8'h00;
11'h2F5: data <= 8'h00;
11'h2F6: data <= 8'h00;
11'h2F7: data <= 8'h00;
// 5Fh: _
11'h2F8: data <= 8'h00;
11'h2F9: data <= 8'h00;
11'h2FA: data <= 8'h00;
11'h2FB: data <= 8'h00;
11'h2FC: data <= 8'h00;
11'h2FD: data <= 8'h00;
11'h2FE: data <= 8'h7C;
11'h2FF: data <= 8'h00;
// 60h: `
11'h300: data <= 8'h20;
11'h301: data <= 8'h10;
11'h302: data <= 8'h08;
11'h303: data <= 8'h00;
11'h304: data <= 8'h00;
11'h305: data <= 8'h00;
11'h306: data <= 8'h00;
11'h307: data <= 8'h00;
// 61h: a
11'h308: data <= 8'h00;
11'h309: data <= 8'h00;
11'h30A: data <= 8'h38;
11'h30B: data <= 8'h04;
11'h30C: data <= 8'h3C;
11'h30D: data <= 8'h44;
11'h30E: data <= 8'h3C;
11'h30F: data <= 8'h00;
// 62h: b
11'h310: data <= 8'h40;
11'h311: data <= 8'h40;
11'h312: data <= 8'h58;
11'h313: data <= 8'h64;
11'h314: data <= 8'h44;
11'h315: data <= 8'h44;
11'h316: data <= 8'h78;
11'h317: data <= 8'h00;
// 63h: c
11'h318: data <= 8'h00;
11'h319: data <= 8'h00;
11'h31A: data <= 8'h38;
11'h31B: data <= 8'h40;
11'h31C: data <= 8'h40;
11'h31D: data <= 8'h44;
11'h31E: data <= 8'h38;
11'h31F: data <= 8'h00;
// 64h: d
11'h320: data <= 8'h04;
11'h321: data <= 8'h04;
11'h322: data <= 8'h34;
11'h323: data <= 8'h4C;
11'h324: data <= 8'h44;
11'h325: data <= 8'h44;
11'h326: data <= 8'h3C;
11'h327: data <= 8'h00;
// 65h: e
11'h328: data <= 8'h00;
11'h329: data <= 8'h00;
11'h32A: data <= 8'h38;
11'h32B: data <= 8'h44;
11'h32C: data <= 8'h7C;
11'h32D: data <= 8'h40;
11'h32E: data <= 8'h38;
11'h32F: data <= 8'h00;
// 66h: f
11'h330: data <= 8'h18;
11'h331: data <= 8'h24;
11'h332: data <= 8'h20;
11'h333: data <= 8'h70;
11'h334: data <= 8'h20;
11'h335: data <= 8'h20;
11'h336: data <= 8'h20;
11'h337: data <= 8'h00;
// 67h: g
11'h338: data <= 8'h00;
11'h339: data <= 8'h00;
11'h33A: data <= 8'h3C;
11'h33B: data <= 8'h44;
11'h33C: data <= 8'h44;
11'h33D: data <= 8'h3C;
11'h33E: data <= 8'h04;
11'h33F: data <= 8'h38;
// 68h: h
11'h340: data <= 8'h40;
11'h341: data <= 8'h40;
11'h342: data <= 8'h58;
11'h343: data <= 8'h64;
11'h344: data <= 8'h44;
11'h345: data <= 8'h44;
11'h346: data <= 8'h44;
11'h347: data <= 8'h00;
// 69h: i
11'h348: data <= 8'h10;
11'h349: data <= 8'h10;
11'h34A: data <= 8'h30;
11'h34B: data <= 8'h10;
11'h34C: data <= 8'h10;
11'h34D: data <= 8'h10;
11'h34E: data <= 8'h38;
11'h34F: data <= 8'h00;
// 6Ah: j
11'h350: data <= 8'h00;
11'h351: data <= 8'h08;
11'h352: data <= 8'h00;
11'h353: data <= 8'h18;
11'h354: data <= 8'h08;
11'h355: data <= 8'h08;
11'h356: data <= 8'h48;
11'h357: data <= 8'h30;
// 6Bh: k
11'h358: data <= 8'h40;
11'h359: data <= 8'h40;
11'h35A: data <= 8'h48;
11'h35B: data <= 8'h50;
11'h35C: data <= 8'h60;
11'h35D: data <= 8'h50;
11'h35E: data <= 8'h48;
11'h35F: data <= 8'h00;
// 6Ch: l
11'h360: data <= 8'h30;
11'h361: data <= 8'h10;
11'h362: data <= 8'h10;
11'h363: data <= 8'h10;
11'h364: data <= 8'h10;
11'h365: data <= 8'h10;
11'h366: data <= 8'h38;
11'h367: data <= 8'h00;
// 6Dh: m
11'h368: data <= 8'h00;
11'h369: data <= 8'h00;
11'h36A: data <= 8'h68;
11'h36B: data <= 8'h54;
11'h36C: data <= 8'h54;
11'h36D: data <= 8'h44;
11'h36E: data <= 8'h44;
11'h36F: data <= 8'h00;
// 6Eh: n
11'h370: data <= 8'h00;
11'h371: data <= 8'h00;
11'h372: data <= 8'h58;
11'h373: data <= 8'h64;
11'h374: data <= 8'h44;
11'h375: data <= 8'h44;
11'h376: data <= 8'h44;
11'h377: data <= 8'h00;
// 6Fh: o
11'h378: data <= 8'h00;
11'h379: data <= 8'h00;
11'h37A: data <= 8'h38;
11'h37B: data <= 8'h44;
11'h37C: data <= 8'h44;
11'h37D: data <= 8'h44;
11'h37E: data <= 8'h38;
11'h37F: data <= 8'h00;
// 70h: p
11'h380: data <= 8'h00;
11'h381: data <= 8'h00;
11'h382: data <= 8'h78;
11'h383: data <= 8'h44;
11'h384: data <= 8'h78;
11'h385: data <= 8'h40;
11'h386: data <= 8'h40;
11'h387: data <= 8'h40;
// 71h: q
11'h388: data <= 8'h00;
11'h389: data <= 8'h00;
11'h38A: data <= 8'h00;
11'h38B: data <= 8'h34;
11'h38C: data <= 8'h4C;
11'h38D: data <= 8'h3C;
11'h38E: data <= 8'h04;
11'h38F: data <= 8'h04;
// 72h: r
11'h390: data <= 8'h00;
11'h391: data <= 8'h00;
11'h392: data <= 8'h58;
11'h393: data <= 8'h64;
11'h394: data <= 8'h40;
11'h395: data <= 8'h40;
11'h396: data <= 8'h40;
11'h397: data <= 8'h00;
// 73h: s
11'h398: data <= 8'h00;
11'h399: data <= 8'h00;
11'h39A: data <= 8'h38;
11'h39B: data <= 8'h40;
11'h39C: data <= 8'h38;
11'h39D: data <= 8'h04;
11'h39E: data <= 8'h78;
11'h39F: data <= 8'h00;
// 74h: t
11'h3A0: data <= 8'h00;
11'h3A1: data <= 8'h20;
11'h3A2: data <= 8'h20;
11'h3A3: data <= 8'h70;
11'h3A4: data <= 8'h20;
11'h3A5: data <= 8'h20;
11'h3A6: data <= 8'h24;
11'h3A7: data <= 8'h18;
// 75h: u
11'h3A8: data <= 8'h00;
11'h3A9: data <= 8'h00;
11'h3AA: data <= 8'h44;
11'h3AB: data <= 8'h44;
11'h3AC: data <= 8'h44;
11'h3AD: data <= 8'h4C;
11'h3AE: data <= 8'h34;
11'h3AF: data <= 8'h00;
// 76h: v
11'h3B0: data <= 8'h00;
11'h3B1: data <= 8'h00;
11'h3B2: data <= 8'h44;
11'h3B3: data <= 8'h44;
11'h3B4: data <= 8'h44;
11'h3B5: data <= 8'h28;
11'h3B6: data <= 8'h10;
11'h3B7: data <= 8'h00;
// 77h: w
11'h3B8: data <= 8'h00;
11'h3B9: data <= 8'h00;
11'h3BA: data <= 8'h44;
11'h3BB: data <= 8'h44;
11'h3BC: data <= 8'h54;
11'h3BD: data <= 8'h54;
11'h3BE: data <= 8'h28;
11'h3BF: data <= 8'h00;
// 78h: x
11'h3C0: data <= 8'h00;
11'h3C1: data <= 8'h00;
11'h3C2: data <= 8'h44;
11'h3C3: data <= 8'h28;
11'h3C4: data <= 8'h10;
11'h3C5: data <= 8'h28;
11'h3C6: data <= 8'h44;
11'h3C7: data <= 8'h00;
// 79h: y
11'h3C8: data <= 8'h00;
11'h3C9: data <= 8'h00;
11'h3CA: data <= 8'h00;
11'h3CB: data <= 8'h44;
11'h3CC: data <= 8'h44;
11'h3CD: data <= 8'h3C;
11'h3CE: data <= 8'h04;
11'h3CF: data <= 8'h38;
// 7Ah: z
11'h3D0: data <= 8'h00;
11'h3D1: data <= 8'h00;
11'h3D2: data <= 8'h7C;
11'h3D3: data <= 8'h08;
11'h3D4: data <= 8'h10;
11'h3D5: data <= 8'h20;
11'h3D6: data <= 8'h7C;
11'h3D7: data <= 8'h00;
// 7Bh: {
11'h3D8: data <= 8'h08;
11'h3D9: data <= 8'h10;
11'h3DA: data <= 8'h10;
11'h3DB: data <= 8'h20;
11'h3DC: data <= 8'h10;
11'h3DD: data <= 8'h10;
11'h3DE: data <= 8'h08;
11'h3DF: data <= 8'h00;
// 7Ch: |
11'h3E0: data <= 8'h10;
11'h3E1: data <= 8'h10;
11'h3E2: data <= 8'h10;
11'h3E3: data <= 8'h10;
11'h3E4: data <= 8'h10;
11'h3E5: data <= 8'h10;
11'h3E6: data <= 8'h10;
11'h3E7: data <= 8'h00;
// 7Dh: }
11'h3E8: data <= 8'h20;
11'h3E9: data <= 8'h10;
11'h3EA: data <= 8'h10;
11'h3EB: data <= 8'h08;
11'h3EC: data <= 8'h10;
11'h3ED: data <= 8'h10;
11'h3EE: data <= 8'h20;
11'h3EF: data <= 8'h00;
// 7Eh: ~
11'h3F0: data <= 8'h00;
11'h3F1: data <= 8'h00;
11'h3F2: data <= 8'h60;
11'h3F3: data <= 8'h92;
11'h3F4: data <= 8'h0C;
11'h3F5: data <= 8'h00;
11'h3F6: data <= 8'h00;
11'h3F7: data <= 8'h00;
//// Hash Pattern ////
// 7Fh: hash pattern
11'h3F8: data <= 8'h55;
11'h3F9: data <= 8'hAA;
11'h3FA: data <= 8'h55;
11'h3FB: data <= 8'hAA;
11'h3FC: data <= 8'h55;
11'h3FD: data <= 8'hAA;
11'h3FE: data <= 8'h55;
11'h3FF: data <= 8'hAA;
//// User Defined Characters ////
// 80h: vertical to the left
11'h400: data <= 8'hF0;
11'h401: data <= 8'hF0;
11'h402: data <= 8'hF0;
11'h403: data <= 8'hF0;
11'h404: data <= 8'hF0;
11'h405: data <= 8'hF0;
11'h406: data <= 8'hF0;
11'h407: data <= 8'hF0;
// 81h: vertical to the right
11'h408: data <= 8'h0F;
11'h409: data <= 8'h0F;
11'h40A: data <= 8'h0F;
11'h40B: data <= 8'h0F;
11'h40C: data <= 8'h0F;
11'h40D: data <= 8'h0F;
11'h40E: data <= 8'h0F;
11'h40F: data <= 8'h0F;
// 82h: circle
11'h410: data <= 8'h00;
11'h411: data <= 8'h18;
11'h412: data <= 8'h3C;
11'h413: data <= 8'h7E;
11'h414: data <= 8'h7E;
11'h415: data <= 8'h3C;
11'h416: data <= 8'h18;
11'h417: data <= 8'h00;
// 83h: Upper left block only
11'h418: data <= 8'hF0;
11'h419: data <= 8'hF0;
11'h41A: data <= 8'hF0;
11'h41B: data <= 8'hF0;
11'h41C: data <= 8'h00;
11'h41D: data <= 8'h00;
11'h41E: data <= 8'h00;
11'h41F: data <= 8'h00;
// 84h: Upper right block only
11'h420: data <= 8'h0F;
11'h421: data <= 8'h0F;
11'h422: data <= 8'h0F;
11'h423: data <= 8'h0F;
11'h424: data <= 8'h00;
11'h425: data <= 8'h00;
11'h426: data <= 8'h00;
11'h427: data <= 8'h00;
// 85h: Lower left block only
11'h428: data <= 8'h00;
11'h429: data <= 8'h00;
11'h42A: data <= 8'h00;
11'h42B: data <= 8'h00;
11'h42C: data <= 8'hF0;
11'h42D: data <= 8'hF0;
11'h42E: data <= 8'hF0;
11'h42F: data <= 8'hF0;
// 86h: Lower right block only
11'h430: data <= 8'h00;
11'h431: data <= 8'h00;
11'h432: data <= 8'h00;
11'h433: data <= 8'h00;
11'h434: data <= 8'h0F;
11'h435: data <= 8'h0F;
11'h436: data <= 8'h0F;
11'h437: data <= 8'h0F;
// 87h: One horizontal line
11'h438: data <= 8'h00;
11'h439: data <= 8'h00;
11'h43A: data <= 8'h00;
11'h43B: data <= 8'h00;
11'h43C: data <= 8'h00;
11'h43D: data <= 8'h00;
11'h43E: data <= 8'h00;
11'h43F: data <= 8'hFF;
// 88h: Two horizontal lines
11'h440: data <= 8'h00;
11'h441: data <= 8'h00;
11'h442: data <= 8'h00;
11'h443: data <= 8'h00;
11'h444: data <= 8'h00;
11'h445: data <= 8'h00;
11'h446: data <= 8'hFF;
11'h447: data <= 8'hFF;
// 89h: Three horizontal lines
11'h448: data <= 8'h00;
11'h449: data <= 8'h00;
11'h44A: data <= 8'h00;
11'h44B: data <= 8'h00;
11'h44C: data <= 8'h00;
11'h44D: data <= 8'hFF;
11'h44E: data <= 8'hFF;
11'h44F: data <= 8'hFF;
// 8Ah: Four horizontal lines
11'h450: data <= 8'h00;
11'h451: data <= 8'h00;
11'h452: data <= 8'h00;
11'h453: data <= 8'h00;
11'h454: data <= 8'hFF;
11'h455: data <= 8'hFF;
11'h456: data <= 8'hFF;
11'h457: data <= 8'hFF;
// 8Bh: Five horizontal lines
11'h458: data <= 8'h00;
11'h459: data <= 8'h00;
11'h45A: data <= 8'h00;
11'h45B: data <= 8'hFF;
11'h45C: data <= 8'hFF;
11'h45D: data <= 8'hFF;
11'h45E: data <= 8'hFF;
11'h45F: data <= 8'hFF;
// 8Ch: Six horizontal lines
11'h460: data <= 8'h00;
11'h461: data <= 8'h00;
11'h462: data <= 8'hFF;
11'h463: data <= 8'hFF;
11'h464: data <= 8'hFF;
11'h465: data <= 8'hFF;
11'h466: data <= 8'hFF;
11'h467: data <= 8'hFF;
// 8Dh: Seven horizontal lines
11'h468: data <= 8'h00;
11'h469: data <= 8'hFF;
11'h46A: data <= 8'hFF;
11'h46B: data <= 8'hFF;
11'h46C: data <= 8'hFF;
11'h46D: data <= 8'hFF;
11'h46E: data <= 8'hFF;
11'h46F: data <= 8'hFF;
// 8Eh: One vertical line
11'h470: data <= 8'h80;
11'h471: data <= 8'h80;
11'h472: data <= 8'h80;
11'h473: data <= 8'h80;
11'h474: data <= 8'h80;
11'h475: data <= 8'h80;
11'h476: data <= 8'h80;
11'h477: data <= 8'h80;
// 8Fh: Two vertical lines
/*11'h478: data <= 8'hc0;
11'h479: data <= 8'hc0;
11'h47A: data <= 8'hc0;
11'h47B: data <= 8'hc0;
11'h47C: data <= 8'hc0;
11'h47D: data <= 8'hc0;
11'h47E: data <= 8'hc0;
11'h47F: data <= 8'hc0;*/
endcase
end
 
endmodule //CHAR_GEN_ROM
 
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_char_gen.v
0,0 → 1,179
`include "vga_char_interface_defines.v"
 
 
 
 
module `VARIANT`CHAR_GEN(
 
input pixel_clock,
input reset,
input [2:0] subchar_line, // line number within 8 line block
input [13:0] char_address, // character address "0" is upper left character
input [2:0] subchar_pixel, // pixel position within 8 pixel block
input [13:0] char_write_addr,
input [11:0] char_write_data,
input char_write_enable,
input char_write_clock,
 
 
output reg pixel_on,
output wire fore_red,
output wire fore_green,
output wire fore_blue,
output wire back_red,
output wire back_green,
output wire back_blue
);
 
 
reg latch_data;
reg latch_low_data;
reg shift_high;
reg shift_low;
reg [3:0] latched_low_char_data;
reg [7:0] latched_char_data;
 
 
wire [11:0] ascii_code;
wire [10:0] chargen_rom_address = {ascii_code[7:0], subchar_line[2:0]};
wire [7:0] char_gen_rom_data;
// instantiate the CHARACTER RAM
`VARIANT`CHAR_RAM CHAR_RAM
(
pixel_clock,
char_write_clock,
char_write_enable,
char_write_addr,
char_write_data,
 
char_address,
ascii_code
);
 
//assign back_red = ascii_code[10];
//assign back_green = ascii_code[9];
//assign back_blue = ascii_code[8];
 
//assign back_red = 0;
assign back_green = 0;
assign back_blue = 0;
 
assign fore_red = ascii_code[8];
assign fore_green = ascii_code[9];
assign fore_blue = ascii_code[10];
assign back_red = ascii_code[11];
 
// instantiate the character generator ROM
`VARIANT`CHAR_GEN_ROM CHAR_GEN_ROM
(
.pixel_clock ( pixel_clock ),
.chargen_rom_address ( chargen_rom_address ),
.char_gen_rom_data ( char_gen_rom_data )
);
 
// LATCH THE CHARTACTER DATA FROM THE CHAR GEN ROM AND CREATE A SERIAL CHAR DATA STREAM
always @ (posedge pixel_clock or posedge reset)begin
if (reset) begin
latch_data <= 1'b0;
end
else if (subchar_pixel == 3'b110) begin
latch_data <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
latch_data <= 1'b0;
end
end
 
always @ (posedge pixel_clock or posedge reset)begin
if (reset) begin
latch_low_data <= 1'b0;
end
else if (subchar_pixel == 3'b010) begin
latch_low_data <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
latch_low_data <= 1'b0;
end
end
 
always @ (posedge pixel_clock or posedge reset)begin
if (reset) begin
shift_high <= 1'b1;
end
else if (subchar_pixel == 3'b011) begin
shift_high <= 1'b0;
end
else if (subchar_pixel == 3'b111) begin
shift_high <= 1'b1;
end
end
 
always @ (posedge pixel_clock or posedge reset)begin
if (reset) begin
shift_low <= 1'b0;
end
else if (subchar_pixel == 3'b011) begin
shift_low <= 1'b1;
end
else if (subchar_pixel == 3'b111) begin
shift_low <= 1'b0;
end
end
 
// serialize the CHARACTER MODE data
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
begin
pixel_on = 1'b0;
latched_low_char_data = 4'h0;
latched_char_data = 8'h00;
end
 
else if (shift_high)
begin
pixel_on = latched_char_data [7];
latched_char_data [7] = latched_char_data [6];
latched_char_data [6] = latched_char_data [5];
latched_char_data [5] = latched_char_data [4];
latched_char_data [4] = latched_char_data [7];
if(latch_low_data) begin
latched_low_char_data [3:0] = latched_char_data [3:0];
end
else begin
latched_low_char_data [3:0] = latched_low_char_data [3:0];
end
end
 
else if (shift_low)
begin
pixel_on = latched_low_char_data [3];
latched_low_char_data [3] = latched_low_char_data [2];
latched_low_char_data [2] = latched_low_char_data [1];
latched_low_char_data [1] = latched_low_char_data [0];
latched_low_char_data [0] = latched_low_char_data [3];
if (latch_data) begin
latched_char_data [7:0] = char_gen_rom_data[7:0];
end
else begin
latched_char_data [7:0] = latched_char_data [7:0];
end
end
else
begin
latched_low_char_data [3:0] = latched_low_char_data [3:0];
latched_char_data [7:0] = latched_char_data [7:0];
pixel_on = pixel_on;
end
end
 
endmodule //CHAR_GEN
 
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_char_ram.v
0,0 → 1,78
`include "vga_char_interface_defines.v"
 
 
 
module `VARIANT`CHAR_RAM
(
clka,
wea,
addra,
dia,
 
clkb,
addrb,
dob
);
 
input clka;
input wea;
input [13:0] addra;
input [11:0] dia;
 
input clkb;
input [13:0] addrb;
output [11:0] dob;
 
//reg [11:0] ram [16383:0];
//reg [11:0] ram [8191:0];
reg [11:0] ram [4095:0];
reg [13:0] read_addrb;
 
always @(posedge clka) begin
if (wea)
ram[addra] <= dia;
end
 
always @(posedge clkb) begin
read_addrb <= addrb;
end
 
assign dob = ram[read_addrb];
 
// fill the character RAM with spaces
integer index;
initial begin
// for (index = 0; index <= 16383; index = index + 1) begin
for (index = 0; index <= 4095; index = index + 1) begin
ram[index] = 8'h20; // ASCII space
end
//for (index = 9998; index <= 16383; index = index + 1) begin
// ram[index] = 8'h20; // ASCII space
//end
end
 
endmodule //CHAR_RAM
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_video_out.v
0,0 → 1,58
`include "vga_char_interface_defines.v"
 
 
 
module `VARIANT`VIDEO_OUT
(
 
input wire pixel_clock,
input wire reset,
input wire vga_red_data,
input wire vga_green_data,
input wire vga_blue_data,
input wire h_synch,
input wire v_synch,
input wire blank,
 
output reg VGA_HSYNCH,
output reg VGA_VSYNCH,
output reg VGA_OUT_RED,
output reg VGA_OUT_GREEN,
output reg VGA_OUT_BLUE
 
);
 
 
 
// make the external video connections
always @ (posedge pixel_clock or posedge reset) begin
if (reset) begin
// shut down the video output during reset
VGA_HSYNCH <= 1'b1;
VGA_VSYNCH <= 1'b1;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else if (blank) begin
// output black during the blank signal
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= 1'b0;
VGA_OUT_GREEN <= 1'b0;
VGA_OUT_BLUE <= 1'b0;
end
else begin
// output color data otherwise
VGA_HSYNCH <= h_synch;
VGA_VSYNCH <= v_synch;
VGA_OUT_RED <= vga_red_data;
VGA_OUT_GREEN <= vga_green_data;
VGA_OUT_BLUE <= vga_blue_data;
end
end
 
endmodule // VIDEO_OUT
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_svga_timing_generator.v
0,0 → 1,269
 
`include "vga_char_interface_defines.v"
 
 
 
 
 
module `VARIANT`SVGA_TIMING_GENERATION
(
 
input wire pixel_clock, // pixel clock
input wire reset, // reset
output reg h_synch, // horizontal synch for VGA connector
output reg v_synch, // vertical synch for VGA connector
output reg blank, // composite blanking
output reg [10:0] pixel_count, // counts the pixels in a line
output reg [9:0] line_count, // counts the display lines
output reg [2:0] subchar_pixel, // pixel position within the character
output reg [2:0] subchar_line, // identifies the line number within a character block
output reg [6:0] char_column, // character number on the current line
output reg [6:0] char_line // line number on the screen
 
);
 
reg h_blank; // horizontal blanking
reg v_blank; // vertical blanking
 
reg [9:0] char_column_count; // a counter used to define the character column number
reg [9:0] char_line_count; // a counter used to define the character line number
reg reset_char_line; // flag to reset the character line during VBI
reg reset_char_column; // flag to reset the character column during HBI
 
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset set pixel counter to 0
pixel_count <= 11'd0;
else if (pixel_count == (`H_TOTAL - 1))
// last pixel in the line, so reset pixel counter
pixel_count <= 11'd0;
else
pixel_count <= pixel_count + 1;
end
 
// CREATE THE HORIZONTAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove h_synch
h_synch <= 1'b0;
else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
// start of h_synch
h_synch <= 1'b1;
else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
// end of h_synch
h_synch <= 1'b0;
end
 
// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset set line counter to 0
line_count <= 10'd0;
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
// last pixel in last line of frame, so reset line counter
line_count <= 10'd0;
else if ((pixel_count == (`H_TOTAL - 1)))
// last pixel but not last line, so increment line counter
line_count <= line_count + 1;
end
 
// CREATE THE VERTICAL SYNCH PULSE
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove v_synch
v_synch = 1'b0;
 
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
(pixel_count == `H_TOTAL - 1)))
// start of v_synch
v_synch = 1'b1;
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
(pixel_count == (`H_TOTAL - 1)))
// end of v_synch
v_synch = 1'b0;
end
 
 
// CREATE THE HORIZONTAL BLANKING SIGNAL
// the "-2" is used instead of "-1" because of the extra register delay
// for the composite blanking signal
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove the h_blank
h_blank <= 1'b0;
 
else if (pixel_count == (`H_ACTIVE -2))
// start of HBI
h_blank <= 1'b1;
else if (pixel_count == (`H_TOTAL -2))
// end of HBI
h_blank <= 1'b0;
end
 
 
// CREATE THE VERTICAL BLANKING SIGNAL
// the "-2" is used instead of "-1" in the horizontal factor because of the extra
// register delay for the composite blanking signal
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove v_blank
v_blank <= 1'b0;
 
else if ((line_count == (`V_ACTIVE - 1) &
(pixel_count == `H_TOTAL - 2)))
// start of VBI
v_blank <= 1'b1;
else if ((line_count == (`V_TOTAL - 1)) &
(pixel_count == (`H_TOTAL - 2)))
// end of VBI
v_blank <= 1'b0;
end
 
 
// CREATE THE COMPOSITE BANKING SIGNAL
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset remove blank
blank <= 1'b0;
 
// blank during HBI or VBI
else if (h_blank || v_blank)
blank <= 1'b1;
else
// active video do not blank
blank <= 1'b0;
end
 
 
/*
CREATE THE CHARACTER COUNTER.
CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
 
A 640 x 480 video mode will display 80 characters on 60 lines.
A 800 x 600 video mode will display 100 characters on 75 lines.
A 1024 x 768 video mode will display 128 characters on 96 lines.
 
"subchar_line" identifies the row in the 8 x 8 block.
"subchar_pixel" identifies the column in the 8 x 8 block.
*/
 
// CREATE THE VERTICAL FRAME LINE COUNTER
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// on reset set line counter to 0
subchar_line <= 3'b000;
 
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY))
// reset line counter
subchar_line <= 3'b000;
 
else if (pixel_count == (`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)
// increment line counter
subchar_line <= line_count + 1;
end
 
// subchar_pixel defines the pixel within the character line
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
// reset to 5 so that the first character data can be latched
subchar_pixel <= 3'b101;
else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY))
// reset to 5 so that the first character data can be latched
subchar_pixel <= 3'b101;
else
subchar_pixel <= subchar_pixel + 1;
end
 
 
wire [9:0] char_column_count_iter = char_column_count + 1;
 
always @ (posedge pixel_clock or posedge reset) begin
if (reset) begin
char_column_count <= 10'd0;
char_column <= 7'd0;
end
else if (reset_char_column) begin
// reset the char column count during the HBI
char_column_count <= 10'd0;
char_column <= 7'd0;
end
else begin
char_column_count <= char_column_count_iter;
char_column <= char_column_count_iter[9:3];
end
end
 
wire [9:0] char_line_count_iter = char_line_count + 1;
 
always @ (posedge pixel_clock or posedge reset) begin
if (reset) begin
char_line_count <= 10'd0;
char_line <= 7'd0;
end
else if (reset_char_line) begin
// reset the char line count during the VBI
char_line_count <= 10'd0;
char_line <= 7'd0;
end
else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)) begin
// last pixel but not last line, so increment line counter
char_line_count <= char_line_count_iter;
char_line <= char_line_count_iter[9:3];
end
end
 
// CREATE THE CONTROL SIGNALS FOR THE CHARACTER ADDRESS COUNTERS
/*
The HOLD and RESET signals are advanced from the beginning and end
of HBI and VBI to compensate for the internal character generation
pipeline.
*/
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
reset_char_column <= 1'b0;
 
else if (pixel_count == ((`H_ACTIVE - 1) - `CHARACTER_DECODE_DELAY))
// start of HBI
reset_char_column <= 1'b1;
else if (pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY))
// end of HBI
reset_char_column <= 1'b0;
end
 
always @ (posedge pixel_clock or posedge reset) begin
if (reset)
reset_char_line <= 1'b0;
 
else if ((line_count == (`V_ACTIVE - 1)) &
(pixel_count == ((`H_ACTIVE - 1) - `CHARACTER_DECODE_DELAY)))
// start of VBI
reset_char_line <= 1'b1;
else if ((line_count == (`V_TOTAL - 1)) &
(pixel_count == ((`H_TOTAL - 1) - `CHARACTER_DECODE_DELAY)))
// end of VBI
reset_char_line <= 1'b0;
end
endmodule //SVGA_TIMING_GENERATION
 
//----------------------------------------------
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface_s3_vga_char_device.v
0,0 → 1,96
`include "vga_char_interface_defines.v"
 
 
module `VARIANT`S3_VGA_CHAR_DEVICE
(
input wire system_clock_buffered,
input wire pixel_clock,
input wire reset,
input wire [13:0] address,
input wire [11:0] character,
input wire loadit,
output VGA_HSYNCH, // horizontal sync for the VGA output connector
output VGA_VSYNCH, // vertical sync for the VGA output connector
output VGA_OUT_RED, // RED DAC data
output VGA_OUT_GREEN, // GREEN DAC data
output VGA_OUT_BLUE // BLUE DAC data
);
 
wire vga_red_data; // red video data
wire vga_green_data; // green video data
wire vga_blue_data; // blue video data
 
// internal video timing signals
wire h_synch; // horizontal synch for VGA connector
wire v_synch; // vertical synch for VGA connector
wire blank; // composite blanking
wire [10:0] pixel_count; // bit mapped pixel position within the line
wire [9:0] line_count; // bit mapped line number in a frame lines within the frame
wire [2:0] subchar_pixel; // pixel position within the character
wire [2:0] subchar_line; // identifies the line number within a character block
wire [6:0] char_column; // character number on the current line
wire [6:0] char_line; // line number on the screen
 
// instantiate the character generator
`VARIANT`CHAR_DISPLAY CHAR_DISPLAY
(
char_column,
char_line,
subchar_line,
subchar_pixel,
pixel_clock,
reset,
vga_red_data,
vga_green_data,
vga_blue_data,
address,
character,
loadit
);
 
 
// instantiate the video timing generator
`VARIANT`SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
(
pixel_clock,
reset,
h_synch,
v_synch,
blank,
pixel_count,
line_count,
subchar_pixel,
subchar_line,
char_column,
char_line
);
 
// instantiate the video output mux
`VARIANT`VIDEO_OUT VIDEO_OUT
(
pixel_clock,
reset,
vga_red_data,
vga_green_data,
vga_blue_data,
h_synch,
v_synch,
blank,
 
VGA_HSYNCH,
VGA_VSYNCH,
VGA_OUT_RED,
VGA_OUT_GREEN,
VGA_OUT_BLUE
);
 
endmodule // MAIN
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/rtl/xxx/vga_char_interface.v
0,0 → 1,189
`include "vga_char_interface_defines.v"
 
//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//----------------------------------------------------------------------------
// Filename: user_logic.v
// Version: 1.00.a
// Description: User logic module.
// Date: Wed Sep 12 16:22:49 2007 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
 
module `VARIANT
 
 
#(parameter C_DWIDTH = 32,
parameter C_NUM_CE = 2)
 
(
input fifty_clock_in,
input Bus2IP_Clk,
input Bus2IP_Reset,
input [0 : C_DWIDTH-1] Bus2IP_Data,
input [0 : C_DWIDTH/8-1] Bus2IP_BE,
input [0 : C_NUM_CE-1] Bus2IP_RdCE,
input [0 : C_NUM_CE-1] Bus2IP_WrCE,
 
 
 
output [0 : C_DWIDTH-1] IP2Bus_Data,
output IP2Bus_Ack,
output IP2Bus_Retry,
output IP2Bus_Error,
output IP2Bus_ToutSup,
output VGA_HSYNCH,
output VGA_VSYNCH,
output VGA_OUT_RED,
output VGA_OUT_GREEN,
output VGA_OUT_BLUE
 
);
 
 
 
// Nets for user logic slave model s/w accessible register example
reg [0 : C_DWIDTH-1] slv_reg0;
reg [0 : C_DWIDTH-1] slv_reg1;
wire [0 : 1] slv_reg_write_select;
wire [0 : 1] slv_reg_read_select;
reg [0 : C_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
 
// --USER logic implementation added here
 
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
// Note:
// The example code presented here is to show you one way of reading/writing
// software accessible registers implemented in the user logic slave model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
// to one software accessible register by the top level template. For example,
// if you have four 32 bit software accessible registers in the user logic, you
// are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE or Memory Mapped
// Bus2IP_RdCE Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_select = Bus2IP_WrCE[0:1],
slv_reg_read_select = Bus2IP_RdCE[0:1],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1];
 
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
 
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
end
else
case ( slv_reg_write_select )
2'b10 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
2'b01 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase
 
end // SLAVE_REG_WRITE_PROC
 
// implement slave model register read mux
always @( slv_reg_read_select or slv_reg0 or slv_reg1 )
begin: SLAVE_REG_READ_PROC
 
case ( slv_reg_read_select )
2'b10 : slv_ip2bus_data <= slv_reg0;
2'b01 : slv_ip2bus_data <= slv_reg1;
default : slv_ip2bus_data <= 0;
endcase
 
end // SLAVE_REG_READ_PROC
 
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
 
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_Ack = slv_write_ack || slv_read_ack;
assign IP2Bus_Error = 0;
assign IP2Bus_Retry = 0;
assign IP2Bus_ToutSup = 0;
`VARIANT`S3_VGA_CHAR_DEVICE
S3E_VGA_CHAR_DEVICE(
.SYSTEM_CLOCK(fifty_clock_in),
.VGA_HSYNCH(VGA_HSYNCH),
.VGA_VSYNCH(VGA_VSYNCH),
.VGA_OUT_RED(VGA_OUT_RED),
.VGA_OUT_GREEN(VGA_OUT_GREEN),
.VGA_OUT_BLUE(VGA_OUT_BLUE),
.address(slv_reg0[0:13]),
.character(slv_reg0[14:25]),
.loadit(1));
 
endmodule
 
//------------------------------------------------------------------------
 
 
 
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/doc/gpl.txt
0,0 → 1,674
GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
 
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
Preamble
 
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software and other kinds of works.
 
The licenses for most software and other practical works are designed
to take away your freedom to share and change the works. By contrast,
the GNU General Public License is intended to guarantee your freedom to
share and change all versions of a program--to make sure it remains free
software for all its users. We, the Free Software Foundation, use the
GNU General Public License for most of our software; it applies also to
any other work released this way by its authors. You can apply it to
your programs, too.
 
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
them if you wish), that you receive source code or can get it if you
want it, that you can change the software or use pieces of it in new
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To protect your rights, we need to prevent others from denying you
these rights or asking you to surrender the rights. Therefore, you have
certain responsibilities if you distribute copies of the software, or if
you modify it: responsibilities to respect the freedom of others.
 
For example, if you distribute copies of such a program, whether
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Developers that use the GNU GPL protect your rights with two steps:
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15. Disclaimer of Warranty.
 
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
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If the disclaimer of warranty and limitation of liability provided
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END OF TERMS AND CONDITIONS
 
How to Apply These Terms to Your New Programs
 
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
 
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
state the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
 
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) <year> <name of author>
 
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
 
Also add information on how to contact you by electronic and paper mail.
 
If the program does terminal interaction, make it output a short
notice like this when it starts in an interactive mode:
 
<program> Copyright (C) <year> <name of author>
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
 
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
 
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<http://www.gnu.org/licenses/>.
 
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
/trunk/projects/logic/ip/vga_char_ctrl/doc/Readme.txt
0,0 → 1,52
 
This component takes the opencores opb_vga_char_display_nodac project and makes it socgen compatible. The original project checked in by Timmothy Pearson in Oct 2007 consisted of a single module that added a asic vga interface to a microblaze system. It had no documentation or test suite and could only work in xilinx spartan parts.
 
I chose it because it was a useful module and had mostly clean coding. It requires only 5 pins and about 5% of a Nexys2 fpga.The following changes were made:
 
 
 
1) Stripped off the bus interface.
 
You never want to create a component and then hard wire it to any particular bus interface. Create the core engine with documentation and test suite.
Then you can create another component that instantiates the core along with the bus of the day interface. If the bus registers are created by a tool
it will be easy to retarget it to any bus the tool supports
 
 
2) Split out each module into a seperate file with replaceable module names and variants
 
There were two variations defined for this component. You can now have two instanciations and use both in a single design
 
3) Removed the spartan 3 clock gen and ported in pixel_clock and reset
 
By receiving the clock and reset from a port this code can now go into any fpga or asic design.
 
 
4) Replaced the char rom with a cde_sram and moved the font into a sw directory
 
The font is now compiled from an asm file and loaded with a readmemh command. This enables the support of a ascii only font that is 1/2 the size of the full one.
 
 
5) Replaced the char ram with a cde_ram.
 
You can now define a starup screen in a asm file
 
6) Connected all signals to instances by name rather than by position
 
7) cleaned up port width mismatch,latches and undefined memory accesses
 
8) converted from async to sync reset
 
9) Combined port i/o and wire/reg declarations
 
10) Changed configurations and magic numbers into parameters
 
11) Added a simplier color mode for more depth and less per character control
 
If you need all the bells and blinking characters you can add it on the outside.
 
12) Inverted h+v sync siganals. Not sure which way is rigth by my other one is active low and it works
 
13) added test suite with vga_model and micro bus host
 
14) Added docs for operating and config modes
/trunk/projects/logic/ip/vga_char_ctrl/doc/copyright.v
0,0 → 1,38
////////////////////////////////////////////////////////////////////
// -------------- //
// / SOC \ //
// / GEN \ //
// / COMPONENT \ //
// ==================== //
// |digital done right| //
// |__________________| //
// //
// //
// //
// Copyright (C) <2009> <Ouabache DesignWorks> //
// //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
////////////////////////////////////////////////////////////////////
 
 
/trunk/projects/logic/ip/vga_char_ctrl/bin/Makefile
0,0 → 1,2
include ../../../bin/Makefile.root
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/liblist
0,0 → 1,3
`include "../../lib/cde_sram/cde_sram.v"
 
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/TB.defs
0,0 → 1,5
`define PERIOD 41.16667
`define TIMEOUT 20000000
`define STARTUP "../../../../../sw/startup/startup.abs"
`define FONT "../../../../../sw/font/font.abs"
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/test_define
0,0 → 1,16
initial
begin
$display(" ");
$display(" ===================================================");
$display("%8d Test Start",$realtime/`PERIOD );
$display(" ===================================================");
$display(" ");
cg.next(12);
cg.reset_off;
cg.next(1300000);
cg.exit;
end
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/dmp_define
0,0 → 1,8
 
$dumpfile ("TestBench.vcd");
$dumpvars (0, TB);
 
 
 
 
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/filelist
0,0 → 1,2
`include "../../../rtl/gen/sim/vga_char_ctrl.v"
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/dut
0,0 → 1,46
wire h_sync;
wire v_sync;
 
wire red;
wire green;
wire blue;
 
 
 
 
wire [7:0] wdata;
wire [13:0] address;
 
wire [2:0] vga_red_pad_out;
wire [2:0] vga_green_pad_out;
wire [1:0] vga_blue_pad_out;
wire hsync_n_pad_out;
wire vsync_n_pad_out;
 
vga_char_ctrl
#(.STARTUP(`STARTUP),
.FONT(`FONT))
dut (
.clk ( clk ),
.reset ( reset ),
 
.ascii_load (1'b0),
.add_l_load (1'b0),
.add_h_load (1'b0),
 
.char_color (8'h92),
.back_color (8'h00),
.cursor_color (8'hff),
 
.wdata (8'h00),
.address ( address),
 
.vga_red_pad_out ( vga_red_pad_out ),
.vga_green_pad_out ( vga_green_pad_out ),
.vga_blue_pad_out ( vga_blue_pad_out ),
 
.hsync_n_pad_out ( hsync_n_pad_out ),
.vsync_n_pad_out ( vsync_n_pad_out )
);
/trunk/projects/logic/ip/vga_char_ctrl/sim/run/default/modellist
0,0 → 1,3
`include "../../bench/verilog/models/clock_gen.v"
 
 
/trunk/projects/logic/ip/vga_char_ctrl/sim/bin/Makefile
0,0 → 1,3
include ../../../../bin/Makefile.root
 
 
/trunk/projects/logic/sw/startup/startup.asm
0,0 → 1,69
 
cpu 6502
output HEX
* = $0000 ;
code
ASC "+------------------------------------------------------------------------------+";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| SOCGEN Project 1234567890 |";
ASC "| |";
ASC "| |";
ASC "| abcdefghijklmnopqrstuvwxyz |";
ASC "| |";
ASC "| ABCDEFGHIJKLMNOPQRSTUVWXYZ |";
ASC "| |";
ASC "| 1234567890 |";
ASC "| |";
ASC "| `~!@#$%^&*()-_=+[{]}|;:,<.>? |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "+------------------------------------------------------------------------------+";
 
code
/trunk/projects/logic/sw/startup/Makefile
0,0 → 1,5
include ../../bin/Makefile.root
code=startup
 
 
all: asm_6502
/trunk/projects/logic/sw/vga_font/vga_font.asm
0,0 → 1,313
 
cpu 6502
output HEX
* = $0000 ; assemble at $f000
code
;-------------------------------------------
; ;
;Code 00h defines a solid block ;
;Codes 01h-04h define block graphics ;
;Codes 05h-1Fh define line graphics ;
;Codes 20h-7Eh define the ASCII characters ;
;Code 7Fh defines a hash pattern ;
;Codes 80h-FFh user defined characters ;
;------------------------------------------- ;
;//// Solid Block ////
;// 00h: solid block address 000
db $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
;// Block graphics ////
; 01h: Left block up, right block down address 008
db $F0,$F0,$F0,$F0,$0F,$0F,$0F,$0F;
; 02h: Left block down, right block up address 010
db $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0;
; 03h: Both blocks down address 018
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 04h: Both blocks up address 020
db $FF,$FF,$FF,$FF,$00,$00,$00,$00;
;// Line Graphics ////
; 05h: corner upper left address 028
db $FF,$80,$80,$80,$80,$80,$80,$80;
; 06h: corner upper right address 030
db $FF,$01,$01,$01,$01,$01,$01,$01;
; 07h: corner lower left address 038
db $80,$80,$80,$80,$80,$80,$80,$FF;
; 08h: corner lower right address 040
db $01,$01,$01,$01,$01,$01,$01,$FF;
; 09h: cross junction address 048
db $10,$10,$10,$FF,$10,$10,$10,$10;
; 0Ah: "T" junction address 050
db $FF,$10,$10,$10,$10,$10,$10,$10;
; 0Bh: "T" juntion rotated 90 clockwise address 058
db $01,$01,$01,$FF,$01,$01,$01,$01;
; 0Ch: "T" juntion rotated 180 address 060
db $10,$10,$10,$10,$10,$10,$10,$FF;
; 0Dh: "T" junction rotated 270 clockwise address 068
db $80,$80,$80,$FF,$80,$80,$80,$80;
; 0Eh: arrow pointing right address 070
db $08,$04,$02,$FF,$02,$04,$08,$00;
; 0Fh: arrow pointing left address 078
db $10,$20,$40,$FF,$40,$20,$10,$00;
; 10h: first (top) horizontal line address 080
db $FF,$00,$00,$00,$00,$00,$00,$00;
; 11h: second horizontal line address 088
db $00,$FF,$00,$00,$00,$00,$00,$00;
; 12h: third horizontal line address 090
db $00,$00,$FF,$00,$00,$00,$00,$00;
; 13h: fourth horizontal line address 098
db $00,$00,$00,$FF,$00,$00,$00,$00;
; 14h: fifth horizontal line address 0A0
db $00,$00,$00,$00,$FF,$00,$00;
; 15h: sixth horizontal line address 0A7
db $00,$00,$00,$00,$00,$00,$FF,$00,$00;
; 16h: seventh horizontal line address 0B0
db $00,$00,$00,$00,$00,$00,$FF,$00;
; 17h: eighth (bottom) horizontal line address 0B8
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 18h: first (left) vertical line address 0C0
db $80,$80,$80,$80,$80,$80,$80,$80;
; 19h: second vertical line address 0C8
db $40,$40,$40,$40,$40,$40,$40,$40;
; 1Ah: third vertical line address 0D0
db $20,$20,$20,$20,$20,$20,$20,$20;
; 1Bh: fourth vertical line address 0D8
db $10,$10,$10,$10,$10,$10,$10,$10;
; 1Ch: fifth vertical line address 0E0
db $08,$08,$08,$08,$08,$08,$08,$08;
; 1Dh: sixth vertical line address 0E8
db $04,$04,$04,$04,$04,$04,$04,$04;
; 1Eh: seventh vertical line address 0F0
db $02,$02,$02,$02,$02,$02,$02,$02;
; 1Fh: eighth (right) vertical line address 0F8
db $01,$01,$01,$01,$01,$01,$01,$01;
;// ASCII Characters ////
; 20h: space address 100
db $00,$00,$00,$00,$00,$00,$00,$00;
; 21h: ! address 108
db $10,$10,$10,$10,$00,$00,$10,$00;
; 22h: " address 110
db $28,$28,$28,$00,$00,$00,$00,$00;
; 23h: # address 118
db $28,$28,$7C,$28,$7C,$28,$28,$00;
; 24h: $ address 120
db $10,$3C,$50,$38,$14,$78,$10,$00;
; 25h: % address 128
db $60,$64,$08,$10,$20,$46,$06,$00;
; 26h: & address 130
db $30,$48,$50,$20,$54,$48,$34,$00;
; 27h: ' address 138
db $30,$10,$20,$00,$00,$00,$00,$00;
; 28h: ( address 140
db $08,$10,$20,$20,$20,$10,$08,$00;
; 29h: ) address 148
db $20,$10,$08,$08,$08,$10,$20,$00;
; 2Ah: * address 150
db $00,$10,$54,$38,$54,$10,$00,$00;
; 2Bh: + address 158
db $00,$10,$10,$7C,$10,$10,$00,$00;
; 2Ch: , address 160
db $00,$00,$00,$00,$00,$30,$10,$20;
; 2Dh: - address 168
db $00,$00,$00,$7C,$00,$00,$00,$00;
; 2Eh: . address 170
db $00,$00,$00,$00,$00,$30,$30,$00;
; 2Fh: / address 178
db $00,$04,$08,$10,$20,$40,$00,$00;
; 30h: 0 address 180
db $38,$44,$4C,$54,$64,$44,$38,$00;
; 31h: 1 address 188
db $10,$30,$10,$10,$10,$10,$38,$00;
; 32h: 2 address 190
db $38,$44,$04,$08,$10,$20,$7C,$00;
; 33h: 3 address 198
db $7C,$08,$10,$08,$04,$44,$38,$00;
; 34h: 4 address 1A0
db $08,$18,$28,$48,$7C,$08,$08,$00;
; 35h: 5 address 1A8
db $7C,$40,$78,$04,$04,$44,$38,$00;
; 36h: 6 address 1B0
db $18,$20,$40,$78,$44,$44,$38,$00;
; 37h: 7 address 1B8
db $7C,$04,$08,$10,$20,$20,$20,$00;
; 38h: 8 address 1C0
db $38,$44,$44,$38,$44,$44,$38,$00;
; 39h: 9 address 1C8
db $38,$44,$44,$3C,$04,$08,$30,$00;
; 3Ah: : address 1D0
db $00,$30,$30,$00,$00,$30,$30,$00;
; 3Bh: ; address 1D8
db $00,$30,$30,$00,$00,$30,$10,$20;
; 3Ch: < address 1E0
db $08,$10,$20,$40,$20,$10,$08,$00;
; 3Dh: = address 1E8
db $00,$00,$7C,$00,$7C,$00,$00,$00;
; 3Eh: > address 1F0
db $20,$10,$08,$04,$08,$10,$20,$00;
; 3Fh: ? address 1F8
db $38,$44,$04,$08,$10,$00,$10,$00;
; 40h: @ address 200
db $38,$44,$04,$34,$54,$54,$38,$00;
; 41h: A address 208
db $38,$44,$44,$44,$7C,$44,$44,$00;
; 42h: B address 210
db $78,$44,$44,$78,$44,$44,$78,$00;
; 43h: C address 218
db $38,$44,$40,$40,$40,$44,$38,$00;
; 44h: D address 220
db $70,$48,$44,$44,$44,$48,$70,$00;
; 45h: E address 228
db $7C,$40,$40,$78,$40,$40,$7C,$00;
; 46h: F address 230
db $7C,$40,$40,$78,$40,$40,$40,$00;
; 47h: G address 238
db $38,$44,$40,$5C,$44,$44,$3C,$00;
; 48h: H address 240
db $44,$44,$44,$7C,$44,$44,$44,$00;
; 49h: I address 248
db $38,$10,$10,$10,$10,$10,$38,$00;
; 4Ah: J address 250
db $1C,$08,$08,$08,$08,$48,$30,$00;
; 4Bh: K address 258
db $44,$48,$50,$60,$50,$48,$44,$00;
; 4Ch: L address 260
db $40,$40,$40,$40,$40,$40,$7C,$00;
; 4Dh: M address 268
db $44,$6C,$54,$54,$44,$44,$44,$00;
; 4Eh: N address 270
db $44,$44,$64,$54,$4C,$44,$44,$00;
; 4Fh: O address 278
db $38,$44,$44,$44,$44,$44,$38,$00;
; 50h: P address 280
db $78,$44,$44,$78,$40,$40,$40,$00;
; 51h: Q address 288
db $38,$44,$44,$44,$54,$48,$34,$00;
; 52h: R address 290
db $78,$44,$44,$78,$50,$48,$44,$00;
; 53h: S address 298
db $3C,$40,$40,$38,$04,$04,$78,$00;
; 54h: T address 2A0
db $7C,$10,$10,$10,$10,$10,$10,$00;
; 55h: U address 2A8
db $44,$44,$44,$44,$44,$44,$38,$00;
; 56h: V address 2B0
db $44,$44,$44,$44,$44,$28,$10,$00;
; 57h: W address 2B8
db $44,$44,$44,$54,$54,$54,$28,$00;
; 58h: X address 2C0
db $44,$44,$28,$10,$28,$44,$44,$00;
; 59h: Y address 2C8
db $44,$44,$44,$28,$10,$10,$10,$00;
; 5Ah: Z address 2D0
db $7C,$04,$08,$10,$20,$40,$7C,$00;
; 5Bh: [ address 2D8
db $38,$20,$20,$20,$20,$20,$38,$00;
; 5Ch: \ address 2E0
db $00,$40,$20,$10,$08,$04,$00,$00;
; 5Dh: ] address 2E8
db $38,$08,$08,$08,$08,$08,$38,$00;
; 5Eh: ^ address 2F0
db $10,$28,$44,$00,$00,$00,$00,$00;
; 5Fh: _ address 2F8
db $00,$00,$00,$00,$00,$00,$7C,$00;
; 60h: ` address 300
db $20,$10,$08,$00,$00,$00,$00,$00;
; 61h: a address 308
db $00,$00,$38,$04,$3C,$44,$3C,$00;
; 62h: b address 310
db $40,$40,$58,$64,$44,$44,$78,$00;
; 63h: c address 318
db $00,$00,$38,$40,$40,$44,$38,$00;
; 64h: d address 320
db $04,$04,$34,$4C,$44,$44,$3C,$00;
; 65h: e address 328
db $00,$00,$38,$44,$7C,$40,$38,$00;
; 66h: f address 330
db $18,$24,$20,$70,$20,$20,$20,$00;
; 67h: g address 338
db $00,$00,$3C,$44,$44,$3C,$04,$38;
; 68h: h address 340
db $40,$40,$58,$64,$44,$44,$44,$00;
; 69h: i address 348
db $10,$10,$30,$10,$10,$10,$38,$00;
; 6Ah: j address 350
db $00,$08,$00,$18,$08,$08,$48,$30;
; 6Bh: k address 358
db $40,$40,$48,$50,$60,$50,$48,$00;
; 6Ch: l address 360
db $30,$10,$10,$10,$10,$10,$38,$00;
; 6Dh: m address 368
db $00,$00,$68,$54,$54,$44,$44,$00;
; 6Eh: n address 370
db $00,$00,$58,$64,$44,$44,$44,$00;
; 6Fh: o address 378
db $00,$00,$38,$44,$44,$44,$38,$00;
; 70h: p address 380
db $00,$00,$78,$44,$78,$40,$40,$40;
; 71h: q address 388
db $00,$00,$00,$34,$4C,$3C,$04,$04;
; 72h: r address 390
db $00,$00,$58,$64,$40,$40,$40,$00;
; 73h: s address 398
db $00,$00,$38,$40,$38,$04,$78,$00;
; 74h: t address 3A0
db $00,$20,$20,$70,$20,$20,$24,$18;
; 75h: u address 3A8
db $00,$00,$44,$44,$44,$4C,$34,$00;
; 76h: v address 3B0
db $00,$00,$44,$44,$44,$28,$10,$00;
; 77h: w address 3B8
db $00,$00,$44,$44,$54,$54,$28,$00;
; 78h: x address 3C0
db $00,$00,$44,$28,$10,$28,$44,$00;
; 79h: y address 3C8
db $00,$00,$00,$44,$44,$3C,$04,$38;
; 7Ah: z address 3D0
db $00,$00,$7C,$08,$10,$20,$7C,$00;
; 7Bh: { address 3D8
db $08,$10,$10,$20,$10,$10,$08,$00;
; 7Ch: | address 3E0
db $10,$10,$10,$10,$10,$10,$10,$00;
; 7Dh: } address 3E8
db $20,$10,$10,$08,$10,$10,$20,$00;
; 7Eh: ~ address 3F0
db $00,$00,$60,$92,$0C,$00,$00,$00;
;// Hash Pattern ////
; 7Fh: hash pattern address 3F8
db $55,$AA,$55,$AA,$55,$AA,$55,$AA;
;// User Defined Characters ////
; 80h: vertical to the left address 400
db $F0,$F0,$F0,$F0,$F0,$F0,$F0,$F0;
; 81h: vertical to the right address 408
db $0F,$0F,$0F,$0F,$0F,$0F,$0F,$0F;
; 82h: circle address 410
db $00,$18,$3C,$7E,$7E,$3C,$18,$00;
; 83h: Upper left block only address 418
db $F0,$F0,$F0,$F0,$00,$00,$00,$00;
; 84h: Upper right block only address 420
db $0F,$0F,$0F,$0F,$00,$00,$00,$00;
; 85h: Lower left block only address 428
db $00,$00,$00,$00,$F0,$F0,$F0,$F0;
; 86h: Lower right block only address 430
db $00,$00,$00,$00,$0F,$0F,$0F,$0F;
; 87h: One horizontal line address 438
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 88h: Two horizontal lines address 440
db $00,$00,$00,$00,$00,$00,$FF,$FF;
; 89h: Three horizontal lines address 448
db $00,$00,$00,$00,$00,$FF,$FF,$FF;
; 8Ah: Four horizontal lines address 450
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 8Bh: Five horizontal lines address 458
db $00,$00,$00,$FF,$FF,$FF,$FF,$FF;
; 8Ch: Six horizontal lines address 460
db $00,$00,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Dh: Seven horizontal lines address 468
db $00,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Eh: One vertical line address 470
db $80,$80,$80,$80,$80,$80,$80,$80;
; 8Fh: Two vertical lines address 478
db $c0,$c0,$c0,$c0,$c0,$c0,$c0,$c0;
 
 
code
/trunk/projects/logic/sw/vga_font/Makefile
0,0 → 1,4
include ../../bin/Makefile.root
code=vga_font
 
all: asm_6502
/trunk/projects/logic/sw/font/font.asm
0,0 → 1,313
 
cpu 6502
output HEX
* = $0000 ; assemble at $f000
code
;-------------------------------------------
; ;
;Code 00h defines a solid block ;
;Codes 01h-04h define block graphics ;
;Codes 05h-1Fh define line graphics ;
;Codes 20h-7Eh define the ASCII characters ;
;Code 7Fh defines a hash pattern ;
;Codes 80h-FFh user defined characters ;
;------------------------------------------- ;
;//// Solid Block ////
;// 00h: solid block address 000
db $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
;// Block graphics ////
; 01h: Left block up, right block down address 008
db $F0,$F0,$F0,$F0,$0F,$0F,$0F,$0F;
; 02h: Left block down, right block up address 010
db $0F,$0F,$0F,$0F,$F0,$F0,$F0,$F0;
; 03h: Both blocks down address 018
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 04h: Both blocks up address 020
db $FF,$FF,$FF,$FF,$00,$00,$00,$00;
;// Line Graphics ////
; 05h: corner upper left address 028
db $FF,$80,$80,$80,$80,$80,$80,$80;
; 06h: corner upper right address 030
db $FF,$01,$01,$01,$01,$01,$01,$01;
; 07h: corner lower left address 038
db $80,$80,$80,$80,$80,$80,$80,$FF;
; 08h: corner lower right address 040
db $01,$01,$01,$01,$01,$01,$01,$FF;
; 09h: cross junction address 048
db $10,$10,$10,$FF,$10,$10,$10,$10;
; 0Ah: "T" junction address 050
db $FF,$10,$10,$10,$10,$10,$10,$10;
; 0Bh: "T" juntion rotated 90 clockwise address 058
db $01,$01,$01,$FF,$01,$01,$01,$01;
; 0Ch: "T" juntion rotated 180 address 060
db $10,$10,$10,$10,$10,$10,$10,$FF;
; 0Dh: "T" junction rotated 270 clockwise address 068
db $80,$80,$80,$FF,$80,$80,$80,$80;
; 0Eh: arrow pointing right address 070
db $08,$04,$02,$FF,$02,$04,$08,$00;
; 0Fh: arrow pointing left address 078
db $10,$20,$40,$FF,$40,$20,$10,$00;
; 10h: first (top) horizontal line address 080
db $FF,$00,$00,$00,$00,$00,$00,$00;
; 11h: second horizontal line address 088
db $00,$FF,$00,$00,$00,$00,$00,$00;
; 12h: third horizontal line address 090
db $00,$00,$FF,$00,$00,$00,$00,$00;
; 13h: fourth horizontal line address 098
db $00,$00,$00,$FF,$00,$00,$00,$00;
; 14h: fifth horizontal line address 0A0
db $00,$00,$00,$00,$FF,$00,$00;
; 15h: sixth horizontal line address 0A7
db $00,$00,$00,$00,$00,$00,$FF,$00,$00;
; 16h: seventh horizontal line address 0B0
db $00,$00,$00,$00,$00,$00,$FF,$00;
; 17h: eighth (bottom) horizontal line address 0B8
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 18h: first (left) vertical line address 0C0
db $80,$80,$80,$80,$80,$80,$80,$80;
; 19h: second vertical line address 0C8
db $40,$40,$40,$40,$40,$40,$40,$40;
; 1Ah: third vertical line address 0D0
db $20,$20,$20,$20,$20,$20,$20,$20;
; 1Bh: fourth vertical line address 0D8
db $10,$10,$10,$10,$10,$10,$10,$10;
; 1Ch: fifth vertical line address 0E0
db $08,$08,$08,$08,$08,$08,$08,$08;
; 1Dh: sixth vertical line address 0E8
db $04,$04,$04,$04,$04,$04,$04,$04;
; 1Eh: seventh vertical line address 0F0
db $02,$02,$02,$02,$02,$02,$02,$02;
; 1Fh: eighth (right) vertical line address 0F8
db $01,$01,$01,$01,$01,$01,$01,$01;
;// ASCII Characters ////
; 20h: space address 100
db $00,$00,$00,$00,$00,$00,$00,$00;
; 21h: ! address 108
db $10,$10,$10,$10,$00,$00,$10,$00;
; 22h: " address 110
db $28,$28,$28,$00,$00,$00,$00,$00;
; 23h: # address 118
db $28,$28,$7C,$28,$7C,$28,$28,$00;
; 24h: $ address 120
db $10,$3C,$50,$38,$14,$78,$10,$00;
; 25h: % address 128
db $60,$64,$08,$10,$20,$46,$06,$00;
; 26h: & address 130
db $30,$48,$50,$20,$54,$48,$34,$00;
; 27h: ' address 138
db $30,$10,$20,$00,$00,$00,$00,$00;
; 28h: ( address 140
db $08,$10,$20,$20,$20,$10,$08,$00;
; 29h: ) address 148
db $20,$10,$08,$08,$08,$10,$20,$00;
; 2Ah: * address 150
db $00,$10,$54,$38,$54,$10,$00,$00;
; 2Bh: + address 158
db $00,$10,$10,$7C,$10,$10,$00,$00;
; 2Ch: , address 160
db $00,$00,$00,$00,$00,$30,$10,$20;
; 2Dh: - address 168
db $00,$00,$00,$7C,$00,$00,$00,$00;
; 2Eh: . address 170
db $00,$00,$00,$00,$00,$30,$30,$00;
; 2Fh: / address 178
db $00,$04,$08,$10,$20,$40,$00,$00;
; 30h: 0 address 180
db $38,$44,$4C,$54,$64,$44,$38,$00;
; 31h: 1 address 188
db $10,$30,$10,$10,$10,$10,$38,$00;
; 32h: 2 address 190
db $38,$44,$04,$08,$10,$20,$7C,$00;
; 33h: 3 address 198
db $7C,$08,$10,$08,$04,$44,$38,$00;
; 34h: 4 address 1A0
db $08,$18,$28,$48,$7C,$08,$08,$00;
; 35h: 5 address 1A8
db $7C,$40,$78,$04,$04,$44,$38,$00;
; 36h: 6 address 1B0
db $18,$20,$40,$78,$44,$44,$38,$00;
; 37h: 7 address 1B8
db $7C,$04,$08,$10,$20,$20,$20,$00;
; 38h: 8 address 1C0
db $38,$44,$44,$38,$44,$44,$38,$00;
; 39h: 9 address 1C8
db $38,$44,$44,$3C,$04,$08,$30,$00;
; 3Ah: : address 1D0
db $00,$30,$30,$00,$00,$30,$30,$00;
; 3Bh: ; address 1D8
db $00,$30,$30,$00,$00,$30,$10,$20;
; 3Ch: < address 1E0
db $08,$10,$20,$40,$20,$10,$08,$00;
; 3Dh: = address 1E8
db $00,$00,$7C,$00,$7C,$00,$00,$00;
; 3Eh: > address 1F0
db $20,$10,$08,$04,$08,$10,$20,$00;
; 3Fh: ? address 1F8
db $38,$44,$04,$08,$10,$00,$10,$00;
; 40h: @ address 200
db $38,$44,$04,$34,$54,$54,$38,$00;
; 41h: A address 208
db $38,$44,$44,$44,$7C,$44,$44,$00;
; 42h: B address 210
db $78,$44,$44,$78,$44,$44,$78,$00;
; 43h: C address 218
db $38,$44,$40,$40,$40,$44,$38,$00;
; 44h: D address 220
db $70,$48,$44,$44,$44,$48,$70,$00;
; 45h: E address 228
db $7C,$40,$40,$78,$40,$40,$7C,$00;
; 46h: F address 230
db $7C,$40,$40,$78,$40,$40,$40,$00;
; 47h: G address 238
db $38,$44,$40,$5C,$44,$44,$3C,$00;
; 48h: H address 240
db $44,$44,$44,$7C,$44,$44,$44,$00;
; 49h: I address 248
db $38,$10,$10,$10,$10,$10,$38,$00;
; 4Ah: J address 250
db $1C,$08,$08,$08,$08,$48,$30,$00;
; 4Bh: K address 258
db $44,$48,$50,$60,$50,$48,$44,$00;
; 4Ch: L address 260
db $40,$40,$40,$40,$40,$40,$7C,$00;
; 4Dh: M address 268
db $44,$6C,$54,$54,$44,$44,$44,$00;
; 4Eh: N address 270
db $44,$44,$64,$54,$4C,$44,$44,$00;
; 4Fh: O address 278
db $38,$44,$44,$44,$44,$44,$38,$00;
; 50h: P address 280
db $78,$44,$44,$78,$40,$40,$40,$00;
; 51h: Q address 288
db $38,$44,$44,$44,$54,$48,$34,$00;
; 52h: R address 290
db $78,$44,$44,$78,$50,$48,$44,$00;
; 53h: S address 298
db $3C,$40,$40,$38,$04,$04,$78,$00;
; 54h: T address 2A0
db $7C,$10,$10,$10,$10,$10,$10,$00;
; 55h: U address 2A8
db $44,$44,$44,$44,$44,$44,$38,$00;
; 56h: V address 2B0
db $44,$44,$44,$44,$44,$28,$10,$00;
; 57h: W address 2B8
db $44,$44,$44,$54,$54,$54,$28,$00;
; 58h: X address 2C0
db $44,$44,$28,$10,$28,$44,$44,$00;
; 59h: Y address 2C8
db $44,$44,$44,$28,$10,$10,$10,$00;
; 5Ah: Z address 2D0
db $7C,$04,$08,$10,$20,$40,$7C,$00;
; 5Bh: [ address 2D8
db $38,$20,$20,$20,$20,$20,$38,$00;
; 5Ch: \ address 2E0
db $00,$40,$20,$10,$08,$04,$00,$00;
; 5Dh: ] address 2E8
db $38,$08,$08,$08,$08,$08,$38,$00;
; 5Eh: ^ address 2F0
db $10,$28,$44,$00,$00,$00,$00,$00;
; 5Fh: _ address 2F8
db $00,$00,$00,$00,$00,$00,$7C,$00;
; 60h: ` address 300
db $20,$10,$08,$00,$00,$00,$00,$00;
; 61h: a address 308
db $00,$00,$38,$04,$3C,$44,$3C,$00;
; 62h: b address 310
db $40,$40,$58,$64,$44,$44,$78,$00;
; 63h: c address 318
db $00,$00,$38,$40,$40,$44,$38,$00;
; 64h: d address 320
db $04,$04,$34,$4C,$44,$44,$3C,$00;
; 65h: e address 328
db $00,$00,$38,$44,$7C,$40,$38,$00;
; 66h: f address 330
db $18,$24,$20,$70,$20,$20,$20,$00;
; 67h: g address 338
db $00,$00,$3C,$44,$44,$3C,$04,$38;
; 68h: h address 340
db $40,$40,$58,$64,$44,$44,$44,$00;
; 69h: i address 348
db $10,$10,$30,$10,$10,$10,$38,$00;
; 6Ah: j address 350
db $00,$08,$00,$18,$08,$08,$48,$30;
; 6Bh: k address 358
db $40,$40,$48,$50,$60,$50,$48,$00;
; 6Ch: l address 360
db $30,$10,$10,$10,$10,$10,$38,$00;
; 6Dh: m address 368
db $00,$00,$68,$54,$54,$44,$44,$00;
; 6Eh: n address 370
db $00,$00,$58,$64,$44,$44,$44,$00;
; 6Fh: o address 378
db $00,$00,$38,$44,$44,$44,$38,$00;
; 70h: p address 380
db $00,$00,$78,$44,$78,$40,$40,$40;
; 71h: q address 388
db $00,$00,$00,$34,$4C,$3C,$04,$04;
; 72h: r address 390
db $00,$00,$58,$64,$40,$40,$40,$00;
; 73h: s address 398
db $00,$00,$38,$40,$38,$04,$78,$00;
; 74h: t address 3A0
db $00,$20,$20,$70,$20,$20,$24,$18;
; 75h: u address 3A8
db $00,$00,$44,$44,$44,$4C,$34,$00;
; 76h: v address 3B0
db $00,$00,$44,$44,$44,$28,$10,$00;
; 77h: w address 3B8
db $00,$00,$44,$44,$54,$54,$28,$00;
; 78h: x address 3C0
db $00,$00,$44,$28,$10,$28,$44,$00;
; 79h: y address 3C8
db $00,$00,$00,$44,$44,$3C,$04,$38;
; 7Ah: z address 3D0
db $00,$00,$7C,$08,$10,$20,$7C,$00;
; 7Bh: { address 3D8
db $08,$10,$10,$20,$10,$10,$08,$00;
; 7Ch: | address 3E0
db $10,$10,$10,$10,$10,$10,$10,$00;
; 7Dh: } address 3E8
db $20,$10,$10,$08,$10,$10,$20,$00;
; 7Eh: ~ address 3F0
db $00,$00,$60,$92,$0C,$00,$00,$00;
;// Hash Pattern ////
; 7Fh: hash pattern address 3F8
db $55,$AA,$55,$AA,$55,$AA,$55,$AA;
;// User Defined Characters ////
; 80h: vertical to the left address 400
db $F0,$F0,$F0,$F0,$F0,$F0,$F0,$F0;
; 81h: vertical to the right address 408
db $0F,$0F,$0F,$0F,$0F,$0F,$0F,$0F;
; 82h: circle address 410
db $00,$18,$3C,$7E,$7E,$3C,$18,$00;
; 83h: Upper left block only address 418
db $F0,$F0,$F0,$F0,$00,$00,$00,$00;
; 84h: Upper right block only address 420
db $0F,$0F,$0F,$0F,$00,$00,$00,$00;
; 85h: Lower left block only address 428
db $00,$00,$00,$00,$F0,$F0,$F0,$F0;
; 86h: Lower right block only address 430
db $00,$00,$00,$00,$0F,$0F,$0F,$0F;
; 87h: One horizontal line address 438
db $00,$00,$00,$00,$00,$00,$00,$FF;
; 88h: Two horizontal lines address 440
db $00,$00,$00,$00,$00,$00,$FF,$FF;
; 89h: Three horizontal lines address 448
db $00,$00,$00,$00,$00,$FF,$FF,$FF;
; 8Ah: Four horizontal lines address 450
db $00,$00,$00,$00,$FF,$FF,$FF,$FF;
; 8Bh: Five horizontal lines address 458
db $00,$00,$00,$FF,$FF,$FF,$FF,$FF;
; 8Ch: Six horizontal lines address 460
db $00,$00,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Dh: Seven horizontal lines address 468
db $00,$FF,$FF,$FF,$FF,$FF,$FF,$FF;
; 8Eh: One vertical line address 470
db $80,$80,$80,$80,$80,$80,$80,$80;
; 8Fh: Two vertical lines address 478
db $c0,$c0,$c0,$c0,$c0,$c0,$c0,$c0;
 
 
code
/trunk/projects/logic/sw/font/Makefile
0,0 → 1,5
include ../../bin/Makefile.root
code=font
 
 
all: asm_6502
/trunk/projects/logic/sw/vga_startup_screen/vga_startup_screen.asm
0,0 → 1,69
 
cpu 6502
output HEX
* = $0000 ;
code
ASC "+------------------------------------------------------------------------------+";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| SOCGEN Project 1234567890 |";
ASC "| |";
ASC "| |";
ASC "| abcdefghijklmnopqrstuvwxyz |";
ASC "| |";
ASC "| ABCDEFGHIJKLMNOPQRSTUVWXYZ |";
ASC "| |";
ASC "| 1234567890 |";
ASC "| |";
ASC "| `~!@#$%^&*()-_=+[{]}|;:,<.>? |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "| |";
ASC "+------------------------------------------------------------------------------+";
 
code
/trunk/projects/logic/sw/vga_startup_screen/Makefile
0,0 → 1,4
include ../../bin/Makefile.root
code=vga_startup_screen
 
all: asm_6502
/trunk/targets/Nexys2/Pad_Ring.v
197,15 → 197,30
wire jc_9_pad_out;
wire jc_10_pad_out;
 
wire rts_pad_out;
wire cts_pad_in;
wire rxd_pad_in;
wire txd_pad_out;
 
wire ramclk_out;
wire ramcre_out;
wire memoe_n_out;
wire ramcs_n_out;
wire ramlb_n_out;
wire flashcs_n_out;
wire flashrp_n_out;
wire flashststs_in;
wire [23:1] memadr_out;
wire [15:0] memdb_out;
wire [15:0] memdb_in;
wire memdb_oe;
wire ramub_n_out;
wire memwr_n_out;
 
wire rts_pad_out;
wire cts_pad_in;
wire rxd_pad_in;
wire txd_pad_out;
wire ramwait_in;
wire ramadv_out_n;
// Pad Ring
cde_pad_se_dig a_clk_pad(
221,14 → 236,7
.pad_out (1'b0),
.pad_oe (1'b0)
);
 
 
 
 
 
 
cde_pad_se_dig seg_0_pad(
.PAD (SEG[0]),
.pad_in (),
236,7 → 244,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig seg_1_pad(
.PAD (SEG[1]),
.pad_in (),
244,7 → 251,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig seg_2_pad(
.PAD (SEG[2]),
.pad_in (),
252,7 → 258,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig seg_3_pad(
.PAD (SEG[3]),
.pad_in (),
260,7 → 265,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig seg_4_pad(
.PAD (SEG[4]),
.pad_in (),
268,7 → 272,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig seg_5_pad(
.PAD (SEG[5]),
.pad_in (),
283,8 → 286,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig dp_pad(
.PAD (DP),
.pad_in (),
292,10 → 293,6
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig an_0_pad(
.PAD (AN[0]),
.pad_in (),
303,7 → 300,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig an_1_pad(
.PAD (AN[1]),
.pad_in (),
311,7 → 307,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig an_2_pad(
.PAD (AN[2]),
.pad_in (),
319,7 → 314,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig an_3_pad(
.PAD (AN[3]),
.pad_in (),
326,8 → 320,6
.pad_out (an_pad_out[3]),
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig sw_0_pad(
.PAD (SW[0]),
343,7 → 335,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_2_pad(
.PAD (SW[2]),
.pad_in (sw_pad_in[2]),
351,7 → 342,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_3_pad(
.PAD (SW[3]),
.pad_in (sw_pad_in[3]),
359,7 → 349,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_4_pad(
.PAD (SW[4]),
.pad_in (sw_pad_in[4]),
367,7 → 356,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_5_pad(
.PAD (SW[5]),
.pad_in (sw_pad_in[5]),
375,7 → 363,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_6_pad(
.PAD (SW[6]),
.pad_in (sw_pad_in[6]),
383,7 → 370,6
.pad_oe (1'b0)
);
 
 
cde_pad_se_dig sw_7_pad(
.PAD (SW[7]),
.pad_in (sw_pad_in[7]),
390,13 → 376,7
.pad_out (1'b0),
.pad_oe (1'b0)
);
 
 
 
 
 
cde_pad_se_dig btn_0_pad(
.PAD (BTN[0]),
.pad_in (btn_pad_in[0]),
425,8 → 405,6
.pad_oe (1'b0)
);
 
cde_pad_se_dig led_0_pad(
.PAD (LED[0]),
.pad_in (),
483,8 → 461,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig ps2_data_pad(
.PAD (PS2D),
.pad_in (ps2_data_pad_in),
499,8 → 475,6
.pad_oe (ps2_clk_pad_oe)
);
 
 
 
cde_pad_se_dig rs_rx_pad(
.PAD (RS_RX),
.pad_in (rs_rx_pad_in),
572,9 → 546,6
.pad_oe (1'b1)
);
 
 
 
 
cde_pad_se_dig jb_1_pad(
.PAD (JB_1),
.pad_in (),
631,8 → 602,6
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig jc_1_pad(
.PAD (JC_1),
.pad_in (),
689,8 → 658,6
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig rts_pad(
.PAD (RTS),
.pad_in (),
719,10 → 686,6
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig vgared_0_pad(
.PAD (VGARED[0]),
.pad_in (),
744,7 → 707,6
.pad_oe (1'b1)
);
 
cde_pad_se_dig vgagreen_0_pad(
.PAD (VGAGREEN[0]),
.pad_in (),
766,9 → 728,6
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig vgablue_0_pad(
.PAD (VGABLUE[0]),
.pad_in (),
783,8 → 742,6
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig hsync_pad(
.PAD (HSYNC),
.pad_in (),
806,12 → 763,11
 
 
 
 
cde_pad_se_dig ramadv_pad(
.PAD (RAMADV),
.pad_in (),
.pad_out (1'b0),
.pad_out (ramadv_out_n),
.pad_oe (1'b1)
);
 
819,11 → 775,10
 
 
 
 
cde_pad_se_dig ramclk_pad(
.PAD (RAMCLK),
.pad_in (),
.pad_out (1'b0),
.pad_out (ramclk_out),
.pad_oe (1'b1)
);
 
831,54 → 786,57
 
 
 
 
cde_pad_se_dig ramcre_pad(
.PAD (RAMCRE),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (ramcre_out),
.pad_oe (1'b1)
);
 
 
 
 
 
cde_pad_se_dig memoe_pad(
.PAD (MEMOE),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
);
.pad_out (memoe_n_out),
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig ramcs_pad(
.PAD (RAMCS),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (ramcs_n_out),
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig ramlb_pad(
.PAD (RAMLB),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (ramlb_n_out),
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig ramub_pad(
.PAD (RAMUB),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (ramub_n_out),
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig memwr_pad(
.PAD (MEMWR),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memwr_n_out),
.pad_oe (1'b1)
);
 
 
888,26 → 846,26
cde_pad_se_dig flashcs_pad(
.PAD (FLASHCS),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (flashcs_n_out),
.pad_oe (1'b1)
);
 
 
 
cde_pad_se_dig flashrp_pad(
.PAD (FLASHRP),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (flashrp_n_out),
.pad_oe (1'b1)
);
 
 
cde_pad_se_dig flashststs_pad(
.PAD (FLASHSTSTS),
.pad_in (),
.pad_in (flashststs_in),
.pad_out (1'b0),
.pad_oe (1'b0)
);
 
 
 
914,18 → 872,18
 
cde_pad_se_dig ramwait_pad(
.PAD (RAMWAIT),
.pad_in (),
.pad_in (ramwait_in),
.pad_out (1'b0),
.pad_oe (1'b0)
);
 
 
 
cde_pad_se_dig memadr_1_pad(
.PAD (MEMADR[1]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[1]),
.pad_oe (1'b1)
);
 
 
932,8 → 890,8
cde_pad_se_dig memadr_2_pad(
.PAD (MEMADR[2]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[2]),
.pad_oe (1'b1)
);
 
 
940,8 → 898,8
cde_pad_se_dig memadr_3_pad(
.PAD (MEMADR[3]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[3]),
.pad_oe (1'b1)
);
 
 
948,50 → 906,50
cde_pad_se_dig memadr_4_pad(
.PAD (MEMADR[4]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[4]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_5_pad(
.PAD (MEMADR[5]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[5]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_6_pad(
.PAD (MEMADR[6]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[6]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_7_pad(
.PAD (MEMADR[7]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[7]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_8_pad(
.PAD (MEMADR[8]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[8]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_9_pad(
.PAD (MEMADR[9]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[9]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_10_pad(
.PAD (MEMADR[10]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[10]),
.pad_oe (1'b1)
);
 
 
998,8 → 956,8
cde_pad_se_dig memadr_11_pad(
.PAD (MEMADR[11]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[11]),
.pad_oe (1'b1)
);
 
 
1006,8 → 964,8
cde_pad_se_dig memadr_12_pad(
.PAD (MEMADR[12]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[12]),
.pad_oe (1'b1)
);
 
 
1014,8 → 972,8
cde_pad_se_dig memadr_13_pad(
.PAD (MEMADR[13]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[13]),
.pad_oe (1'b1)
);
 
 
1022,43 → 980,43
cde_pad_se_dig memadr_14_pad(
.PAD (MEMADR[14]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[14]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_15_pad(
.PAD (MEMADR[15]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[15]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_16_pad(
.PAD (MEMADR[16]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[16]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_17_pad(
.PAD (MEMADR[17]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[17]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_18_pad(
.PAD (MEMADR[18]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[18]),
.pad_oe (1'b1)
);
 
cde_pad_se_dig memadr_19_pad(
.PAD (MEMADR[19]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[19]),
.pad_oe (1'b1)
);
 
 
1066,8 → 1024,8
cde_pad_se_dig memadr_20_pad(
.PAD (MEMADR[20]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[20]),
.pad_oe (1'b1)
);
 
 
1074,8 → 1032,8
cde_pad_se_dig memadr_21_pad(
.PAD (MEMADR[21]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[21]),
.pad_oe (1'b1)
);
 
 
1082,8 → 1040,8
cde_pad_se_dig memadr_22_pad(
.PAD (MEMADR[22]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[22]),
.pad_oe (1'b1)
);
 
 
1091,8 → 1049,8
cde_pad_se_dig memadr_23_pad(
.PAD (MEMADR[23]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_out (memadr_out[23]),
.pad_oe (1'b1)
);
 
 
1099,123 → 1057,119
 
cde_pad_se_dig memdb_00_pad(
.PAD (MEMDB[0]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[0]),
.pad_out (memdb_out[0]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_01_pad(
.PAD (MEMDB[1]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[1]),
.pad_out (memdb_out[1]),
.pad_oe (memdb_oe)
);
 
 
 
cde_pad_se_dig memdb_02_pad(
.PAD (MEMDB[2]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[2]),
.pad_out (memdb_out[2]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_03_pad(
.PAD (MEMDB[3]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[3]),
.pad_out (memdb_out[3]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_04_pad(
.PAD (MEMDB[4]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[4]),
.pad_out (memdb_out[4]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_05_pad(
.PAD (MEMDB[5]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[5]),
.pad_out (memdb_out[5]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_06_pad(
.PAD (MEMDB[6]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[6]),
.pad_out (memdb_out[6]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_07_pad(
.PAD (MEMDB[7]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[7]),
.pad_out (memdb_out[7]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_08_pad(
.PAD (MEMDB[8]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[8]),
.pad_out (memdb_out[8]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_09_pad(
.PAD (MEMDB[9]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[9]),
.pad_out (memdb_out[9]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_10_pad(
.PAD (MEMDB[10]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[10]),
.pad_out (memdb_out[10]),
.pad_oe (memdb_oe)
);
 
 
 
cde_pad_se_dig memdb_11_pad(
.PAD (MEMDB[11]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[11]),
.pad_out (memdb_out[11]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_12_pad(
.PAD (MEMDB[12]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[12]),
.pad_out (memdb_out[12]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_13_pad(
.PAD (MEMDB[13]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[13]),
.pad_out (memdb_out[13]),
.pad_oe (memdb_oe)
);
 
cde_pad_se_dig memdb_14_pad(
.PAD (MEMDB[14]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[14]),
.pad_out (memdb_out[14]),
.pad_oe (memdb_oe)
);
 
 
cde_pad_se_dig memdb_15_pad(
.PAD (MEMDB[15]),
.pad_in (),
.pad_out (1'b0),
.pad_oe (1'b0)
.pad_in (memdb_in[15]),
.pad_out (memdb_out[15]),
.pad_oe (memdb_oe)
);
 
 
1807,11 → 1761,24
);
 
 
//wire ramwait_in;
//wire ramadv_out_n;
assign memoe_n_out = 1'b1;
assign ramcs_n_out = 1'b1;
assign ramlb_n_out = 1'b1;
assign flashcs_n_out = 1'b1;
assign ramadv_out_n = 1'b1;
assign ramclk_out = 1'b0;
assign ramcre_out = 1'b0;
assign flashrp_n_out = 1'b1;
assign memadr_out = 23'b00000000000000000000000;
assign memdb_oe = 1'b0;
assign memdb_out = 16'h0000;
assign memwr_n_out = 1'b1;
assign ramub_n_out = 1'b1;
 
 
 
 
 
 
`include "../core.v"
/trunk/Makefile
74,13 → 74,13
echo " number of errors";\
find . | grep _sim.log | xargs grep ERROR $1 |grep pic_micro | wc -l ;\
echo " number of M6502 sims run";\
find . | grep dut| grep -v children| grep M6502 | wc -l ;\
find . | grep dut| grep -v children| grep Mos6502 | wc -l ;\
echo " number of sims that finished";\
find . | grep _sim.log | xargs grep PASSED $1 | grep M6502| wc -l ;\
find . | grep _sim.log | xargs grep PASSED $1 | grep Mos6502| wc -l ;\
echo " number of warnings";\
find . | grep _sim.log | xargs grep WARNING $1 |grep M6502 | wc -l ;\
find . | grep _sim.log | xargs grep WARNING $1 |grep Mos6502 | wc -l ;\
echo " number of errors";\
find . | grep _sim.log | xargs grep ERROR $1 |grep M6502 | wc -l ;\
find . | grep _sim.log | xargs grep ERROR $1 |grep Mos6502 | wc -l ;\
echo " number of open sims run";\
find . | grep dut| grep -v children| grep open | wc -l ;\
echo " number of sims that finished";\

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