URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
Compare Revisions
- This comparison shows the changes necessary to convert path
/socgen
- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/trunk/bin/Makefile.root
0,0 → 1,249
SHELL=/bin/sh |
MAKE=make |
|
VPP_NAME=vppreproc |
|
|
CUR_DIR=$(shell pwd) |
VAR_DIR=$(CUR_DIR)/varients |
SRC_DIR=$(CUR_DIR)/verilog |
GEN_DIR=$(CUR_DIR)/gen |
|
|
|
|
|
|
################################################################################ |
# Build rtl code |
################################################################################ |
|
prepare_dirs: |
@if [ ! -d $(GEN_DIR) ]; then mkdir -p $(GEN_DIR);mkdir $(GEN_DIR)/syn;mkdir $(GEN_DIR)/sim; fi |
|
|
build_fsm: prepare_dirs |
@for COMP in `ls $(CUR_DIR)/fzm`; do \ |
echo "################################################"; \ |
echo; \ |
echo "FSM : $$COMP ####"; echo; \ |
perl ~/bin/fizzim.pl -encoding onehot -terse < ./fzm/$$COMP > $(SRC_DIR)/$$COMP.v;\ |
done; \ |
|
|
|
|
|
|
|
build_hw: build_fsm |
@echo |
@for VARIENT in `ls $(VAR_DIR)`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Building: $$VARIENT ####"; echo; \ |
cp $(VAR_DIR)/$$VARIENT/$(DEF_FILE) $(DEF_FILE); \ |
cp ../doc/copyright.v $(GEN_DIR)/sim/$$VARIENT.v ; \ |
$(VPP_NAME) --simple $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/sim/$$VARIENT.v ; \ |
cp ../doc/copyright.v $(GEN_DIR)/syn/$$VARIENT.v ; \ |
$(VPP_NAME) --simple -DSYNTHESIS $(DEF_FILE) $(SRC_DIR)/*.v >> $(GEN_DIR)/syn/$$VARIENT.v ; \ |
rm $(DEF_FILE); \ |
done; \ |
|
|
################################################################################ |
# Build software |
################################################################################ |
|
.PHONY asm_6502: |
asm_6502: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
crasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs16 $(code); \ |
hex2abs $(code); \ |
hex2abs_split $(code); \ |
) |
|
|
.PHONY asm_pic: |
asm_pic: |
(\ |
echo "#################################################################"; \ |
echo; \ |
echo "assembling: $(code) ####"; echo; \ |
gpasm $(code).asm -o $(code).hex > $(code).lst; \ |
hex2abs12 $(code); \ |
) |
|
|
################################################################################ |
# run simulation suite |
################################################################################ |
|
|
.PHONY run_sims: |
run_sims: |
@for VARIENT_PROG in `ls $(CUR_DIR)/../run`; do \ |
echo "################################################################################"; \ |
echo; \ |
echo "Simulating: $$VARIENT_PROG ####"; echo; \ |
cd $(CUR_DIR)/../run/$$VARIENT_PROG/;\ |
echo "include ../../../../../bin/Makefile.root" > Makefile;\ |
echo -n "test=" >> Makefile;\ |
echo $$VARIENT_PROG >> Makefile;\ |
make sim;\ |
done; \ |
|
|
|
sim: |
(\ |
iverilog -D VCD ../../bench/verilog/TestBench;\ |
./a.out | tee ./${test}_sim.log ;\ |
mv *.log ../../log;\ |
mv TestBench.vcd ../../out/${test}.vcd ;\ |
rm a.out;\ |
) |
|
|
|
|
.PHONY group_build_fpgas: |
group_build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make build_fpgas;\ |
done; \ |
|
|
|
|
|
|
|
|
.PHONY build_fpgas: |
build_fpgas: |
@for COMP in `ls $(CUR_DIR)/../syn`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Synthesising: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../syn/$$COMP/;\ |
make fpga;\ |
done; \ |
|
|
|
|
|
|
PHONY: fpga |
fpga: |
(\ |
rm -r xilinx;\ |
mkdir xilinx;\ |
cd xilinx;\ |
echo "run -ifn ../filelist -ifmt mixed -top " $(board)_$(Design) " -ofn " $(board)_$(Design)".ngc -ofmt NGC -p " $(Part) "-opt_mode Speed -opt_level 1" > Xst;\ |
xst -ifn ./Xst -ofn $(board)_$(Design).log;\ |
ngdbuild -uc ../targets/$(board)/$(board).ucf $(board)_$(Design);\ |
map -p $(Part) -cm area -pr b -k 4 -c 100 -o $(board)_$(Design)_map.ncd $(board)_$(Design).ngd $(board)_$(Design).pcf;\ |
par -w -ol std -t 1 $(board)_$(Design)_map.ncd $(board)_$(Design).ncd $(board)_$(Design).pcf ;\ |
trce -e 3 -s 5 -xml $(board)_$(Design) $(board)_$(Design).ncd -o $(board)_$(Design).twr $(board)_$(Design).pcf -ucf ../targets/$(board)/$(board).ucf ;\ |
bitgen -f ../targets/$(board)/jtag.ut $(board)_$(Design).ncd;\ |
mv $(board)_$(Design).bit $(board)_$(Design)_jtag.bit ;\ |
bit_2_svf $(board)_$(Design)_jtag.bit ;\ |
cp $(board)_$(Design)_jtag.svf ../debug/bitstream.svf ;\ |
) |
|
|
|
|
|
|
|
|
.PHONY group_composite: |
group_composite: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/bin;\ |
make comp_lnk;\ |
done; \ |
|
|
|
|
|
.PHONY group_build_hw: |
group_build_hw: group_start_hw |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/rtl;\ |
echo "include ../../../bin/Makefile.root" > Makefile;\ |
echo -n "DEF_FILE=" >> Makefile;\ |
echo -n $$COMP >> Makefile;\ |
echo "_defines.v" >> Makefile;\ |
make build_hw;\ |
done; \ |
|
|
|
.PHONY group_start_hw: |
group_start_hw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_hw;\ |
done; \ |
|
|
|
|
.PHONY group_build_sw: |
group_build_sw: group_start_sw |
@for COMP in `ls $(CUR_DIR)/../sw`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../sw/$$COMP;\ |
make all;\ |
done; \ |
|
|
.PHONY group_start_sw: |
group_start_sw: |
@for CHILD in `ls $(CUR_DIR)/../children`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$CHILD ####"; echo; \ |
cd $(CUR_DIR)/../children/$$CHILD/bin;\ |
${MAKE} group_build_sw;\ |
done; \ |
|
|
|
.PHONY group_run_sims: |
group_run_sims: |
@for COMP in `ls $(CUR_DIR)/../ip`; do \ |
echo "################################################"; \ |
echo; \ |
echo "Linking: $$COMP ####"; echo; \ |
cd $(CUR_DIR)/../ip/$$COMP/sim/bin;\ |
make run_sims;\ |
done; \ |
|
|
|
|
trunk/bin/Makefile.root
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/bin/Makefile
===================================================================
--- trunk/bin/Makefile (nonexistent)
+++ trunk/bin/Makefile (revision 6)
@@ -0,0 +1,2 @@
+include ./Makefile.root
+
trunk/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/bin/build_cmp
===================================================================
--- trunk/bin/build_cmp (nonexistent)
+++ trunk/bin/build_cmp (revision 6)
@@ -0,0 +1,264 @@
+eval 'exec `which perl` -S $0 ${1+"$@"}'
+ if 0;
+
+#/**********************************************************************/
+#/* */
+#/* ------- */
+#/* / SOC \ */
+#/* / GEN \ */
+#/* / TOOL \ */
+#/* ============== */
+#/* | | */
+#/* |____________| */
+#/* */
+#/* makes a directory in a composite */
+#/* */
+#/* */
+#/* Author(s): */
+#/* - John Eaton, jt_eaton@opencores.org */
+#/* */
+#/**********************************************************************/
+#/* */
+#/* Copyright (C) <2010> */
+#/* */
+#/* This source file may be used and distributed without */
+#/* restriction provided that this copyright statement is not */
+#/* removed from the file and that any derivative work contains */
+#/* the original copyright notice and the associated disclaimer. */
+#/* */
+#/* This source file is free software; you can redistribute it */
+#/* and/or modify it under the terms of the GNU Lesser General */
+#/* Public License as published by the Free Software Foundation; */
+#/* either version 2.1 of the License, or (at your option) any */
+#/* later version. */
+#/* */
+#/* This source is distributed in the hope that it will be */
+#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+#/* PURPOSE. See the GNU Lesser General Public License for more */
+#/* details. */
+#/* */
+#/* You should have received a copy of the GNU Lesser General */
+#/* Public License along with this source; if not, download it */
+#/* from http://www.opencores.org/lgpl.shtml */
+#/* */
+#/**********************************************************************/
+
+# ToDO: add handling unaligned words
+
+
+############################################################################
+# General PERL config
+############################################################################
+use Getopt::Long;
+use English;
+use File::Basename;
+
+$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
+
+
+############################################################################
+### Process the options
+############################################################################
+
+Getopt::Long::config("require_order", "prefix=-");
+GetOptions("h"
+) || die "(use '$program_name -h' for help)";
+
+
+##############################################################################
+## Help option
+##############################################################################
+if ( ($opt_h eq "1") )
+ { print "\n type> build_cmp directory_name";
+ print "\n";
+ exit 1;
+ }
+
+
+
+#############################################################################
+##
+##
+##
+#############################################################################
+
+my $design = $ARGV[0];
+
+ $_ = qx(pwd);
+ chomp;
+my $home = $_;
+
+
+my $cmd = "ls $design > /dev/null ";
+
+
+
+ if (system ($cmd) ) {
+ die "Failed to find $design ";
+ }
+
+ print " making $home/${design}_cmp\n";
+
+
+ $cmd = "mkdir $home/${design}_cmp > /dev/null " ;
+ if (system($cmd)) {die "Failed $status ";}
+
+ $cmd = "ln -s $home/${design}/Makefile $home/${design}_cmp > /dev/null " ;
+ if (system($cmd)) {die "Failed $status ";}
+
+
+ $cmd = "mkdir $home/${design}_cmp/projects > /dev/null ";
+ if (system($cmd)) {die "Failed $status ";}
+
+
+ my @projects = qx(ls $home/${design}/projects );
+
+ foreach my $project (@projects)
+ {
+ chomp($project);
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project} > /dev/null " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ $cmd = "lndir -silent ${home}/${design}/projects/${project} ${home}/${design}_cmp/projects/${project} " ;
+
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ $cmd = "ln -s ${home}/${design}/bin/Makefile.root ${home}/${design}_cmp/projects/${project}"."/bin " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+
+ my @components = qx(ls ${home}/${design}/projects/${project}/ip );
+ foreach my $component (@components)
+ {
+ chomp($component);
+
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/bench " ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/lib " ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+ $cmd =
+ "lndir -silent ${home}/${design}/bench ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/bench " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ $cmd =
+ "lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/sim/lib " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+
+
+
+
+
+
+
+
+
+
+ my @syns = qx(ls ${home}/${design}/projects/${project}/ip/${component}/syn );
+ foreach my $syn (@syns)
+ {
+ chomp($syn);
+ print ("SYN $syn \n");
+
+
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets " ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+ $cmd =
+ "lndir -silent ${home}/${design}/targets ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets " ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+ $cmd =
+ "lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets/Basys/lib/syn" ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+ $cmd =
+ "lndir -silent ${home}/${design}/lib ${home}/${design}_cmp/projects/${project}/ip/${component}/syn/${syn}/targets/Nexys/lib/syn" ;
+ if (system($cmd)) { }
+ print ("$cmd \n");
+
+
+ }
+
+
+
+
+
+
+
+
+
+
+
+
+
+ }
+
+
+
+
+
+ my @children = qx(ls ${home}/${design}/projects/${project}/children );
+ foreach my $child (@children)
+ {
+ chomp($child);
+
+ print ("CHILD $home/${design}/projects/${project}/children/${child}\n" );
+
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ $cmd = "ln -s ${home}/${design}/bin/Makefile.root ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
+ if (system($cmd)) {die "Failed ";}
+ $cmd = "ln -s ${home}/${design}/bin/Makefile ${home}/${design}_cmp/projects/${project}/children/${child}/bin " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+
+ $cmd = "mkdir ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ $cmd = "lndir -silent ${home}/${design}/projects/${child}/sw ${home}/${design}_cmp/projects/${project}/children/${child}/sw " ;
+ if (system($cmd)) {}
+ print ("$cmd \n");
+
+
+
+
+
+
+
+
+ my @grand_children = qx(ls ${home}/${design}/projects/${project}/children/${child}/ip );
+ foreach my $grand_child (@grand_children)
+ {
+ chomp($grand_child);
+ $cmd =
+ "lndir -silent ${home}/${design}/projects/${child}/ip/${grand_child} ${home}/${design}_cmp/projects/${project}/children/${child}/ip/${grand_child} " ;
+ if (system($cmd)) {die "Failed ";}
+ print ("$cmd \n");
+ }
+
+
+
+
+
+
+
+ }
+
+ }
+
+
+
+
+
+
+
+
+
+1
+
+
trunk/bin/build_cmp
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/bin/Makefile
===================================================================
--- trunk/projects/pic_micro/bin/Makefile (nonexistent)
+++ trunk/projects/pic_micro/bin/Makefile (revision 6)
@@ -0,0 +1,2 @@
+include ./Makefile.root
+
trunk/projects/pic_micro/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc.v (revision 6)
@@ -0,0 +1,836 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// Mini-Risc Core ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+`include "mrisc_defines.v"
+
+
+
+module
+`VARIENT
+(
+ clk,
+ rst_in,
+
+ inst_addr,
+ inst_data,
+
+ portain,
+ portbin,
+ portcin,
+
+ portaout,
+ portbout,
+ portcout,
+
+ trisa,
+ trisb,
+ trisc,
+
+ tcki,
+ wdt_en );
+
+// Basic Core I/O.
+input clk;
+input rst_in;
+
+// Program memory interface
+output [10:0] inst_addr;
+input [11:0] inst_data;
+
+// Basic I/O Ports
+input [7:0] portain;
+input [7:0] portbin;
+input [7:0] portcin;
+
+output [7:0] portaout;
+output [7:0] portbout;
+output [7:0] portcout;
+
+output [7:0] trisa;
+output [7:0] trisb;
+output [7:0] trisc;
+
+input tcki;
+input wdt_en;
+
+// This should be set to the ROM location where our restart vector is.
+// As set here, we have 512 words of program space.
+parameter PC_RST_VECTOR = 11'h000, // Should be: 11'h7FF,
+ STAT_RST_VALUE = 8'h18,
+ OPT_RST_VALUE = 8'h3f,
+ FSR_RST_VALUE = 7'h0,
+ TRIS_RST_VALUE = 8'hff;
+
+parameter ALU_ADD = 4'h0,
+ ALU_SUB = 4'h1,
+ ALU_INC = 4'h2,
+ ALU_DEC = 4'h3,
+
+ ALU_AND = 4'h4,
+ ALU_CLR = 4'h5,
+ ALU_NOT = 4'h6,
+ ALU_IOR = 4'h7,
+ ALU_MOV = 4'h8,
+ ALU_MOVW = 4'h9,
+ ALU_RLF = 4'ha,
+ ALU_RRF = 4'hb,
+ ALU_SWP = 4'hc,
+ ALU_XOR = 4'hd,
+ ALU_BCF = 4'he,
+ ALU_BSF = 4'hf;
+
+parameter // Byte Oriented RF Operations
+ I_ADDWF = 12'b0001_11??_????,
+ I_ANDWF = 12'b0001_01??_????,
+ I_CLRF = 12'b0000_011?_????,
+ I_CLRW = 12'b0000_0100_0000,
+ I_COMF = 12'b0010_01??_????,
+ I_DEC = 12'b0000_11??_????,
+ I_DECFSZ = 12'b0010_11??_????,
+ I_INCF = 12'b0010_10??_????,
+ I_INCFSZ = 12'b0011_11??_????,
+ I_IORWF = 12'b0001_00??_????,
+ I_MOV = 12'b0010_00??_????,
+ I_MOVWF = 12'b0000_001?_????,
+ I_NOP = 12'b0000_0000_0000,
+ I_RLF = 12'b0011_01??_????,
+ I_RRF = 12'b0011_00??_????,
+ I_SUBWF = 12'b0000_10??_????,
+ I_SWAPF = 12'b0011_10??_????,
+ I_XORWF = 12'b0001_10??_????,
+
+ // Bit Oriented RF Operations
+ I_BCF = 12'b0100_????_????,
+ I_BSF = 12'b0101_????_????,
+ I_BTFSC = 12'b0110_????_????,
+ I_BTFSS = 12'b0111_????_????,
+
+ // Literal & Controll Operations
+ I_ANDLW = 12'b1110_????_????,
+ I_CALL = 12'b1001_????_????,
+ I_CLRWDT = 12'b0000_0000_0100,
+ I_GOTO = 12'b101?_????_????,
+ I_IORLW = 12'b1101_????_????,
+ I_MOVLW = 12'b1100_????_????,
+ I_OPTION = 12'b0000_0000_0010,
+ I_RETLW = 12'b1000_????_????,
+ I_SLEEP = 12'b0000_0000_0011,
+ I_TRIS = 12'b0000_0000_0???,
+ I_XORLW = 12'b1111_????_????;
+
+parameter // sfr register address encodings
+ INDF_ADDR = 3'h0,
+ TMR0_ADDR = 3'h1,
+ PCL_ADDR = 3'h2,
+ STAT_ADDR = 3'h3,
+ FSR_ADDR = 3'h4,
+ PORTA_ADDR = 3'h5,
+ PORTB_ADDR = 3'h6,
+ PORTC_ADDR = 3'h7;
+
+parameter // Source 1 Select
+ K_SEL = 2'b10,
+ SFR_SEL = 2'b00,
+ RF_SEL = 2'b01;
+
+parameter // STATUS Register status bits we
+ STAT_WR_C = 3'b001,
+ STAT_WR_DC = 3'b010,
+ STAT_WR_Z = 3'b100;
+
+
+// Instruction Register
+reg rst;
+reg [11:0] instr_0, instr_1;
+reg rst_r1, rst_r2;
+wire valid;
+reg valid_1;
+
+reg [7:0] mask;
+reg [7:0] sfr_rd_data;
+reg [3:0] alu_op;
+reg src1_sel;
+reg [1:0] src1_sel_;
+
+wire [7:0] dout; // ALU output
+wire [7:0] src1; // ALU Source 1
+
+reg [2:0] stat_bwe; // status bits we
+wire c_out, dc_out, z_out;
+
+reg pc_skz, pc_skz_;
+reg pc_bset, pc_bset_;
+reg pc_bclr, pc_bclr_;
+reg pc_call, pc_call_;
+reg pc_goto, pc_goto_;
+reg pc_retlw, pc_retlw_;
+
+wire invalidate_1;
+wire invalidate_0_;
+reg invalidate_0;
+
+// stage 1 dst decode
+reg w_we_;
+reg rf_we_;
+reg sfr_we_;
+reg tris_we_;
+
+// stage 2 dst decode
+reg w_we;
+wire rf_we;
+reg rf_we1, rf_we2, rf_we3;
+
+reg opt_we;
+reg trisa_we;
+reg trisb_we;
+reg trisc_we;
+
+wire indf_we_;
+reg tmr0_we;
+wire pc_we_;
+reg pc_we;
+reg stat_we;
+reg fsr_we;
+reg porta_we;
+reg portb_we;
+reg portc_we;
+
+wire bit_sel;
+wire [7:0] tmr0_next, tmr0_next1, tmr0_plus_1;
+wire tmr0_cnt_en;
+reg wdt_clr;
+wire wdt_to;
+wire wdt_en;
+wire tcki;
+
+wire [7:0] sfr_rd_data_tmp1, sfr_rd_data_tmp2, sfr_rd_data_tmp3;
+
+// Register File Connections
+wire [1:0] rf_rd_bnk, rf_wr_bnk;
+wire [4:0] rf_rd_addr, rf_wr_addr;
+wire [7:0] rf_rd_data, rf_wr_data;
+
+// Program Counter
+reg [10:0] inst_addr;
+reg [10:0] pc;
+reg [10:0] pc_next;
+wire [10:0] pc_plus_1;
+wire [10:0] stack_out;
+reg [10:0] pc_r, pc_r2;
+wire [10:0] pc_next1, pc_next2, pc_next3;
+
+// W Register
+reg [7:0] w; // Working Register
+reg [7:0] status; // Status Register
+reg [7:0] status_next;
+reg [6:0] fsr; // fsr register ( for indirect addressing)
+wire [6:0] fsr_next;
+reg [7:0] tmr0; // Timer 0
+reg [5:0] option; // Option Register
+
+// Tristate Control registers.
+reg [7:0] trisa;
+reg [7:0] trisb;
+reg [7:0] trisc;
+
+// I/O Port registers
+reg [7:0] porta_r; // PORTA input register
+reg [7:0] portb_r; // PORTB input register
+reg [7:0] portc_r; // PORTC input register
+reg [7:0] portaout; // PORTA output register
+reg [7:0] portbout; // PORTB output register
+reg [7:0] portcout; // PORTC output register
+
+////////////////////////////////////////////////////////////////////////
+// External Reset is Synchrounous to clock
+always @(posedge clk)
+ rst <= #1 rst_in;
+
+////////////////////////////////////////////////////////////////////////
+// Synchrounous Register File
+`VARIENT`REGISTER_FILE reg_file ( .clk( clk ),
+ .rst( rst ),
+ .rf_rd_bnk( rf_rd_bnk ),
+ .rf_rd_addr( rf_rd_addr ),
+ .rf_rd_data( rf_rd_data ),
+ .rf_we( rf_we ),
+ .rf_wr_bnk( rf_wr_bnk ),
+ .rf_wr_addr( rf_wr_addr ),
+ .rf_wr_data( rf_wr_data )
+ );
+
+////////////////////////////////////////////////////////////////////////
+// Always Fetch Next Instruction
+always @(posedge clk)
+ instr_0 <= #1 inst_data;
+
+////////////////////////////////////////////////////////////////////////
+// Instr Decode & Read Logic
+
+always @(posedge clk)
+ begin
+ rst_r1 <= #1 rst | wdt_to;
+ rst_r2 <= #1 rst | rst_r1 | wdt_to;
+ end
+
+assign valid = ~rst_r2 & ~invalidate_1;
+always @(posedge clk)
+ valid_1 <= #1 valid;
+
+always @(posedge clk)
+ instr_1 <= #1 instr_0;
+
+always @(posedge clk) // Basic Decode extracted directly from the instruction
+ begin
+ // Mask for bit modification instructions
+ case(instr_0[7:5]) // synopsys full_case parallel_case
+ 0: mask <= #1 8'h01;
+ 1: mask <= #1 8'h02;
+ 2: mask <= #1 8'h04;
+ 3: mask <= #1 8'h08;
+ 4: mask <= #1 8'h10;
+ 5: mask <= #1 8'h20;
+ 6: mask <= #1 8'h40;
+ 7: mask <= #1 8'h80;
+ endcase
+ end
+
+always @(posedge clk)
+ pc_r <= #1 pc; // Previous version of PC to accomodate for pipeline
+
+always @(posedge clk) // SFR Read Operands
+ if(src1_sel_[1]) sfr_rd_data <= #1 instr_0[7:0];
+ else
+ case(instr_0[2:0]) // synopsys full_case parallel_case
+ 1: sfr_rd_data <= #1 tmr0_next;
+ 2: sfr_rd_data <= #1 pc_r[7:0];
+ 3: sfr_rd_data <= #1 status_next;
+ 4: sfr_rd_data <= #1 {1'b1, fsr_next};
+ 5: sfr_rd_data <= #1 porta_r;
+ 6: sfr_rd_data <= #1 portb_r;
+ 7: sfr_rd_data <= #1 portc_r;
+ endcase
+
+
+
+
+reg instd_zero;
+
+always @(posedge clk)
+ instd_zero <= #1 !(|inst_data[4:0]);
+
+// Register File Read Port
+assign rf_rd_bnk = fsr_next[6:5];
+assign rf_rd_addr = instd_zero ? fsr_next[4:0] : instr_0[4:0];
+
+// ALU OP
+always @(posedge clk)
+ casex(instr_0) // synopsys full_case parallel_case
+ // Byte Oriented RF Operations
+ I_ADDWF: alu_op <= #1 ALU_ADD; // ADDWF
+ I_ANDWF: alu_op <= #1 ALU_AND; // ANDWF
+ I_CLRF: alu_op <= #1 ALU_CLR; // CLRF
+ I_CLRW: alu_op <= #1 ALU_CLR; // CLRW
+ I_COMF: alu_op <= #1 ALU_NOT; // COMF
+ I_DEC: alu_op <= #1 ALU_DEC; // DEC
+ I_DECFSZ: alu_op <= #1 ALU_DEC; // DECFSZ
+ I_INCF: alu_op <= #1 ALU_INC; // INCF
+ I_INCFSZ: alu_op <= #1 ALU_INC; // INCFSZ
+ I_IORWF: alu_op <= #1 ALU_IOR; // IORWF
+ I_MOV: alu_op <= #1 ALU_MOV; // MOV
+ I_MOVWF: alu_op <= #1 ALU_MOVW; // MOVWF
+ I_RLF: alu_op <= #1 ALU_RLF; // RLF
+ I_RRF: alu_op <= #1 ALU_RRF; // RRF
+ I_SUBWF: alu_op <= #1 ALU_SUB; // SUBWF
+ I_SWAPF: alu_op <= #1 ALU_SWP; // SWAPF
+ I_XORWF: alu_op <= #1 ALU_XOR; // XORWF
+ // Bit Oriented RF Operations
+ I_BCF: alu_op <= #1 ALU_BCF; // BCF
+ I_BSF: alu_op <= #1 ALU_BSF; // BSF
+ // Literal & Controll Operations
+ I_ANDLW: alu_op <= #1 ALU_AND; // ANDLW
+ I_IORLW: alu_op <= #1 ALU_IOR; // IORLW
+ I_MOVLW: alu_op <= #1 ALU_MOV; // MOWLW
+ I_RETLW: alu_op <= #1 ALU_MOV; // RETLW
+ I_XORLW: alu_op <= #1 ALU_XOR; // XORLW
+ endcase
+
+
+// Source Select
+// This CPU source 1 can be one of: rf (or sfr) or k,
+// second source (if any) is always w
+always @(instr_0)
+ casex(instr_0) // synopsys full_case parallel_case
+ I_ANDLW: src1_sel_ = K_SEL;
+ I_CALL: src1_sel_ = K_SEL;
+ I_GOTO: src1_sel_ = K_SEL;
+ I_IORLW: src1_sel_ = K_SEL;
+ I_MOVLW: src1_sel_ = K_SEL;
+ I_RETLW: src1_sel_ = K_SEL;
+ I_XORLW: src1_sel_ = K_SEL;
+ default: src1_sel_ = ( (instr_0[4:3]==2'h0) & (instr_0[2:0] != 3'h0 )) ? SFR_SEL : RF_SEL;
+ endcase
+
+always @(posedge clk)
+ src1_sel <= #1 src1_sel_[0];
+
+// Destination Select
+// Destination can be one of: rf, w, option, tris OR one of sfr registers:
+// indf, tmr0, pc, status, fsr, porta, portb, portc, option, trisa, trisb, trisc
+// Stage 1
+// select w, pc, rf or sfr
+reg w_we1, w_we1_;
+
+always @(instr_0)
+ begin
+ casex(instr_0) // synopsys full_case parallel_case
+ I_ADDWF, I_ANDWF, I_COMF, I_DEC,
+ I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF,
+ I_MOV, I_RLF, I_RRF, I_SUBWF,
+ I_SWAPF, I_XORWF: // w or f
+ w_we1_ = 1;
+ default: w_we1_ = 0;
+ endcase
+ end
+
+always @(instr_0)
+ begin
+ w_we_ = 0;
+ rf_we_ = 0;
+ sfr_we_ = 0;
+ tris_we_= 0;
+ casex(instr_0) // synopsys full_case parallel_case
+
+ I_ADDWF, I_ANDWF, I_COMF, I_DEC,
+ I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF,
+ I_MOV, I_RLF, I_RRF, I_SUBWF,
+ I_SWAPF, I_XORWF: // w or f
+ begin
+ rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]);
+ sfr_we_ = instr_0[5] & ~instr_0[4] & ~instr_0[3];
+ end
+
+ I_MOVWF, I_CLRF, I_BCF, I_BSF: // only f
+ begin
+ rf_we_ = instr_0[4] | instr_0[3];
+ sfr_we_ = ~instr_0[4] & ~instr_0[3];
+ end
+
+ I_CLRW, I_IORLW, I_MOVLW,
+ I_ANDLW, I_RETLW, I_XORLW: w_we_ = 1; // only w
+ I_TRIS: tris_we_ = 1; // trisa or trisb or trisc
+
+ endcase
+ end
+
+assign indf_we_ = sfr_we_ & (instr_0[2:0] == INDF_ADDR);
+assign pc_we_ = sfr_we_ & (instr_0[2:0] == PCL_ADDR);
+
+// Stage 2 destination encoder
+// write enable outputs are registered now
+always @(posedge clk) w_we <= #1 w_we_; // working register write 0 enable
+
+always @(posedge clk) w_we1 <= #1 w_we1_; // working register write 1 enable
+
+
+// Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f);
+// 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing
+// The logic has been partitioned and balanced between the decode and execute stage ...
+assign rf_we = rf_we1 | (rf_we2 & rf_we3); // register file write enable Composite
+
+always @(posedge clk)
+ rf_we1 <= #1 valid & rf_we_; // register file write enable 1
+
+always @(posedge clk)
+ rf_we2 <= #1 valid & (fsr_next[4] | fsr_next[3]);// register file write enable 2
+
+always @(posedge clk)
+ rf_we3 <= #1 indf_we_; // register file write enable 3
+
+always @(posedge clk)
+ wdt_clr <= #1 instr_0[11:0] == I_CLRWDT;
+
+
+always @(posedge clk)
+ opt_we <= #1 instr_0[11:0] == I_OPTION;
+
+
+always @(posedge clk)
+ trisa_we <= #1 tris_we_ & (instr_0[2:0] == PORTA_ADDR);
+
+always @(posedge clk)
+ trisb_we <= #1 tris_we_ & (instr_0[2:0] == PORTB_ADDR);
+
+always @(posedge clk)
+ trisc_we <= #1 tris_we_ & (instr_0[2:0] == PORTC_ADDR);
+
+always @(posedge clk)
+ begin
+ // SFR registers
+ tmr0_we <= #1 sfr_we_ & (instr_0[2:0] == TMR0_ADDR);
+ pc_we <= #1 valid & pc_we_;
+ stat_we <= #1 valid & sfr_we_ & (instr_0[2:0] == STAT_ADDR);
+ fsr_we <= #1 valid & sfr_we_ & (instr_0[2:0] == FSR_ADDR);
+ porta_we <= #1 sfr_we_ & (instr_0[2:0] == PORTA_ADDR);
+ portb_we <= #1 sfr_we_ & (instr_0[2:0] == PORTB_ADDR);
+ portc_we <= #1 sfr_we_ & (instr_0[2:0] == PORTC_ADDR);
+ end
+
+
+// Instructions that directly modify PC
+always @(instr_0)
+ begin
+ pc_skz_ = 0;
+ pc_bset_ = 0;
+ pc_bclr_ = 0;
+ pc_call_ = 0;
+ pc_goto_ = 0;
+ pc_retlw_ = 0;
+ casex(instr_0) // synopsys full_case parallel_case
+ // Byte Oriented RF Operations
+ I_DECFSZ,
+ I_INCFSZ: pc_skz_ = 1;
+ // Bit Oriented RF Operations
+ I_BTFSS: pc_bset_ = 1;
+ I_BTFSC: pc_bclr_ = 1;
+ // Literal & Controll Operations
+ I_CALL: pc_call_ = 1;
+ I_GOTO: pc_goto_ = 1;
+ I_RETLW: pc_retlw_ = 1;
+ endcase
+ end
+
+always @(posedge clk)
+ begin
+ pc_skz <= #1 valid & pc_skz_;
+ pc_bset <= #1 valid & pc_bset_;
+ pc_bclr <= #1 valid & pc_bclr_;
+ pc_call <= #1 valid & pc_call_;
+ pc_goto <= #1 valid & pc_goto_;
+ pc_retlw <= #1 valid & pc_retlw_;
+ end
+
+assign invalidate_0_ = (pc_call_ | pc_goto_ | pc_retlw_ | pc_we_);
+
+always @(posedge clk)
+ invalidate_0 <= #1 invalidate_0_;
+
+// Status bits WE
+always @(posedge clk)
+ begin
+ stat_bwe <= #1 0;
+ if(valid)
+ casex(instr_0) // synopsys full_case parallel_case
+ // Byte Oriented RF Operations
+ I_ADDWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z;
+ I_ANDWF: stat_bwe <= #1 STAT_WR_Z;
+ I_CLRF: stat_bwe <= #1 STAT_WR_Z;
+ I_CLRW: stat_bwe <= #1 STAT_WR_Z;
+ I_COMF: stat_bwe <= #1 STAT_WR_Z;
+ I_DEC: stat_bwe <= #1 STAT_WR_Z;
+ I_INCF: stat_bwe <= #1 STAT_WR_Z;
+ I_IORWF: stat_bwe <= #1 STAT_WR_Z;
+ I_MOV: stat_bwe <= #1 STAT_WR_Z;
+ I_RLF: stat_bwe <= #1 STAT_WR_C;
+ I_RRF: stat_bwe <= #1 STAT_WR_C;
+ I_SUBWF: stat_bwe <= #1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z;
+ I_XORWF: stat_bwe <= #1 STAT_WR_Z;
+ // Literal & Control Operations
+ I_ANDLW: stat_bwe <= #1 STAT_WR_Z;
+ //I_CLRWDT: // Modifies TO & PD *** FIX ME ***
+ I_IORLW: stat_bwe <= #1 STAT_WR_Z;
+ //I_SLEEP: // Modifies TO & PD *** FIX ME ***
+ I_XORLW: stat_bwe <= #1 STAT_WR_Z;
+ endcase
+ end
+
+////////////////////////////////////////////////////////////////////////
+// Wr & Execute Logic (including PC)
+// Second Pipeline Stage
+////////////////////////////////////////////////////////////////////////
+
+// Source OP Sel
+assign src1 = src1_sel ? rf_rd_data : sfr_rd_data;
+
+
+`VARIENT`ALU
+alu(
+ .s1 ( src1 ),
+ .s2 ( w ),
+ .mask ( mask ),
+ .out ( dout ),
+ .op ( alu_op ),
+ .c_in ( status[0] ),
+ .c ( c_out ),
+ .dc ( dc_out ),
+ .z ( z_out ));
+
+// Register file connections
+assign rf_wr_bnk = fsr[6:5];
+assign rf_wr_addr = (instr_1[4:0]==0) ? fsr[4:0] : instr_1[4:0];
+assign rf_wr_data = dout;
+
+wire [7:0] status_next2;
+
+// Deal with all special registers (SFR) writes
+
+always @(rst or status or stat_we or stat_bwe or dout or c_out or dc_out or z_out)
+ if(rst) status_next = STAT_RST_VALUE;
+ else
+ begin
+ status_next = status; // Default Keep Value
+ if(stat_we) status_next = dout | 8'h18;
+ else
+ begin
+ if(stat_bwe[0]) status_next[0] = c_out;
+ if(stat_bwe[1]) status_next[1] = dc_out;
+ if(stat_bwe[2]) status_next[2] = z_out;
+ end
+ end
+
+
+
+
+
+
+always @(posedge clk)
+ if(rst) status <= #1 STAT_RST_VALUE;
+ else status <= #1 status_next;
+
+assign fsr_next = fsr_we ? dout[6:0] : fsr;
+
+
+always @(posedge clk)
+ if(rst) fsr <= #1 FSR_RST_VALUE;
+ else fsr <= #1 fsr_next;
+
+always @(posedge clk)
+ if(valid_1 & (w_we | (w_we1 & ~instr_1[5])) ) w <= #1 dout;
+
+always @(posedge clk)
+ if(rst) trisa <= #1 TRIS_RST_VALUE;
+ else
+ if(trisa_we & valid_1) trisa <= #1 w;
+
+always @(posedge clk)
+ if(rst) trisb <= #1 TRIS_RST_VALUE;
+ else
+ if(trisb_we & valid_1) trisb <= #1 w;
+
+always @(posedge clk)
+ if(rst) trisc <= #1 TRIS_RST_VALUE;
+ else
+ if(trisc_we & valid_1) trisc <= #1 w;
+
+always @(posedge clk)
+ if(rst) option <= #1 OPT_RST_VALUE;
+ else
+ if(opt_we & valid_1) option <= #1 w[5:0];
+
+always @(posedge clk)
+ if(porta_we & valid_1) portaout <= #1 dout;
+
+always @(posedge clk)
+ if(portb_we & valid_1) portbout <= #1 dout;
+
+always @(posedge clk)
+ if(portc_we & valid_1) portcout <= #1 dout;
+
+always @(posedge clk)
+ begin
+ porta_r <= #1 portain;
+ portb_r <= #1 portbin;
+ portc_r <= #1 portcin;
+ end
+
+///////////////////////////////////////////////////////////////////////
+// Timer Logic
+
+assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? tmr0_plus_1 : tmr0;
+assign tmr0_plus_1 = tmr0 + 8'h1;
+
+
+always @(posedge clk)
+ tmr0 <= #1 tmr0_next;
+
+`VARIENT`PRESCLR_WDT
+presclr_wdt(
+ .clk ( clk ),
+ .rst ( rst ),
+ .tcki ( tcki ),
+ .option ( option[5:0] ),
+ .tmr0_we ( tmr0_we & valid_1 ),
+ .tmr0_cnt_en( tmr0_cnt_en ),
+ .wdt_en ( wdt_en ),
+ .wdt_clr ( wdt_clr & valid_1 ),
+ .wdt_to ( wdt_to )
+ );
+
+
+////////////////////////////////////////////////////////////////////////
+// Programm Counter Logic
+
+always @(posedge clk)
+ pc_r2 <= #1 pc_r;
+
+// 'inst_addr' is a duplication of the 'pc'. The only time when it is really needed
+// is when the program memory is not on the chip and we want to place the registers
+// directly in the IO pads to reduce Tcq (For example in a Xilinx FPGA implementation).
+// If the program memory is on the chip or if the implmentation allows feedback from
+// registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to
+// make the correct decission either way, and gett rid of unneded logic ...
+
+always @(posedge clk)
+ if(rst) inst_addr <= #1 PC_RST_VECTOR;
+ else inst_addr <= #1 pc_next;
+
+always @(posedge clk)
+ if(rst) pc <= #1 PC_RST_VECTOR;
+ else pc <= #1 pc_next;
+
+
+always @(*)
+ if(pc_we) pc_next = {status[6:5], 1'b0, dout};
+ else
+ if(!pc_call & !pc_goto & !pc_retlw) pc_next = pc_plus_1;
+ else
+ if(pc_call) pc_next = {status[6:5], 1'b0, instr_1[7:0]};
+ else
+ if(pc_goto) pc_next = {status[6:5], instr_1[8:0]};
+ else
+ if(pc_retlw) pc_next = stack_out;
+
+
+
+
+
+
+
+
+assign pc_plus_1 = pc + 11'h1;
+
+
+reg invalidate_1_r1, invalidate_1_r2;
+
+assign invalidate_1 = (pc_skz & z_out) | (pc_bset & bit_sel) |
+ (pc_bclr & !bit_sel) | (invalidate_0 & valid_1) | invalidate_1_r1;
+
+
+always @(posedge clk)
+ begin
+ invalidate_1_r1 <= #1 (invalidate_0 & valid_1) | invalidate_1_r2;
+ invalidate_1_r2 <= #1 (invalidate_0 & valid_1);
+ end
+
+assign bit_sel = src1[ instr_1[7:5] ];
+
+
+`VARIENT`FIFO4
+#(.WIDTH(11))
+fifo4( .clk (clk),
+ .push (pc_call),
+ .din (pc_r2),
+ .pop (pc_retlw),
+ .dout (stack_out) );
+
+
+`ifndef SYNTHESIS
+
+
+
+
+reg [8*8-1:0] inst_string;
+
+always @(inst_data) begin
+ casex (inst_data)
+ 12'b0000_0000_0000: inst_string = "NOP ";
+ 12'b0000_001X_XXXX: inst_string = "MOVWF ";
+ 12'b0000_0100_0000: inst_string = "CLRW ";
+ 12'b0000_011X_XXXX: inst_string = "CLRF ";
+ 12'b0000_10XX_XXXX: inst_string = "SUBWF ";
+ 12'b0000_11XX_XXXX: inst_string = "DECF ";
+ 12'b0001_00XX_XXXX: inst_string = "IORWF ";
+ 12'b0001_01XX_XXXX: inst_string = "ANDWF ";
+ 12'b0001_10XX_XXXX: inst_string = "XORWF ";
+ 12'b0001_11XX_XXXX: inst_string = "ADDWF ";
+ 12'b0010_00XX_XXXX: inst_string = "MOVF ";
+ 12'b0010_01XX_XXXX: inst_string = "COMF ";
+ 12'b0010_10XX_XXXX: inst_string = "INCF ";
+ 12'b0010_11XX_XXXX: inst_string = "DECFSZ ";
+ 12'b0011_00XX_XXXX: inst_string = "RRF ";
+ 12'b0011_01XX_XXXX: inst_string = "RLF ";
+ 12'b0011_10XX_XXXX: inst_string = "SWAPF ";
+ 12'b0011_11XX_XXXX: inst_string = "INCFSZ ";
+
+ // *** Bit-Oriented File Register Operations
+ 12'b0100_XXXX_XXXX: inst_string = "BCF ";
+ 12'b0101_XXXX_XXXX: inst_string = "BSF ";
+ 12'b0110_XXXX_XXXX: inst_string = "BTFSC ";
+ 12'b0111_XXXX_XXXX: inst_string = "BTFSS ";
+
+ // *** Literal and Control Operations
+ 12'b0000_0000_0010: inst_string = "OPTION ";
+ 12'b0000_0000_0011: inst_string = "SLEEP ";
+ 12'b0000_0000_0100: inst_string = "CLRWDT ";
+ 12'b0000_0000_0101: inst_string = "TRIS ";
+ 12'b0000_0000_0110: inst_string = "TRIS ";
+ 12'b0000_0000_0111: inst_string = "TRIS ";
+ 12'b1000_XXXX_XXXX: inst_string = "RETLW ";
+ 12'b1001_XXXX_XXXX: inst_string = "CALL ";
+ 12'b101X_XXXX_XXXX: inst_string = "GOTO ";
+ 12'b1100_XXXX_XXXX: inst_string = "MOVLW ";
+ 12'b1101_XXXX_XXXX: inst_string = "IORLW ";
+ 12'b1110_XXXX_XXXX: inst_string = "ANDLW ";
+ 12'b1111_XXXX_XXXX: inst_string = "XORLW ";
+
+ default: inst_string = "-XXXXXX-";
+ endcase
+ $display("%t %m %h %s",$realtime,inst_addr, inst_string);
+end
+
+
+
+`endif
+
+
+
+
+
+endmodule
Index: trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_alu.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_alu.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_alu.v (revision 6)
@@ -0,0 +1,132 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// ALU ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+`include "mrisc_defines.v"
+
+module
+`VARIENT`ALU
+ (
+input wire [7:0] s1,
+input wire [7:0] s2,
+input wire [7:0] mask,
+
+input wire [3:0] op,
+input wire c_in,
+
+output reg [7:0] out,
+output wire c,
+output wire dc,
+output wire z
+ );
+
+
+
+
+
+
+parameter ALU_ADD = 4'h0,
+ ALU_SUB = 4'h1,
+ ALU_INC = 4'h2,
+ ALU_DEC = 4'h3,
+ ALU_AND = 4'h4,
+ ALU_CLR = 4'h5,
+ ALU_NOT = 4'h6,
+ ALU_IOR = 4'h7,
+ ALU_MOV = 4'h8,
+ ALU_MOVW = 4'h9,
+ ALU_RLF = 4'ha,
+ ALU_RRF = 4'hb,
+ ALU_SWP = 4'hc,
+ ALU_XOR = 4'hd,
+ ALU_BCF = 4'he,
+ ALU_BSF = 4'hf;
+
+
+wire co, bo;
+wire [5:0] tmp_add;
+wire borrow_dc;
+wire [7:0] add_sub_out;
+wire add_sub_sel;
+wire [7:0] s2_a;
+
+
+
+
+always @(*)
+ begin
+ case(op) // synopsys full_case parallel_case
+ ALU_ADD: out = s1 + s2;
+ ALU_AND: out = s1 & s2;
+ ALU_CLR: out = 8'h00;
+ ALU_NOT: out = ~s1;
+ ALU_DEC: out = s1 - 1;
+ ALU_INC: out = s1 + 1;
+ ALU_IOR: out = s1 | s2;
+ ALU_MOV: out = s1;
+ ALU_MOVW: out = s2;
+ ALU_RLF: out = {s1[7:0], c_in};
+ ALU_RRF: out = {s1[0], c_in, s1[7:1]};
+ ALU_SUB: out = s1 - s2;
+ ALU_SWP: out = {s1[3:0], s1[7:4]};
+ ALU_XOR: out = s1 ^ s2;
+ ALU_BCF: out = s1 & ~mask;
+ ALU_BSF: out = s1 | mask;
+ endcase
+ end
+
+assign add_sub_sel = (op[3:2]==2'b0);
+assign s2_a = op[1] ? 8'h01 : s2;
+assign {co, add_sub_out} = op[0] ? (s1 - s2_a) : (s1 + s2_a);
+
+
+// C bit generation
+assign c = add_sub_sel ? co : op[0] ? s1[0] : s1[7];
+
+// Z Bit generation
+assign z = (out==8'h0);
+
+// DC Bit geberation
+// This section is really bad, but not in the critical path,
+// so I leave it alone for now ....
+assign borrow_dc = s1[3:0] >= s2[3:0];
+assign tmp_add = s1[3:0] + s2[3:0];
+assign dc = (op==ALU_SUB) ? borrow_dc : tmp_add[4];
+
+endmodule
Index: trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_fifo.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_fifo.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_fifo.v (revision 6)
@@ -0,0 +1,83 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// ALU ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// A Basic Synchrounous FIFO (4 entries deep)
+
+
+`include "mrisc_defines.v"
+
+module
+`VARIENT`FIFO4
+#(parameter WIDTH=8)
+
+(
+input wire clk,
+input wire push,
+input wire [WIDTH-1:0] din,
+input wire pop,
+output wire [WIDTH-1:0] dout
+
+);
+
+reg [WIDTH-1:0] stack1, stack2, stack3, stack4;
+
+assign dout = stack1;
+
+always @(posedge clk)
+ begin
+ if(push) // PUSH stack
+ begin
+ stack4 <= #1 stack3;
+ stack3 <= #1 stack2;
+ stack2 <= #1 stack1;
+ stack1 <= #1 din;
+ end
+ if(pop) // POP stack
+ begin
+ stack1 <= #1 stack2;
+ stack2 <= #1 stack3;
+ stack3 <= #1 stack4;
+ end
+ end
+
+
+
+
+
+endmodule
Index: trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v (revision 6)
@@ -0,0 +1,105 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// Register File ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+
+`include "mrisc_defines.v"
+
+
+
+module `VARIENT`REGISTER_FILE( clk, rst,
+ rf_rd_bnk, rf_rd_addr, rf_rd_data,
+ rf_we, rf_wr_bnk, rf_wr_addr, rf_wr_data);
+
+input clk,rst;
+input [1:0] rf_rd_bnk;
+input [4:0] rf_rd_addr;
+output [7:0] rf_rd_data;
+input rf_we;
+input [1:0] rf_wr_bnk;
+input [4:0] rf_wr_addr;
+input [7:0] rf_wr_data;
+
+wire clk;
+wire [7:0] rf_rd_data;
+wire [6:0] rd_addr;
+wire [6:0] wr_addr;
+wire [7:0] rf_rd_data_mem;
+reg [7:0] wr_data_tmp;
+reg rd_wr_addr_equal;
+
+// Simple Read & Write Address Mapping to memory address
+assign rd_addr[6] = ~rf_rd_addr[4];
+assign rd_addr[5:3] = rf_rd_addr[4] ? {rf_rd_bnk, rf_rd_addr[3]} : 3'h0;
+assign rd_addr[2:0] = rf_rd_addr[2:0];
+
+assign wr_addr[6] = ~rf_wr_addr[4];
+assign wr_addr[5:3] = rf_wr_addr[4] ? {rf_wr_bnk, rf_wr_addr[3]} : 3'h0;
+assign wr_addr[2:0] = rf_wr_addr[2:0];
+
+// This logic is to bypass the register file if we are reading and
+// writing (in previous instruction) to the same register
+always @(posedge clk)
+ rd_wr_addr_equal <= #1 (rd_addr==wr_addr) & rf_we;
+
+assign rf_rd_data = rd_wr_addr_equal ? wr_data_tmp : rf_rd_data_mem;
+
+always @(posedge clk)
+ wr_data_tmp <= #1 rf_wr_data;
+
+// This is the actual Memory
+cde_sram #(.ADDR (7),
+ .WIDTH (8),
+ .WORDS (128))
+
+ rf0(
+ .clk ( clk ),
+ .CS ( 1'b1 ),
+
+
+ .RD ( 1'b1 ),
+ .RD_Add ( rd_addr ),
+ .Read_Data ( rf_rd_data_mem ),
+
+
+ .WR ( rf_we ),
+ .WR_Add ( wr_addr ),
+ .Write_Data ( rf_wr_data )
+ );
+
+endmodule
Index: trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_presclr_wdt.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_presclr_wdt.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_presclr_wdt.v (revision 6)
@@ -0,0 +1,131 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// Prescaler and Wachdog Counter ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+`include "mrisc_defines.v"
+
+
+// Prescaler and Wachdog Counter
+module
+`VARIENT`PRESCLR_WDT
+(clk, rst, tcki, option, tmr0_we, tmr0_cnt_en, wdt_en, wdt_clr, wdt_to);
+
+
+input clk;
+input rst;
+input tcki;
+input [5:0] option;
+input tmr0_we;
+output tmr0_cnt_en;
+input wdt_en, wdt_clr;
+output wdt_to;
+
+
+reg [7:0] prescaler;
+reg [7:0] wdt;
+reg tmr0_cnt_en;
+reg tcki_r;
+reg wdt_to;
+wire tose;
+wire tosc;
+wire psa;
+wire [2:0] ps;
+wire tcki_a, tcki_b;
+wire presclr_ce;
+wire prsclr_clr;
+wire wdt_to_direct;
+reg presclr_out, presclr_out_r1;
+reg presclr_out_next;
+wire [7:0] presclr_plus_1, wdt_plus_1;
+wire [7:0] prescaler_next, prescaler_next1;
+wire [7:0] wdt_next, wdt_next1;
+
+// Inputs select
+assign ps = option[2:0];
+assign psa = option[3];
+assign tose = option[4];
+assign tosc = option[5];
+
+always @(posedge clk)
+ tcki_r <= #1 tcki;
+
+assign tcki_a = tose ^ tcki_r;
+assign tcki_b = tosc ? tcki_a : 1'b1;
+assign presclr_ce = psa ? wdt_to_direct : tcki_b;
+
+always @(posedge clk)
+ tmr0_cnt_en <= #1 psa ? tcki_b : presclr_out;
+
+// Prescaler
+assign prsclr_clr = psa ? wdt_clr : tmr0_we;
+
+always @(posedge clk)
+ if(rst | prsclr_clr) prescaler <= #1 8'h00;
+ else
+ if(presclr_ce) prescaler <= #1 prescaler + 8'h01;
+
+always @(ps or prescaler)
+ case(ps)
+ 3'd0: presclr_out_next = prescaler[0];
+ 3'd1: presclr_out_next = prescaler[1];
+ 3'd2: presclr_out_next = prescaler[2];
+ 3'd3: presclr_out_next = prescaler[3];
+ 3'd4: presclr_out_next = prescaler[4];
+ 3'd5: presclr_out_next = prescaler[5];
+ 3'd6: presclr_out_next = prescaler[6];
+ 3'd7: presclr_out_next = prescaler[7];
+ endcase
+
+always @(posedge clk)
+ presclr_out_r1 <= #1 presclr_out_next;
+
+always @(posedge clk) // Edge detector for prescaler output
+ presclr_out <= #1 presclr_out_next & ~presclr_out_r1 & ~prsclr_clr;
+
+// Wachdog timer
+always @(posedge clk)
+ wdt_to <= #1 psa ? presclr_out : wdt_to_direct;
+
+always @(posedge clk)
+ if(rst | wdt_clr) wdt <= #1 8'h00;
+ else
+ if(wdt_en) wdt <= #1 wdt + 8'h01; // wdt_plus_1;
+
+assign wdt_to_direct = (wdt == 8'hff);
+
+endmodule
Index: trunk/projects/pic_micro/ip/mrisc/rtl/varients/mrisc/mrisc_defines.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/rtl/varients/mrisc/mrisc_defines.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/rtl/varients/mrisc/mrisc_defines.v (revision 6)
@@ -0,0 +1,5 @@
+`define VARIENT mrisc
+`define ALU _alu
+`define PRESCLR_WDT _presclr_wdt
+`define REGISTER_FILE _register_file
+`define FIFO4 _fifo4
Index: trunk/projects/pic_micro/ip/mrisc/doc/README.txt
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/doc/README.txt (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/doc/README.txt (revision 6)
@@ -0,0 +1,120 @@
+
+This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the
+PIC 16C57 from Microchip.
+
+
+Legal
+=====
+
+PIC, Microship, etc. are Trademarks of Microchip Technology Inc.
+
+I have no idea if implementing this core will or will not violate
+patents, copyrights or cause any other type of lawsuits.
+
+I provide this core AS IS, without any warrenties. If you decide to
+build this core, you are responsible for any legal resolutions, such
+as patents and copyrights, and perhaps others ....
+
+ This source file(s) may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
+ LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
+ FITNESS FOR A PARTICULAR PURPOSE.
+
+
+Motivation
+==========
+
+After seeing the "free_risc8" on the free-ip web site, I got excited
+and downloaded the core. Pretty soon I found out that it had many
+many errors and omissions from the original 16C57. So I started looking
+at the code. This is when I realized it was very badly designed and
+could not be made run faster. So, I sat down and wrote my own PIC IP
+core last night. A lot of work was spend in writing test code to ensure
+that it was 100% compatible from the software point of view.
+
+- A PIC compatible Microcontroller that runs a lot faster
+- Separate (External to the core) Program Memory
+- Options to extend the core
+
+
+Compatibility
+=============
+
+This design should be fully software compatible to the Microchip Implementation
+of the PIC 16C57, except for the following extensions:
+
+- Port A is full 8 bits wide
+- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded)
+- Executions of instructions that modify the PC has become a lot more expensive
+ due to the pipeline and execution of instructions on every cycle.
+ Any instruction that writes to the PC (PC as destination (f), call, goto, retlw)
+ now takes 4 cycles to execute (instead of 2 in the origianl implementation).
+ The 4 'skip' instructions, remain as in the original implmentation: 1 cycle
+ if not skipped, 2 cycles if skipped.
+- Sampling of IO ports might be off
+- Timer and watchdog might be off a few cycles
+
+
+Performance
+===========
+
+- Single cycle instruction execution, except as noted above.
+- Here are results of some sample implementations:
+ - Xilinx Spartan 2e ((Device: xc2s50e-6): Fmax: 80Mhz, Utilization: 30%
+ - Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS
+ - Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS
+ - Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS
+ Half of the cycle time is spend in routing delays. My guess is that by placing
+ proper locatiuon contrains and guiding the back-end tools, a significant
+ speed improvement can be achieved ....
+- I estimat about 25K gates with the xilinx primitives, (excluding Register
+ File and Programm Memory).
+
+Implementing the core
+=====================
+
+The only file you should edit if you really want to implement this core, is the
+'primitives.v' file. It contains all parts that can be optimized, depending on
+the technology used. It includes memories, and arithmetic modules.
+I added a primitives_xilinx,v file and xilinx_primitives.zip which contain
+primitives for xilinx.
+'risc_core.v' is the top level without program memory and tristate Io buffers for ports.
+This is probably a good starting point if you want to instantiate the core in to a larger
+design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written
+with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just
+replace the memory blocks ...
+
+To-Do
+=====
+
+Things that need to be done
+
+1) Write more test/compliance test vectors
+ - Verify that all instructions after a goto/call/retlw/write to PCL are not executed
+ - Verify ALU
+ - Timer and Watchdog tests
+ - Perhaps some other ereas ?
+
+2) Extensions ?
+ - I guess this is on a "as needed" basis
+ - A friend suggested to add registers that can be shared by two or more cores in a MP type configuration
+
+Author
+======
+
+I have been doing ASIC design, verification and synthesis for over 15 years.
+This core is only a "mid-night hack", and should used with caution.
+
+I'd also like to know if anyone will actually use this core. Please send me a
+note if you will !
+
+Rudolf Usselmann
+russelmann@hotmail.com
+
+Feel free to send me comments, suggestions and bug reports.
+
Index: trunk/projects/pic_micro/ip/mrisc/doc/copyright.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/doc/copyright.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/doc/copyright.v (revision 6)
@@ -0,0 +1,44 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Mini-RISC-1 ////
+//// Mini-Risc Core ////
+//// ////
+//// ////
+//// Author: Rudolf Usselmann ////
+//// rudi@asics.ws ////
+//// ////
+//// ////
+//// D/L from: http://www.opencores.org/cores/minirisc/ ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000-2002 Rudolf Usselmann ////
+//// www.asics.ws ////
+//// rudi@asics.ws ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+`ifndef SYNTHESIS
+`include "timescale.v"
+`endif
+
+
Index: trunk/projects/pic_micro/ip/mrisc/bin/Makefile
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/bin/Makefile (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/bin/Makefile (revision 6)
@@ -0,0 +1,2 @@
+include ../../../bin/Makefile.root
+
trunk/projects/pic_micro/ip/mrisc/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs (revision 6)
@@ -0,0 +1,13 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/rf1/rf1.abs12"
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/test_define (revision 6)
@@ -0,0 +1,37 @@
+
+initial
+ begin
+ $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
+`TIMEFORMAT
+
+ $display ("========== Starting Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+ while(porta == 8'hFF) @(posedge clk);
+ while(porta == 8'h00) @(posedge clk);
+
+ if(porta == 8'h01)
+ begin
+ $display("Test PASSED !!!");
+ end
+ else
+ if(porta == 8'hff)
+ begin
+ $display("Test FAILED in test %d !!!", portb);
+ end
+ else
+ $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb);
+
+
+ repeat(4) @(posedge clk);
+ $display("\n=============================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dmp_define (revision 6)
@@ -0,0 +1,4 @@
+$dumpfile ("./TestBench.vcd");
+$dumpvars (0, TB);
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/modellist (revision 6)
@@ -0,0 +1 @@
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (tcki),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs (revision 6)
@@ -0,0 +1,15 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/sanity1/sanity1.abs12"
+`define GOOD 12'h0aa
+`define BAD 12'h0af
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/test_define (revision 6)
@@ -0,0 +1,36 @@
+
+
+initial
+ begin
+`TIMEFORMAT
+ $display ("\n\nMini-RISC. Version 1.0\n\n");
+ $display ("========== Starting Sanity 1 Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+ while(inst_addr != `GOOD & inst_addr != `BAD) @(posedge clk);
+
+ if(inst_addr == `GOOD)
+ begin
+ $display("Sanity1 test PASSED !!!");
+ end
+ else
+ if(inst_addr == `BAD)
+ begin
+ $display("Sanity1 test FAILED !!!");
+ end
+ else
+ $display("Sanity1 test status UNKNOWN !!!");
+
+
+ repeat(4) @(posedge clk);
+ $display("=============================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dmp_define (revision 6)
@@ -0,0 +1,3 @@
+$dumpfile ("TestBench.vcd");
+$dumpvars (0, TB);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (tcki),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/modellist (revision 6)
@@ -0,0 +1,2 @@
+
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs (revision 6)
@@ -0,0 +1,13 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/loop/loop.abs12"
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/loop/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/test_define (revision 6)
@@ -0,0 +1,24 @@
+
+initial
+ begin
+`TIMEFORMAT
+ $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
+
+
+ $display ("========== Starting Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+
+
+ repeat(40000) @(posedge clk);
+ $display("\n== PASSED ===========================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/loop/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dmp_define (revision 6)
@@ -0,0 +1,4 @@
+$dumpfile ("./TestBench.vcd");
+$dumpvars (0, TB);
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/loop/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/modellist (revision 6)
@@ -0,0 +1 @@
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (1'b0),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs (revision 6)
@@ -0,0 +1,13 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/rf2/rf2.abs12"
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/test_define (revision 6)
@@ -0,0 +1,37 @@
+
+initial
+ begin
+ $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
+`TIMEFORMAT
+
+ $display ("========== Starting Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+ while(porta == 8'hFF) @(posedge clk);
+ while(porta == 8'h00) @(posedge clk);
+
+ if(porta == 8'h01)
+ begin
+ $display("Test PASSED !!!");
+ end
+ else
+ if(porta == 8'hff)
+ begin
+ $display("Test FAILED in test %d !!!", portb);
+ end
+ else
+ $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb);
+
+
+ repeat(4) @(posedge clk);
+ $display("\n=============================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dmp_define (revision 6)
@@ -0,0 +1,4 @@
+$dumpfile ("./TestBench.vcd");
+$dumpvars (0, TB);
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/modellist (revision 6)
@@ -0,0 +1 @@
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (tcki),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs (revision 6)
@@ -0,0 +1,13 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/sanity2/sanity2.abs12"
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/test_define (revision 6)
@@ -0,0 +1,38 @@
+
+initial
+ begin
+`TIMEFORMAT
+ $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
+
+
+ $display ("========== Starting Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+ while(porta == 8'hFF) @(posedge clk);
+ while(porta == 8'h00) @(posedge clk);
+
+ if(porta == 8'h01)
+ begin
+ $display("Test PASSED !!!");
+ end
+ else
+ if(porta == 8'hff)
+ begin
+ $display("Test FAILED in test %d !!!", portb);
+ end
+ else
+ $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb);
+
+
+ repeat(4) @(posedge clk);
+ $display("\n=============================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dmp_define (revision 6)
@@ -0,0 +1,4 @@
+$dumpfile ("./TestBench.vcd");
+$dumpvars (0, TB);
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (tcki),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/modellist (revision 6)
@@ -0,0 +1 @@
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/liblist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/liblist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/liblist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../lib/cde_sram/cde_sram.v"
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs (revision 6)
@@ -0,0 +1,13 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 40.0000
+`define ROM_WORDS 2048
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define ROM_FILE "../../../../../sw/rf3/rf3.abs12"
+
+
+
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/TB.defs
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/copyright
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/copyright (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/copyright (revision 6)
@@ -0,0 +1,42 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / SIM \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Simulation fileset */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/test_define (revision 6)
@@ -0,0 +1,37 @@
+
+initial
+ begin
+ $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n");
+`TIMEFORMAT
+
+ $display ("========== Starting Test ========== \n");
+ cg.reset_on;
+ repeat(10) @(posedge clk);
+ cg.reset_off;
+
+
+ while(porta == 8'hFF) @(posedge clk);
+ while(porta == 8'h00) @(posedge clk);
+
+ if(porta == 8'h01)
+ begin
+ $display("Test PASSED !!!");
+ end
+ else
+ if(porta == 8'hff)
+ begin
+ $display("Test FAILED in test %d !!!", portb);
+ end
+ else
+ $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb);
+
+
+ repeat(4) @(posedge clk);
+ $display("\n=============================================\n\n\n");
+
+
+ $dumpflush;
+ $finish;
+ end
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/timescale.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/timescale.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dmp_define
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dmp_define (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dmp_define (revision 6)
@@ -0,0 +1,4 @@
+$dumpfile ("./TestBench.vcd");
+$dumpvars (0, TB);
+
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/filelist (revision 6)
@@ -0,0 +1,4 @@
+`include "../../../rtl/gen/sim/mrisc.v"
+
+
+
trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/modellist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/modellist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/modellist (revision 6)
@@ -0,0 +1 @@
+`include "../../bench/verilog/models/clock_gen.v"
\ No newline at end of file
Index: trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dut
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dut (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dut (revision 6)
@@ -0,0 +1,114 @@
+
+
+
+
+// Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc u0(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (tcki),
+ .wdt_en (1'b1)
+
+ );
+
+// IO buffers for IO Ports
+assign porta = trisa ? 8'bz : portaout;
+assign portain = porta;
+
+assign portb = trisb ? 8'bz : portbout;
+assign portbin = portb;
+
+assign portc = trisc ? 8'bz : portcout;
+assign portcin = portc;
+
+// Pullups for IO Ports
+pullup ua0(porta[0]);
+pullup ua1(porta[1]);
+pullup ua2(porta[2]);
+pullup ua3(porta[3]);
+pullup ua4(porta[4]);
+pullup ua5(porta[5]);
+pullup ua6(porta[6]);
+pullup ua7(porta[7]);
+
+pullup ub0(portb[0]);
+pullup ub1(portb[1]);
+pullup ub2(portb[2]);
+pullup ub3(portb[3]);
+pullup ub4(portb[4]);
+pullup ub5(portb[5]);
+pullup ub6(portb[6]);
+pullup ub7(portb[7]);
+
+pullup uc0(portc[0]);
+pullup uc1(portc[1]);
+pullup uc2(portc[2]);
+pullup uc3(portc[3]);
+pullup uc4(portc[4]);
+pullup uc5(portc[5]);
+pullup uc6(portc[6]);
+pullup uc7(portc[7]);
+
+
+// Instantiate the Program RAM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ u1 (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0), // This testbench doesn't allow writing to PRAM
+ .Write_Data (12'b000000000000), // This testbench doesn't allow writing to PRAM
+ .Read_Data (inst_data)
+);
+
Index: trunk/projects/pic_micro/ip/mrisc/sim/bin/Makefile
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/sim/bin/Makefile (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/sim/bin/Makefile (revision 6)
@@ -0,0 +1,3 @@
+include ../../../../bin/Makefile.root
+
+
trunk/projects/pic_micro/ip/mrisc/sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/bsdl/xc3s100e_vq100_1532.bsd
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/bsdl/xc3s100e_vq100_1532.bsd (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/bsdl/xc3s100e_vq100_1532.bsd (revision 6)
@@ -0,0 +1,722 @@
+--$ XILINX$RCSfile: xc3s100e_vq100_1532.bsd,v $
+--$ XILINX$Revision: 1.2.124.1 $
+
+--###################################################################
+-- WARNING !!!! .. This is a 1532 PROTOTYPE BDSL file.
+--###################################################################
+--
+-- It should not be be used in place of, or along side of 1149.1 bsdl files.
+--
+-- This file conforms to the unapproved IEEE Standard 1532 BSDL draft
+-- Standard. It may not function as expected with IEEE 1149.1 BSDL
+-- and is subject to change pending the ratification of the 1532 Standard
+-- by the IEEE. When denoted as FINAL, it has been verified
+-- syntactically, and against hardware.
+--
+-- Prototype 1532 BSDL file for device XC3S100E, package VQ100
+-- Xilinx, Inc. $State: Exp $ $Date: 2008/07/07 22:23:21 $
+--
+-- Generated by BSDLnet bsdlnet Version 1.39a
+------------------------------------------------------------------------
+-- Modification History
+-- | Generated on 05/28/08
+-- | CR # 471899
+-- | Details - Initial Release using BSDLnet.
+-- | Added 'attribute COMPLIANCE_PATTERNS' & changed boundary
+-- | register attribute to internal for PROG_B & PUDC_B.
+------------------------------------------------------------------------
+--
+-- createBSDL template $RCSfile: xc3s100e_vq100_1532.bsd,v $ $Revision: 1.2.124.1 $ $Date: 2008/07/07 22:23:21 $
+--
+--###################################################################
+--
+--
+-- For technical support, contact Xilinx on the web at:
+--
+-- http://support.xilinx.com
+--
+-- Technical support can also take place via email or phone at:
+--
+-- North America 1-800-255-7778 hotline@xilinx.com
+-- United Kingdom (44) 1932 820821 ukhelp@xilinx.com
+-- France (33) 1 3463 0100 frhelp@xilinx.com
+-- Germany (49) 89 991 54930 dlhelp@xilinx.com
+-- Japan (81) 3-3297-9163 jhotline@xilinx.com
+--
+--
+-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
+-- the post-configuration JTAG behavior (if any), edit this file as described
+-- below. Many of these changes are demonstrated by commented-out template
+-- lines preceeding the lines they would replace:
+--
+-- 1. Set disable result of all pads as configured.
+-- 2. Set safe state of boundary cells as necessary.
+-- 3. Rename entity if necessary to avoid name collisions.
+-- 4. Modify USERCODE value in USERCODE_REGISTER declaration.
+--
+--###################################################################--
+
+----------------------------------
+
+-- BSDL File for 1532 Standard.
+
+----------------------------------
+
+entity XC3S100E_VQ100 is
+
+-- Generic Parameter
+
+generic (PHYSICAL_PIN_MAP : string := "VQ100" );
+
+-- Logical Port Description
+
+port (
+ DONE: inout bit;
+ GND: linkage bit_vector (1 to 12);
+ IPAD12: in bit;
+ IPAD13: in bit;
+ IPAD36: in bit;
+ IPAD66: in bit;
+ IPAD67: in bit;
+ IPAD73: in bit;
+ IPAD95: in bit;
+ P10: inout bit; -- PAD98
+ P11: inout bit; -- PAD97
+ P12: inout bit; -- PAD96
+ P15: inout bit; -- PAD94
+ P16: inout bit; -- PAD93
+ P17: inout bit; -- PAD92
+ P18: inout bit; -- PAD91
+ P2: inout bit; -- PAD108
+ P22: inout bit; -- PAD83
+ P23: inout bit; -- PAD82
+ P24: inout bit; -- PAD79
+ P25: inout bit; -- PAD78
+ P26: inout bit; -- PAD76
+ P27: inout bit; -- PAD75
+ P3: inout bit; -- PAD107
+ P32: inout bit; -- PAD72
+ P33: inout bit; -- PAD71
+ P34: inout bit; -- PAD70
+ P35: inout bit; -- PAD69
+ P36: inout bit; -- PAD68
+ P4: inout bit; -- PAD106
+ P40: inout bit; -- PAD65
+ P41: inout bit; -- PAD64
+ P42: inout bit; -- PAD63
+ P43: inout bit; -- PAD62
+ P44: inout bit; -- PAD61
+ P47: inout bit; -- PAD59
+ P48: inout bit; -- PAD58
+ P49: inout bit; -- PAD56
+ P5: inout bit; -- PAD105
+ P50: inout bit; -- PAD55
+ P53: inout bit; -- PAD54
+ P54: inout bit; -- PAD53
+ P57: inout bit; -- PAD49
+ P58: inout bit; -- PAD48
+ P60: inout bit; -- PAD45
+ P61: inout bit; -- PAD44
+ P62: inout bit; -- PAD43
+ P63: inout bit; -- PAD42
+ P65: inout bit; -- PAD40
+ P66: inout bit; -- PAD39
+ P67: inout bit; -- PAD38
+ P68: inout bit; -- PAD37
+ P70: inout bit; -- PAD35
+ P71: inout bit; -- PAD34
+ P78: inout bit; -- PAD25
+ P79: inout bit; -- PAD24
+ P83: inout bit; -- PAD18
+ P84: inout bit; -- PAD17
+ P85: inout bit; -- PAD15
+ P86: inout bit; -- PAD14
+ P9: inout bit; -- PAD99
+ P90: inout bit; -- PAD11
+ P91: inout bit; -- PAD10
+ P92: inout bit; -- PAD9
+ P94: inout bit; -- PAD8
+ P95: inout bit; -- PAD7
+ P98: inout bit; -- PAD2
+ PROG_B: in bit;
+ PUDC_B: in bit; -- PAD1
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit;
+ VCCAUX: linkage bit_vector (1 to 4);
+ VCCINT: linkage bit_vector (1 to 4);
+ VCCO_0: linkage bit_vector (1 to 2);
+ VCCO_1: linkage bit_vector (1 to 2);
+ VCCO_2: linkage bit_vector (1 to 2);
+ VCCO_3: linkage bit_vector (1 to 2)
+); --end port list
+
+-- Use Statements
+
+use STD_1149_1_2001.all;
+use STD_1532_2002.all;
+
+-- Component Conformance Statement(s)
+
+attribute COMPONENT_CONFORMANCE of XC3S100E_VQ100 : entity is
+ "STD_1149_1_2001";
+
+-- Device Package Pin Mappings
+
+attribute PIN_MAP of XC3S100E_VQ100 : entity is PHYSICAL_PIN_MAP;
+
+constant VQ100: PIN_MAP_STRING:=
+ "DONE:P51," &
+ "GND:(P7,P14,P19,P29,P37,P52,P59,P64,P72,P81," &
+ "P87,P93)," &
+ "IPAD12:P89," &
+ "IPAD13:P88," &
+ "IPAD36:P69," &
+ "IPAD66:P39," &
+ "IPAD67:P38," &
+ "IPAD73:P30," &
+ "IPAD95:P13," &
+ "P10:P10," &
+ "P11:P11," &
+ "P12:P12," &
+ "P15:P15," &
+ "P16:P16," &
+ "P17:P17," &
+ "P18:P18," &
+ "P2:P2," &
+ "P22:P22," &
+ "P23:P23," &
+ "P24:P24," &
+ "P25:P25," &
+ "P26:P26," &
+ "P27:P27," &
+ "P3:P3," &
+ "P32:P32," &
+ "P33:P33," &
+ "P34:P34," &
+ "P35:P35," &
+ "P36:P36," &
+ "P4:P4," &
+ "P40:P40," &
+ "P41:P41," &
+ "P42:P42," &
+ "P43:P43," &
+ "P44:P44," &
+ "P47:P47," &
+ "P48:P48," &
+ "P49:P49," &
+ "P5:P5," &
+ "P50:P50," &
+ "P53:P53," &
+ "P54:P54," &
+ "P57:P57," &
+ "P58:P58," &
+ "P60:P60," &
+ "P61:P61," &
+ "P62:P62," &
+ "P63:P63," &
+ "P65:P65," &
+ "P66:P66," &
+ "P67:P67," &
+ "P68:P68," &
+ "P70:P70," &
+ "P71:P71," &
+ "P78:P78," &
+ "P79:P79," &
+ "P83:P83," &
+ "P84:P84," &
+ "P85:P85," &
+ "P86:P86," &
+ "P9:P9," &
+ "P90:P90," &
+ "P91:P91," &
+ "P92:P92," &
+ "P94:P94," &
+ "P95:P95," &
+ "P98:P98," &
+ "PROG_B:P1," &
+ "PUDC_B:P99," &
+ "TCK:P77," &
+ "TDI:P100," &
+ "TDO:P76," &
+ "TMS:P75," &
+ "VCCAUX:(P21,P46,P74,P96)," &
+ "VCCINT:(P6,P28,P56,P80)," &
+ "VCCO_0:(P82,P97)," &
+ "VCCO_1:(P55,P73)," &
+ "VCCO_2:(P31,P45)," &
+ "VCCO_3:(P8,P20)";
+
+
+-- Scan Port Identification
+
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both);
+attribute TAP_SCAN_MODE of TMS : signal is true;
+
+-- Compliance-Enable Description
+
+attribute COMPLIANCE_PATTERNS of XC3S100E_VQ100 : entity is
+ "(PROG_B, PUDC_B) (10)";
+
+-- Instruction Register Description
+
+attribute INSTRUCTION_LENGTH of XC3S100E_VQ100 : entity is 6;
+
+attribute INSTRUCTION_OPCODE of XC3S100E_VQ100 : entity is
+
+ "EXTEST (001111)," &
+ "SAMPLE (000001)," &
+ "PRELOAD (000001)," & -- Same as SAMPLE
+ "USER1 (000010)," & -- Not available until after configuration
+ "USER2 (000011)," & -- Not available until after configuration
+ "CFG_OUT (000100)," & -- Not available during configuration with another mode.
+ "CFG_IN (000101)," & -- Not available during configuration with another mode.
+ "INTEST (000111)," &
+ "USERCODE (001000)," &
+ "IDCODE (001001)," &
+ "HIGHZ (001010)," &
+ "JPROGRAM (001011)," & -- Not available during configuration with another mode.
+ "JSTART (001100)," & -- Not available during configuration with another mode.
+ "JSHUTDOWN (001101)," & -- Not available during configuration with another mode.
+ "BYPASS (111111)," &
+ "ISC_ENABLE (010000)," &
+ "ISC_PROGRAM (010001)," &
+ "ISC_NOOP (010100)," &
+ "ISC_READ (010101)," &
+ "ISC_DISABLE (010110)";
+
+attribute INSTRUCTION_CAPTURE of XC3S100E_VQ100 : entity is
+-- Bit 5 is 1 when DONE is released (part of startup sequence)
+-- Bit 4 is 1 if house-cleaning is complete
+-- Bit 3 is ISC_Enabled
+-- Bit 2 is ISC_Done
+ "XXXX01" ;
+
+attribute INSTRUCTION_PRIVATE of XC3S100E_VQ100 : entity is
+ "USER1," &
+ "USER2," &
+ "CFG_OUT," &
+ "CFG_IN," &
+ "JPROGRAM," &
+ "JSTART," &
+ "JSHUTDOWN," &
+ "ISC_ENABLE," &
+ "ISC_PROGRAM," &
+ "ISC_NOOP," &
+ "ISC_READ," &
+ "ISC_DISABLE";
+
+-- Optional Register Description
+
+attribute IDCODE_REGISTER of XC3S100E_VQ100 : entity is "XXXX" & -- version
+ "0001110" & -- family
+ "000010000" & -- array size
+ "00001001001" & -- manufacturer
+ "1"; -- required by 1149.1
+
+
+attribute USERCODE_REGISTER of XC3S100E_VQ100 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+-- Register Access Description
+
+attribute REGISTER_ACCESS of XC3S100E_VQ100 : entity is
+ "TEST1[8] (USER1)," &
+ "TEST2[8] (USER2)," &
+ "DEVICE_ID (USERCODE,IDCODE)," &
+ "BYPASS (BYPASS,HIGHZ,JPROGRAM,JSTART,JSHUTDOWN)," &
+ "CFG_DATA[581344] (CFG_IN)," &
+ "ISC_PDATA[16] (ISC_PROGRAM),"&
+ "ISC_RDATA[16] (ISC_READ),"&
+ "ISC_DEFAULT[5] (ISC_NOOP)," &
+ "ISC_CONFIG[5] (ISC_ENABLE,ISC_DISABLE)," &
+ "BOUNDARY (EXTEST, SAMPLE, PRELOAD, INTEST)";
+
+-- Boundary-Scan Register Description
+
+attribute BOUNDARY_LENGTH of XC3S100E_VQ100 : entity is 272;
+
+attribute BOUNDARY_REGISTER of XC3S100E_VQ100 : entity is
+-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
+ " 271 (BC_2, *, internal, X)," & -- IPAD27
+ " 270 (BC_2, *, internal, X)," & -- PAD28.I
+ " 269 (BC_2, *, internal, X)," & -- PAD28.O
+ " 268 (BC_2, *, internal, 1)," & -- PAD28.T
+ " 267 (BC_2, *, internal, X)," & -- PAD29.I
+ " 266 (BC_2, *, internal, X)," & -- PAD29.O
+ " 265 (BC_2, *, internal, 1)," & -- PAD29.T
+ " 264 (BC_2, *, internal, X)," & -- PAD30.I
+ " 263 (BC_2, *, internal, X)," & -- PAD30.O
+ " 262 (BC_2, *, internal, 1)," & -- PAD30.T
+ " 261 (BC_2, *, internal, X)," & -- PAD31.I
+ " 260 (BC_2, *, internal, X)," & -- PAD31.O
+ " 259 (BC_2, *, internal, 1)," & -- PAD31.T
+ " 258 (BC_2, *, internal, X)," & -- IPAD32
+ " 257 (BC_2, *, internal, X)," & -- PAD33.I
+ " 256 (BC_2, *, internal, X)," & -- PAD33.O
+ " 255 (BC_2, *, internal, 1)," & -- PAD33.T
+ " 254 (BC_2, P71, input, X)," & -- PAD34
+ " 253 (BC_2, P71, output3, X, 252, 1, PULL1)," & -- PAD34
+ " 252 (BC_2, *, controlr, 1)," &
+ " 251 (BC_2, P70, input, X)," & -- PAD35
+ " 250 (BC_2, P70, output3, X, 249, 1, PULL1)," & -- PAD35
+ " 249 (BC_2, *, controlr, 1)," &
+ " 248 (BC_2, IPAD36, input, X)," &
+ " 247 (BC_2, P68, input, X)," & -- PAD37
+ " 246 (BC_2, P68, output3, X, 245, 1, PULL1)," & -- PAD37
+ " 245 (BC_2, *, controlr, 1)," &
+ " 244 (BC_2, P67, input, X)," & -- PAD38
+ " 243 (BC_2, P67, output3, X, 242, 1, PULL1)," & -- PAD38
+ " 242 (BC_2, *, controlr, 1)," &
+ " 241 (BC_2, P66, input, X)," & -- PAD39
+ " 240 (BC_2, P66, output3, X, 239, 1, PULL1)," & -- PAD39
+ " 239 (BC_2, *, controlr, 1)," &
+ " 238 (BC_2, P65, input, X)," & -- PAD40
+ " 237 (BC_2, P65, output3, X, 236, 1, PULL1)," & -- PAD40
+ " 236 (BC_2, *, controlr, 1)," &
+ " 235 (BC_2, *, internal, X)," & -- IPAD41
+ " 234 (BC_2, P63, input, X)," & -- PAD42
+ " 233 (BC_2, P63, output3, X, 232, 1, PULL1)," & -- PAD42
+ " 232 (BC_2, *, controlr, 1)," &
+ " 231 (BC_2, P62, input, X)," & -- PAD43
+ " 230 (BC_2, P62, output3, X, 229, 1, PULL1)," & -- PAD43
+ " 229 (BC_2, *, controlr, 1)," &
+ " 228 (BC_2, P61, input, X)," & -- PAD44
+ " 227 (BC_2, P61, output3, X, 226, 1, PULL1)," & -- PAD44
+ " 226 (BC_2, *, controlr, 1)," &
+ " 225 (BC_2, P60, input, X)," & -- PAD45
+ " 224 (BC_2, P60, output3, X, 223, 1, PULL1)," & -- PAD45
+ " 223 (BC_2, *, controlr, 1)," &
+ " 222 (BC_2, *, internal, X)," & -- IPAD46
+ " 221 (BC_2, *, internal, X)," & -- PAD47.I
+ " 220 (BC_2, *, internal, X)," & -- PAD47.O
+ " 219 (BC_2, *, internal, 1)," & -- PAD47.T
+ " 218 (BC_2, P58, input, X)," & -- PAD48
+ " 217 (BC_2, P58, output3, X, 216, 1, PULL1)," & -- PAD48
+ " 216 (BC_2, *, controlr, 1)," &
+ " 215 (BC_2, P57, input, X)," & -- PAD49
+ " 214 (BC_2, P57, output3, X, 213, 1, PULL1)," & -- PAD49
+ " 213 (BC_2, *, controlr, 1)," &
+ " 212 (BC_2, *, internal, X)," & -- IPAD50
+ " 211 (BC_2, *, internal, X)," & -- PAD51.I
+ " 210 (BC_2, *, internal, X)," & -- PAD51.O
+ " 209 (BC_2, *, internal, 1)," & -- PAD51.T
+ " 208 (BC_2, *, internal, X)," & -- PAD52.I
+ " 207 (BC_2, *, internal, X)," & -- PAD52.O
+ " 206 (BC_2, *, internal, 1)," & -- PAD52.T
+ " 205 (BC_2, P54, input, X)," & -- PAD53
+ " 204 (BC_2, P54, output3, X, 203, 1, PULL1)," & -- PAD53
+ " 203 (BC_2, *, controlr, 1)," &
+ " 202 (BC_2, P53, input, X)," & -- PAD54
+ " 201 (BC_2, P53, output3, X, 200, 1, PULL1)," & -- PAD54
+ " 200 (BC_2, *, controlr, 1)," &
+ " 199 (BC_2, DONE, input, X)," &
+ " 198 (BC_2, DONE, output3, X, 197, 1, PULL1)," &
+ " 197 (BC_2, *, controlr, 1)," &
+ " 196 (BC_2, P50, input, X)," & -- PAD55
+ " 195 (BC_2, P50, output3, X, 194, 1, PULL1)," & -- PAD55
+ " 194 (BC_2, *, controlr, 1)," &
+ " 193 (BC_2, P49, input, X)," & -- PAD56
+ " 192 (BC_2, P49, output3, X, 191, 1, PULL1)," & -- PAD56
+ " 191 (BC_2, *, controlr, 1)," &
+ " 190 (BC_2, *, internal, X)," & -- IPAD57
+ " 189 (BC_2, P48, input, X)," & -- PAD58
+ " 188 (BC_2, P48, output3, X, 187, 1, PULL1)," & -- PAD58
+ " 187 (BC_2, *, controlr, 1)," &
+ " 186 (BC_2, P47, input, X)," & -- PAD59
+ " 185 (BC_2, P47, output3, X, 184, 1, PULL1)," & -- PAD59
+ " 184 (BC_2, *, controlr, 1)," &
+ " 183 (BC_2, *, internal, X)," & -- IPAD60
+ " 182 (BC_2, P44, input, X)," & -- PAD61
+ " 181 (BC_2, P44, output3, X, 180, 1, PULL1)," & -- PAD61
+ " 180 (BC_2, *, controlr, 1)," &
+ " 179 (BC_2, P43, input, X)," & -- PAD62
+ " 178 (BC_2, P43, output3, X, 177, 1, PULL1)," & -- PAD62
+ " 177 (BC_2, *, controlr, 1)," &
+ " 176 (BC_2, P42, input, X)," & -- PAD63
+ " 175 (BC_2, P42, output3, X, 174, 1, PULL1)," & -- PAD63
+ " 174 (BC_2, *, controlr, 1)," &
+ " 173 (BC_2, P41, input, X)," & -- PAD64
+ " 172 (BC_2, P41, output3, X, 171, 1, PULL1)," & -- PAD64
+ " 171 (BC_2, *, controlr, 1)," &
+ " 170 (BC_2, P40, input, X)," & -- PAD65
+ " 169 (BC_2, P40, output3, X, 168, 1, PULL1)," & -- PAD65
+ " 168 (BC_2, *, controlr, 1)," &
+ " 167 (BC_2, IPAD66, input, X)," &
+ " 166 (BC_2, IPAD67, input, X)," &
+ " 165 (BC_2, P36, input, X)," & -- PAD68
+ " 164 (BC_2, P36, output3, X, 163, 1, PULL1)," & -- PAD68
+ " 163 (BC_2, *, controlr, 1)," &
+ " 162 (BC_2, P35, input, X)," & -- PAD69
+ " 161 (BC_2, P35, output3, X, 160, 1, PULL1)," & -- PAD69
+ " 160 (BC_2, *, controlr, 1)," &
+ " 159 (BC_2, P34, input, X)," & -- PAD70
+ " 158 (BC_2, P34, output3, X, 157, 1, PULL1)," & -- PAD70
+ " 157 (BC_2, *, controlr, 1)," &
+ " 156 (BC_2, P33, input, X)," & -- PAD71
+ " 155 (BC_2, P33, output3, X, 154, 1, PULL1)," & -- PAD71
+ " 154 (BC_2, *, controlr, 1)," &
+ " 153 (BC_2, P32, input, X)," & -- PAD72
+ " 152 (BC_2, P32, output3, X, 151, 1, PULL1)," & -- PAD72
+ " 151 (BC_2, *, controlr, 1)," &
+ " 150 (BC_2, IPAD73, input, X)," &
+ " 149 (BC_2, *, internal, X)," & -- IPAD74
+ " 148 (BC_2, P27, input, X)," & -- PAD75
+ " 147 (BC_2, P27, output3, X, 146, 1, PULL1)," & -- PAD75
+ " 146 (BC_2, *, controlr, 1)," &
+ " 145 (BC_2, P26, input, X)," & -- PAD76
+ " 144 (BC_2, P26, output3, X, 143, 1, PULL1)," & -- PAD76
+ " 143 (BC_2, *, controlr, 1)," &
+ " 142 (BC_2, *, internal, X)," & -- IPAD77
+ " 141 (BC_2, P25, input, X)," & -- PAD78
+ " 140 (BC_2, P25, output3, X, 139, 1, PULL1)," & -- PAD78
+ " 139 (BC_2, *, controlr, 1)," &
+ " 138 (BC_2, P24, input, X)," & -- PAD79
+ " 137 (BC_2, P24, output3, X, 136, 1, PULL1)," & -- PAD79
+ " 136 (BC_2, *, controlr, 1)," &
+ " 135 (BC_2, *, internal, X)," & -- IPAD80
+ " 134 (BC_2, *, internal, X)," & -- IPAD81
+ " 133 (BC_2, P23, input, X)," & -- PAD82
+ " 132 (BC_2, P23, output3, X, 131, 1, PULL1)," & -- PAD82
+ " 131 (BC_2, *, controlr, 1)," &
+ " 130 (BC_2, P22, input, X)," & -- PAD83
+ " 129 (BC_2, P22, output3, X, 128, 1, PULL1)," & -- PAD83
+ " 128 (BC_2, *, controlr, 1)," &
+ " 127 (BC_2, *, internal, X)," & -- PAD84.I
+ " 126 (BC_2, *, internal, X)," & -- PAD84.O
+ " 125 (BC_2, *, internal, 1)," & -- PAD84.T
+ " 124 (BC_2, *, internal, X)," & -- PAD85.I
+ " 123 (BC_2, *, internal, X)," & -- PAD85.O
+ " 122 (BC_2, *, internal, 1)," & -- PAD85.T
+ " 121 (BC_2, *, internal, X)," & -- IPAD86
+ " 120 (BC_2, *, internal, X)," & -- PAD87.I
+ " 119 (BC_2, *, internal, X)," & -- PAD87.O
+ " 118 (BC_2, *, internal, 1)," & -- PAD87.T
+ " 117 (BC_2, *, internal, X)," & -- PAD88.I
+ " 116 (BC_2, *, internal, X)," & -- PAD88.O
+ " 115 (BC_2, *, internal, 1)," & -- PAD88.T
+ " 114 (BC_2, *, internal, X)," & -- PAD89.I
+ " 113 (BC_2, *, internal, X)," & -- PAD89.O
+ " 112 (BC_2, *, internal, 1)," & -- PAD89.T
+ " 111 (BC_2, *, internal, X)," & -- IPAD90
+ " 110 (BC_2, P18, input, X)," & -- PAD91
+ " 109 (BC_2, P18, output3, X, 108, 1, PULL1)," & -- PAD91
+ " 108 (BC_2, *, controlr, 1)," &
+ " 107 (BC_2, P17, input, X)," & -- PAD92
+ " 106 (BC_2, P17, output3, X, 105, 1, PULL1)," & -- PAD92
+ " 105 (BC_2, *, controlr, 1)," &
+ " 104 (BC_2, P16, input, X)," & -- PAD93
+ " 103 (BC_2, P16, output3, X, 102, 1, PULL1)," & -- PAD93
+ " 102 (BC_2, *, controlr, 1)," &
+ " 101 (BC_2, P15, input, X)," & -- PAD94
+ " 100 (BC_2, P15, output3, X, 99, 1, PULL1)," & -- PAD94
+ " 99 (BC_2, *, controlr, 1)," &
+ " 98 (BC_2, IPAD95, input, X)," &
+ " 97 (BC_2, P12, input, X)," & -- PAD96
+ " 96 (BC_2, P12, output3, X, 95, 1, PULL1)," & -- PAD96
+ " 95 (BC_2, *, controlr, 1)," &
+ " 94 (BC_2, P11, input, X)," & -- PAD97
+ " 93 (BC_2, P11, output3, X, 92, 1, PULL1)," & -- PAD97
+ " 92 (BC_2, *, controlr, 1)," &
+ " 91 (BC_2, P10, input, X)," & -- PAD98
+ " 90 (BC_2, P10, output3, X, 89, 1, PULL1)," & -- PAD98
+ " 89 (BC_2, *, controlr, 1)," &
+ " 88 (BC_2, P9, input, X)," & -- PAD99
+ " 87 (BC_2, P9, output3, X, 86, 1, PULL1)," & -- PAD99
+ " 86 (BC_2, *, controlr, 1)," &
+ " 85 (BC_2, *, internal, X)," & -- IPAD100
+ " 84 (BC_2, *, internal, X)," & -- PAD101.I
+ " 83 (BC_2, *, internal, X)," & -- PAD101.O
+ " 82 (BC_2, *, internal, 1)," & -- PAD101.T
+ " 81 (BC_2, *, internal, X)," & -- PAD102.I
+ " 80 (BC_2, *, internal, X)," & -- PAD102.O
+ " 79 (BC_2, *, internal, 1)," & -- PAD102.T
+ " 78 (BC_2, *, internal, X)," & -- PAD103.I
+ " 77 (BC_2, *, internal, X)," & -- PAD103.O
+ " 76 (BC_2, *, internal, 1)," & -- PAD103.T
+ " 75 (BC_2, *, internal, X)," & -- IPAD104
+ " 74 (BC_2, P5, input, X)," & -- PAD105
+ " 73 (BC_2, P5, output3, X, 72, 1, PULL1)," & -- PAD105
+ " 72 (BC_2, *, controlr, 1)," &
+ " 71 (BC_2, P4, input, X)," & -- PAD106
+ " 70 (BC_2, P4, output3, X, 69, 1, PULL1)," & -- PAD106
+ " 69 (BC_2, *, controlr, 1)," &
+ " 68 (BC_2, P3, input, X)," & -- PAD107
+ " 67 (BC_2, P3, output3, X, 66, 1, PULL1)," & -- PAD107
+ " 66 (BC_2, *, controlr, 1)," &
+ " 65 (BC_2, P2, input, X)," & -- PAD108
+ " 64 (BC_2, P2, output3, X, 63, 1, PULL1)," & -- PAD108
+ " 63 (BC_2, *, controlr, 1)," &
+ " 62 (BC_2, *, internal, 1)," & -- PROG_B
+ " 61 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 60 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 59 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 58 (BC_2, P98, input, X)," & -- PAD2
+ " 57 (BC_2, P98, output3, X, 56, 1, PULL1)," & -- PAD2
+ " 56 (BC_2, *, controlr, 1)," &
+ " 55 (BC_2, *, internal, X)," & -- IPAD3
+ " 54 (BC_2, *, internal, X)," & -- PAD4.I
+ " 53 (BC_2, *, internal, X)," & -- PAD4.O
+ " 52 (BC_2, *, internal, 1)," & -- PAD4.T
+ " 51 (BC_2, *, internal, X)," & -- PAD5.I
+ " 50 (BC_2, *, internal, X)," & -- PAD5.O
+ " 49 (BC_2, *, internal, 1)," & -- PAD5.T
+ " 48 (BC_2, *, internal, X)," & -- IPAD6
+ " 47 (BC_2, P95, input, X)," & -- PAD7
+ " 46 (BC_2, P95, output3, X, 45, 1, PULL1)," & -- PAD7
+ " 45 (BC_2, *, controlr, 1)," &
+ " 44 (BC_2, P94, input, X)," & -- PAD8
+ " 43 (BC_2, P94, output3, X, 42, 1, PULL1)," & -- PAD8
+ " 42 (BC_2, *, controlr, 1)," &
+ " 41 (BC_2, P92, input, X)," & -- PAD9
+ " 40 (BC_2, P92, output3, X, 39, 1, PULL1)," & -- PAD9
+ " 39 (BC_2, *, controlr, 1)," &
+ " 38 (BC_2, P91, input, X)," & -- PAD10
+ " 37 (BC_2, P91, output3, X, 36, 1, PULL1)," & -- PAD10
+ " 36 (BC_2, *, controlr, 1)," &
+ " 35 (BC_2, P90, input, X)," & -- PAD11
+ " 34 (BC_2, P90, output3, X, 33, 1, PULL1)," & -- PAD11
+ " 33 (BC_2, *, controlr, 1)," &
+ " 32 (BC_2, IPAD12, input, X)," &
+ " 31 (BC_2, IPAD13, input, X)," &
+ " 30 (BC_2, P86, input, X)," & -- PAD14
+ " 29 (BC_2, P86, output3, X, 28, 1, PULL1)," & -- PAD14
+ " 28 (BC_2, *, controlr, 1)," &
+ " 27 (BC_2, P85, input, X)," & -- PAD15
+ " 26 (BC_2, P85, output3, X, 25, 1, PULL1)," & -- PAD15
+ " 25 (BC_2, *, controlr, 1)," &
+ " 24 (BC_2, *, internal, X)," & -- PAD16.I
+ " 23 (BC_2, *, internal, X)," & -- PAD16.O
+ " 22 (BC_2, *, internal, 1)," & -- PAD16.T
+ " 21 (BC_2, P84, input, X)," & -- PAD17
+ " 20 (BC_2, P84, output3, X, 19, 1, PULL1)," & -- PAD17
+ " 19 (BC_2, *, controlr, 1)," &
+ " 18 (BC_2, P83, input, X)," & -- PAD18
+ " 17 (BC_2, P83, output3, X, 16, 1, PULL1)," & -- PAD18
+ " 16 (BC_2, *, controlr, 1)," &
+ " 15 (BC_2, *, internal, X)," & -- IPAD19
+ " 14 (BC_2, *, internal, X)," & -- IPAD20
+ " 13 (BC_2, *, internal, X)," & -- PAD21.I
+ " 12 (BC_2, *, internal, X)," & -- PAD21.O
+ " 11 (BC_2, *, internal, 1)," & -- PAD21.T
+ " 10 (BC_2, *, internal, X)," & -- PAD22.I
+ " 9 (BC_2, *, internal, X)," & -- PAD22.O
+ " 8 (BC_2, *, internal, 1)," & -- PAD22.T
+ " 7 (BC_2, *, internal, X)," & -- IPAD23
+ " 6 (BC_2, P79, input, X)," & -- PAD24
+ " 5 (BC_2, P79, output3, X, 4, 1, PULL1)," & -- PAD24
+ " 4 (BC_2, *, controlr, 1)," &
+ " 3 (BC_2, P78, input, X)," & -- PAD25
+ " 2 (BC_2, P78, output3, X, 1, 1, PULL1)," & -- PAD25
+ " 1 (BC_2, *, controlr, 1)," &
+ " 0 (BC_2, *, internal, X)"; -- IPAD26
+
+
+attribute ISC_PIN_BEHAVIOR of XC3S100E_VQ100 : entity is
+ "HIGHZ" ; -- clamp behavior
+ -- no status
+
+attribute ISC_STATUS of XC3S100E_VQ100 : entity is
+ "NOT IMPLEMENTED" ;
+
+attribute ISC_BLANK_USERCODE of XC3S100E_VQ100 : entity is
+ "00000000000000000000000000000000";
+
+attribute ISC_FLOW of XC3S100E_VQ100 : entity is
+ -- Enable program
+ "flow_enable " &
+ "initialize " &
+ " (ISC_ENABLE 5:00 wait TCK 16)," &
+
+ "flow_disable " &
+ "initialize " &
+ " (ISC_DISABLE wait TCK 16)" &
+ " (BYPASS 1:0 wait TCK 1)," &
+
+ "flow_program(array) " &
+ "Repeat 36334 " &
+ " (ISC_PROGRAM 16:? wait TCK 1 )," &
+
+ "flow_program(legacy) " &
+ "Initialize " &
+ " (JSHUTDOWN wait TCK 16)" &
+ " (CFG_IN 581344:? wait TCK 1)" &
+ " (JSTART wait TCK 32)" &
+ " (BYPASS 1:0 wait TCK 1)," &
+
+ "flow_verify(idcode) " &
+ "initialize " &
+ " (IDCODE wait TCK 1 32:01C10093*0FFFFFFF)," &
+
+ "flow_read(usercode) " &
+ "initialize " &
+ " (USERCODE wait TCK 1 32:!)," &
+
+ "flow_read(idcode) " &
+ "initialize " &
+ " (IDCODE wait TCK 1 32:!)," &
+
+ "flow_program_done " &
+ "initialize " &
+ " (BYPASS wait TCK 1)," &
+
+ "flow_error_exit " &
+ "initialize " &
+ " (BYPASS wait TCK 1)";
+
+attribute ISC_PROCEDURE of XC3S100E_VQ100 : entity is
+ "proc_enable = (flow_enable)," &
+ "proc_disable = (flow_disable)," &
+ "proc_program = (flow_program(array))," &
+ "proc_program(legacy) = (flow_program(legacy))," &
+ "proc_verify(idcode) = (flow_verify(idcode))," &
+ "proc_read(idcode) = (flow_read(idcode))," &
+ "proc_read(usercode) = (flow_read(usercode))," &
+ "proc_program_done = (flow_program_done)," &
+ "proc_error_exit = (flow_error_exit)";
+
+attribute ISC_ACTION of XC3S100E_VQ100 : entity is
+ "program = (proc_verify(idcode) recommended," &
+ " proc_enable, proc_program," &
+ " proc_disable)," &
+ "program(lgcy) = (proc_verify(idcode) recommended," &
+ " proc_enable, proc_program(legacy)," &
+ " proc_disable)," &
+ "verify(idcode) = (proc_verify(idcode))," &
+ "read(idcode) = (proc_read(idcode))," &
+ "read(usercode) = (proc_read(usercode))";
+
+-- Design Warning Section
+
+attribute DESIGN_WARNING of XC3S100E_VQ100 : entity is
+ "This is a preliminary BSDL file which has not been verified." &
+ "This BSDL file must be modified by the FPGA designer in order to" &
+ "reflect post-configuration behavior (if any)." &
+ "To avoid losing the current configuration, the PROG_B should be" &
+ "kept high. If the PROG_B pin goes low by any means," &
+ "the configuration will be cleared." &
+ "PROG_B can only be captured, not updated." &
+ "The value at the pin is always used by the device." &
+ "PUDC_B can be captured and updated." &
+ "The value at the pin is always used by the device" &
+ "before configuration is done." &
+ "During pre-configuration, the disable result of a 3-stated" &
+ "I/O in this file corresponds to PUDC_B being low" &
+ "or during EXTEST instruction." &
+ "When PUDC_B is high AND during SAMPLE instruction, change" &
+ "all PULL1s to PULL0s." &
+ "After configuration, the disable result only depends on" &
+ "the individual IO configuration setting." &
+ "In EXTEST, output and tristate values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "In INTEST, the pin input values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "The output and tristate capture values are not valid until after" &
+ "the device is configured." &
+ "The tristate control value is not captured properly when" &
+ "GTS is activated.";
+
+end XC3S100E_VQ100;
+
trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/bsdl/xc3s100e_vq100_1532.bsd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist (revision 6)
@@ -0,0 +1,11 @@
+verilog work ./targets/Basys/Pad_Ring.v
+verilog work ../../../../../ip/mrisc/rtl/gen/syn/mrisc.v
+verilog work ../../../../../children/logic/ip/disp_io/rtl/gen/syn/disp_io.v
+
+verilog work ./targets/Basys/lib/syn/cde_pads/cde_pad_se_dig.v
+verilog work ./targets/Basys/lib/syn/cde_clock_sys/cde_clock_sys.v
+verilog work ./targets/Basys/lib/syn/cde_jtag/cde_jtag.v
+verilog work ./targets/Basys/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
+verilog work ./targets/Basys/lib/syn/cde_sram/cde_sram.v
+
+
trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/filelist
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v (revision 6)
@@ -0,0 +1,138 @@
+
+
+
+
+
+
+ // Declare I/O Port connections
+wire [7:0] porta; // I/O Port A
+wire [7:0] portb; // I/O Port B
+wire [7:0] portc; // I/O Port C
+
+wire [7:0] portain;
+wire [7:0] portbin;
+wire [7:0] portcin;
+
+wire [7:0] portaout;
+wire [7:0] portbout;
+wire [7:0] portcout;
+
+wire [7:0] trisa;
+wire [7:0] trisb;
+wire [7:0] trisc;
+
+// Declare ROM and rom signals
+wire [10:0] inst_addr;
+wire [11:0] inst_data;
+
+
+
+wire clk = ck25MHz;
+
+
+assign jtag_user1_cap = jtag_user1_upd;
+assign jtag_user2_cap = PosS;
+
+
+
+
+assign vgared_pad_out = 3'b000;
+assign vgagreen_pad_out = 3'b000;
+assign vgablue_pad_out = 2'b00;
+assign hsync_pad_out = 1'b0;
+assign vsync_pad_out = 1'b0;
+
+
+
+
+
+
+
+
+assign ja_1_pad_out = ck25MHz;
+assign ja_2_pad_out = reset;
+assign ja_3_pad_out = one_usec;
+assign ja_4_pad_out = 1'b0 ;
+
+assign jb_1_pad_out = 1'b0;
+assign jb_2_pad_out = 1'b0;
+assign jb_3_pad_out = 1'b0;
+assign jb_4_pad_out = 1'b0;
+
+assign jc_1_pad_out = 1'b1;
+assign jc_2_pad_out = 1'b0;
+assign jc_3_pad_out = 1'b1;
+assign jc_4_pad_out = 1'b0;
+
+
+
+
+
+
+
+
+// Instantiate one CPU to be tested.
+mrisc cpu(
+ .clk (clk),
+ .rst_in (reset),
+ .inst_addr (inst_addr),
+ .inst_data (inst_data),
+
+ .portain (portain),
+ .portbin (portbin),
+ .portcin (portcin),
+
+ .portaout (portaout),
+ .portbout (portbout),
+ .portcout (portcout),
+
+ .trisa (trisa),
+ .trisb (trisb),
+ .trisc (trisc),
+
+ .tcki (1'b0),
+ .wdt_en (1'b1)
+
+ );
+
+
+
+
+
+// Instantiate the Program ROM.
+cde_sram
+#(
+
+.WORDS( `ROM_WORDS),
+.ADDR( `ROM_ADDR ),
+.WIDTH ( `ROM_WIDTH ),
+.INIT_FILE(`ROM_FILE)
+)
+
+
+ sram (
+ .clk (clk),
+ .RD_Add (inst_addr),
+ .WR_Add (inst_addr),
+ .RD (1'b1),
+ .CS (1'b1),
+ .WR (1'b0),
+ .Write_Data (12'b000000000000),
+ .Read_Data (inst_data)
+);
+
+
+assign ps2_data_pad_oe = 1'b0;
+assign ps2_clk_pad_oe = 1'b0;
+
+
+assign PosD = {trisa[4:0],inst_addr};
+assign PosL = portaout;
+
+
+
+
+
+
+
+
\ No newline at end of file
trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/Makefile
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/Makefile (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/Makefile (revision 6)
@@ -0,0 +1,4 @@
+include ../../../../bin/Makefile.root
+include ./targets/Basys/Makefile.brd
+Design=loop
+
trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file
===================================================================
--- trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file (nonexistent)
+++ trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file (revision 6)
@@ -0,0 +1,14 @@
+`define SYNTHESIS
+`define ROM_FILE "../../../../../../../projects/pic_micro/sw/loop/loop.abs12"
+`define ROM_WORDS 27
+`define ROM_ADDR 11
+`define ROM_WIDTH 12
+`define MODULE_NAME Basys_loop
+
+
+
+`define JTAG_USER1_WIDTH 8
+`define JTAG_USER1_RESET 8'h12
+
+`define JTAG_USER2_WIDTH 8
+`define JTAG_USER2_RESET 8'h00
trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/def_file
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/rf1/rf1.asm
===================================================================
--- trunk/projects/pic_micro/sw/rf1/rf1.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/rf1/rf1.asm (revision 6)
@@ -0,0 +1,694 @@
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Mini-RISC-1 ////
+;//// Register File Test 1 ////
+;//// Tests Register File ////
+;//// ////
+;//// Author: Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Copyright (C) 2000 Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;//// This source file may be used and distributed without ////
+;//// restriction provided that this copyright statement is not ////
+;//// removed from the file and that any derivative work contains ////
+;//// the original copyright notice and the associated disclaimer.////
+;//// ////
+;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY ////
+;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT ////
+;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND ////
+;//// FITNESS FOR A PARTICULAR PURPOSE. ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+
+ list p=16c57
+ #include p16c5x.inc
+
+; global Registers
+r0 equ 0x8
+r1 equ 0x9
+r2 equ 0xa
+r3 equ 0xb
+r4 equ 0xc
+r5 equ 0xd
+r6 equ 0xe
+r7 equ 0xf
+
+; banked Registers
+br0 equ 0x10
+br1 equ 0x11
+br2 equ 0x12
+br3 equ 0x13
+br4 equ 0x14
+br5 equ 0x15
+br6 equ 0x16
+br7 equ 0x17
+br8 equ 0x18
+br9 equ 0x19
+br10 equ 0x1a
+br11 equ 0x1b
+br12 equ 0x1c
+br13 equ 0x1d
+br14 equ 0x1e
+br15 equ 0x1f
+
+
+; PORTB Indicates Test Number
+; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error
+
+main ; Main code entry
+ ; Port IO Test
+ ; All ports have a Pull up resistor
+
+ ; SETUP all ports
+ clrw
+ movwf FSR
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+ bsf STATUS,5
+
+ ; ---------------------------------------
+ ; ---- Test the entire register file ----
+ ; ---------------------------------------
+
+ movlw 0x81
+ movwf r0
+ movlw 0x82
+ movwf r1
+ movlw 0x83
+ movwf r2
+ movlw 0x84
+ movwf r3
+ movlw 0x85
+ movwf r4
+ movlw 0x86
+ movwf r5
+ movlw 0x87
+ movwf r6
+ movlw 0x88
+ movwf r7
+
+
+ movlw 0x90
+ movwf br0
+ movlw 0x91
+ movwf br1
+ movlw 0x92
+ movwf br2
+ movlw 0x93
+ movwf br3
+ movlw 0x94
+ movwf br4
+ movlw 0x95
+ movwf br5
+ movlw 0x96
+ movwf br6
+ movlw 0x97
+ movwf br7
+ movlw 0x98
+ movwf br8
+ movlw 0x99
+ movwf br9
+ movlw 0x9a
+ movwf br10
+ movlw 0x9b
+ movwf br11
+ movlw 0x9c
+ movwf br12
+ movlw 0x9d
+ movwf br13
+ movlw 0x9e
+ movwf br14
+ movlw 0x9f
+ movwf br15
+
+ bsf FSR,5 ; Select Register Bank 01
+
+ movlw 0xa0
+ movwf br0
+ movlw 0xa1
+ movwf br1
+ movlw 0xa2
+ movwf br2
+ movlw 0xa3
+ movwf br3
+ movlw 0xa4
+ movwf br4
+ movlw 0xa5
+ movwf br5
+ movlw 0xa6
+ movwf br6
+ movlw 0xa7
+ movwf br7
+ movlw 0xa8
+ movwf br8
+ movlw 0xa9
+ movwf br9
+ movlw 0xaa
+ movwf br10
+ movlw 0xab
+ movwf br11
+ movlw 0xac
+ movwf br12
+ movlw 0xad
+ movwf br13
+ movlw 0xae
+ movwf br14
+ movlw 0xaf
+ movwf br15
+
+ bcf FSR,5 ; Select Register Bank 10
+ bsf FSR,6
+
+ movlw 0xb0
+ movwf br0
+ movlw 0xb1
+ movwf br1
+ movlw 0xb2
+ movwf br2
+ movlw 0xb3
+ movwf br3
+ movlw 0xb4
+ movwf br4
+ movlw 0xb5
+ movwf br5
+ movlw 0xb6
+ movwf br6
+ movlw 0xb7
+ movwf br7
+ movlw 0xb8
+ movwf br8
+ movlw 0xb9
+ movwf br9
+ movlw 0xba
+ movwf br10
+ movlw 0xbb
+ movwf br11
+ movlw 0xbc
+ movwf br12
+ movlw 0xbd
+ movwf br13
+ movlw 0xbe
+ movwf br14
+ movlw 0xbf
+ movwf br15
+
+ bsf FSR,5 ; Select Register Bank 11
+ bsf FSR,6
+
+ movlw 0xc0
+ movwf br0
+ movlw 0xc1
+ movwf br1
+ movlw 0xc2
+ movwf br2
+ movlw 0xc3
+ movwf br3
+ movlw 0xc4
+ movwf br4
+ movlw 0xc5
+ movwf br5
+ movlw 0xc6
+ movwf br6
+ movlw 0xc7
+ movwf br7
+ movlw 0xc8
+ movwf br8
+ movlw 0xc9
+ movwf br9
+ movlw 0xca
+ movwf br10
+ movlw 0xcb
+ movwf br11
+ movlw 0xcc
+ movwf br12
+ movlw 0xcd
+ movwf br13
+ movlw 0xce
+ movwf br14
+ movlw 0xcf
+ movwf br15
+
+ ; Register File TEST 1
+ movlw 0x01
+ movwf PORTB ; Set Test Number
+
+ clrw
+ movwf FSR
+
+ movlw 0x81
+ subwf r0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x82
+ subwf r1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x83
+ subwf r2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x84
+ subwf r3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x85
+ subwf r4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x86
+ subwf r5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x87
+ subwf r6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x88
+ subwf r7,W
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x90
+ subwf br0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x91
+ subwf br1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x92
+ subwf br2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x93
+ subwf br3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x94
+ subwf br4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x95
+ subwf br5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x96
+ subwf br6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x97
+ subwf br7,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x98
+ subwf br8,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x99
+ subwf br9,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9a
+ subwf br10,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9b
+ subwf br11,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9c
+ subwf br12,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9d
+ subwf br13,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9e
+ subwf br14,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x9f
+ subwf br15,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; Register File TEST 2
+ movlw 0x02
+ movwf PORTB ; Set Test Number
+
+ bsf FSR,5 ; Select Register Bank 01
+
+ movlw 0x81
+ subwf r0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x82
+ subwf r1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x83
+ subwf r2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x84
+ subwf r3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x85
+ subwf r4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x86
+ subwf r5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x87
+ subwf r6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x88
+ subwf r7,W
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0xa0
+ subwf br0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa1
+ subwf br1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa2
+ subwf br2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa3
+ subwf br3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa4
+ subwf br4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa5
+ subwf br5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa6
+ subwf br6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa7
+ subwf br7,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa8
+ subwf br8,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xa9
+ subwf br9,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xaa
+ subwf br10,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xab
+ subwf br11,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xac
+ subwf br12,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xad
+ subwf br13,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xae
+ subwf br14,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xaf
+ subwf br15,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; Register File TEST 3
+ movlw 0x03
+ movwf PORTB ; Set Test Number
+
+ bcf FSR,5 ; Select Register Bank 10
+ bsf FSR,6
+
+ movlw 0x81
+ subwf r0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x82
+ subwf r1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x83
+ subwf r2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x84
+ subwf r3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x85
+ subwf r4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x86
+ subwf r5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x87
+ subwf r6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x88
+ subwf r7,W
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0xb0
+ subwf br0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb1
+ subwf br1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb2
+ subwf br2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb3
+ subwf br3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb4
+ subwf br4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb5
+ subwf br5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb6
+ subwf br6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb7
+ subwf br7,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb8
+ subwf br8,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xb9
+ subwf br9,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xba
+ subwf br10,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xbb
+ subwf br11,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xbc
+ subwf br12,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xbd
+ subwf br13,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xbe
+ subwf br14,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xbf
+ subwf br15,W
+ btfss STATUS,Z
+ goto lerr
+
+
+ ; Register File TEST 4
+ movlw 0x04
+ movwf PORTB ; Set Test Number
+
+ bsf FSR,5 ; Select Register Bank 11
+ bsf FSR,6
+
+ movlw 0x81
+ subwf r0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x82
+ subwf r1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x83
+ subwf r2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x84
+ subwf r3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x85
+ subwf r4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x86
+ subwf r5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x87
+ subwf r6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x88
+ subwf r7,W
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0xc0
+ subwf br0,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc1
+ subwf br1,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc2
+ subwf br2,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc3
+ subwf br3,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc4
+ subwf br4,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc5
+ subwf br5,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc6
+ subwf br6,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc7
+ subwf br7,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc8
+ subwf br8,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xc9
+ subwf br9,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xca
+ subwf br10,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xcb
+ subwf br11,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xcc
+ subwf br12,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xcd
+ subwf br13,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xce
+ subwf br14,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0xcf
+ subwf br15,W
+ btfss STATUS,Z
+ goto lerr
+
+
+ nop
+ nop
+ nop
+ nop
+ movlw 0x01
+ movwf PORTA
+ nop
+ nop
+ nop
+ nop
+good ; Loop in good on success
+ goto good
+ nop
+ nop
+ nop
+ nop
+
+lerr
+ movlw 0xff
+ movwf PORTA
+
+ nop
+ nop
+ nop
+ nop
+lerr_loop ; Loop in lerr on failure
+ goto lerr_loop
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/rf1/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/rf1/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/rf1/Makefile (revision 6)
@@ -0,0 +1,4 @@
+include ../../bin/Makefile.root
+code=rf1
+all: asm_pic
+
trunk/projects/pic_micro/sw/rf1/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/sanity1/sanity1.asm
===================================================================
--- trunk/projects/pic_micro/sw/sanity1/sanity1.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/sanity1/sanity1.asm (revision 6)
@@ -0,0 +1,250 @@
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Mini-RISC-1 ////
+;//// Compliance Test 1 ////
+;//// Tests Ports ////
+;//// ////
+;//// Author: Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Copyright (C) 2000 Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;//// This source file may be used and distributed without ////
+;//// restriction provided that this copyright statement is not ////
+;//// removed from the file and that any derivative work contains ////
+;//// the original copyright notice and the associated disclaimer.////
+;//// ////
+;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY ////
+;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT ////
+;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND ////
+;//// FITNESS FOR A PARTICULAR PURPOSE. ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+
+ list p=16c57
+ #include p16c5x.inc
+
+
+main ; Main code entry
+ ; Port IO Test
+ ; All ports have a Pull up resistor
+
+ ; Tristate all ports
+ clrw
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+ xorlw 0xff
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+ ; Now check that porta is 0xff
+ btfss PORTA,0
+ goto lerr
+ btfss PORTA,1
+ goto lerr
+ btfss PORTA,2
+ goto lerr
+ btfss PORTA,3
+ goto lerr
+ btfss PORTA,4
+ goto lerr
+ btfss PORTA,5
+ goto lerr
+ btfss PORTA,6
+ goto lerr
+ btfss PORTA,7
+ goto lerr
+
+
+ ; Now check that portb is 0xff
+ btfss PORTB,0
+ goto lerr
+ btfss PORTB,1
+ goto lerr
+ btfss PORTB,2
+ goto lerr
+ btfss PORTB,3
+ goto lerr
+ btfss PORTB,4
+ goto lerr
+ btfss PORTB,5
+ goto lerr
+ btfss PORTB,6
+ goto lerr
+ btfss PORTB,7
+ goto lerr
+
+ ; Now check that portc is 0xff
+ btfss PORTC,0
+ goto lerr
+ btfss PORTC,1
+ goto lerr
+ btfss PORTC,2
+ goto lerr
+ btfss PORTC,3
+ goto lerr
+ btfss PORTC,4
+ goto lerr
+ btfss PORTC,5
+ goto lerr
+ btfss PORTA,6
+ goto lerr
+ btfss PORTC,7
+ goto lerr
+
+
+
+ ; Enable all ports
+ clrw
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+ ; Drive them all 0xaa
+ clrw
+ xorlw 0xaa
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+
+ ; Now check that porta is 0xaa
+ btfsc PORTA,0
+ goto lerr
+ btfss PORTA,1
+ goto lerr
+ btfsc PORTA,2
+ goto lerr
+ btfss PORTA,3
+ goto lerr
+ btfsc PORTA,4
+ goto lerr
+ btfss PORTA,5
+ goto lerr
+ btfsc PORTA,6
+ goto lerr
+ btfss PORTA,7
+ goto lerr
+
+ ; Now check that portb is 0xaa
+ btfsc PORTB,0
+ goto lerr
+ btfss PORTB,1
+ goto lerr
+ btfsc PORTB,2
+ goto lerr
+ btfss PORTB,3
+ goto lerr
+ btfsc PORTB,4
+ goto lerr
+ btfss PORTB,5
+ goto lerr
+ btfsc PORTB,6
+ goto lerr
+ btfss PORTB,7
+ goto lerr
+
+ ; Now check that portc is 0xaa
+ btfsc PORTC,0
+ goto lerr
+ btfss PORTC,1
+ goto lerr
+ btfsc PORTC,2
+ goto lerr
+ btfss PORTC,3
+ goto lerr
+ btfsc PORTC,4
+ goto lerr
+ btfss PORTC,5
+ goto lerr
+ btfsc PORTC,6
+ goto lerr
+ btfss PORTC,7
+ goto lerr
+
+ ; Drive them all 0x55
+ clrw
+ xorlw 0x55
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+
+ ; Now check that porta is 0x55
+ btfss PORTA,0
+ goto lerr
+ btfsc PORTA,1
+ goto lerr
+ btfss PORTA,2
+ goto lerr
+ btfsc PORTA,3
+ goto lerr
+ btfss PORTA,4
+ goto lerr
+ btfsc PORTA,5
+ goto lerr
+ btfss PORTA,6
+ goto lerr
+ btfsc PORTA,7
+ goto lerr
+
+ ; Now check that portb is 0x55
+ btfss PORTB,0
+ goto lerr
+ btfsc PORTB,1
+ goto lerr
+ btfss PORTB,2
+ goto lerr
+ btfsc PORTB,3
+ goto lerr
+ btfss PORTB,4
+ goto lerr
+ btfsc PORTB,5
+ goto lerr
+ btfss PORTB,6
+ goto lerr
+ btfsc PORTB,7
+ goto lerr
+
+ ; Now check that portc is 0x55
+ btfss PORTC,0
+ goto lerr
+ btfsc PORTC,1
+ goto lerr
+ btfss PORTC,2
+ goto lerr
+ btfsc PORTC,3
+ goto lerr
+ btfss PORTC,4
+ goto lerr
+ btfsc PORTC,5
+ goto lerr
+ btfss PORTC,6
+ goto lerr
+ btfsc PORTC,7
+ goto lerr
+
+ nop
+ nop
+ nop
+ nop
+
+good ; Loop in good on success
+ goto good
+ nop
+ nop
+ nop
+ nop
+
+lerr ; Loop in lerr on failure
+ goto lerr
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/sanity1/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/sanity1/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/sanity1/Makefile (revision 6)
@@ -0,0 +1,3 @@
+include ../../bin/Makefile.root
+code=sanity1
+all: asm_pic
trunk/projects/pic_micro/sw/sanity1/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/loop/loop.asm
===================================================================
--- trunk/projects/pic_micro/sw/loop/loop.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/loop/loop.asm (revision 6)
@@ -0,0 +1,106 @@
+;/**********************************************************************/
+;/* */
+;/* ------- */
+;/* / SOC \ */
+;/* / GEN \ */
+;/* / FIRMWARE \ */
+;/* ============== */
+;/* | | */
+;/* |____________| */
+;/* */
+;/* Simple loop for outputing data on porta */
+;/* */
+;/* */
+;/* Author(s): */
+;/* - John Eaton, jt_eaton@opencores.org */
+;/* */
+;/**********************************************************************/
+;/* */
+;/* Copyright (C) <2010> */
+;/* */
+;/* This source file may be used and distributed without */
+;/* restriction provided that this copyright statement is not */
+;/* removed from the file and that any derivative work contains */
+;/* the original copyright notice and the associated disclaimer. */
+;/* */
+;/* This source file is free software; you can redistribute it */
+;/* and/or modify it under the terms of the GNU Lesser General */
+;/* Public License as published by the Free Software Foundation; */
+;/* either version 2.1 of the License, or (at your option) any */
+;/* later version. */
+;/* */
+;/* This source is distributed in the hope that it will be */
+;/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+;/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+;/* PURPOSE. See the GNU Lesser General Public License for more */
+;/* details. */
+;/* */
+;/* You should have received a copy of the GNU Lesser General */
+;/* Public License along with this source; if not, download it */
+;/* from http://www.opencores.org/lgpl.shtml */
+;/* */
+;/**********************************************************************/
+
+
+
+
+
+ list p=16c57
+ #include p16c5x.inc
+
+
+main ; Main code entry
+
+ clrw
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+
+
+ ; Drive
+ clrw
+ xorlw 0x03
+ movwf PORTA
+
+
+ ; Drive
+ clrw
+ xorlw 0xf3
+ movwf PORTA
+
+
+ ; Drive
+ clrw
+ xorlw 0x03
+ movwf PORTA
+
+
+
+ ; Drive
+ clrw
+ xorlw 0xf3
+ movwf PORTA
+
+
+ ; Drive
+ clrw
+ xorlw 0x03
+ movwf PORTA
+
+
+ ; Drive
+ clrw
+ xorlw 0xf3
+ movwf PORTA
+
+
+
+ ; loop forever
+ goto main
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/loop/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/loop/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/loop/Makefile (revision 6)
@@ -0,0 +1,6 @@
+include ../../bin/Makefile.root
+code=loop
+
+all: asm_pic
+
+
trunk/projects/pic_micro/sw/loop/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/rf2/rf2.asm
===================================================================
--- trunk/projects/pic_micro/sw/rf2/rf2.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/rf2/rf2.asm (revision 6)
@@ -0,0 +1,827 @@
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Mini-RISC-1 ////
+;//// Register File Test 2 ////
+;//// Tests Register File ////
+;//// ////
+;//// Author: Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Copyright (C) 2000 Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;//// This source file may be used and distributed without ////
+;//// restriction provided that this copyright statement is not ////
+;//// removed from the file and that any derivative work contains ////
+;//// the original copyright notice and the associated disclaimer.////
+;//// ////
+;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY ////
+;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT ////
+;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND ////
+;//// FITNESS FOR A PARTICULAR PURPOSE. ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+
+ list p=16c57
+ #include p16c5x.inc
+
+; global Registers
+r0 equ 0x8
+r1 equ 0x9
+r2 equ 0xa
+r3 equ 0xb
+r4 equ 0xc
+r5 equ 0xd
+r6 equ 0xe
+r7 equ 0xf
+
+; banked Registers
+br0 equ 0x10
+br1 equ 0x11
+br2 equ 0x12
+br3 equ 0x13
+br4 equ 0x14
+br5 equ 0x15
+br6 equ 0x16
+br7 equ 0x17
+br8 equ 0x18
+br9 equ 0x19
+br10 equ 0x1a
+br11 equ 0x1b
+br12 equ 0x1c
+br13 equ 0x1d
+br14 equ 0x1e
+br15 equ 0x1f
+
+
+; PORTB Indicates Test Number
+; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error
+
+main ; Main code entry
+ ; Port IO Test
+ ; All ports have a Pull up resistor
+
+ ; SETUP all ports
+ clrw
+ movwf FSR
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+ bsf STATUS,5
+
+ ; ---------------------------------------
+ ; ---- Test the entire register file ----
+ ; ---------------------------------------
+
+ movlw 0x81
+ movwf r0
+ movlw 0x82
+ movwf r1
+ movlw 0x83
+ movwf r2
+ movlw 0x84
+ movwf r3
+ movlw 0x85
+ movwf r4
+ movlw 0x86
+ movwf r5
+ movlw 0x87
+ movwf r6
+ movlw 0x88
+ movwf r7
+
+
+ movlw 0x90
+ movwf br0
+ movlw 0x91
+ movwf br1
+ movlw 0x92
+ movwf br2
+ movlw 0x93
+ movwf br3
+ movlw 0x94
+ movwf br4
+ movlw 0x95
+ movwf br5
+ movlw 0x96
+ movwf br6
+ movlw 0x97
+ movwf br7
+ movlw 0x98
+ movwf br8
+ movlw 0x99
+ movwf br9
+ movlw 0x9a
+ movwf br10
+ movlw 0x9b
+ movwf br11
+ movlw 0x9c
+ movwf br12
+ movlw 0x9d
+ movwf br13
+ movlw 0x9e
+ movwf br14
+ movlw 0x9f
+ movwf br15
+
+ bsf FSR,5 ; Select Register Bank 01
+
+ movlw 0xa0
+ movwf br0
+ movlw 0xa1
+ movwf br1
+ movlw 0xa2
+ movwf br2
+ movlw 0xa3
+ movwf br3
+ movlw 0xa4
+ movwf br4
+ movlw 0xa5
+ movwf br5
+ movlw 0xa6
+ movwf br6
+ movlw 0xa7
+ movwf br7
+ movlw 0xa8
+ movwf br8
+ movlw 0xa9
+ movwf br9
+ movlw 0xaa
+ movwf br10
+ movlw 0xab
+ movwf br11
+ movlw 0xac
+ movwf br12
+ movlw 0xad
+ movwf br13
+ movlw 0xae
+ movwf br14
+ movlw 0xaf
+ movwf br15
+
+ bcf FSR,5 ; Select Register Bank 10
+ bsf FSR,6
+
+ movlw 0xb0
+ movwf br0
+ movlw 0xb1
+ movwf br1
+ movlw 0xb2
+ movwf br2
+ movlw 0xb3
+ movwf br3
+ movlw 0xb4
+ movwf br4
+ movlw 0xb5
+ movwf br5
+ movlw 0xb6
+ movwf br6
+ movlw 0xb7
+ movwf br7
+ movlw 0xb8
+ movwf br8
+ movlw 0xb9
+ movwf br9
+ movlw 0xba
+ movwf br10
+ movlw 0xbb
+ movwf br11
+ movlw 0xbc
+ movwf br12
+ movlw 0xbd
+ movwf br13
+ movlw 0xbe
+ movwf br14
+ movlw 0xbf
+ movwf br15
+
+ bsf FSR,5 ; Select Register Bank 11
+ bsf FSR,6
+
+ movlw 0xc0
+ movwf br0
+ movlw 0xc1
+ movwf br1
+ movlw 0xc2
+ movwf br2
+ movlw 0xc3
+ movwf br3
+ movlw 0xc4
+ movwf br4
+ movlw 0xc5
+ movwf br5
+ movlw 0xc6
+ movwf br6
+ movlw 0xc7
+ movwf br7
+ movlw 0xc8
+ movwf br8
+ movlw 0xc9
+ movwf br9
+ movlw 0xca
+ movwf br10
+ movlw 0xcb
+ movwf br11
+ movlw 0xcc
+ movwf br12
+ movlw 0xcd
+ movwf br13
+ movlw 0xce
+ movwf br14
+ movlw 0xcf
+ movwf br15
+
+ movlw r0
+ movwf FSR
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+
+
+ movlw br0
+ movwf FSR
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+
+ movlw br0
+ movwf FSR
+ bsf FSR,5
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+
+ movlw br0
+ movwf FSR
+ bsf FSR,6
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+
+ movlw br0
+ movwf FSR
+ bsf FSR,5
+ bsf FSR,6
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+ comf INDF,F
+ incf FSR,F
+
+ ; Register File TEST 1
+ movlw 0x01
+ movwf PORTB ; Set Test Number
+
+ movlw r0
+ movwf FSR
+ movlw 0x7e
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x7d
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x7c
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x7b
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x7a
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x79
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x78
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x77
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+
+ movlw br0
+ movwf FSR
+ movlw 0x6f
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x6e
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x6d
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x6c
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x6b
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x6a
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x69
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x68
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x67
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x66
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x65
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x64
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x63
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x62
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x61
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x60
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; Register File TEST 2
+ movlw 0x02
+ movwf PORTB ; Set Test Number
+
+ movlw br0
+ movwf FSR
+ bsf FSR,5
+ movlw 0x5f
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x5e
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x5d
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x5c
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x5b
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x5a
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x59
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x58
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x57
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x56
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x55
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x54
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x53
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x52
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x51
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x50
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; Register File TEST 3
+ movlw 0x03
+ movwf PORTB ; Set Test Number
+
+ movlw br0
+ movwf FSR
+ bsf FSR,6
+ movlw 0x4f
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x4e
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x4d
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x4c
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x4b
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x4a
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x49
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x48
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x47
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x46
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x45
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x44
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x43
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x42
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x41
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x40
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; Register File TEST 4
+ movlw 0x04
+ movwf PORTB ; Set Test Number
+
+ movlw br0
+ movwf FSR
+ bsf FSR,5
+ bsf FSR,6
+ movlw 0x3f
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x3e
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x3d
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x3c
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x3b
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x3a
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x39
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x38
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x37
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x36
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x35
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x34
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x33
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x32
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x31
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+ movlw 0x30
+ incf FSR,F
+ subwf INDF,W
+ btfss STATUS,Z
+ goto lerr
+
+ nop
+ nop
+ nop
+ nop
+ movlw 0x01
+ movwf PORTA
+ nop
+ nop
+ nop
+ nop
+good ; Loop in good on success
+ goto good
+ nop
+ nop
+ nop
+ nop
+
+lerr
+ movlw 0xff
+ movwf PORTA
+
+ nop
+ nop
+ nop
+ nop
+lerr_loop ; Loop in lerr on failure
+ goto lerr_loop
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/rf2/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/rf2/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/rf2/Makefile (revision 6)
@@ -0,0 +1,5 @@
+include ../../bin/Makefile.root
+code=rf2
+all: asm_pic
+
+
trunk/projects/pic_micro/sw/rf2/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/sanity2/sanity2.asm
===================================================================
--- trunk/projects/pic_micro/sw/sanity2/sanity2.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/sanity2/sanity2.asm (revision 6)
@@ -0,0 +1,457 @@
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Mini-RISC-1 ////
+;//// Compliance Test 2 ////
+;//// Tests PLC register Rd/Wr ////
+;//// ////
+;//// Author: Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Copyright (C) 2000 Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;//// This source file may be used and distributed without ////
+;//// restriction provided that this copyright statement is not ////
+;//// removed from the file and that any derivative work contains ////
+;//// the original copyright notice and the associated disclaimer.////
+;//// ////
+;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY ////
+;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT ////
+;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND ////
+;//// FITNESS FOR A PARTICULAR PURPOSE. ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+
+ list p=16c57
+ #include p16c5x.inc
+
+; global Registers
+r0 equ 0x8
+r1 equ 0x9
+r2 equ 0xa
+r3 equ 0xb
+r4 equ 0xc
+r5 equ 0xd
+r6 equ 0xe
+r7 equ 0xf
+
+; banked Registers
+br0 equ 0x10
+br1 equ 0x11
+br2 equ 0x12
+br3 equ 0x13
+br4 equ 0x14
+br5 equ 0x15
+br6 equ 0x16
+br7 equ 0x17
+br8 equ 0x18
+br9 equ 0x19
+br10 equ 0x1a
+br11 equ 0x1b
+br12 equ 0x1c
+br13 equ 0x1d
+br14 equ 0x1e
+br15 equ 0x1f
+
+
+; PORTB Indicates Test Number
+; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error
+
+main ; Main code entry
+ ; Port IO Test
+ ; All ports have a Pull up resistor
+
+
+ ; SETUP all ports
+ ; Tristate all ports
+ clrw
+ movwf FSR
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+
+ ; -------------------------------
+ ; ---- Test the PLC register ----
+ ; -------------------------------
+
+ ; PLC read test 1 TEST 0
+
+ movlw pclrd1
+ movwf r0
+ movf PCL,W
+pclrd1 subwf r0,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; PLC read test 2 TEST 1
+ movlw 0x01
+ movwf PORTB ; Set Test Number
+
+ movlw pclrd2
+ movwf r3
+ movf PCL,W
+pclrd2 subwf r3,W
+ btfss STATUS,Z
+ goto lerr
+
+ ; PLC write test 2 TEST 2
+ movlw 0x02
+ movwf PORTB ; Set Test Number
+
+ movlw pclwr1
+ movwf PCL
+
+ goto lerr
+ goto lerr
+ goto lerr
+pclwr1 goto pcl1
+ goto lerr
+ goto lerr
+ goto lerr
+
+pcl1
+ ; PLC write test 2 TEST 3
+ movlw 0x03
+ movwf PORTB ; Set Test Number
+
+ movlw pclwr2
+ movwf PCL
+
+ goto lerr
+ goto lerr
+ goto lerr
+pclwr2 goto pcl2
+ goto lerr
+ goto lerr
+ goto lerr
+
+pcl2 ; Test other instructions that modify PC
+ ; This are ADDWF PC, BSF PC,X and BCF PC,X
+ ; (movwf pc already tested above)
+
+ ; PLC write test 3 TEST 4
+ ; test addwf PC
+ movlw 0x04
+ movwf PORTB ; Set Test Number
+
+ movlw pcl3b
+ movwf r0
+ movlw pcl3a
+ subwf r0,W
+pcl3a addwf PCL,1
+
+ goto lerr
+ goto lerr
+pcl3b goto lerr
+ goto pcl3c
+ goto lerr
+ goto lerr
+ goto lerr
+pcl3c
+
+ ; PLC write test 4 TEST 5
+ ; test addwf PC
+ movlw 0x05
+ movwf PORTB ; Set Test Number
+
+ movlw pcl4b
+ movwf br8
+ movlw pcl4a
+ subwf br8,W
+pcl4a addwf PCL,1
+
+ goto lerr
+ goto lerr
+pcl4b goto lerr
+ goto pcl4c
+ goto lerr
+ goto lerr
+ goto lerr
+pcl4c
+
+ ; PLC write test 5 TEST 6
+ ; test bsf PC,N
+ movlw 0x06
+ movwf PORTB ; Set Test N
+
+; allign memory
+ goto pcl50
+
+pcl50 org 0x60
+
+ bsf PCL,1 ; 60
+ goto lerr ; 61
+ goto lerr ; 62
+ goto pcl5a ; 63
+ goto lerr ; 64
+ goto lerr ; 65
+ goto lerr ; 66
+ goto lerr ; 67
+
+pcl5a
+
+ ; PLC write test 6 TEST 7
+ ; test bsf PC,N
+ movlw 0x07
+ movwf PORTB ; Set Test N
+
+ bsf PCL,2 ; 6A
+ goto lerr ; 6B
+ goto lerr ; 6C
+ goto lerr ; 6D
+ goto lerr ; 6E
+ goto pcl6a ; 6F
+ goto lerr ; 70
+ goto lerr ; 71
+
+pcl6a
+
+ ; PLC write test 7 TEST 8
+ ; test bcf PC,N
+ movlw 0x08
+ movwf PORTB ; Set Test N
+
+ goto pcl7a ; 74
+ goto lerr ; 75
+ goto lerr ; 76
+ goto lerr ; 77
+ goto lerr ; 78
+ goto pcl7b ; 79
+ goto lerr ; 7a
+ goto lerr ; 7b
+
+pcl7a
+ bcf PCL,2 ; 7c
+
+pcl7b
+
+
+ ; Make sure goto works
+ movlw 0x09 ; TEST 9
+ movwf PORTB ; Set Test Number
+
+
+ goto gt1
+ nop
+ nop
+ nop
+ nop
+ movlw 0xff
+ movwf PORTA
+ nop
+ nop
+ nop
+ nop
+gt1
+
+ ; Make sure call works
+ movlw 0x0a ; TEST 10
+ movwf PORTB ; Set Test Number
+
+ call cal1
+ movwf r0
+ movlw 0x55
+ subwf r0,w
+ btfss STATUS,Z
+ goto lerr
+
+ call cal2
+ movwf r0
+ movlw 0xaa
+ subwf r0,w
+ btfss STATUS,Z
+ goto lerr
+
+ call cal3
+ movwf r0
+ movlw 0xc3
+ subwf r0,w
+ btfss STATUS,Z
+ goto lerr
+
+ call cal4
+ movwf r0
+ movlw 0x3c
+ subwf r0,w
+ btfss STATUS,Z
+ goto lerr
+
+ goto next1
+
+cal1
+ retlw 0x55
+ goto lerr
+
+cal2
+ nop
+ retlw 0xaa
+ goto lerr
+
+cal3
+ nop
+ nop
+ retlw 0xc3
+ goto lerr
+
+cal4
+ nop
+ nop
+ nop
+ retlw 0x3c
+ goto lerr
+
+table1
+ addwf PCL,F
+ retlw 0xff
+ retlw 0xfe
+ retlw 0xfd
+ retlw 0xfc
+ retlw 0xfb
+ retlw 0xfa
+ retlw 0xf9
+ retlw 0xf8
+ retlw 0xf7
+ retlw 0xf6
+ retlw 0xf5
+ goto lerr
+ goto lerr
+ goto lerr
+ goto lerr
+ goto lerr
+ goto lerr
+
+next1
+
+
+ ; Make sure call works (2)
+ movlw 0x0b ; TEST 11
+ movwf PORTB ; Set Test Number
+
+ movlw 0x0
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x1
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x2
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x3
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x4
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x5
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x6
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x7
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x8
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x9
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0xa
+ movwf r0
+ call table1
+ comf r0,F
+ subwf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ nop
+ nop
+ nop
+ nop
+ movlw 0x01
+ movwf PORTA
+ nop
+ nop
+ nop
+ nop
+good ; Loop in good on success
+ goto good
+ nop
+ nop
+ nop
+ nop
+
+lerr
+ movlw 0xff
+ movwf PORTA
+
+ nop
+ nop
+ nop
+ nop
+lerr_loop ; Loop in lerr on failure
+ goto lerr_loop
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/sanity2/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/sanity2/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/sanity2/Makefile (revision 6)
@@ -0,0 +1,6 @@
+include ../../bin/Makefile.root
+code=sanity2
+
+all:asm_pic
+
+
trunk/projects/pic_micro/sw/sanity2/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/pic_micro/sw/rf3/rf3.asm
===================================================================
--- trunk/projects/pic_micro/sw/rf3/rf3.asm (nonexistent)
+++ trunk/projects/pic_micro/sw/rf3/rf3.asm (revision 6)
@@ -0,0 +1,338 @@
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Mini-RISC-1 ////
+;//// Register File Test 3 ////
+;//// Tests Register File ////
+;//// ////
+;//// Author: Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+;//// ////
+;//// Copyright (C) 2000 Rudolf Usselmann ////
+;//// russelmann@hotmail.com ////
+;//// ////
+;//// This source file may be used and distributed without ////
+;//// restriction provided that this copyright statement is not ////
+;//// removed from the file and that any derivative work contains ////
+;//// the original copyright notice and the associated disclaimer.////
+;//// ////
+;//// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY ////
+;//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT ////
+;//// LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND ////
+;//// FITNESS FOR A PARTICULAR PURPOSE. ////
+;//// ////
+;/////////////////////////////////////////////////////////////////////
+
+ list p=16c57
+ #include p16c5x.inc
+
+; global Registers
+r0 equ 0x8
+r1 equ 0x9
+r2 equ 0xa
+r3 equ 0xb
+r4 equ 0xc
+r5 equ 0xd
+r6 equ 0xe
+r7 equ 0xf
+
+; banked Registers
+br0 equ 0x10
+br1 equ 0x11
+br2 equ 0x12
+br3 equ 0x13
+br4 equ 0x14
+br5 equ 0x15
+br6 equ 0x16
+br7 equ 0x17
+br8 equ 0x18
+br9 equ 0x19
+br10 equ 0x1a
+br11 equ 0x1b
+br12 equ 0x1c
+br13 equ 0x1d
+br14 equ 0x1e
+br15 equ 0x1f
+
+
+; PORTB Indicates Test Number
+; PORTA Indicates Status: 0 - Running; 1 - done OK; ff - stoped on error
+
+main ; Main code entry
+ ; Port IO Test
+ ; All ports have a Pull up resistor
+
+ ; SETUP all ports
+ clrw
+ movwf FSR
+ movwf PORTA
+ movwf PORTB
+ movwf PORTC
+ tris PORTA
+ tris PORTB
+ tris PORTC
+
+ ; ---------------------------------------
+ ; ---- Test RMW on Register fil ----
+ ; ---------------------------------------
+
+ movlw 0x01 ; TEST 1
+ movwf PORTB ; Set Test Number
+
+ movlw 0xfc
+ movwf r0
+ incf r0,F
+ incf r0,F
+ incf r0,F
+ incf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0xfc
+ movwf br8
+ incf br8,F
+ incf br8,F
+ incf br8,F
+ incf br8,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x02 ; TEST 2
+ movwf PORTB ; Set Test Number
+
+ movlw r1
+ movwf FSR
+ movlw 0xfc
+ movwf INDF
+ incf INDF,F
+ incf INDF,F
+ incf INDF,F
+ incf INDF,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw br9
+ movwf FSR
+ movlw 0xfc
+ movwf INDF
+ incf INDF,F
+ incf INDF,F
+ incf INDF,F
+ incf INDF,F
+ btfss STATUS,Z
+ goto lerr
+
+
+
+ movlw 0x03 ; TEST 3
+ movwf PORTB ; Set Test Number
+
+ movlw 0x04
+ movwf r0
+ decf r0,F
+ decf r0,F
+ decf r0,F
+ decf r0,F
+ btfss STATUS,Z
+ goto lerr
+
+
+ movlw 0x04
+ movwf br0
+ decf br0,F
+ decf br0,F
+ decf br0,F
+ decf br0,F
+ btfss STATUS,Z
+ goto lerr
+
+
+ movlw 0x04 ; TEST 4
+ movwf PORTB ; Set Test Number
+
+ movlw r1
+ movwf FSR
+ movlw 0x04
+ movwf INDF
+ decf INDF,F
+ decf INDF,F
+ decf INDF,F
+ decf INDF,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw br9
+ movwf FSR
+ movlw 0x04
+ movwf INDF
+ decf INDF,F
+ decf INDF,F
+ decf INDF,F
+ decf INDF,F
+ btfss STATUS,Z
+ goto lerr
+
+
+ movlw 0x05 ; TEST 5
+ movwf PORTB ; Set Test Number
+
+ movlw 0xfc
+ movwf r4
+ incfsz r4,F
+ incfsz r4,F
+ incfsz r4,F
+ incfsz r4,F
+ goto lerr
+
+ movlw 0xfc
+ movwf br8
+ incfsz br8,F
+ incfsz br8,F
+ incfsz br8,F
+ incfsz br8,F
+ goto lerr
+
+
+ movlw 0x06 ; TEST 6
+ movwf PORTB ; Set Test Number
+
+ movlw r1
+ movwf FSR
+ movlw 0xfc
+ movwf INDF
+ incfsz INDF,F
+ incfsz INDF,F
+ incfsz INDF,F
+ incfsz INDF,F
+ goto lerr
+
+ movlw br9
+ movwf FSR
+ movlw 0xfc
+ movwf INDF
+ incfsz INDF,F
+ incfsz INDF,F
+ incfsz INDF,F
+ incfsz INDF,F
+ goto lerr
+
+ movlw 0x07 ; TEST 7
+ movwf PORTB ; Set Test Number
+
+ movlw 0x04
+ movwf r0
+ decfsz r0,F
+ decfsz r0,F
+ decfsz r0,F
+ decfsz r0,F
+ goto lerr
+
+
+ movlw 0x04
+ movwf br0
+ decfsz br0,F
+ decfsz br0,F
+ decfsz br0,F
+ decfsz br0,F
+ goto lerr
+
+
+ movlw 0x08 ; TEST 8
+ movwf PORTB ; Set Test Number
+
+ movlw r1
+ movwf FSR
+ movlw 0x04
+ movwf INDF
+ decfsz INDF,F
+ decfsz INDF,F
+ decfsz INDF,F
+ decfsz INDF,F
+ goto lerr
+
+ movlw br9
+ movwf FSR
+ movlw 0x04
+ movwf INDF
+ decfsz INDF,F
+ decfsz INDF,F
+ decfsz INDF,F
+ decfsz INDF,F
+ goto lerr
+
+
+ movlw 0x09 ; TEST 9
+ movwf PORTB ; Set Test Number
+
+ movlw 0xfc
+ movwf FSR
+ incf FSR,F
+ incf FSR,F
+ incf FSR,F
+ incf FSR,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x04
+ movwf FSR
+ movlw 0x7f
+ decf FSR,F
+ decf FSR,F
+ decf FSR,F
+ decf FSR,F
+ andwf FSR,F
+ btfss STATUS,Z
+ goto lerr
+
+ movlw 0x0a ; TEST 10
+ movwf PORTB ; Set Test Number
+
+ movlw 0xfc
+ movwf STATUS
+ movlw 0x18
+ incf STATUS,F
+ incf STATUS,F
+ incf STATUS,F
+ incf STATUS,F
+ subwf STATUS,W
+ btfss STATUS,Z
+ goto lerr
+
+
+
+
+ nop
+ nop
+ nop
+ nop
+ movlw 0x01
+ movwf PORTA
+ nop
+ nop
+ nop
+ nop
+good ; Loop in good on success
+ goto good
+ nop
+ nop
+ nop
+ nop
+
+lerr
+ movlw 0xff
+ movwf PORTA
+
+ nop
+ nop
+ nop
+ nop
+lerr_loop ; Loop in lerr on failure
+ goto lerr_loop
+ nop
+ nop
+ nop
+ nop
+
+ END
+
Index: trunk/projects/pic_micro/sw/rf3/Makefile
===================================================================
--- trunk/projects/pic_micro/sw/rf3/Makefile (nonexistent)
+++ trunk/projects/pic_micro/sw/rf3/Makefile (revision 6)
@@ -0,0 +1,7 @@
+include ../../bin/Makefile.root
+code=rf3
+
+all: asm_pic
+
+
+
trunk/projects/pic_micro/sw/rf3/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/logic/bin/Makefile
===================================================================
--- trunk/projects/logic/bin/Makefile (nonexistent)
+++ trunk/projects/logic/bin/Makefile (revision 6)
@@ -0,0 +1,2 @@
+include ./Makefile.root
+
trunk/projects/logic/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v
===================================================================
--- trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v (nonexistent)
+++ trunk/projects/logic/ip/disp_io/rtl/verilog/disp_io.v (revision 6)
@@ -0,0 +1,160 @@
+
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / COMPONENT \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
+
+
+// display io controller for digilent Basys fpga board
+
+
+
+
+`include "disp_io_defines.v"
+
+module
+`VARIENT
+(
+input wire clk,
+input wire reset,
+input wire one_usec,
+input wire [15:0] PosD, // 16 bit hex to 4 led modules
+input wire [7:0] PosL, // 8 individual leds
+
+output reg [3:0] PosB, // 4 button inputs
+output reg [7:0] PosS, // 8 switch inputs
+
+input wire [3:0] btn_pad_in,
+input wire [7:0] sw_pad_in,
+
+
+output reg [7:0] led_pad_out,
+output reg [6:0] seg_pad_out,
+output reg dp_pad_out,
+output reg [3:0] an_pad_out
+ );
+
+
+
+reg [3:0] divide;
+reg [3:0] number;
+
+
+
+always@(*) led_pad_out = PosL;
+always@(*) PosS = sw_pad_in;
+always@(*) PosB = btn_pad_in;
+
+
+
+
+always@(posedge clk)
+ if(reset) divide <= 4'b0000;
+ else
+ if(one_usec) divide <= divide+4'b0001;
+ else divide <= divide;
+
+always@(posedge clk) dp_pad_out <= 1'b1;
+
+
+
+always@(posedge clk)
+ if(reset) an_pad_out <= 4'b1111;
+ else
+ if(divide[3:0] == 4'b0010) an_pad_out <= 4'b1110;
+ else
+ if(divide[3:0] == 4'b0110) an_pad_out <= 4'b1101;
+ else
+ if(divide[3:0] == 4'b1010) an_pad_out <= 4'b1011;
+ else
+ if(divide[3:0] == 4'b1110) an_pad_out <= 4'b0111;
+ else an_pad_out <= 4'b1111;
+
+
+
+always@(posedge clk)
+ if(divide[3:2] == 2'b00) number <= PosD[3:0];
+ else
+ if(divide[3:2] == 2'b01) number <= PosD[7:4];
+ else
+ if(divide[3:2] == 2'b10) number <= PosD[11:8];
+ else
+ if(divide[3:2] == 2'b11) number <= PosD[15:12];
+ else number <= number;
+
+
+
+always@(posedge clk)
+ if(reset) seg_pad_out <= 7'b1111111;
+ else
+ if(number[3:0] == 4'b0000) seg_pad_out <= 7'b1000000;
+ else
+ if(number[3:0] == 4'b0001) seg_pad_out <= 7'b1111001;
+ else
+ if(number[3:0] == 4'b0010) seg_pad_out <= 7'b0100100;
+ else
+ if(number[3:0] == 4'b0011) seg_pad_out <= 7'b0110000;
+ else
+ if(number[3:0] == 4'b0100) seg_pad_out <= 7'b0011001;
+ else
+ if(number[3:0] == 4'b0101) seg_pad_out <= 7'b0010010;
+ else
+ if(number[3:0] == 4'b0110) seg_pad_out <= 7'b0000010;
+ else
+ if(number[3:0] == 4'b0111) seg_pad_out <= 7'b1111000;
+ else
+ if(number[3:0] == 4'b1000) seg_pad_out <= 7'b0000000;
+ else
+ if(number[3:0] == 4'b1001) seg_pad_out <= 7'b0011000;
+ else
+ if(number[3:0] == 4'b1010) seg_pad_out <= 7'b0001000;
+ else
+ if(number[3:0] == 4'b1011) seg_pad_out <= 7'b0000011;
+ else
+ if(number[3:0] == 4'b1100) seg_pad_out <= 7'b1000110;
+ else
+ if(number[3:0] == 4'b1101) seg_pad_out <= 7'b0100001;
+ else
+ if(number[3:0] == 4'b1110) seg_pad_out <= 7'b0000110;
+ else
+ if(number[3:0] == 4'b1111) seg_pad_out <= 7'b0001110;
+ else seg_pad_out <= 7'b1111111;
+
+
+endmodule
\ No newline at end of file
Index: trunk/projects/logic/ip/disp_io/rtl/varients/disp_io/disp_io_defines.v
===================================================================
--- trunk/projects/logic/ip/disp_io/rtl/varients/disp_io/disp_io_defines.v (nonexistent)
+++ trunk/projects/logic/ip/disp_io/rtl/varients/disp_io/disp_io_defines.v (revision 6)
@@ -0,0 +1,3 @@
+
+`define VARIENT disp_io
+`define CDE cde
\ No newline at end of file
Index: trunk/projects/logic/ip/disp_io/doc/copyright.v
===================================================================
--- trunk/projects/logic/ip/disp_io/doc/copyright.v (nonexistent)
+++ trunk/projects/logic/ip/disp_io/doc/copyright.v (revision 6)
@@ -0,0 +1,51 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / COMPONENT \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* display io interface for Digilent FPGA boards */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
+
+
+`ifndef SYNTHESIS
+
+`include "timescale.v"
+
+`endif
+
+
Index: trunk/projects/logic/ip/disp_io/bin/Makefile
===================================================================
--- trunk/projects/logic/ip/disp_io/bin/Makefile (nonexistent)
+++ trunk/projects/logic/ip/disp_io/bin/Makefile (revision 6)
@@ -0,0 +1,2 @@
+include ../../../bin/Makefile.root
+
trunk/projects/logic/ip/disp_io/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/projects/logic/ip/disp_io/sim/run/default/liblist
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/liblist (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/liblist (revision 6)
@@ -0,0 +1,2 @@
+
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/TB.defs
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/TB.defs (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/TB.defs (revision 6)
@@ -0,0 +1,4 @@
+`include "timescale.v"
+`define TIMEFORMAT $timeformat(-9, 2, " ns", 14);
+`define PERIOD 20.00000
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/test_define
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/test_define (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/test_define (revision 6)
@@ -0,0 +1,56 @@
+initial
+ begin
+ $timeformat(-9, 2, " ns", 14);
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Test Start",$realtime);
+ $display(" ===================================================");
+ $display(" ");
+ one_usec = 1'b1;
+ PosD = 16'b0000000000000000;
+ PosL = 8'b00000000;
+ sw_pad_in = 8'b00000000;
+ btn_pad_in = 4'b0000;
+
+
+
+ cg.next(8);
+ cg.reset_off;
+ cg.next(88);
+ $display("%t Start xmit test ",$realtime );
+
+ cg.next(1000);
+
+ PosD = 16'b1010101010101010;
+ PosL = 8'b10101010;
+ sw_pad_in = 8'b10101010;
+ btn_pad_in = 4'b1010;
+
+ cg.next(1000);
+
+ PosD = 16'b1111111111111111;
+ PosL = 8'b11111111;
+ sw_pad_in = 8'b11111111;
+ btn_pad_in = 4'b1111;
+
+
+
+
+
+
+
+
+ $display(" ");
+ $display(" ===================================================");
+ $display("%t Test PASSED",$realtime);
+ $display(" ===================================================");
+
+ $finish;
+end
+
+
+
+
+
+
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/timescale.v
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/timescale.v (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/timescale.v (revision 6)
@@ -0,0 +1,2 @@
+`timescale 1ns/10ps
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/dmp_define
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/dmp_define (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/dmp_define (revision 6)
@@ -0,0 +1,8 @@
+ $dumpfile ("TestBench.vcd");
+ $dumpvars (0, TB);
+
+
+
+
+
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/filelist
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/filelist (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/filelist (revision 6)
@@ -0,0 +1,3 @@
+
+`include "../../../rtl/gen/sim/disp_io.v"
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/dut
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/dut (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/dut (revision 6)
@@ -0,0 +1,42 @@
+
+
+reg one_usec;
+
+reg [3:0] btn_pad_in;
+reg [7:0] sw_pad_in;
+
+wire [7:0] led;
+wire [6:0] seg;
+wire dp;
+wire [3:0] an;
+
+reg [15:0] PosD;
+reg [7:0] PosL;
+wire [7:0] PosS;
+wire [3:0] PosB;
+
+
+
+
+disp_io
+dut ( .clk (clk),
+ .reset (reset),
+ .one_usec (one_usec),
+ .btn_pad_in (btn_pad_in),
+ .sw_pad_in (sw_pad_in),
+ .PosD (PosD),
+ .PosL (PosL),
+ .PosB (PosB),
+ .PosS (PosS),
+ .led_pad_out (led),
+ .seg_pad_out (seg),
+ .dp_pad_out (dp),
+ .an_pad_out (an)
+ );
+
+
+
+
+
+
+
Index: trunk/projects/logic/ip/disp_io/sim/run/default/modellist
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/run/default/modellist (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/run/default/modellist (revision 6)
@@ -0,0 +1,3 @@
+`include "../../bench/verilog/models/clock_gen.v"
+
+
Index: trunk/projects/logic/ip/disp_io/sim/bin/Makefile
===================================================================
--- trunk/projects/logic/ip/disp_io/sim/bin/Makefile (nonexistent)
+++ trunk/projects/logic/ip/disp_io/sim/bin/Makefile (revision 6)
@@ -0,0 +1,3 @@
+include ../../../../bin/Makefile.root
+
+
trunk/projects/logic/ip/disp_io/sim/bin/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/targets/Basys/xcf02s_vo20.bsd
===================================================================
--- trunk/targets/Basys/xcf02s_vo20.bsd (nonexistent)
+++ trunk/targets/Basys/xcf02s_vo20.bsd (revision 6)
@@ -0,0 +1,226 @@
+--$ XILINX$RCSfile: xcf02s_vo20.bsd,v $
+-- XILINX Revision: 1.4
+-------------------------------------------------------------------------------
+-- Copyright (c) 2006 Xilinx, Inc.
+-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
+-------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: v1.0 (PROM BSDL template version)
+-- \ \ Application: Generate_Prom_Bsdl_Files.pl, 1.00
+-- / / Filename: xcf02s_vo20.bsd
+-- /___/ /\ Generated: Wed Oct 11 19:34:18 2006
+-- \ \ / \ State: State: PRELIMINARY
+-- \___\/\___\
+--
+-- Device: XCF02S
+-- Package(s): VO20, VOG20
+-- Purpose: IEEE 1149.1 BSDL file
+-- Reference: None
+-- Revisions:
+--
+------------------------------------------------------------------------------
+-- Technical Support:
+--
+-- Find the latest version of this BSDL file, find technical support answers,
+-- or find contact information at: http://www.support.xilinx.com
+--
+------------------------------------------------------------------------------
+-- Special Instructions:
+--
+-- This BSDL file reflects the pre-configuration behavior. To reflect
+-- the post-configuration JTAG behavior (if any), edit this file as
+-- described below:
+-- 1. Rename file and entity if necessary to avoid name collisions.
+-- 2. Modify USERCODE value in USERCODE_REGISTER declaration.
+------------------------------------------------------------------------------
+-- BSDL Silicon Validation Information
+-- None.
+------------------------------------------------------------------------------
+entity XCF02S_VO20 is
+
+generic (PHYSICAL_PIN_MAP : string := "VO20");
+
+port (
+ CE: in bit;
+ CEO: out bit;
+ CF: out bit;
+ CLK: in bit;
+ D0: out bit;
+ OE_RESET: inout bit;
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit;
+ GND: linkage bit;
+ VCCINT: linkage bit;
+ VCCJ: linkage bit;
+ VCCO: linkage bit;
+ DNC: linkage bit_vector(1 to 6)
+); --end port list
+
+use STD_1149_1_2001.all;
+
+attribute COMPONENT_CONFORMANCE of XCF02S_VO20 : entity is
+ "STD_1149_1_2001";
+
+attribute PIN_MAP of XCF02S_VO20 : entity is
+ PHYSICAL_PIN_MAP;
+
+constant VO20: PIN_MAP_STRING:=
+ "CE: 10," &
+ "CEO: 13," &
+ "CF: 7," &
+ "CLK: 3," &
+ "D0: 1," &
+ "OE_RESET: 8," &
+ "TCK: 6," &
+ "TDI: 4," &
+ "TDO: 17," &
+ "TMS: 5," &
+ "GND: 11," &
+ "VCCINT: 18," &
+ "VCCJ: 20," &
+ "VCCO: 19," &
+ "DNC: (2, 9, 12, 14, 15, 16)";
+
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_MODE of TMS : signal is true;
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (15.00e+06, BOTH);
+attribute INSTRUCTION_LENGTH of XCF02S_VO20 : entity is
+ 8;
+
+attribute INSTRUCTION_OPCODE of XCF02S_VO20 : entity is
+ -- IEEE 1149.1 standard instructions
+ "BYPASS (11111111)," &
+ "SAMPLE (00000001)," &
+ "PRELOAD (00000001)," &
+ "EXTEST (00000000)," &
+ "IDCODE (11111110)," &
+ "USERCODE (11111101)," &
+ "HIGHZ (11111100)," &
+ "CLAMP (11111010)," &
+ -- Xilinx special function instructions
+ "CONFIG (11101110)," &
+ -- Xilinx ISP instructions
+ "ISPEN (11101000)," &
+ "ISPENC (11101001)," &
+ "NORMRST (11110000)," &
+ "FPGM (11101010)," &
+ "FERASE (11101100)," &
+ "FADDR (11101011)," &
+ "FDATA0 (11101101)," &
+ "FVFY0 (11101111)," &
+ "FDATA3 (11110011)," &
+ "FVFY1 (11111000)," &
+ "FVFY3 (11100010)," &
+ "FVFY6 (11100110)," &
+ "FBLANK0 (11100101)," &
+ "FBLANK3 (11100001)," &
+ "FBLANK6 (11100100)," &
+ "SERASE (00001010)," &
+ "ISC_READ_INFO (11110001)," &
+ "ISCTESTSTATUS (11100011)," &
+ "priv3 (11100111)," &
+ "priv4 (11110110)," &
+ "priv5 (11100000)," &
+ "priv6 (11110111)," &
+ "priv7 (11110010)," &
+ "ISCCLRSTATUS (11110100)," &
+ "priv9 (11110101)";
+
+attribute INSTRUCTION_CAPTURE of XCF02S_VO20: entity is
+ "XXXXX001";
+-- IR[7:6]= Erase/Program Result (10=success; 01=fail; 00/11=N/A)
+-- IR[5] = Erase/Program Status (1=ready; 0=busy)
+-- IR[4] = ISP mode (1=in-system programming mode; 0=normal download mode)
+-- IR[3] = JTAG read-protection (1=secured; 0=unsecured)
+-- IR[2] = 0 value
+-- IR[1:0]= 01 as defined by IEEE STD 1149.1
+
+attribute INSTRUCTION_PRIVATE of XCF02S_VO20: entity is
+ "priv3," &
+ "priv4," &
+ "priv5," &
+ "priv6," &
+ "priv7," &
+ "priv9";
+
+attribute IDCODE_REGISTER of XCF02S_VO20: entity is
+ "XXXX" & -- version
+ "0101000001000101" & -- part number
+ "00001001001" & -- manufacturer's id
+ "1"; -- required by IEEE STD 1149.1
+
+attribute USERCODE_REGISTER of XCF02S_VO20: entity is
+ "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+
+attribute REGISTER_ACCESS of XCF02S_VO20 : entity is
+ -- IEEE 1149.1 standard data registers
+ "BOUNDARY (EXTEST, SAMPLE, PRELOAD),"&
+ "DEVICE_ID (IDCODE, USERCODE),"&
+ "BYPASS (BYPASS, HIGHZ, CLAMP, CONFIG)," &
+ -- Xilinx ISP data registers
+ "ISC_DEFAULT[1] (NORMRST, FPGM),"&
+ "ISPENABLE[6] (ISPEN, ISPENC)," &
+ "ADDRESS[16] (FADDR, FERASE, SERASE),"&
+ "DATA0[4096] (FVFY0, FDATA0),"&
+ "DATA1[2097152] (FVFY1, FBLANK0),"&
+ "DATA3[3] (FVFY3, FDATA3, FBLANK3),"&
+ "USERCODEV[32] (FVFY6, FBLANK6),"&
+ "ISC_INFO[8] (ISC_READ_INFO),"&
+ "XSC_STATUS[8] (ISCTESTSTATUS, ISCCLRSTATUS)";
+
+attribute BOUNDARY_LENGTH of XCF02S_VO20 : entity is
+ 25;
+
+attribute BOUNDARY_REGISTER of XCF02S_VO20 : entity is
+-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
+ " 0 (BC_1, CLK, input, X )," &
+ " 1 (BC_1, *, internal, 0 )," &
+ " 2 (BC_1, *, internal, X )," &
+ " 3 (BC_1, *, controlr, 0 )," &
+ " 4 (BC_1, D0, output3, X, 3, 0, Z)," &
+ " 5 (BC_1, *, internal, 0 )," &
+ " 6 (BC_1, *, internal, X )," &
+ " 7 (BC_1, *, internal, 0 )," &
+ " 8 (BC_1, *, internal, X )," &
+ " 9 (BC_1, *, internal, 0 )," &
+ " 10 (BC_1, *, internal, X )," &
+ " 11 (BC_1, *, controlr, 0 )," &
+ " 12 (BC_1, CEO, output3, X, 11, 0, Z)," &
+ " 13 (BC_1, *, internal, 0 )," &
+ " 14 (BC_1, *, internal, X )," &
+ " 15 (BC_1, CE, input, X )," &
+ " 16 (BC_1, *, internal, 0 )," &
+ " 17 (BC_1, *, internal, X )," &
+ " 18 (BC_1, *, controlr, 0 )," &
+ " 19 (BC_1, OE_RESET, output3, X, 18, 0, Z)," &
+ " 20 (BC_1, OE_RESET, input, X )," &
+ " 21 (BC_1, *, controlr, 0 )," &
+ " 22 (BC_1, CF, output3, X, 21, 0, Z)," &
+ " 23 (BC_1, *, internal, 0 )," &
+ " 24 (BC_1, *, internal, X )";
+
+attribute DESIGN_WARNING of XCF02S_VO20 : entity is
+ "The FERASE and FPGM instructions require " &
+ "a falling-edge of TCK AFTER the Run-Test/Idle TAP state is entered " &
+ "in order to start the operation corresponding to the instruction. " &
+ "The FVFY0, FVFY1, and FBLANK0 instructions activate a non-standard, " &
+ "output-only data register that does not pass TDI through to TDO. Thus, " &
+ "data beyond the specififed length of the corresponding data register " &
+ "is undefined. " &
+ "When the FVFY0, FVFY1, and FBLANK0 instructions are in use, " &
+ "all components between TDO of this device and the tester must select " &
+ "the BYPASS register to avoid acting on the undefined data values. " &
+ "Do not drive CF low when CF is connected to the PROGRAM/PROG_B pin of " &
+ "a Virtex, Virtex-E, Virtex-4, Spartan-II, Spartan-IIE FPGA and when " &
+ "the FPGA is in the same boundary-scan chain as this XCF02S. " &
+ "A Low applied to the PROGRAM/PROG_B pin of these FPGAs resets the TAP " &
+ "in these FPGAs.";
+
+end XCF02S_VO20;
+
Index: trunk/targets/Basys/cclk.ut
===================================================================
--- trunk/targets/Basys/cclk.ut (nonexistent)
+++ trunk/targets/Basys/cclk.ut (revision 6)
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
Index: trunk/targets/Basys/Makefile.brd
===================================================================
--- trunk/targets/Basys/Makefile.brd (nonexistent)
+++ trunk/targets/Basys/Makefile.brd (revision 6)
@@ -0,0 +1,4 @@
+Part=xc3s100e-tq144-5
+board=Basys
+
+
Index: trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag.v
===================================================================
--- trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag.v (nonexistent)
+++ trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag.v (revision 6)
@@ -0,0 +1,132 @@
+
+
+
+
+
+
+
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / TARGET \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Jtag tap controller for xilinx spartan 3e fpga */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
+
+//////////////////////////////////////////////////////////////////////
+// //
+// This file is a wrapper for the various Xilinx internal BSCAN //
+// TAP devices. It is designed to take the place of a separate TAP //
+// controller in Xilinx systems, to allow a user to access a CPU //
+// debug module (such as that of the OR1200) through the FPGA's //
+// dedicated JTAG / configuration port. //
+// //
+//////////////////////////////////////////////////////////////////////
+//
+
+// Note that the SPARTAN BSCAN controllers have more than one channel.
+// This implementation always uses channel 1, this is not configurable.
+// If you want to use another channel, then it is probably because you
+// want to attach multiple devices to the BSCAN device, which means
+// you'll be making changes to this file anyway.
+
+
+module cde_jtag (
+
+input wire tdi_1,
+input wire tdi_2,
+output wire tck_1,
+output wire tck_2,
+output wire tdo_o,
+output wire test_logic_reset_o,
+output wire shift_dr_o,
+output wire capture_dr_o,
+output wire update_dr_o,
+output wire select_1,
+output wire select_2
+
+);
+
+wire update_dr_i;
+
+
+BSCAN_SPARTAN3
+BSCAN_SPARTAN3_inst (
+ .CAPTURE (capture_dr_o), // CAPTURE output from TAP controller
+ .DRCK1 (tck_1_i), // Data register output for USER1 functions
+ .DRCK2 (tck_2_i), // Data register output for USER2 functions
+ .RESET (test_logic_reset_o), // Reset output from TAP controller
+ .SEL1 (select_1), // USER1 active output
+ .SEL2 (select_2), // USER2 active output
+ .SHIFT (shift_dr_o), // SHIFT output from TAP controller
+ .TDI (tdo_o), // TDI output from TAP controller
+ .UPDATE (update_dr_i), // UPDATE output from TAP controller
+ .TDO1 (tdi_1), // Data input for USER1 function
+ .TDO2 (tdi_2) // Data input for USER2 function
+);
+
+
+BUFG
+update_buf (
+ .O (update_dr_o), // Clock buffer output
+ .I (update_dr_i) // Clock buffer input
+ );
+
+
+BUFG
+tck_1_buf (
+ .O (tck_1), // Clock buffer output
+ .I (tck_1_i) // Clock buffer input
+ );
+
+
+BUFG
+tck_2_buf (
+ .O (tck_2), // Clock buffer output
+ .I (tck_2_i) // Clock buffer input
+ );
+
+
+
+
+
+
+
+
+
+endmodule
\ No newline at end of file
Index: trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag_rpc_reg.v
===================================================================
--- trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag_rpc_reg.v (nonexistent)
+++ trunk/targets/Basys/lib/syn/cde_jtag/cde_jtag_rpc_reg.v (revision 6)
@@ -0,0 +1,93 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / LIB \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* jtag reduced pin count register with update clock */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
+
+
+module
+cde_jtag_rpc_reg
+#(parameter BITS = 16, // number of bits in the register (2 or more)
+ parameter RESET_VALUE = 'h0 // reset value of register
+)
+(
+
+input wire clk, // clock input
+input wire reset, // async reset
+input wire tdi, // scan-in of jtag_register
+input wire select, // '1' when jtag accessing this register
+output wire tdo, // scan-out of jtag register
+input wire update_dr, // clock input
+input wire capture_dr,
+input wire shift_dr,
+
+output reg [BITS-1:0] update_value, // the update register
+input wire [BITS-1:0] capture_value // value to latch on a capture_dr
+
+ );
+
+// shift buffer and shadow
+reg [BITS-1:0] buffer;
+
+always @(posedge clk or posedge reset)
+ if (reset) buffer <= RESET_VALUE;
+ else
+ if (select && capture_dr) buffer <= capture_value;
+ else
+ if (select && shift_dr) buffer <= { tdi, buffer[BITS-1:1] };
+ else buffer <= buffer;
+
+
+
+
+ always @(posedge update_dr or posedge reset)
+ if (reset) update_value <= RESET_VALUE;
+ else
+ if (select) update_value <= buffer;
+ else update_value <= update_value;
+
+
+
+
+assign tdo = buffer[0];
+
+
+
+endmodule
Index: trunk/targets/Basys/lib/syn/cde_clock_sys/cde_clock_sys.v
===================================================================
--- trunk/targets/Basys/lib/syn/cde_clock_sys/cde_clock_sys.v (nonexistent)
+++ trunk/targets/Basys/lib/syn/cde_clock_sys/cde_clock_sys.v (revision 6)
@@ -0,0 +1,140 @@
+/**********************************************************************/
+/* */
+/* ------- */
+/* / SOC \ */
+/* / GEN \ */
+/* / TARGET \ */
+/* ============== */
+/* | | */
+/* |____________| */
+/* */
+/* Clock_sys model for xilinx spartan 3e fpga */
+/* */
+/* */
+/* Author(s): */
+/* - John Eaton, jt_eaton@opencores.org */
+/* */
+/**********************************************************************/
+/* */
+/* Copyright (C) <2010> */
+/* */
+/* This source file may be used and distributed without */
+/* restriction provided that this copyright statement is not */
+/* removed from the file and that any derivative work contains */
+/* the original copyright notice and the associated disclaimer. */
+/* */
+/* This source file is free software; you can redistribute it */
+/* and/or modify it under the terms of the GNU Lesser General */
+/* Public License as published by the Free Software Foundation; */
+/* either version 2.1 of the License, or (at your option) any */
+/* later version. */
+/* */
+/* This source is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied */
+/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
+/* PURPOSE. See the GNU Lesser General Public License for more */
+/* details. */
+/* */
+/* You should have received a copy of the GNU Lesser General */
+/* Public License along with this source; if not, download it */
+/* from http://www.opencores.org/lgpl.shtml */
+/* */
+/**********************************************************************/
+
+
+module cde_clock_sys
+#(parameter FREQ = 48 ,
+ parameter MULT = 4 )
+(
+input wire a_clk_pad_in,
+input wire b_clk_pad_in,
+
+input wire pwron_pad_in,
+
+output wire ckOut,
+output wire ckDivOut,
+output reg one_usec,
+
+output reg reset
+
+);
+
+reg [3:0] reset_cnt;
+reg [6:0] counter;
+
+
+always@(posedge ckOut or negedge pwron_pad_in)
+ if(!pwron_pad_in) reset_cnt <= 4'b1111;
+ else
+ if(|reset_cnt) reset_cnt <= reset_cnt - 4'b0001;
+ else reset_cnt <= 4'b0000;
+
+
+
+
+always@(posedge ckOut or negedge pwron_pad_in)
+ if(!pwron_pad_in) reset <= 1'b1;
+ else reset <= (|reset_cnt);
+
+
+
+DCM_SP #(
+ .CLKDV_DIVIDE (2.0),
+ .CLKFX_DIVIDE (1),
+ .CLKFX_MULTIPLY (4),
+ .CLKIN_DIVIDE_BY_2 ("FALSE"),
+ .CLKIN_PERIOD (20.5),
+ .CLKOUT_PHASE_SHIFT ("NONE"),
+ .CLK_FEEDBACK ("1X"),
+ .DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
+ .DFS_FREQUENCY_MODE ("LOW"),
+ .DLL_FREQUENCY_MODE ("LOW"),
+ .DUTY_CYCLE_CORRECTION("TRUE"),
+ .PHASE_SHIFT (0),
+ .STARTUP_WAIT ("FALSE")
+) DCM_SP_inst (
+ .CLKFX (),
+ .CLKFX180 (),
+ .PSDONE (),
+ .STATUS (),
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .CLK0 (),
+ .CLK180 (),
+ .CLK270 (),
+ .CLK2X (ckOut_pre),
+ .CLK2X180 (),
+ .CLK90 (),
+ .CLKDV (ckDivOut),
+ .LOCKED (),
+ .CLKFB (ckOut),
+ .CLKIN (a_clk_pad_in),
+ .RST (1'b0)
+ );
+
+
+ BUFG
+ BUFG_inst (
+ .O(ckOut), // Clock buffer output
+ .I(ckOut_pre) // Clock buffer input
+ );
+
+
+
+
+
+ always@(posedge ckOut)
+ if (counter == 7'b0000000) counter <= 7'b1011110;
+ else counter <= counter -7'b0000001;
+
+ always@(posedge ckOut)
+ one_usec <= (counter == 7'b0000000);
+
+
+
+
+
+
+
+endmodule
Index: trunk/targets/Basys/Pad_Ring.v
===================================================================
--- trunk/targets/Basys/Pad_Ring.v (nonexistent)
+++ trunk/targets/Basys/Pad_Ring.v (revision 6)
@@ -0,0 +1,675 @@
+`include "../def_file"
+
+module `MODULE_NAME
+(
+
+inout wire A_CLK,
+inout wire B_CLK,
+inout wire PS2D,
+inout wire PS2C,
+inout wire RTS,
+inout wire CTS,
+inout wire RXD,
+inout wire TXD,
+output wire [2:0] VGARED,
+output wire [2:0] VGAGREEN,
+output wire [1:0] VGABLUE,
+output wire HSYNC,
+output wire VSYNC,
+inout wire [3:0] BTN,
+inout wire [7:0] SW,
+inout wire DP,
+inout wire [7:0] LED,
+inout wire [6:0] SEG,
+inout wire [3:0] AN,
+
+inout wire JA_1,
+inout wire JA_2,
+inout wire JA_3,
+inout wire JA_4,
+inout wire JB_1,
+inout wire JB_2,
+inout wire JB_3,
+inout wire JB_4,
+inout wire JC_1,
+inout wire JC_2,
+inout wire JC_3,
+inout wire JC_4
+
+);
+
+
+
+
+// Pad Mux signals
+
+
+wire a_clk_pad_in;
+wire b_clk_pad_in;
+
+wire ps2_data_pad_in;
+wire ps2_data_pad_oe;
+
+wire ps2_clk_pad_in;
+wire ps2_clk_pad_oe;
+
+
+wire [2:0] vgared_pad_out;
+wire [2:0] vgagreen_pad_out;
+wire [1:0] vgablue_pad_out;
+wire hsync_pad_out;
+wire vsync_pad_out;
+
+
+
+wire [3:0] btn_pad_in;
+wire [7:0] sw_pad_in;
+wire dp_pad_out;
+wire [7:0] led_pad_out;
+wire [6:0] seg_pad_out;
+wire [3:0] an_pad_out;
+
+
+wire ja_1_pad_out;
+wire ja_2_pad_out;
+wire ja_3_pad_out;
+wire ja_4_pad_out;
+
+
+wire jb_1_pad_out;
+wire jb_2_pad_out;
+wire jb_3_pad_out;
+wire jb_4_pad_out;
+
+wire jc_1_pad_out;
+wire jc_2_pad_out;
+wire jc_3_pad_out;
+wire jc_4_pad_out;
+
+
+
+
+
+
+// Pad Ring
+
+cde_pad_se_dig a_clk_pad(
+ .PAD (A_CLK),
+ .pad_in (a_clk_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig b_clk_pad(
+ .PAD (B_CLK),
+ .pad_in (b_clk_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig btn_0_pad(
+ .PAD (BTN[0]),
+ .pad_in (btn_pad_in[0]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig btn_1_pad(
+ .PAD (BTN[1]),
+ .pad_in (btn_pad_in[1]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig btn_2_pad(
+ .PAD (BTN[2]),
+ .pad_in (btn_pad_in[2]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig btn_3_pad(
+ .PAD (BTN[3]),
+ .pad_in (btn_pad_in[3]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_0_pad(
+ .PAD (SW[0]),
+ .pad_in (sw_pad_in[0]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_1_pad(
+ .PAD (SW[1]),
+ .pad_in (sw_pad_in[1]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_2_pad(
+ .PAD (SW[2]),
+ .pad_in (sw_pad_in[2]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_3_pad(
+ .PAD (SW[3]),
+ .pad_in (sw_pad_in[3]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_4_pad(
+ .PAD (SW[4]),
+ .pad_in (sw_pad_in[4]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_5_pad(
+ .PAD (SW[5]),
+ .pad_in (sw_pad_in[5]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_6_pad(
+ .PAD (SW[6]),
+ .pad_in (sw_pad_in[6]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig sw_7_pad(
+ .PAD (SW[7]),
+ .pad_in (sw_pad_in[7]),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig dp_pad(
+ .PAD (DP),
+ .pad_in (),
+ .pad_out (dp_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_0_pad(
+ .PAD (LED[0]),
+ .pad_in (),
+ .pad_out (led_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_1_pad(
+ .PAD (LED[1]),
+ .pad_in (),
+ .pad_out (led_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_2_pad(
+ .PAD (LED[2]),
+ .pad_in (),
+ .pad_out (led_pad_out[2]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_3_pad(
+ .PAD (LED[3]),
+ .pad_in (),
+ .pad_out (led_pad_out[3]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_4_pad(
+ .PAD (LED[4]),
+ .pad_in (),
+ .pad_out (led_pad_out[4]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_5_pad(
+ .PAD (LED[5]),
+ .pad_in (),
+ .pad_out (led_pad_out[5]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_6_pad(
+ .PAD (LED[6]),
+ .pad_in (),
+ .pad_out (led_pad_out[6]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig led_7_pad(
+ .PAD (LED[7]),
+ .pad_in (),
+ .pad_out (led_pad_out[7]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_0_pad(
+ .PAD (SEG[0]),
+ .pad_in (),
+ .pad_out (seg_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_1_pad(
+ .PAD (SEG[1]),
+ .pad_in (),
+ .pad_out (seg_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_2_pad(
+ .PAD (SEG[2]),
+ .pad_in (),
+ .pad_out (seg_pad_out[2]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_3_pad(
+ .PAD (SEG[3]),
+ .pad_in (),
+ .pad_out (seg_pad_out[3]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_4_pad(
+ .PAD (SEG[4]),
+ .pad_in (),
+ .pad_out (seg_pad_out[4]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_5_pad(
+ .PAD (SEG[5]),
+ .pad_in (),
+ .pad_out (seg_pad_out[5]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig seg_6_pad(
+ .PAD (SEG[6]),
+ .pad_in (),
+ .pad_out (seg_pad_out[6]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig an_0_pad(
+ .PAD (AN[0]),
+ .pad_in (),
+ .pad_out (an_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig an_1_pad(
+ .PAD (AN[1]),
+ .pad_in (),
+ .pad_out (an_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig an_2_pad(
+ .PAD (AN[2]),
+ .pad_in (),
+ .pad_out (an_pad_out[2]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig an_3_pad(
+ .PAD (AN[3]),
+ .pad_in (),
+ .pad_out (an_pad_out[3]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig ps2_data_pad(
+ .PAD (PS2D),
+ .pad_in (ps2_data_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (ps2_data_pad_oe)
+);
+
+cde_pad_se_dig ps2_clk_pad(
+ .PAD (PS2C),
+ .pad_in (ps2_clk_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (ps2_clk_pad_oe)
+);
+
+cde_pad_se_dig ja_1_pad(
+ .PAD (JA_1),
+ .pad_in (),
+ .pad_out (ja_1_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig ja_2_pad(
+ .PAD (JA_2),
+ .pad_in (),
+ .pad_out (ja_2_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig ja_3_pad(
+ .PAD (JA_3),
+ .pad_in (),
+ .pad_out (ja_3_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig ja_4_pad(
+ .PAD (JA_4),
+ .pad_in (),
+ .pad_out (ja_4_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jb_1_pad(
+ .PAD (JB_1),
+ .pad_in (),
+ .pad_out (jb_1_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jb_2_pad(
+ .PAD (JB_2),
+ .pad_in (),
+ .pad_out (jb_2_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jb_3_pad(
+ .PAD (JB_3),
+ .pad_in (),
+ .pad_out (jb_3_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jb_4_pad(
+ .PAD (JB_4),
+ .pad_in (),
+ .pad_out (jb_4_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jc_1_pad(
+ .PAD (JC_1),
+ .pad_in (),
+ .pad_out (jc_1_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jc_2_pad(
+ .PAD (JC_2),
+ .pad_in (),
+ .pad_out (jc_2_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jc_3_pad(
+ .PAD (JC_3),
+ .pad_in (),
+ .pad_out (jc_3_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig jc_4_pad(
+ .PAD (JC_4),
+ .pad_in (),
+ .pad_out (jc_4_pad_out),
+ .pad_oe (1'b1)
+);
+
+
+cde_pad_se_dig rts_pad(
+ .PAD (RTS),
+ .pad_in (),
+ .pad_out (rts_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig cts_pad(
+ .PAD (CTS),
+ .pad_in (cts_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig rxd_pad(
+ .PAD (RXD),
+ .pad_in (rxd_pad_in),
+ .pad_out (1'b0),
+ .pad_oe (1'b0)
+);
+
+cde_pad_se_dig txd_pad(
+ .PAD (TXD),
+ .pad_in (),
+ .pad_out (txd_pad_out),
+ .pad_oe (1'b1)
+);
+
+
+
+cde_pad_se_dig vgared_0_pad(
+ .PAD (VGARED[0]),
+ .pad_in (),
+ .pad_out (vgared_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vgared_1_pad(
+ .PAD (VGARED[1]),
+ .pad_in (),
+ .pad_out (vgared_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vgared_2_pad(
+ .PAD (VGARED[2]),
+ .pad_in (),
+ .pad_out (vgared_pad_out[2]),
+ .pad_oe (1'b1)
+);
+
+
+cde_pad_se_dig vgagreen_0_pad(
+ .PAD (VGAGREEN[0]),
+ .pad_in (),
+ .pad_out (vgagreen_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vgagreen_1_pad(
+ .PAD (VGAGREEN[1]),
+ .pad_in (),
+ .pad_out (vgagreen_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vgagreen_2_pad(
+ .PAD (VGAGREEN[2]),
+ .pad_in (),
+ .pad_out (vgagreen_pad_out[2]),
+ .pad_oe (1'b1)
+);
+
+
+
+
+cde_pad_se_dig vgablue_0_pad(
+ .PAD (VGABLUE[0]),
+ .pad_in (),
+ .pad_out (vgablue_pad_out[0]),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vgablue_1_pad(
+ .PAD (VGABLUE[1]),
+ .pad_in (),
+ .pad_out (vgablue_pad_out[1]),
+ .pad_oe (1'b1)
+);
+
+
+
+cde_pad_se_dig hsync_pad(
+ .PAD (HSYNC),
+ .pad_in (),
+ .pad_out (hsync_pad_out),
+ .pad_oe (1'b1)
+);
+
+cde_pad_se_dig vsync_pad(
+ .PAD (VSYNC),
+ .pad_in (),
+ .pad_out (vsync_pad_out),
+ .pad_oe (1'b1)
+);
+
+
+
+// Clock System
+
+
+
+wire ck25MHz;
+wire ck100MHz;
+wire one_usec;
+wire reset;
+
+wire [15:0] PosD;
+wire [ 7:0] PosL;
+wire [ 3:0] PosB;
+wire [ 7:0] PosS;
+
+
+cde_clock_sys clock_sys (
+ .a_clk_pad_in (a_clk_pad_in),
+ .b_clk_pad_in (b_clk_pad_in),
+ .pwron_pad_in (!cts_pad_in),
+ .ckDivOut (ck25MHz),
+ .ckOut (ck100MHz),
+ .one_usec (one_usec),
+ .reset (reset)
+
+ );
+
+
+
+
+
+disp_io
+disp_io (
+ .clk (ck25MHz),
+ .reset (reset),
+ .one_usec (one_usec),
+ .PosD (PosD),
+ .PosL (PosL),
+ .PosB (PosB),
+ .PosS (PosS),
+ .dp_pad_out (dp_pad_out),
+ .led_pad_out (led_pad_out[7:0]),
+ .seg_pad_out (seg_pad_out[6:0]),
+ .an_pad_out (an_pad_out[3:0]),
+ .sw_pad_in (sw_pad_in[7:0]),
+ .btn_pad_in (btn_pad_in[3:0])
+ );
+
+
+cde_jtag
+jtag_tap(
+
+ .tdi_1 (td1),
+ .tdi_2 (td2),
+ .tck_1 (tck1),
+ .tck_2 (tck2),
+ .tdo_o (tdo),
+ .test_logic_reset_o (test_logic_reset),
+ .shift_dr_o (shift_dr),
+ .capture_dr_o (capture_dr),
+ .update_dr_o (update_dr),
+ .select_1 (select1),
+ .select_2 (select2)
+
+);
+
+
+
+
+
+wire [`JTAG_USER1_WIDTH-1:0] jtag_user1_cap;
+wire [`JTAG_USER2_WIDTH-1:0] jtag_user2_cap;
+
+wire [`JTAG_USER1_WIDTH-1:0] jtag_user1_upd;
+wire [`JTAG_USER2_WIDTH-1:0] jtag_user2_upd;
+
+
+
+
+cde_jtag_rpc_reg #(`JTAG_USER1_WIDTH ,`JTAG_USER1_RESET )
+user1_reg
+(
+ .clk (tck1),
+ .reset (test_logic_reset),
+ .tdi (tdo),
+ .select (select1),
+ .tdo (td1),
+ .update_dr (update_dr),
+ .capture_dr (capture_dr),
+ .shift_dr (shift_dr),
+ .capture_value (jtag_user1_cap),
+ .update_value (jtag_user1_upd)
+);
+
+
+cde_jtag_rpc_reg #(`JTAG_USER2_WIDTH,`JTAG_USER2_RESET )
+user2_reg
+(
+ .clk (tck2),
+ .reset (test_logic_reset),
+ .tdi (tdo),
+ .select (select2),
+ .tdo (td2),
+ .update_dr (update_dr),
+ .capture_dr (capture_dr),
+ .shift_dr (shift_dr),
+ .capture_value (jtag_user2_cap),
+ .update_value (jtag_user2_upd)
+);
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+`include "../core.v"
+
+
+
+
+
+
+endmodule
\ No newline at end of file
Index: trunk/targets/Basys/xc3s100e_tq144.bsd
===================================================================
--- trunk/targets/Basys/xc3s100e_tq144.bsd (nonexistent)
+++ trunk/targets/Basys/xc3s100e_tq144.bsd (revision 6)
@@ -0,0 +1,727 @@
+-- $ XILINX$RCSfile: xc3s100e_tq144.bsd,v $
+-- $ XILINX$Revision: 1.7 $
+--
+-- BSDL file for device XC3S100E_TQ144
+-- Xilinx, Inc. $State: PRELIMINARY $ $Date: 2008-05-29 16:00:42-07 $
+-- Generated by BSDLnet bsdlnet Version 1.39a
+
+------------------------------------------------------------------------
+-- Modification History
+-- | Generated on 05/28/08
+-- | CR # 471899
+-- | Details - Initial Release using BSDLnet.
+-- | Added 'attribute COMPLIANCE_PATTERNS' & changed boundary
+-- | register attribute to internal for PROG_B & PUDC_B.
+------------------------------------------------------------------------
+--
+-- For technical support, http://support.xilinx.com -> enter text 'bsdl'
+-- in the text search box at the left of the page. If none of
+-- these records resolve your problem you should open a web support case
+-- or contact our technical support at:
+-- This BSDL file reflects the pre-configuration JTAG behavior.
+-- =================================================
+-- North American Support
+-- (Mon,Tues,Wed,Fri 6:30am-5pm
+-- Thr 6:30am - 4:00pm Pacific Standard Time)
+-- Hotline: 1-800-255-7778
+-- or (408) 879-5199
+-- Fax: (408) 879-4442
+-- Email: hotline\@xilinx.com
+
+-- United Kingdom Support
+-- (Mon-Fri 08:00 to 17:30 GMT)
+-- Hotline: +44 870 7350 610
+-- Fax: +44 870 7350 620
+-- Email : eurosupport\@xilinx.com
+--
+-- France Support
+-- (Mon-Fri 08:00 to 17:30 GMT)
+-- Hotline: +33 1 3463 0100
+-- Fax: +44 870 7350 620
+-- Email : eurosupport\@xilinx.com
+--
+-- Germany Support
+-- (Mon-Fri 08:00 to 17:30 GMT)
+-- Hotline: +49 180 3 60 60 60
+-- Fax: +44 870 7350 620
+-- Email : eurosupport\@xilinx.com
+
+-- Sweden Support
+-- (Mon-Fri 08:00 to 17:30 GMT)
+-- Hotline: +46 8 33 14 00
+-- Fax: +44 870 7350 620
+-- Email : eurosupport\@xilinx.com
+--
+-- Japan Support
+-- (Mon,Tues,Thu,Fri 9:00am -5:00pm ()
+-- Wed 9:00am -4:00pm)
+-- Hotline: (81)3-3297-9163
+-- Fax:: (81)3-3297-0067
+-- Email: jhotline\@xilinx.com
+-- =================================================
+
+----------------------------------
+
+-- BSDL File for P1149.1 Standard.
+
+----------------------------------
+
+entity XC3S100E_TQ144 is
+
+-- Generic Parameter
+
+generic (PHYSICAL_PIN_MAP : string := "TQ144" );
+
+-- Logical Port Description
+
+port (
+ DONE: inout bit;
+ GND: linkage bit_vector (1 to 13);
+ IPAD100: in bit;
+ IPAD104: in bit;
+ IPAD12: in bit;
+ IPAD13: in bit;
+ IPAD19: in bit;
+ IPAD20: in bit;
+ IPAD23: in bit;
+ IPAD26: in bit;
+ IPAD27: in bit;
+ IPAD3: in bit;
+ IPAD32: in bit;
+ IPAD36: in bit;
+ IPAD41: in bit;
+ IPAD46: in bit;
+ IPAD50: in bit;
+ IPAD57: in bit;
+ IPAD6: in bit;
+ IPAD60: in bit;
+ IPAD66: in bit;
+ IPAD67: in bit;
+ IPAD73: in bit;
+ IPAD74: in bit;
+ IPAD77: in bit;
+ IPAD80: in bit;
+ IPAD81: in bit;
+ IPAD86: in bit;
+ IPAD90: in bit;
+ IPAD95: in bit;
+ P10: inout bit; -- PAD101
+ P103: inout bit; -- PAD31
+ P104: inout bit; -- PAD30
+ P105: inout bit; -- PAD29
+ P106: inout bit; -- PAD28
+ P112: inout bit; -- PAD25
+ P113: inout bit; -- PAD24
+ P116: inout bit; -- PAD22
+ P117: inout bit; -- PAD21
+ P122: inout bit; -- PAD18
+ P123: inout bit; -- PAD17
+ P124: inout bit; -- PAD16
+ P125: inout bit; -- PAD15
+ P126: inout bit; -- PAD14
+ P130: inout bit; -- PAD11
+ P131: inout bit; -- PAD10
+ P132: inout bit; -- PAD9
+ P134: inout bit; -- PAD8
+ P135: inout bit; -- PAD7
+ P139: inout bit; -- PAD5
+ P14: inout bit; -- PAD99
+ P140: inout bit; -- PAD4
+ P142: inout bit; -- PAD2
+ P15: inout bit; -- PAD98
+ P16: inout bit; -- PAD97
+ P17: inout bit; -- PAD96
+ P2: inout bit; -- PAD108
+ P20: inout bit; -- PAD94
+ P21: inout bit; -- PAD93
+ P22: inout bit; -- PAD92
+ P23: inout bit; -- PAD91
+ P25: inout bit; -- PAD89
+ P26: inout bit; -- PAD88
+ P29: inout bit; -- PAD87
+ P3: inout bit; -- PAD107
+ P32: inout bit; -- PAD85
+ P33: inout bit; -- PAD84
+ P34: inout bit; -- PAD83
+ P35: inout bit; -- PAD82
+ P39: inout bit; -- PAD79
+ P4: inout bit; -- PAD106
+ P40: inout bit; -- PAD78
+ P43: inout bit; -- PAD76
+ P44: inout bit; -- PAD75
+ P5: inout bit; -- PAD105
+ P50: inout bit; -- PAD72
+ P51: inout bit; -- PAD71
+ P52: inout bit; -- PAD70
+ P53: inout bit; -- PAD69
+ P54: inout bit; -- PAD68
+ P58: inout bit; -- PAD65
+ P59: inout bit; -- PAD64
+ P60: inout bit; -- PAD63
+ P62: inout bit; -- PAD62
+ P63: inout bit; -- PAD61
+ P67: inout bit; -- PAD59
+ P68: inout bit; -- PAD58
+ P7: inout bit; -- PAD103
+ P70: inout bit; -- PAD56
+ P71: inout bit; -- PAD55
+ P74: inout bit; -- PAD54
+ P75: inout bit; -- PAD53
+ P76: inout bit; -- PAD52
+ P77: inout bit; -- PAD51
+ P8: inout bit; -- PAD102
+ P81: inout bit; -- PAD49
+ P82: inout bit; -- PAD48
+ P83: inout bit; -- PAD47
+ P85: inout bit; -- PAD45
+ P86: inout bit; -- PAD44
+ P87: inout bit; -- PAD43
+ P88: inout bit; -- PAD42
+ P91: inout bit; -- PAD40
+ P92: inout bit; -- PAD39
+ P93: inout bit; -- PAD38
+ P94: inout bit; -- PAD37
+ P96: inout bit; -- PAD35
+ P97: inout bit; -- PAD34
+ P98: inout bit; -- PAD33
+ PROG_B: in bit;
+ PUDC_B: in bit; -- PAD1
+ TCK: in bit;
+ TDI: in bit;
+ TDO: out bit;
+ TMS: in bit;
+ VCCAUX: linkage bit_vector (1 to 4);
+ VCCINT: linkage bit_vector (1 to 4);
+ VCCO_0: linkage bit_vector (1 to 2);
+ VCCO_1: linkage bit_vector (1 to 2);
+ VCCO_2: linkage bit_vector (1 to 3);
+ VCCO_3: linkage bit_vector (1 to 2)
+); --end port list
+
+-- Use Statements
+
+use STD_1149_1_2001.all;
+
+-- Component Conformance Statement(s)
+
+attribute COMPONENT_CONFORMANCE of XC3S100E_TQ144 : entity is
+ "STD_1149_1_2001";
+
+-- Device Package Pin Mappings
+
+attribute PIN_MAP of XC3S100E_TQ144 : entity is PHYSICAL_PIN_MAP;
+
+constant TQ144: PIN_MAP_STRING:=
+ "DONE:P72," &
+ "GND:(P11,P19,P27,P37,P46,P55,P61,P73,P90,P99," &
+ "P118,P127,P133)," &
+ "IPAD100:P12," &
+ "IPAD104:P6," &
+ "IPAD12:P129," &
+ "IPAD13:P128," &
+ "IPAD19:P120," &
+ "IPAD20:P119," &
+ "IPAD23:P114," &
+ "IPAD26:P111," &
+ "IPAD27:P107," &
+ "IPAD3:P141," &
+ "IPAD32:P101," &
+ "IPAD36:P95," &
+ "IPAD41:P89," &
+ "IPAD46:P84," &
+ "IPAD50:P78," &
+ "IPAD57:P69," &
+ "IPAD6:P136," &
+ "IPAD60:P66," &
+ "IPAD66:P57," &
+ "IPAD67:P56," &
+ "IPAD73:P48," &
+ "IPAD74:P47," &
+ "IPAD77:P41," &
+ "IPAD80:P38," &
+ "IPAD81:P36," &
+ "IPAD86:P31," &
+ "IPAD90:P24," &
+ "IPAD95:P18," &
+ "P10:P10," &
+ "P103:P103," &
+ "P104:P104," &
+ "P105:P105," &
+ "P106:P106," &
+ "P112:P112," &
+ "P113:P113," &
+ "P116:P116," &
+ "P117:P117," &
+ "P122:P122," &
+ "P123:P123," &
+ "P124:P124," &
+ "P125:P125," &
+ "P126:P126," &
+ "P130:P130," &
+ "P131:P131," &
+ "P132:P132," &
+ "P134:P134," &
+ "P135:P135," &
+ "P139:P139," &
+ "P14:P14," &
+ "P140:P140," &
+ "P142:P142," &
+ "P15:P15," &
+ "P16:P16," &
+ "P17:P17," &
+ "P2:P2," &
+ "P20:P20," &
+ "P21:P21," &
+ "P22:P22," &
+ "P23:P23," &
+ "P25:P25," &
+ "P26:P26," &
+ "P29:P29," &
+ "P3:P3," &
+ "P32:P32," &
+ "P33:P33," &
+ "P34:P34," &
+ "P35:P35," &
+ "P39:P39," &
+ "P4:P4," &
+ "P40:P40," &
+ "P43:P43," &
+ "P44:P44," &
+ "P5:P5," &
+ "P50:P50," &
+ "P51:P51," &
+ "P52:P52," &
+ "P53:P53," &
+ "P54:P54," &
+ "P58:P58," &
+ "P59:P59," &
+ "P60:P60," &
+ "P62:P62," &
+ "P63:P63," &
+ "P67:P67," &
+ "P68:P68," &
+ "P7:P7," &
+ "P70:P70," &
+ "P71:P71," &
+ "P74:P74," &
+ "P75:P75," &
+ "P76:P76," &
+ "P77:P77," &
+ "P8:P8," &
+ "P81:P81," &
+ "P82:P82," &
+ "P83:P83," &
+ "P85:P85," &
+ "P86:P86," &
+ "P87:P87," &
+ "P88:P88," &
+ "P91:P91," &
+ "P92:P92," &
+ "P93:P93," &
+ "P94:P94," &
+ "P96:P96," &
+ "P97:P97," &
+ "P98:P98," &
+ "PROG_B:P1," &
+ "PUDC_B:P143," &
+ "TCK:P110," &
+ "TDI:P144," &
+ "TDO:P109," &
+ "TMS:P108," &
+ "VCCAUX:(P30,P65,P102,P137)," &
+ "VCCINT:(P9,P45,P80,P115)," &
+ "VCCO_0:(P121,P138)," &
+ "VCCO_1:(P79,P100)," &
+ "VCCO_2:(P42,P49,P64)," &
+ "VCCO_3:(P13,P28)";
+
+
+-- Scan Port Identification
+
+attribute TAP_SCAN_OUT of TDO : signal is true;
+attribute TAP_SCAN_IN of TDI : signal is true;
+attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, both);
+attribute TAP_SCAN_MODE of TMS : signal is true;
+
+-- Compliance-Enable Description
+
+attribute COMPLIANCE_PATTERNS of XC3S100E_TQ144 : entity is
+ "(PROG_B, PUDC_B) (10)";
+
+-- Instruction Register Description
+
+attribute INSTRUCTION_LENGTH of XC3S100E_TQ144 : entity is 6;
+
+attribute INSTRUCTION_OPCODE of XC3S100E_TQ144 : entity is
+
+ "EXTEST (001111)," &
+ "SAMPLE (000001)," &
+ "PRELOAD (000001)," & -- Same as SAMPLE
+ "USER1 (000010)," & -- Not available until after configuration
+ "USER2 (000011)," & -- Not available until after configuration
+ "CFG_OUT (000100)," & -- Not available during configuration with another mode.
+ "CFG_IN (000101)," & -- Not available during configuration with another mode.
+ "INTEST (000111)," &
+ "USERCODE (001000)," &
+ "IDCODE (001001)," &
+ "HIGHZ (001010)," &
+ "JPROGRAM (001011)," & -- Not available during configuration with another mode.
+ "JSTART (001100)," & -- Not available during configuration with another mode.
+ "JSHUTDOWN (001101)," & -- Not available during configuration with another mode.
+ "BYPASS (111111)," &
+ "ISC_ENABLE (010000)," &
+ "ISC_PROGRAM (010001)," &
+ "ISC_NOOP (010100)," &
+ "ISC_READ (010101)," &
+ "ISC_DISABLE (010110)";
+
+attribute INSTRUCTION_CAPTURE of XC3S100E_TQ144 : entity is
+-- Bit 5 is 1 when DONE is released (part of startup sequence)
+-- Bit 4 is 1 if house-cleaning is complete
+-- Bit 3 is ISC_Enabled
+-- Bit 2 is ISC_Done
+ "XXXX01" ;
+
+attribute INSTRUCTION_PRIVATE of XC3S100E_TQ144 : entity is
+ "USER1," &
+ "USER2," &
+ "CFG_OUT," &
+ "CFG_IN," &
+ "JPROGRAM," &
+ "JSTART," &
+ "JSHUTDOWN," &
+ "ISC_ENABLE," &
+ "ISC_PROGRAM," &
+ "ISC_NOOP," &
+ "ISC_READ," &
+ "ISC_DISABLE";
+
+-- Optional Register Description
+
+attribute IDCODE_REGISTER of XC3S100E_TQ144 : entity is "XXXX" & -- version
+ "0001110" & -- family
+ "000010000" & -- array size
+ "00001001001" & -- manufacturer
+ "1"; -- required by 1149.1
+
+
+attribute USERCODE_REGISTER of XC3S100E_TQ144 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
+
+-- Register Access Description
+
+attribute REGISTER_ACCESS of XC3S100E_TQ144 : entity is
+"BYPASS (HIGHZ, BYPASS)," &
+"DEVICE_ID (USERCODE, IDCODE)," &
+"BOUNDARY (EXTEST, SAMPLE, PRELOAD, INTEST)";
+
+-- Boundary-Scan Register Description
+
+attribute BOUNDARY_LENGTH of XC3S100E_TQ144 : entity is 272;
+
+attribute BOUNDARY_REGISTER of XC3S100E_TQ144 : entity is
+-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
+ " 271 (BC_2, IPAD27, input, X)," &
+ " 270 (BC_2, P106, input, X)," & -- PAD28
+ " 269 (BC_2, P106, output3, X, 268, 1, PULL1)," & -- PAD28
+ " 268 (BC_2, *, controlr, 1)," &
+ " 267 (BC_2, P105, input, X)," & -- PAD29
+ " 266 (BC_2, P105, output3, X, 265, 1, PULL1)," & -- PAD29
+ " 265 (BC_2, *, controlr, 1)," &
+ " 264 (BC_2, P104, input, X)," & -- PAD30
+ " 263 (BC_2, P104, output3, X, 262, 1, PULL1)," & -- PAD30
+ " 262 (BC_2, *, controlr, 1)," &
+ " 261 (BC_2, P103, input, X)," & -- PAD31
+ " 260 (BC_2, P103, output3, X, 259, 1, PULL1)," & -- PAD31
+ " 259 (BC_2, *, controlr, 1)," &
+ " 258 (BC_2, IPAD32, input, X)," &
+ " 257 (BC_2, P98, input, X)," & -- PAD33
+ " 256 (BC_2, P98, output3, X, 255, 1, PULL1)," & -- PAD33
+ " 255 (BC_2, *, controlr, 1)," &
+ " 254 (BC_2, P97, input, X)," & -- PAD34
+ " 253 (BC_2, P97, output3, X, 252, 1, PULL1)," & -- PAD34
+ " 252 (BC_2, *, controlr, 1)," &
+ " 251 (BC_2, P96, input, X)," & -- PAD35
+ " 250 (BC_2, P96, output3, X, 249, 1, PULL1)," & -- PAD35
+ " 249 (BC_2, *, controlr, 1)," &
+ " 248 (BC_2, IPAD36, input, X)," &
+ " 247 (BC_2, P94, input, X)," & -- PAD37
+ " 246 (BC_2, P94, output3, X, 245, 1, PULL1)," & -- PAD37
+ " 245 (BC_2, *, controlr, 1)," &
+ " 244 (BC_2, P93, input, X)," & -- PAD38
+ " 243 (BC_2, P93, output3, X, 242, 1, PULL1)," & -- PAD38
+ " 242 (BC_2, *, controlr, 1)," &
+ " 241 (BC_2, P92, input, X)," & -- PAD39
+ " 240 (BC_2, P92, output3, X, 239, 1, PULL1)," & -- PAD39
+ " 239 (BC_2, *, controlr, 1)," &
+ " 238 (BC_2, P91, input, X)," & -- PAD40
+ " 237 (BC_2, P91, output3, X, 236, 1, PULL1)," & -- PAD40
+ " 236 (BC_2, *, controlr, 1)," &
+ " 235 (BC_2, IPAD41, input, X)," &
+ " 234 (BC_2, P88, input, X)," & -- PAD42
+ " 233 (BC_2, P88, output3, X, 232, 1, PULL1)," & -- PAD42
+ " 232 (BC_2, *, controlr, 1)," &
+ " 231 (BC_2, P87, input, X)," & -- PAD43
+ " 230 (BC_2, P87, output3, X, 229, 1, PULL1)," & -- PAD43
+ " 229 (BC_2, *, controlr, 1)," &
+ " 228 (BC_2, P86, input, X)," & -- PAD44
+ " 227 (BC_2, P86, output3, X, 226, 1, PULL1)," & -- PAD44
+ " 226 (BC_2, *, controlr, 1)," &
+ " 225 (BC_2, P85, input, X)," & -- PAD45
+ " 224 (BC_2, P85, output3, X, 223, 1, PULL1)," & -- PAD45
+ " 223 (BC_2, *, controlr, 1)," &
+ " 222 (BC_2, IPAD46, input, X)," &
+ " 221 (BC_2, P83, input, X)," & -- PAD47
+ " 220 (BC_2, P83, output3, X, 219, 1, PULL1)," & -- PAD47
+ " 219 (BC_2, *, controlr, 1)," &
+ " 218 (BC_2, P82, input, X)," & -- PAD48
+ " 217 (BC_2, P82, output3, X, 216, 1, PULL1)," & -- PAD48
+ " 216 (BC_2, *, controlr, 1)," &
+ " 215 (BC_2, P81, input, X)," & -- PAD49
+ " 214 (BC_2, P81, output3, X, 213, 1, PULL1)," & -- PAD49
+ " 213 (BC_2, *, controlr, 1)," &
+ " 212 (BC_2, IPAD50, input, X)," &
+ " 211 (BC_2, P77, input, X)," & -- PAD51
+ " 210 (BC_2, P77, output3, X, 209, 1, PULL1)," & -- PAD51
+ " 209 (BC_2, *, controlr, 1)," &
+ " 208 (BC_2, P76, input, X)," & -- PAD52
+ " 207 (BC_2, P76, output3, X, 206, 1, PULL1)," & -- PAD52
+ " 206 (BC_2, *, controlr, 1)," &
+ " 205 (BC_2, P75, input, X)," & -- PAD53
+ " 204 (BC_2, P75, output3, X, 203, 1, PULL1)," & -- PAD53
+ " 203 (BC_2, *, controlr, 1)," &
+ " 202 (BC_2, P74, input, X)," & -- PAD54
+ " 201 (BC_2, P74, output3, X, 200, 1, PULL1)," & -- PAD54
+ " 200 (BC_2, *, controlr, 1)," &
+ " 199 (BC_2, DONE, input, X)," &
+ " 198 (BC_2, DONE, output3, X, 197, 1, PULL1)," &
+ " 197 (BC_2, *, controlr, 1)," &
+ " 196 (BC_2, P71, input, X)," & -- PAD55
+ " 195 (BC_2, P71, output3, X, 194, 1, PULL1)," & -- PAD55
+ " 194 (BC_2, *, controlr, 1)," &
+ " 193 (BC_2, P70, input, X)," & -- PAD56
+ " 192 (BC_2, P70, output3, X, 191, 1, PULL1)," & -- PAD56
+ " 191 (BC_2, *, controlr, 1)," &
+ " 190 (BC_2, IPAD57, input, X)," &
+ " 189 (BC_2, P68, input, X)," & -- PAD58
+ " 188 (BC_2, P68, output3, X, 187, 1, PULL1)," & -- PAD58
+ " 187 (BC_2, *, controlr, 1)," &
+ " 186 (BC_2, P67, input, X)," & -- PAD59
+ " 185 (BC_2, P67, output3, X, 184, 1, PULL1)," & -- PAD59
+ " 184 (BC_2, *, controlr, 1)," &
+ " 183 (BC_2, IPAD60, input, X)," &
+ " 182 (BC_2, P63, input, X)," & -- PAD61
+ " 181 (BC_2, P63, output3, X, 180, 1, PULL1)," & -- PAD61
+ " 180 (BC_2, *, controlr, 1)," &
+ " 179 (BC_2, P62, input, X)," & -- PAD62
+ " 178 (BC_2, P62, output3, X, 177, 1, PULL1)," & -- PAD62
+ " 177 (BC_2, *, controlr, 1)," &
+ " 176 (BC_2, P60, input, X)," & -- PAD63
+ " 175 (BC_2, P60, output3, X, 174, 1, PULL1)," & -- PAD63
+ " 174 (BC_2, *, controlr, 1)," &
+ " 173 (BC_2, P59, input, X)," & -- PAD64
+ " 172 (BC_2, P59, output3, X, 171, 1, PULL1)," & -- PAD64
+ " 171 (BC_2, *, controlr, 1)," &
+ " 170 (BC_2, P58, input, X)," & -- PAD65
+ " 169 (BC_2, P58, output3, X, 168, 1, PULL1)," & -- PAD65
+ " 168 (BC_2, *, controlr, 1)," &
+ " 167 (BC_2, IPAD66, input, X)," &
+ " 166 (BC_2, IPAD67, input, X)," &
+ " 165 (BC_2, P54, input, X)," & -- PAD68
+ " 164 (BC_2, P54, output3, X, 163, 1, PULL1)," & -- PAD68
+ " 163 (BC_2, *, controlr, 1)," &
+ " 162 (BC_2, P53, input, X)," & -- PAD69
+ " 161 (BC_2, P53, output3, X, 160, 1, PULL1)," & -- PAD69
+ " 160 (BC_2, *, controlr, 1)," &
+ " 159 (BC_2, P52, input, X)," & -- PAD70
+ " 158 (BC_2, P52, output3, X, 157, 1, PULL1)," & -- PAD70
+ " 157 (BC_2, *, controlr, 1)," &
+ " 156 (BC_2, P51, input, X)," & -- PAD71
+ " 155 (BC_2, P51, output3, X, 154, 1, PULL1)," & -- PAD71
+ " 154 (BC_2, *, controlr, 1)," &
+ " 153 (BC_2, P50, input, X)," & -- PAD72
+ " 152 (BC_2, P50, output3, X, 151, 1, PULL1)," & -- PAD72
+ " 151 (BC_2, *, controlr, 1)," &
+ " 150 (BC_2, IPAD73, input, X)," &
+ " 149 (BC_2, IPAD74, input, X)," &
+ " 148 (BC_2, P44, input, X)," & -- PAD75
+ " 147 (BC_2, P44, output3, X, 146, 1, PULL1)," & -- PAD75
+ " 146 (BC_2, *, controlr, 1)," &
+ " 145 (BC_2, P43, input, X)," & -- PAD76
+ " 144 (BC_2, P43, output3, X, 143, 1, PULL1)," & -- PAD76
+ " 143 (BC_2, *, controlr, 1)," &
+ " 142 (BC_2, IPAD77, input, X)," &
+ " 141 (BC_2, P40, input, X)," & -- PAD78
+ " 140 (BC_2, P40, output3, X, 139, 1, PULL1)," & -- PAD78
+ " 139 (BC_2, *, controlr, 1)," &
+ " 138 (BC_2, P39, input, X)," & -- PAD79
+ " 137 (BC_2, P39, output3, X, 136, 1, PULL1)," & -- PAD79
+ " 136 (BC_2, *, controlr, 1)," &
+ " 135 (BC_2, IPAD80, input, X)," &
+ " 134 (BC_2, IPAD81, input, X)," &
+ " 133 (BC_2, P35, input, X)," & -- PAD82
+ " 132 (BC_2, P35, output3, X, 131, 1, PULL1)," & -- PAD82
+ " 131 (BC_2, *, controlr, 1)," &
+ " 130 (BC_2, P34, input, X)," & -- PAD83
+ " 129 (BC_2, P34, output3, X, 128, 1, PULL1)," & -- PAD83
+ " 128 (BC_2, *, controlr, 1)," &
+ " 127 (BC_2, P33, input, X)," & -- PAD84
+ " 126 (BC_2, P33, output3, X, 125, 1, PULL1)," & -- PAD84
+ " 125 (BC_2, *, controlr, 1)," &
+ " 124 (BC_2, P32, input, X)," & -- PAD85
+ " 123 (BC_2, P32, output3, X, 122, 1, PULL1)," & -- PAD85
+ " 122 (BC_2, *, controlr, 1)," &
+ " 121 (BC_2, IPAD86, input, X)," &
+ " 120 (BC_2, P29, input, X)," & -- PAD87
+ " 119 (BC_2, P29, output3, X, 118, 1, PULL1)," & -- PAD87
+ " 118 (BC_2, *, controlr, 1)," &
+ " 117 (BC_2, P26, input, X)," & -- PAD88
+ " 116 (BC_2, P26, output3, X, 115, 1, PULL1)," & -- PAD88
+ " 115 (BC_2, *, controlr, 1)," &
+ " 114 (BC_2, P25, input, X)," & -- PAD89
+ " 113 (BC_2, P25, output3, X, 112, 1, PULL1)," & -- PAD89
+ " 112 (BC_2, *, controlr, 1)," &
+ " 111 (BC_2, IPAD90, input, X)," &
+ " 110 (BC_2, P23, input, X)," & -- PAD91
+ " 109 (BC_2, P23, output3, X, 108, 1, PULL1)," & -- PAD91
+ " 108 (BC_2, *, controlr, 1)," &
+ " 107 (BC_2, P22, input, X)," & -- PAD92
+ " 106 (BC_2, P22, output3, X, 105, 1, PULL1)," & -- PAD92
+ " 105 (BC_2, *, controlr, 1)," &
+ " 104 (BC_2, P21, input, X)," & -- PAD93
+ " 103 (BC_2, P21, output3, X, 102, 1, PULL1)," & -- PAD93
+ " 102 (BC_2, *, controlr, 1)," &
+ " 101 (BC_2, P20, input, X)," & -- PAD94
+ " 100 (BC_2, P20, output3, X, 99, 1, PULL1)," & -- PAD94
+ " 99 (BC_2, *, controlr, 1)," &
+ " 98 (BC_2, IPAD95, input, X)," &
+ " 97 (BC_2, P17, input, X)," & -- PAD96
+ " 96 (BC_2, P17, output3, X, 95, 1, PULL1)," & -- PAD96
+ " 95 (BC_2, *, controlr, 1)," &
+ " 94 (BC_2, P16, input, X)," & -- PAD97
+ " 93 (BC_2, P16, output3, X, 92, 1, PULL1)," & -- PAD97
+ " 92 (BC_2, *, controlr, 1)," &
+ " 91 (BC_2, P15, input, X)," & -- PAD98
+ " 90 (BC_2, P15, output3, X, 89, 1, PULL1)," & -- PAD98
+ " 89 (BC_2, *, controlr, 1)," &
+ " 88 (BC_2, P14, input, X)," & -- PAD99
+ " 87 (BC_2, P14, output3, X, 86, 1, PULL1)," & -- PAD99
+ " 86 (BC_2, *, controlr, 1)," &
+ " 85 (BC_2, IPAD100, input, X)," &
+ " 84 (BC_2, P10, input, X)," & -- PAD101
+ " 83 (BC_2, P10, output3, X, 82, 1, PULL1)," & -- PAD101
+ " 82 (BC_2, *, controlr, 1)," &
+ " 81 (BC_2, P8, input, X)," & -- PAD102
+ " 80 (BC_2, P8, output3, X, 79, 1, PULL1)," & -- PAD102
+ " 79 (BC_2, *, controlr, 1)," &
+ " 78 (BC_2, P7, input, X)," & -- PAD103
+ " 77 (BC_2, P7, output3, X, 76, 1, PULL1)," & -- PAD103
+ " 76 (BC_2, *, controlr, 1)," &
+ " 75 (BC_2, IPAD104, input, X)," &
+ " 74 (BC_2, P5, input, X)," & -- PAD105
+ " 73 (BC_2, P5, output3, X, 72, 1, PULL1)," & -- PAD105
+ " 72 (BC_2, *, controlr, 1)," &
+ " 71 (BC_2, P4, input, X)," & -- PAD106
+ " 70 (BC_2, P4, output3, X, 69, 1, PULL1)," & -- PAD106
+ " 69 (BC_2, *, controlr, 1)," &
+ " 68 (BC_2, P3, input, X)," & -- PAD107
+ " 67 (BC_2, P3, output3, X, 66, 1, PULL1)," & -- PAD107
+ " 66 (BC_2, *, controlr, 1)," &
+ " 65 (BC_2, P2, input, X)," & -- PAD108
+ " 64 (BC_2, P2, output3, X, 63, 1, PULL1)," & -- PAD108
+ " 63 (BC_2, *, controlr, 1)," &
+ " 62 (BC_2, *, internal, 1)," & -- PROG_B
+ " 61 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 60 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 59 (BC_2, *, internal, 1)," & -- PUDC_B
+ " 58 (BC_2, P142, input, X)," & -- PAD2
+ " 57 (BC_2, P142, output3, X, 56, 1, PULL1)," & -- PAD2
+ " 56 (BC_2, *, controlr, 1)," &
+ " 55 (BC_2, IPAD3, input, X)," &
+ " 54 (BC_2, P140, input, X)," & -- PAD4
+ " 53 (BC_2, P140, output3, X, 52, 1, PULL1)," & -- PAD4
+ " 52 (BC_2, *, controlr, 1)," &
+ " 51 (BC_2, P139, input, X)," & -- PAD5
+ " 50 (BC_2, P139, output3, X, 49, 1, PULL1)," & -- PAD5
+ " 49 (BC_2, *, controlr, 1)," &
+ " 48 (BC_2, IPAD6, input, X)," &
+ " 47 (BC_2, P135, input, X)," & -- PAD7
+ " 46 (BC_2, P135, output3, X, 45, 1, PULL1)," & -- PAD7
+ " 45 (BC_2, *, controlr, 1)," &
+ " 44 (BC_2, P134, input, X)," & -- PAD8
+ " 43 (BC_2, P134, output3, X, 42, 1, PULL1)," & -- PAD8
+ " 42 (BC_2, *, controlr, 1)," &
+ " 41 (BC_2, P132, input, X)," & -- PAD9
+ " 40 (BC_2, P132, output3, X, 39, 1, PULL1)," & -- PAD9
+ " 39 (BC_2, *, controlr, 1)," &
+ " 38 (BC_2, P131, input, X)," & -- PAD10
+ " 37 (BC_2, P131, output3, X, 36, 1, PULL1)," & -- PAD10
+ " 36 (BC_2, *, controlr, 1)," &
+ " 35 (BC_2, P130, input, X)," & -- PAD11
+ " 34 (BC_2, P130, output3, X, 33, 1, PULL1)," & -- PAD11
+ " 33 (BC_2, *, controlr, 1)," &
+ " 32 (BC_2, IPAD12, input, X)," &
+ " 31 (BC_2, IPAD13, input, X)," &
+ " 30 (BC_2, P126, input, X)," & -- PAD14
+ " 29 (BC_2, P126, output3, X, 28, 1, PULL1)," & -- PAD14
+ " 28 (BC_2, *, controlr, 1)," &
+ " 27 (BC_2, P125, input, X)," & -- PAD15
+ " 26 (BC_2, P125, output3, X, 25, 1, PULL1)," & -- PAD15
+ " 25 (BC_2, *, controlr, 1)," &
+ " 24 (BC_2, P124, input, X)," & -- PAD16
+ " 23 (BC_2, P124, output3, X, 22, 1, PULL1)," & -- PAD16
+ " 22 (BC_2, *, controlr, 1)," &
+ " 21 (BC_2, P123, input, X)," & -- PAD17
+ " 20 (BC_2, P123, output3, X, 19, 1, PULL1)," & -- PAD17
+ " 19 (BC_2, *, controlr, 1)," &
+ " 18 (BC_2, P122, input, X)," & -- PAD18
+ " 17 (BC_2, P122, output3, X, 16, 1, PULL1)," & -- PAD18
+ " 16 (BC_2, *, controlr, 1)," &
+ " 15 (BC_2, IPAD19, input, X)," &
+ " 14 (BC_2, IPAD20, input, X)," &
+ " 13 (BC_2, P117, input, X)," & -- PAD21
+ " 12 (BC_2, P117, output3, X, 11, 1, PULL1)," & -- PAD21
+ " 11 (BC_2, *, controlr, 1)," &
+ " 10 (BC_2, P116, input, X)," & -- PAD22
+ " 9 (BC_2, P116, output3, X, 8, 1, PULL1)," & -- PAD22
+ " 8 (BC_2, *, controlr, 1)," &
+ " 7 (BC_2, IPAD23, input, X)," &
+ " 6 (BC_2, P113, input, X)," & -- PAD24
+ " 5 (BC_2, P113, output3, X, 4, 1, PULL1)," & -- PAD24
+ " 4 (BC_2, *, controlr, 1)," &
+ " 3 (BC_2, P112, input, X)," & -- PAD25
+ " 2 (BC_2, P112, output3, X, 1, 1, PULL1)," & -- PAD25
+ " 1 (BC_2, *, controlr, 1)," &
+ " 0 (BC_2, IPAD26, input, X)";
+
+
+-- Design Warning Section
+
+attribute DESIGN_WARNING of XC3S100E_TQ144 : entity is
+ "This is a preliminary BSDL file which has not been verified." &
+ "This BSDL file must be modified by the FPGA designer in order to" &
+ "reflect post-configuration behavior (if any)." &
+ "To avoid losing the current configuration, the PROG_B should be" &
+ "kept high. If the PROG_B pin goes low by any means," &
+ "the configuration will be cleared." &
+ "PROG_B can only be captured, not updated." &
+ "The value at the pin is always used by the device." &
+ "PUDC_B can be captured and updated." &
+ "The value at the pin is always used by the device" &
+ "before configuration is done." &
+ "During pre-configuration, the disable result of a 3-stated" &
+ "I/O in this file corresponds to PUDC_B being low" &
+ "or during EXTEST instruction." &
+ "When PUDC_B is high AND during SAMPLE instruction, change" &
+ "all PULL1s to PULL0s." &
+ "After configuration, the disable result only depends on" &
+ "the individual IO configuration setting." &
+ "In EXTEST, output and tristate values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "In INTEST, the pin input values are not captured in the" &
+ "Capture-DR state - those register cells are unchanged." &
+ "The output and tristate capture values are not valid until after" &
+ "the device is configured." &
+ "The tristate control value is not captured properly when" &
+ "GTS is activated.";
+
+end XC3S100E_TQ144;
Index: trunk/targets/Basys/jtag.ut
===================================================================
--- trunk/targets/Basys/jtag.ut (nonexistent)
+++ trunk/targets/Basys/jtag.ut (revision 6)
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:1
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g DCMShutdown:Disable
+-g StartUpClk:JtagClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
Index: trunk/targets/Basys/Basys.ucf
===================================================================
--- trunk/targets/Basys/Basys.ucf (nonexistent)
+++ trunk/targets/Basys/Basys.ucf (revision 6)
@@ -0,0 +1,87 @@
+# clock pin for Basys Board
+NET "A_CLK" LOC = "p53" ; # oscillator 48 Mhz
+NET "B_CLK" LOC = "p54" ; # resonator 100/50/25
+
+
+
+# Pin assignment for DispCtl
+# Connected to Basys onBoard 7seg display
+
+NET "SEG<0>" LOC = "p25" ; # Signal name = CA
+NET "SEG<1>" LOC = "p16" ; # Signal name = CB
+NET "SEG<2>" LOC = "p23" ; # Signal name = CC
+NET "SEG<3>" LOC = "p21" ; # Signal name = CD
+NET "SEG<4>" LOC = "p20" ; # Signal name = CE
+NET "SEG<5>" LOC = "p17" ; # Signal name = CF
+NET "SEG<6>" LOC = "p83" ; # Signal name = CG
+NET "DP" LOC = "p22" ; # Signal name = DP
+
+NET "AN<3>" LOC = "p26" ; # Signal name = AN3
+NET "AN<2>" LOC = "p32" ; # Signal name = AN2
+NET "AN<1>" LOC = "p33" ; # Signal name = AN1
+NET "AN<0>" LOC = "p34" ; # Signal name = AN0
+
+# Pin assignment for LEDs
+NET "LED<7>" LOC = "p2" ; # Bank = 3, Signal name = LD7
+NET "LED<6>" LOC = "p3" ; # Bank = 3, Signal name = LD6
+NET "LED<5>" LOC = "p4" ; # Bank = 3, Signal name = LD5
+NET "LED<4>" LOC = "p5" ; # Bank = 3, Signal name = LD4
+NET "LED<3>" LOC = "p7" ; # Bank = 3, Signal name = LD3
+NET "LED<2>" LOC = "p8" ; # Bank = 3, Signal name = LD2
+NET "LED<1>" LOC = "p14" ; # Bank = 3, Signal name = LD1
+NET "LED<0>" LOC = "p15" ; # Bank = 3, Signal name = LD0
+
+# Pin assignment for SWs
+NET "SW<7>" LOC = "p6" ; # Bank = 3, Signal name = SW7
+NET "SW<6>" LOC = "p10" ; # Bank = 3, Signal name = SW6
+NET "SW<5>" LOC = "p12" ; # Bank = 3, Signal name = SW5
+NET "SW<4>" LOC = "p18" ; # Bank = 3, Signal name = SW4
+NET "SW<3>" LOC = "p24" ; # Bank = 3, Signal name = SW3
+NET "SW<2>" LOC = "p29" ; # Bank = 3, Signal name = SW2
+NET "SW<1>" LOC = "p36" ; # Bank = 3, Signal name = SW1
+NET "SW<0>" LOC = "p38" ; # Bank = 2, Signal name = SW0
+
+# Pin assignment for BTNs
+NET "BTN<3>" LOC = "p41" ; # Bank = 2, Signal name = BTN3
+NET "BTN<2>" LOC = "p47" ; # Bank = 2, Signal name = BTN2
+NET "BTN<1>" LOC = "p48" ; # Bank = 2, Signal name = BTN1
+NET "BTN<0>" LOC = "p69" ; # Bank = 2, Signal name = BTN0
+
+# Loop back/demo signals
+# Pin assignment for PS2
+NET "PS2C" LOC = "p96" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2C
+NET "PS2D" LOC = "p97" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2D
+
+# Pin assignment for VGA
+NET "HSYNC" LOC = "p39" | DRIVE = 2 ; # Bank = 2, Signal name = HSYNC
+NET "VSYNC" LOC = "p35" | DRIVE = 2 ; # Bank = 3, Signal name = VSYNC
+NET "VGARED<2>" LOC = "p67" | DRIVE = 2 ; # Bank = 2, Signal name = RED2
+NET "VGARED<1>" LOC = "p68" | DRIVE = 2 ; # Bank = 2, Signal name = RED1
+NET "VGARED<0>" LOC = "p70" | DRIVE = 2 ; # Bank = 2, Signal name = RED0
+NET "VGAGREEN<2>" LOC = "p50" | DRIVE = 2 ; # Bank = 2, Signal name = GRN2
+NET "VGAGREEN<1>" LOC = "p51" | DRIVE = 2 ; # Bank = 2, Signal name = GRN1
+NET "VGAGREEN<0>" LOC = "p52" | DRIVE = 2 ; # Bank = 2, Signal name = GRN0
+NET "VGABLUE<1>" LOC = "p43" | DRIVE = 2 ; # Bank = 2, Signal name = BLU2
+NET "VGABLUE<0>" LOC = "p44" | DRIVE = 2 ; # Bank = 2, Signal name = BLU1
+
+# Pin assignment for Expansion Ports
+
+NET "JA_1" LOC = "p81" | DRIVE = 6 ;
+NET "JA_2" LOC = "p91" | DRIVE = 6 ;
+NET "JA_3" LOC = "p82" | DRIVE = 6 ;
+NET "JA_4" LOC = "p92" | DRIVE = 6 ;
+
+NET "JB_1" LOC = "p87" ;
+NET "JB_2" LOC = "p93" ;
+NET "JB_3" LOC = "p88" ;
+NET "JB_4" LOC = "p94" ;
+
+NET "JC_1" LOC = "p77" ;
+NET "JC_2" LOC = "p86" ;
+NET "JC_3" LOC = "p76" ;
+NET "JC_4" LOC = "p85" ;
+
+NET "RTS" LOC = "p75" ;
+NET "CTS" LOC = "p59" ;
+NET "RXD" LOC = "p74" ;
+NET "TXD" LOC = "p58" ;
Index: trunk/Makefile
===================================================================
--- trunk/Makefile (nonexistent)
+++ trunk/Makefile (revision 6)
@@ -0,0 +1,95 @@
+SHELL=/bin/sh
+MAKE=make
+CUR_DIR=$(shell pwd)
+home=$(CUR_DIR)/..
+design=socgen
+
+
+all: run_sims build_fpgas check_sims check_fpgas
+
+
+
+
+
+.PHONY build_hw:
+build_hw:
+ @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ echo "################################################"; \
+ echo "build_hw: $$PROJECT ####"; echo; \
+ cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ ${MAKE} group_build_hw;\
+ done; \
+
+.PHONY build_sw:
+build_sw: build_hw
+ @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ echo "################################################"; \
+ echo "build_sw: $$PROJECT ####"; echo; \
+ cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ ${MAKE} group_build_sw;\
+ done; \
+
+.PHONY run_sims:
+run_sims: build_sw
+ @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ echo "################################################"; \
+ echo "run_sims: $$PROJECT ####"; echo; \
+ cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ ${MAKE} group_run_sims;\
+ done; \
+
+.PHONY build_fpgas:
+build_fpgas:
+ @for PROJECT in `ls $(CUR_DIR)/projects`; do \
+ echo "################################################"; \
+ echo "build_fpgas: $$PROJECT ####"; echo; \
+ cd ${home}/${design}_cmp/projects/$$PROJECT/bin;\
+ ${MAKE} group_build_fpgas;\
+ done; \
+
+.PHONY check_sims:
+check_sims:
+ (\
+ cd ${home}/${design}_cmp ;\
+ echo " number of sims run";\
+ find . | grep dut| grep -v children | wc -l ;\
+ echo " number of sims that finished";\
+ find . | grep _sim.log | xargs grep PASSED $1 | wc -l ;\
+ echo " number of warnings";\
+ find . | grep _sim.log | xargs grep WARNING $1 | wc -l ;\
+ echo " number of errors";\
+ find . | grep _sim.log | xargs grep ERROR $1 | wc -l ;\
+ )
+
+
+.PHONY check_fpgas:
+check_fpgas:
+ (\
+ cd ${home}/${design}_cmp ;\
+ echo " number of fpgas";\
+ find . | grep def_file | wc ;\
+ echo " number that finished";\
+ find . | grep bitstream.svf |wc ;\
+ )
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
trunk/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property