Subversion Repositories socgen

/trunk/tools/etc/udev/rules.d/40-basic-permissions.rules File deleted

/trunk/tools/Jtag_programmers/etc/udev/rules.d/xusbdfwu.rules

/trunk/tools/install/msp430-gcc-4.4.3/Readme.txt File deleted

/trunk/tools/install/msp430-gcc-4.4.3/Makefile File deleted

/trunk/tools/bin/build_geda

trunk/tools/bin/build_geda Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/soc_link_1 =================================================================== --- trunk/tools/bin/soc_link_1 (revision 87) +++ trunk/tools/bin/soc_link_1 (revision 88) @@ -132,7 +132,7 @@ &link_dir( "${home}/targets/${chip_target}", "${home}/${prefix}/ip/${component}/syn/${chip}/target" ); &link_dir( "${home}/lib", "${home}/${prefix}/ip/${component}/syn/${chip}/target/lib/syn" ); - + &link_dir( "${home}/tools/Jtag_programmers/debug", "${home}/${prefix}/ip/${component}/syn/${chip}/debug" ); }

/trunk/tools/bin/soc_link_2

/trunk/tools/bin/build_verilog

/trunk/tools/bin/soc_builder

/trunk/tools/bin/Makefile.root

/trunk/tools/bin/soc_link

/trunk/tools/bin/build_filelists

/trunk/projects/Testbench/soc/library.soc

/trunk/projects/Testbench/bin/repeater

trunk/projects/Testbench/bin/repeater Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml =================================================================== --- trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/rtl/xml/ps2_host.xml (revision 88) @@ -0,0 +1,184 @@ + + + + +opencores.org +Testbench +ps2_host + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + ps2_host + + + variant + ps2_host + + + + + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + +clk +wire +input + + +reset +wire +input + + + +busy +wire +input + + +rx_read +wire +input + + + +rx_full +wire +input + + +rx_parity_error +wire +input + + +rx_parity_rcv +wire +input + + +rx_parity_cal +wire +input + + +rx_frame_error +wire +input + + +rx_clr +wire +output + + + + +tx_write +wire +output + + + +output reg [7:0] tx_data, +inout wire [7:0] rx_data, + + + + + + + + + + + + + + + fs-sim + + + + + ../verilog/top + verilogSourceTop + + + + + ../verilog/ps2h_probe + verilogSource + + + + + + + + + + + + + + Index: trunk/projects/Testbench/ip/ps2_host/rtl/verilog/top =================================================================== --- trunk/projects/Testbench/ip/ps2_host/rtl/verilog/top (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/rtl/verilog/top (revision 88) @@ -0,0 +1,179 @@ + +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* ps2 host model for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + + +module ps2_host + +( +input wire clk, +input wire reset, +input wire busy, + +inout wire [7:0] rx_data, +input wire rx_read, +input wire rx_full, +input wire rx_parity_error, +input wire rx_parity_rcv, +input wire rx_parity_cal, +input wire rx_frame_error, +inout wire tx_ack_error, + +output reg rx_clr, +output reg [7:0] tx_data, +output reg tx_write +); + + +reg exp_tx_ack_err; +reg mask_tx_ack_err; + +reg [7:0] exp_rcv_byte; +reg [7:0] mask_rcv_byte; + + +task automatic next; + input [31:0] num; + repeat (num) @ (posedge clk); +endtask + + + +always@(posedge clk) + if(reset) + begin + tx_data <= 8'h00; + tx_write <= 1'b0; + rx_clr <= 1'b0; + exp_tx_ack_err <= 1'b0; + mask_tx_ack_err <= 1'b0; + exp_rcv_byte <= 8'h00; + mask_rcv_byte <= 8'h00; + + + + end + + +task clear_rx_host; + begin + rx_clr <= 1'b1; + next(1); + rx_clr <= 1'b0; + end +endtask + + + + +task send_byte; + input [7:0] byte_out; + begin + $display("%t %m %2h",$realtime ,byte_out ); + tx_data <= byte_out; + next(1); + tx_write <= 1'b1; + next(1); + tx_write <= 1'b0; + next(1); + while(busy) next(1); + mask_tx_ack_err <= 1'b1; + next(1); + mask_tx_ack_err <= 1'b0; + end +endtask // send_byte + + + + +ps2h_probe +#( .MESG("ps2_host tx_ack error") + ) +tx_ack_err_tpb +( + .clk ( clk ), + .drive_value ( 1'bz ), + .expected_value ( exp_tx_ack_err ), + .mask ( mask_tx_ack_err ), + .signal ( tx_ack_error ) +); + + + + + +task rcv_byte; + input [7:0] byte_in; + begin + exp_rcv_byte <= byte_in; + + while(!rx_read) next(1); + $display("%t checking %h",$realtime,byte_in); + mask_rcv_byte <= 8'hff; + next(1); + mask_rcv_byte <= 8'h00; +end +endtask + + + + +ps2h_probe +#( .MESG("ps2_host receive error"), + .WIDTH (8) + ) +rcv_byte_tpb +( + .clk ( clk ), + .drive_value ( {8{1'bz}} ), + .expected_value ( exp_rcv_byte ), + .mask ( mask_rcv_byte ), + .signal ( rx_data ) +); + + + + +endmodule + Index: trunk/projects/Testbench/ip/ps2_host/rtl/verilog/ps2h_probe =================================================================== --- trunk/projects/Testbench/ip/ps2_host/rtl/verilog/ps2h_probe (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/rtl/verilog/ps2h_probe (revision 88) @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* io_probe for handling timing delays in dut */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + +module ps2h_probe +#(parameter MESG = " ", + parameter WIDTH = 1, + parameter RESET = {WIDTH{1'bz}}, + parameter IN_DELAY = 5, + parameter OUT_DELAY = 15, + parameter OUT_WIDTH = 10 + ) +( +input wire clk, + +input wire [WIDTH-1:0] drive_value, +input wire [WIDTH-1:0] expected_value, +input wire [WIDTH-1:0] mask, + +inout wire [WIDTH-1:0] signal + + +); + + +reg [WIDTH-1:0] filtered_value; +reg [WIDTH:1] fail; + + + + + + +assign signal = drive_value; + + + + + + +always @(posedge clk) filtered_value <= signal; +always @(posedge clk) fail <= mask & (signal^ expected_value); + + + + + +initial + begin + cg.next(3); + while(1) + begin + if(fail !== {WIDTH{1'b0}}) + begin + $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); + cg.fail(MESG); + end + cg.next(1); + end // while (1) + end // initial begin + + + + + + + + +endmodule + + + Index: trunk/projects/Testbench/ip/ps2_host/soc/design.soc =================================================================== --- trunk/projects/Testbench/ip/ps2_host/soc/design.soc (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/soc/design.soc (revision 88) @@ -0,0 +1,41 @@ + + + + + + +ps2_host +ps2_host + + + + + + Index: trunk/projects/Testbench/ip/ps2_host/doc/copyright.v =================================================================== --- trunk/projects/Testbench/ip/ps2_host/doc/copyright.v (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/doc/copyright.v (revision 88) @@ -0,0 +1,43 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + Index: trunk/projects/Testbench/ip/ps2_host/bin/Makefile =================================================================== --- trunk/projects/Testbench/ip/ps2_host/bin/Makefile (nonexistent) +++ trunk/projects/Testbench/ip/ps2_host/bin/Makefile (revision 88) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml =================================================================== --- trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml (nonexistent) +++ trunk/projects/Testbench/ip/clock_gen/rtl/xml/clock_gen.xml (revision 88) @@ -0,0 +1,136 @@ + + + + +opencores.org +Testbench +clock_gen + + + + + + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + clock_gen + + + variant + clock_gen + + + + + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + +10 +0 + + + + +clk +reg +output + + +reset +reg +output + + + + + + + + + + + + + + + + fs-sim + + + + + ../verilog/top + verilogSourceTop + + + + + + + + + + + + + Index: trunk/projects/Testbench/ip/clock_gen/rtl/verilog/top =================================================================== --- trunk/projects/Testbench/ip/clock_gen/rtl/verilog/top (nonexistent) +++ trunk/projects/Testbench/ip/clock_gen/rtl/verilog/top (revision 88) @@ -0,0 +1,138 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + +`timescale 1ns/1ns + +module clock_gen +#(parameter PERIOD=10, + parameter TIMEOUT=0 + ) + (output reg clk, + output reg reset + ); + + + +`ifndef SYNTHESIS + +reg failed; +reg [31:0] fail_count; + + +task automatic next; + input [31:0] num; + repeat (num) @ (posedge clk); +endtask // next + + + +task reset_on; + reset = 1; +endtask // reset_on + + +task automatic fail; + input [799:0] message; + begin + failed = 1; + fail_count = fail_count+1; + $display("%t Simulation FAILURE: %s ",$realtime,message ); + end +endtask + + +task reset_off; + begin + reset = 0; + end +endtask // reset_off + + +task exit; + begin + if(failed) + begin + $display("%t Sim over: ERROR %d failures",$realtime ,fail_count ); + end + else + begin + $display("%t Sim over: PASSED",$realtime ); + end // else: !if(failed) + $dumpflush; + $finish; + end +endtask + + +initial +begin +clk=0; +reset=1; +failed=0; +fail_count =32'h00000000; +end + +always +#(PERIOD/2) clk = !clk; + + + +initial + begin + if(TIMEOUT) + begin + next(TIMEOUT); + $display("%t Sim over :ERROR TIMEOUT",$realtime ); + $finish; + end + + end + +`endif + + + +endmodule + + + Index: trunk/projects/Testbench/ip/clock_gen/soc/design.soc =================================================================== --- trunk/projects/Testbench/ip/clock_gen/soc/design.soc (nonexistent) +++ trunk/projects/Testbench/ip/clock_gen/soc/design.soc (revision 88) @@ -0,0 +1,41 @@ + + + + + + +clock_gen +clock_gen + + + + + + Index: trunk/projects/Testbench/ip/clock_gen/doc/copyright.v =================================================================== --- trunk/projects/Testbench/ip/clock_gen/doc/copyright.v (nonexistent) +++ trunk/projects/Testbench/ip/clock_gen/doc/copyright.v (revision 88) @@ -0,0 +1,43 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + Index: trunk/projects/Testbench/ip/clock_gen/bin/Makefile =================================================================== --- trunk/projects/Testbench/ip/clock_gen/bin/Makefile (nonexistent) +++ trunk/projects/Testbench/ip/clock_gen/bin/Makefile (revision 88) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml =================================================================== --- trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/rtl/xml/ps2_model.xml (revision 88) @@ -0,0 +1,151 @@ + + + + +opencores.org +Testbench +ps2_model + + + + + + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + ps2_model + + + variant + ps2_model + + + + + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + +10'h1f0 + + + + +clk +wire +input + + +reset +wire +input + + + +ps2_clk +wire +inout + + +ps2_data +wire +inout + + + + + + + + + + + + + + + + fs-sim + + + + + ../verilog/top + verilogSourceTop + + + + + ../verilog/ps2_probe + verilogSource + + + + + + + + + + + + + + Index: trunk/projects/Testbench/ip/ps2_model/rtl/verilog/top =================================================================== --- trunk/projects/Testbench/ip/ps2_model/rtl/verilog/top (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/rtl/verilog/top (revision 88) @@ -0,0 +1,388 @@ + +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* ps2 device model for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + + +module ps2_model + #(parameter CLKCNT = 10'h1f0) + +( +input wire clk, +input wire reset, +inout wire ps2_clk, +inout wire ps2_data + + +); + + +//******************************************************************** +//*** TAP Controller State Machine +//******************************************************************** + +// TAP state parameters +parameter RESET = 2'b00, + WAIT_63US = 2'b01, + CLOCK = 2'b10, + IDLE = 2'b11; + + + +reg device_rx_parity; +reg [7:0] device_rx_data; + +wire prb_device_rx_parity; +wire [7:0] prb_device_rx_data; + +wire device_rx_read; +reg ps2_data_out; +reg dev_host; +reg [1:0] tap_state, next_tap_state; +reg [9:0] count; +reg clk_out; +reg [4:0] bit_cnt; +reg ack; +reg [10:0] frame; +reg clk_fall; +reg clk_rise; +reg device_write; +reg [7:0] device_tx_data; +reg device_tx_parity; +reg device_ack; +reg device_stop; +reg [7:0] exp_device_rx_data; +reg [7:0] mask_device_rx_data; +reg exp_device_rx_parity; +reg mask_device_rx_parity; + + + + +initial + begin + device_write <= 1'b0; + device_tx_data <= 8'h00; + device_tx_parity <= 1'b0; + device_ack <= 1'b1; + device_stop <= 1'b1; + + exp_device_rx_data <= 8'h00; + mask_device_rx_data <= 8'h00; + exp_device_rx_parity <= 1'b0; + mask_device_rx_parity <= 1'b0; + + end + + +assign prb_device_rx_parity = device_rx_parity; +assign prb_device_rx_data = device_rx_data; + + + +task next; + input [31:0] num; + repeat (num) @ (posedge clk); +endtask + + +task send_byte; + input [7:0] byte_out; + +begin + while(tap_state != IDLE) next(1); + $display("%t %m %2h parity %b",$realtime ,byte_out,device_tx_parity ); + device_tx_data <= byte_out; + next(1); + device_write <= 1'b1; + next(1); + device_write <= 1'b0; +end +endtask // send_byte + + + + + + +task rcv_byte; + input [7:0] byte_in; + input parity; + begin + + exp_device_rx_data <= byte_in; + exp_device_rx_parity <= parity; + + while(!device_rx_read) next(1); + $display("%t checking %h %b",$realtime,byte_in,parity); + mask_device_rx_data <= 8'hff; + mask_device_rx_parity <= 1'b1; + next(1); + + mask_device_rx_data <= 8'h00; + mask_device_rx_parity <= 1'b0; + + +end +endtask + + + + +ps2_probe +#(.MESG ( "ps2 data receive error"), + .WIDTH ( 8)) +device_rx_data_tpb ( + .clk ( clk ), + .drive_value (8'bzzzzzzzz ), + .expected_value ( exp_device_rx_data ), + .mask ( mask_device_rx_data ), + .signal ( prb_device_rx_data ) + ); + + + + + +ps2_probe +#(.MESG ( "ps2 parity receive error")) +device_rx_parity_tpb ( + .clk ( clk ), + .drive_value (1'bz ), + .expected_value ( exp_device_rx_parity ), + .mask ( mask_device_rx_parity ), + .signal ( prb_device_rx_parity ) + ); + + + + +assign ps2_clk = clk_out ? 1'b0 : 1'bz ; +assign ps2_data = ps2_data_out ? 1'b0 : 1'bz ; + + + + + + + + +always @(posedge clk or posedge reset ) + begin + if (reset) + begin + tap_state <= RESET; + ps2_data_out <= 1'b0; + end + else + begin + tap_state <= next_tap_state; + ps2_data_out <= ( (tap_state == CLOCK) && (dev_host? frame[0] : ack) ); + end + end + + + +always @(posedge clk or posedge reset ) + begin + if (reset) dev_host <= 1'b0; + else + if( device_write) dev_host <= 1'b1; + else + if( bit_cnt == 5'h16 ) dev_host <= 1'b0; + else dev_host <= dev_host ; + end + + + +always@(*) ack = (((bit_cnt == 5'h14)|| (bit_cnt == 5'h15)) && device_ack ) ; + + + + +// next state decode for tap controller +always @(*) + begin + if(device_write) next_tap_state = CLOCK; + else + case (tap_state) // synopsys parallel_case + RESET: + begin + next_tap_state = ps2_clk ? RESET : WAIT_63US ; + end + + WAIT_63US: + begin + next_tap_state = ps2_clk ? CLOCK : WAIT_63US ; + end + + CLOCK: + begin + next_tap_state = ((bit_cnt == 5'h16)&& (count == 10'h000)) ? IDLE : CLOCK; + end + + IDLE: + begin + next_tap_state = ps2_data ? IDLE : WAIT_63US; + end + endcase + end + + + + +always @(posedge clk or posedge reset ) + begin + if (reset) + begin + count <= CLKCNT; + clk_out <= 1'b0; + bit_cnt <= 5'h00; + clk_fall <= 1'b0; + clk_rise <= 1'b0; + end + else + if((next_tap_state != CLOCK)) + begin + count <= CLKCNT; + clk_out <= 1'b0; + bit_cnt <= 5'h00; + clk_fall <= 1'b0; + clk_rise <= 1'b0; + end + else + if((count == 10'h000) ) + begin + count <= CLKCNT; + clk_out <= !clk_out; + bit_cnt <= bit_cnt+5'b0001; + clk_fall <= !clk_out; + clk_rise <= clk_out; + end + else + begin + count <= count - 10'h001; + clk_out <= clk_out; + bit_cnt <= bit_cnt; + clk_fall <= 1'b0; + clk_rise <= 1'b0; + end + end + + + + + +always @(posedge clk or posedge reset ) + begin + if (reset) + begin + frame <= {device_ack,10'h000}; + end + else + if(device_write) + begin + frame <= {!device_stop,device_tx_parity,~device_tx_data,1'b1}; + end + else + if((tap_state == WAIT_63US) || (tap_state == IDLE)) + begin + frame <= {device_ack,10'h000}; + end + else + if((tap_state == CLOCK) && clk_fall && !dev_host ) frame <= { ps2_data,frame[10:1]}; + else + if((tap_state == CLOCK) && clk_rise && dev_host ) frame <= { 1'b0,frame[10:1]}; + else frame <= frame; + end + + + + +always @(posedge clk or posedge reset ) + begin + if (reset) + begin + device_rx_data <= 8'h00; + device_rx_parity <= 1'b0; + end + else + if(tap_state == WAIT_63US) + begin + device_rx_data <= 8'h00; + device_rx_parity <= 1'b0; + end + + else + if((bit_cnt == 5'h12) && clk_rise) + begin + device_rx_data <= frame[10:3]; + device_rx_parity <= ps2_data; + end + else + begin + device_rx_data <= device_rx_data; + device_rx_parity <= device_rx_parity; + end + + end + + + +assign device_rx_read = (bit_cnt == 5'h13) && !dev_host && clk_fall; + + +always@(posedge clk) + if( device_rx_read) + $display ("%t %m device rec %h parity %b",$realtime,device_rx_data,device_rx_parity); + +always@(posedge clk) + if(device_write) + $display ("%t %m device send %h parity %b stop %b ",$realtime,device_tx_data,device_tx_parity,device_stop); + + + + + +endmodule + Index: trunk/projects/Testbench/ip/ps2_model/rtl/verilog/ps2_probe =================================================================== --- trunk/projects/Testbench/ip/ps2_model/rtl/verilog/ps2_probe (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/rtl/verilog/ps2_probe (revision 88) @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* io_probe for handling timing delays in dut */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + +module ps2_probe +#(parameter MESG = " ", + parameter WIDTH = 1, + parameter RESET = {WIDTH{1'bz}}, + parameter IN_DELAY = 5, + parameter OUT_DELAY = 15, + parameter OUT_WIDTH = 10 + ) +( +input wire clk, + +input wire [WIDTH-1:0] drive_value, +input wire [WIDTH-1:0] expected_value, +input wire [WIDTH-1:0] mask, + +inout wire [WIDTH-1:0] signal + + +); + + +reg [WIDTH-1:0] filtered_value; +reg [WIDTH:1] fail; + + + + + + +assign signal = drive_value; + + + + + + +always @(posedge clk) filtered_value <= signal; +always @(posedge clk) fail <= mask & (signal^ expected_value); + + + + + +initial + begin + cg.next(3); + while(1) + begin + if(fail !== {WIDTH{1'b0}}) + begin + $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); + cg.fail(MESG); + end + cg.next(1); + end // while (1) + end // initial begin + + + + + + + + +endmodule + + + Index: trunk/projects/Testbench/ip/ps2_model/soc/design.soc =================================================================== --- trunk/projects/Testbench/ip/ps2_model/soc/design.soc (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/soc/design.soc (revision 88) @@ -0,0 +1,41 @@ + + + + + + +ps2_model +ps2_model + + + + + + Index: trunk/projects/Testbench/ip/ps2_model/doc/copyright.v =================================================================== --- trunk/projects/Testbench/ip/ps2_model/doc/copyright.v (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/doc/copyright.v (revision 88) @@ -0,0 +1,43 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + Index: trunk/projects/Testbench/ip/ps2_model/bin/Makefile =================================================================== --- trunk/projects/Testbench/ip/ps2_model/bin/Makefile (nonexistent) +++ trunk/projects/Testbench/ip/ps2_model/bin/Makefile (revision 88) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml =================================================================== --- trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/rtl/xml/uart_host.xml (revision 88) @@ -0,0 +1,154 @@ + + + + +opencores.org +Testbench +uart_host + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + ps2_host + + + variant + ps2_host + + + + + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + +clk +wire +input + + +reset +wire +input + + + + + + + +output reg parity_enable, +output reg txd_parity, +output reg txd_force_parity, +output reg [7:0] txd_data_in, +input wire txd_buffer_empty, +output reg txd_load, +output reg txd_break, +output reg rxd_parity, +output reg rxd_force_parity, +output reg rxd_data_avail_stb, +inout wire [7:0] rxd_data_out, +input wire rxd_data_avail, +inout wire rxd_stop_error, +inout wire rxd_parity_error + + + + + + + + + + + + + + + + + + fs-sim + + + + + ../verilog/top + verilogSourceTop + + + + + ../verilog/uarth_probe + verilogSource + + + + + + + + + + + + + + Index: trunk/projects/Testbench/ip/uart_host/rtl/verilog/top =================================================================== --- trunk/projects/Testbench/ip/uart_host/rtl/verilog/top (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/rtl/verilog/top (revision 88) @@ -0,0 +1,211 @@ + +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* uart host model for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + + +module uart_host ( +input wire clk, +input wire reset, +output reg parity_enable, +output reg txd_parity, +output reg txd_force_parity, +output reg [7:0] txd_data_in, +input wire txd_buffer_empty, +output reg txd_load, +output reg txd_break, +output reg rxd_parity, +output reg rxd_force_parity, +output reg rxd_data_avail_stb, +inout wire [7:0] rxd_data_out, +input wire rxd_data_avail, +inout wire rxd_stop_error, +inout wire rxd_parity_error +); + +reg exp_rxd_stop_error; +reg exp_rxd_parity_error; +reg [7:0] exp_rxd_data_out; + +reg mask_rxd_stop_error; +reg mask_rxd_parity_error; +reg [7:0] mask_rxd_data_out; + + + + + +task automatic next; + input [31:0] num; + repeat (num) @ (posedge clk); +endtask + + + +always@(posedge clk) +if(reset) + begin + parity_enable <= 1'b0; + txd_data_in <= 8'h00; + txd_parity <= 1'b0; + txd_force_parity <= 1'b0; + txd_load <= 1'b0; + txd_break <= 1'b0; + rxd_parity <= 1'b0; + rxd_force_parity <= 1'b0; + rxd_data_avail_stb <= 1'b0; + exp_rxd_stop_error <= 1'b0; + exp_rxd_parity_error <= 1'b0; + exp_rxd_data_out <= 8'h00; + + mask_rxd_stop_error <= 1'b0; + mask_rxd_parity_error <= 1'b0; + mask_rxd_data_out <= 8'h00; + + + end + + +task clear_rx_host; + begin + next(1); + end +endtask + + + + +task send_byte; + input [7:0] byte_out; + + begin + while(!txd_buffer_empty) next(1); + $display("%t %m %2h",$realtime ,byte_out); + txd_data_in <= byte_out; + next(1); + txd_load <= 1'b1; + next(1); + txd_load <= 1'b0; + next(1); + end +endtask // send_byte + + + +task rcv_byte; + input [7:0] byte_in; + begin + exp_rxd_data_out <= byte_in; + while(!rxd_data_avail) next(1); + $display("%t %m checking %h",$realtime,byte_in); + mask_rxd_stop_error <= 1'b1; + mask_rxd_parity_error <= 1'b1; + mask_rxd_data_out <= 8'hff; + next(1); + mask_rxd_stop_error <= 1'b0; + mask_rxd_parity_error <= 1'b0; + mask_rxd_data_out <= 8'h00; + rxd_data_avail_stb <= 1'b1; + next(1); + rxd_data_avail_stb <= 1'b0; + next(1); +end +endtask + + +uarth_probe +#(.MESG("uart_host receive error"), + .WIDTH(8)) +rxd_data_out_prb +( + .clk ( clk ), + .drive_value (8'bzzzzzzzz ), + .expected_value ( exp_rxd_data_out ), + .mask ( mask_rxd_data_out ), + .signal ( rxd_data_out ) + + +); + + + + + + +uarth_probe +#(.MESG("uart_host stop error")) +rxd_stop_error_prb +( + .clk ( clk ), + .drive_value (1'bz ), + .expected_value ( exp_rxd_stop_error ), + .mask ( mask_rxd_stop_error ), + .signal ( rxd_stop_error ) + + +); + + + + +uarth_probe +#(.MESG("uart_host parity error")) +rxd_parity_error_prb +( + .clk ( clk ), + .drive_value (1'bz ), + .expected_value ( exp_rxd_parity_error ), + .mask ( mask_rxd_parity_error ), + .signal ( rxd_parity_error ) + + +); + + + + + + + +endmodule + Index: trunk/projects/Testbench/ip/uart_host/rtl/verilog/uarth_probe =================================================================== --- trunk/projects/Testbench/ip/uart_host/rtl/verilog/uarth_probe (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/rtl/verilog/uarth_probe (revision 88) @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* io_probe for handling timing delays in dut */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + +module uarth_probe +#(parameter MESG = " ", + parameter WIDTH = 1, + parameter RESET = {WIDTH{1'bz}}, + parameter IN_DELAY = 5, + parameter OUT_DELAY = 15, + parameter OUT_WIDTH = 10 + ) +( +input wire clk, + +input wire [WIDTH-1:0] drive_value, +input wire [WIDTH-1:0] expected_value, +input wire [WIDTH-1:0] mask, + +inout wire [WIDTH-1:0] signal + + +); + + +reg [WIDTH-1:0] filtered_value; +reg [WIDTH:1] fail; + + + + + + +assign signal = drive_value; + + + + + + +always @(posedge clk) filtered_value <= signal; +always @(posedge clk) fail <= mask & (signal^ expected_value); + + + + + +initial + begin + cg.next(3); + while(1) + begin + if(fail !== {WIDTH{1'b0}}) + begin + $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); + cg.fail(MESG); + end + cg.next(1); + end // while (1) + end // initial begin + + + + + + + + +endmodule + + + Index: trunk/projects/Testbench/ip/uart_host/soc/design.soc =================================================================== --- trunk/projects/Testbench/ip/uart_host/soc/design.soc (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/soc/design.soc (revision 88) @@ -0,0 +1,41 @@ + + + + + + +uart_host +uart_host + + + + + + Index: trunk/projects/Testbench/ip/uart_host/doc/copyright.v =================================================================== --- trunk/projects/Testbench/ip/uart_host/doc/copyright.v (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/doc/copyright.v (revision 88) @@ -0,0 +1,43 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + Index: trunk/projects/Testbench/ip/uart_host/bin/Makefile =================================================================== --- trunk/projects/Testbench/ip/uart_host/bin/Makefile (nonexistent) +++ trunk/projects/Testbench/ip/uart_host/bin/Makefile (revision 88) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/xml/uart_model.xml (revision 88) @@ -0,0 +1,174 @@ + + + + +opencores.org +Testbench +uart_model + + + + + + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + uart_model + + + variant + uart_model + + + + + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + +4'h5 +4 + + + + +clk +wire +input + + +reset +wire +input + + + +txd_in +wire +input + + +rxd_out +wire +output + + + + + + + + + + + + + + + + fs-sim + + + + + ../verilog/top + verilogSourceTop + + + + + ../verilog/serial_rcvr + verilogSource + + + + + ../verilog/serial_xmit + verilogSource + + + + + + ../verilog/divider + verilogSource + + + + + + ../verilog/io_probe + verilogSource + + + + + + + + + + + + + + Index: trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_xmit =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_xmit (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_xmit (revision 88) @@ -0,0 +1,181 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / LIB \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Generic model for a serial asynchronous transmitter */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + +module +uart_model_serial_xmit +#(parameter WIDTH=8, // Number of data bits + parameter SIZE=4 // binary size of shift_cnt, must be able to hold WIDTH + 4 states + ) + + +( +input wire clk, +input wire reset, +input wire edge_enable, // one pulse per bit time for data rate timing +input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent +input wire two_stop_enable, // 0 = 1 stop bit, 1 = 2 stop bits +input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1 +input wire load, // start transmiting data +input wire start_value, // value out at start bit time +input wire stop_value, // value out for stop bit also used for break +input wire [WIDTH-1:0] data, // data byte + +output reg buffer_empty, // ready for next byte +output reg ser_out // to pad_ring + ); + +reg [SIZE-1:0] shift_cnt; +reg [WIDTH-1:0] shift_buffer; +reg parity_calc; +reg delayed_edge_enable; + + +// +// shift_cnt controls the serial bit out +// +// 0 Start bit +// 1-> WIDTH Data bit lsb first +// WIDTH+1 Parity bit if enabled +// 2^SIZE-2 Second stop bit if enabled +// 2^SIZE-1 Last stop bit and idle + +always@(posedge clk) + if(reset || buffer_empty) shift_cnt <= {SIZE{1'b1}}; + else + if(!edge_enable) shift_cnt <= shift_cnt; + else + if(( shift_cnt == {SIZE{1'b1}} ) && ! buffer_empty ) shift_cnt <= {SIZE{1'b0}}; + else + if ( shift_cnt == WIDTH) + case({two_stop_enable,parity_enable}) + (2'b00): shift_cnt <= {SIZE{1'b1}}; + (2'b01): shift_cnt <= shift_cnt + 1'b1; + (2'b10): shift_cnt <= {SIZE{1'b1}} - 1'b1; + (2'b11): shift_cnt <= shift_cnt + 1'b1; + endcase // case ({two_stop_enable,parity_enable}) + else + if ( shift_cnt == (WIDTH+1)) + case( two_stop_enable) + (1'b0): shift_cnt <= {SIZE{1'b1}}; + (1'b1): shift_cnt <= {SIZE{1'b1}} - 1'b1; + endcase + else shift_cnt <= shift_cnt + 1'b1; + +// +// +// Clear buffer_empty upon load pulse +// set it back at the start of the final stop pulse +// if load happens BEFORE the next edge_enable then data transfer will have no pauses +// logic ensures that having load happen on a edge_enable will work +// + +always@(posedge clk) + if(reset) delayed_edge_enable <= 1'b0; + else delayed_edge_enable <= edge_enable && ! load; + + +always@(posedge clk) +if(reset) buffer_empty <= 1'b1; +else +if(load) buffer_empty <= 1'b0; +else +if((shift_cnt == {SIZE{1'b1}}) && delayed_edge_enable) + buffer_empty <= 1'b1; +else buffer_empty <= buffer_empty; + + + + + +// +// +// load shift_buffer during start_bit +// shift down every bit +// +// +always@(posedge clk) + if(reset) shift_buffer <= {WIDTH{1'b0}}; + else + if(!edge_enable) shift_buffer <= shift_buffer; + else + if(shift_cnt == {SIZE{1'b0}}) shift_buffer <= data; + else shift_buffer <= {1'b0,shift_buffer[WIDTH-1:1]}; + + + + + + +// +// +// calculate parity on the fly +// seed reg with 0 for odd and 1 for even +// force reg to 0 or 1 if needed +// +always@(posedge clk) + if(reset) parity_calc <= 1'b0; + else + if(!edge_enable) parity_calc <= parity_calc; + else + if(parity_type[1] || (shift_cnt == {SIZE{1'b0}})) parity_calc <= parity_type[0]; + else parity_calc <= parity_calc ^ shift_buffer[0]; + + +// send start_bit,data,parity and stop based on shift_cnt + + + always@(posedge clk) + if(reset) ser_out <= stop_value; + else + if( shift_cnt == {SIZE{1'b0}} ) ser_out <= start_value; + else + if( shift_cnt == {SIZE{1'b1}} ) ser_out <= stop_value; + else + if( shift_cnt == ({SIZE{1'b1}}+1'b1) ) ser_out <= stop_value; + else + if( shift_cnt == (WIDTH+1) ) ser_out <= parity_calc; + else ser_out <= shift_buffer[0]; + + +endmodule + + Index: trunk/projects/Testbench/ip/uart_model/rtl/verilog/top =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/verilog/top (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/verilog/top (revision 88) @@ -0,0 +1,408 @@ + +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* uart device model for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + +`timescale 1ns/1ns + +module uart_model + #(parameter CLKCNT = 4'h5, + parameter SIZE = 4) + +( +input wire clk, +input wire reset, +input wire txd_in, +output wire rxd_out + +); + + + + +reg rx_parity_enable; // 0 = no parity bit sent; 1= parity bit sent +reg rx_parity ; +reg rx_force_parity ; +reg rx_stop_value; // value out for stop bit +reg rx_start_detect; +reg [7:0] rx_shift_buffer; +reg rx_parity_calc; +reg rx_parity_samp; +reg rx_parity_error; +reg rx_frame_err; +reg [7:0] exp_rx_shift_buffer; +reg exp_rx_parity_err; +reg exp_rx_frame_err; +reg [7:0] mask_rx_shift_buffer; +reg mask_rx_parity_err; +reg mask_rx_frame_err; + + +reg rx_frame_rdy; + + +reg rx_baud_enable; +wire rx_stop_cnt; +wire rx_last_cnt; +wire [7:0] next_rx_shift_buffer; +wire next_rx_parity_calc; +wire next_rx_parity_samp; +wire next_rx_frame_err; + + +reg rxd_pad_sig; +reg [1:0] rx_rdy_del; +reg [SIZE-1:0] rx_baudgen; +reg edge_enable; +reg [SIZE-1:0] divide_cnt; + + + wire xmit_enable; +reg txd_parity_enable; +reg txd_force_parity; +reg txd_parity; +reg txd_load; +reg txd_break; +reg [7:0] txd_data_in; +wire txd_buffer_empty; + + +// +// watch for start bit +// + + + +always@(posedge clk) + if(reset) + begin + rx_parity_enable <= 1'b0; + rx_parity <= 1'b0; + rx_force_parity <= 1'b0; + rx_stop_value <= 1'b1; + exp_rx_frame_err <= 1'b0; + exp_rx_parity_err <= 1'b0; + exp_rx_shift_buffer <= 8'h00; + mask_rx_frame_err <= 1'b0; + mask_rx_parity_err <= 1'b0; + mask_rx_shift_buffer <= 8'h00; + txd_parity_enable <= 1'b0; + txd_force_parity <= 1'b0; + txd_parity <= 1'b0; + txd_load <= 1'b0; + txd_break <= 1'b0; + txd_data_in <= 8'h00; + end + + + + +task next; + input [31:0] num; + repeat (num) @ (posedge clk); +endtask + + + + +task wait_tx; + +begin + while(!txd_buffer_empty) next(1); +end +endtask // wait_tx + + + +task send_byte; + input [7:0] byte_out; + +begin + while(!txd_buffer_empty) next(1); + $display("%t %m %2h",$realtime ,byte_out ); + txd_data_in = byte_out; + next(1); + txd_load = 1'b1; + next(1); + txd_load = 1'b0; + next(1); +end +endtask // send_byte + + +task rcv_byte; + input [7:0] byte_in; + begin + exp_rx_shift_buffer <= byte_in; + while(!rx_frame_rdy) next(1); + $display("%t %m check %h %h ",$realtime,rx_shift_buffer,byte_in); + mask_rx_frame_err <= 1'b1; + mask_rx_parity_err <= 1'b1; + mask_rx_shift_buffer <= 8'hff; + next(1); + mask_rx_frame_err <= 1'b0; + mask_rx_parity_err <= 1'b0; + mask_rx_shift_buffer <= 8'h00; +end +endtask + + +wire [7:0] prb_rx_shift_buffer; +wire prb_rx_frame_err; +wire prb_rx_parity_err; + +assign prb_rx_shift_buffer = rx_shift_buffer; +assign prb_rx_frame_err = rx_frame_err; +assign prb_rx_parity_err = rx_parity_error; + + +io_probe +#(.MESG ("uart data receive error"), + .WIDTH (8) + ) +rx_shift_buffer_prb +( + .clk ( clk ), + .drive_value (8'bzzzzzzzz), + .expected_value( exp_rx_shift_buffer), + .mask ( mask_rx_shift_buffer), + .signal ( prb_rx_shift_buffer) +); + + +io_probe +#(.MESG ("uart parity error")) +rx_parity_err_prb +( + .clk ( clk ), + .drive_value (1'bz), + .expected_value( exp_rx_parity_err), + .mask ( mask_rx_parity_err), + .signal ( prb_rx_parity_err) +); + + + + + + + + + + + + +always@(posedge clk) +if(reset) rx_baudgen <= CLKCNT; +else +if(rx_baudgen == 4'h0) rx_baudgen <= CLKCNT; +else rx_baudgen <= rx_baudgen - 1'h1; + + + +always@(posedge clk) +if(reset) edge_enable <= 1'b0; +else edge_enable <= (rx_baudgen == {SIZE{1'b0}}); + + + + + + +always@(posedge clk) +if(reset) rxd_pad_sig <= 1'b1; +else rxd_pad_sig <= txd_in; + + +always@(posedge clk) +if(reset) rx_start_detect <= 1'b0; +else +if(rx_start_detect) + begin + if(rx_stop_cnt && edge_enable ) rx_start_detect <= !rxd_pad_sig; + else + if(rx_last_cnt) rx_start_detect <= 1'b0; + else rx_start_detect <= 1'b1; + end +else +if(!rxd_pad_sig ) rx_start_detect <= 1'b1; +else rx_start_detect <= rx_start_detect; + + +always@(posedge clk) + if(reset) + begin + rx_frame_rdy <= 1'b0; + rx_rdy_del <= 2'b00; + end + else + begin + rx_frame_rdy <= rx_rdy_del[1] ; + rx_rdy_del <= {rx_rdy_del[0],rx_last_cnt}; + end + + +uart_model_serial_rcvr +#(.WIDTH(8), .SIZE(4) ) +serial_rcvr + ( + .clk ( clk ), + .reset ( reset ), + .edge_enable ( rx_baud_enable ), + .parity_enable ( rx_parity_enable ), + .parity_type ( {rx_force_parity, rx_parity } ), + .stop_cnt ( rx_stop_cnt ), + .last_cnt ( rx_last_cnt ), + .stop_value ( rx_stop_value ), + .ser_in ( txd_in ), + .shift_buffer ( next_rx_shift_buffer ), + .parity_calc ( next_rx_parity_calc ), + .parity_samp ( next_rx_parity_samp ), + .frame_err ( next_rx_frame_err ) +); + + + + + + + + +always@(posedge clk) + if( reset || (!rx_start_detect)) rx_baud_enable <= 1'b0; + else + if(!edge_enable) rx_baud_enable <= 1'b0; + else rx_baud_enable <= ( divide_cnt == 4'b1000 ); + + + +always@(posedge clk) + if( reset || (!rx_start_detect)) divide_cnt <= 4'b1111; + else + if(!edge_enable) divide_cnt <= divide_cnt; + else + if(!(|divide_cnt)) divide_cnt <= 4'b1111; + else divide_cnt <= divide_cnt - 'b1; + + + + + + +always@(posedge clk) + if(reset) + begin + rx_shift_buffer <= 8'h00; + rx_parity_calc <= 1'b0; + rx_parity_samp <= 1'b0; + rx_parity_error <= 1'b0; + rx_frame_err <= 1'b0; + end + else + if(rx_last_cnt ) + begin + rx_shift_buffer <= next_rx_shift_buffer; + rx_parity_calc <= next_rx_parity_calc; + rx_parity_samp <= next_rx_parity_samp; + rx_parity_error <= (next_rx_parity_samp ^ next_rx_parity_calc) && rx_parity_enable; + rx_frame_err <= next_rx_frame_err; + end + else + begin + rx_shift_buffer <= rx_shift_buffer; + rx_parity_calc <= rx_parity_calc; + rx_parity_samp <= rx_parity_samp; + rx_parity_error <= rx_parity_error; + rx_frame_err <= rx_frame_err; + end + + +///////////////// Xmit + + + + + + + + + + + +uart_model_divider +#(.SIZE(4)) +x_divider ( + .clk ( clk ), + .reset ( reset ), + .divider_in ( 4'b1111 ), + .enable ( edge_enable ), + .divider_out ( xmit_enable ) + ); + + + + + +uart_model_serial_xmit +serial_xmit ( + .clk ( clk ), + .reset ( reset ), + .edge_enable ( xmit_enable ), + .parity_enable ( txd_parity_enable ), + .two_stop_enable ( 1'b0 ), + .parity_type ( {txd_force_parity, txd_parity } ), + .load ( txd_load ), + .start_value ( 1'b0 ), + .stop_value (!txd_break ), + .data ( txd_data_in ), + .buffer_empty ( txd_buffer_empty ), + .ser_out ( rxd_out ) + ); + + + + + + + +endmodule + Index: trunk/projects/Testbench/ip/uart_model/rtl/verilog/divider =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/verilog/divider (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/verilog/divider (revision 88) @@ -0,0 +1,87 @@ + +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / LIB \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Generic model for a rate divider */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + + +module +uart_model_divider + +#(parameter SIZE=4, + parameter SAMPLE=0, + parameter RESET=1 + ) +( +input wire clk, +input wire reset, +input wire enable, +input wire [SIZE-1:0] divider_in, +output reg divider_out + ); + +reg [SIZE-1:0] divide_cnt; + +always@(posedge clk) + if(reset) divider_out <= RESET; + else + if(!enable) divider_out <= 1'b0; + else divider_out <= ( divide_cnt == SAMPLE ); + + + +always@(posedge clk) + if(reset) divide_cnt <= divider_in; + else + if(!enable) divide_cnt <= divide_cnt; + else + if(!(|divide_cnt)) divide_cnt <= divider_in; + else divide_cnt <= divide_cnt - 'b1; + + + + + + +endmodule + + + Index: trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_rcvr =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_rcvr (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/verilog/serial_rcvr (revision 88) @@ -0,0 +1,183 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / LIB \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Generic model for a serial asynchronous receiver */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + +module +uart_model_serial_rcvr +#(parameter WIDTH=8, // Number of data bits + parameter SIZE=4 // binary size of shift_cnt, must be able to hold WIDTH + 4 states + )( +input wire clk, +input wire reset, +input wire edge_enable, // one pulse per bit time for 16 x data rate timing +input wire parity_enable, // 0 = no parity bit sent, 1= parity bit sent +input wire [1:0] parity_type, // 00= odd,01=even,10=force a 0,11= force a 1 +input wire stop_value, // value out for stop bit +input wire ser_in, // from pad_ring +output reg [WIDTH-1:0] shift_buffer, +output reg stop_cnt, +output reg last_cnt, +output reg parity_calc, +output reg parity_samp, +output reg frame_err + +); + +reg [SIZE-1:0] shift_cnt; + +// +// shift_cnt controls the serial bit out +// +// 0 Start bit +// 1-> WIDTH Data bit lsb first +// WIDTH+1 Parity bit if enabled +// 2^SIZE-2 Second stop bit if enabled +// 2^SIZE-1 Last stop bit and idle + +always@(posedge clk) + if( reset ) + begin + shift_cnt <= {SIZE{1'b1}}; + last_cnt <= 1'b0; + end + else + if(!edge_enable) + begin + shift_cnt <= shift_cnt; + last_cnt <= 1'b0; + end + else + if(( shift_cnt == {SIZE{1'b1}})) + begin + shift_cnt <= {SIZE{1'b0}}; + last_cnt <= 1'b0; + end + else + if ( shift_cnt == WIDTH) + case( parity_enable ) + (2'b0): + begin + shift_cnt <= {SIZE{1'b1}}; + last_cnt <= 1'b1; + end + + (2'b1): + begin + shift_cnt <= shift_cnt + 1'b1; + last_cnt <= 1'b0; + end + endcase // case (parity_enable) + else + if ( shift_cnt == (WIDTH+1)) + begin + shift_cnt <= {SIZE{1'b1}}; + last_cnt <= 1'b1; + end + else + begin + shift_cnt <= shift_cnt + 1'b1; + last_cnt <= 1'b0; + end +// +// +// load shift_buffer during start_bit +// shift down every bit +// +// +always@(posedge clk) + if(reset) shift_buffer <= {WIDTH{1'b0}}; + else + if(!edge_enable) shift_buffer <= shift_buffer; + else + if(shift_cnt == {SIZE{1'b1}}) shift_buffer <= {WIDTH{1'b0}}; + else + if(shift_cnt <= WIDTH-1 ) shift_buffer <= {ser_in,shift_buffer[WIDTH-1:1]}; + else shift_buffer <= shift_buffer; +// +// +// calculate parity on the fly +// seed reg with 0 for odd and 1 for even +// force reg to 0 or 1 if needed +// +always@(posedge clk) + if(reset) parity_calc <= 1'b0; + else + if(!edge_enable) parity_calc <= parity_calc; + else + if(parity_type[1] || (shift_cnt == {SIZE{1'b1}})) parity_calc <= parity_type[0]; + else + if(shift_cnt <= WIDTH-1 ) parity_calc <= parity_calc ^ ser_in; + else parity_calc <= parity_calc; +// +// sample parity bit and hold it until next start bit +// +always@(posedge clk) + if(reset) parity_samp <= 1'b0; + else + if(!edge_enable) parity_samp <= parity_samp; + else + if(shift_cnt == {SIZE{1'b1}}) parity_samp <= 1'b0; + else + if(shift_cnt == WIDTH ) parity_samp <= ser_in; + else parity_samp <= parity_samp; +// +// check for stop bit error +// +always@(posedge clk) + if(reset) frame_err <= 1'b0; + else + if(!edge_enable) frame_err <= frame_err; + else + if(shift_cnt == {SIZE{1'b1}}) frame_err <= 1'b0; + else + if(shift_cnt == WIDTH+1 ) frame_err <= ser_in ^ stop_value; + else frame_err <= frame_err; + +always@(*) + if( shift_cnt == {SIZE{1'b1}}) stop_cnt <= 1'b1; + else stop_cnt <= 1'b0; + + +endmodule + + + + Index: trunk/projects/Testbench/ip/uart_model/rtl/verilog/io_probe =================================================================== --- trunk/projects/Testbench/ip/uart_model/rtl/verilog/io_probe (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/rtl/verilog/io_probe (revision 88) @@ -0,0 +1,112 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* io_probe for handling timing delays in dut */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + + +module io_probe +#(parameter MESG = " ", + parameter WIDTH = 1, + parameter RESET = {WIDTH{1'bz}}, + parameter IN_DELAY = 5, + parameter OUT_DELAY = 15, + parameter OUT_WIDTH = 10 + ) +( +input wire clk, + +input wire [WIDTH-1:0] drive_value, +input wire [WIDTH-1:0] expected_value, +input wire [WIDTH-1:0] mask, + +inout wire [WIDTH-1:0] signal + + +); + + +reg [WIDTH-1:0] filtered_value; +reg [WIDTH:1] fail; + + + + + + +assign signal = drive_value; + + + + + + +always @(posedge clk) filtered_value <= signal; +always @(posedge clk) fail <= mask & (signal^ expected_value); + + + + + +initial + begin + cg.next(3); + while(1) + begin + if(fail !== {WIDTH{1'b0}}) + begin + $display("%t %m value %x failure on bit(s) %b",$realtime,filtered_value,fail ); + cg.fail(MESG); + end + cg.next(1); + end // while (1) + end // initial begin + + + + + + + + +endmodule + + + Index: trunk/projects/Testbench/ip/uart_model/soc/design.soc =================================================================== --- trunk/projects/Testbench/ip/uart_model/soc/design.soc (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/soc/design.soc (revision 88) @@ -0,0 +1,41 @@ + + + + + + +uart_model +uart_model + + + + + + Index: trunk/projects/Testbench/ip/uart_model/doc/copyright.v =================================================================== --- trunk/projects/Testbench/ip/uart_model/doc/copyright.v (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/doc/copyright.v (revision 88) @@ -0,0 +1,43 @@ +/**********************************************************************/ +/* */ +/* ------- */ +/* / SOC \ */ +/* / GEN \ */ +/* / SIM \ */ +/* ============== */ +/* | | */ +/* |____________| */ +/* */ +/* Clock and Reset generator for simulations */ +/* */ +/* */ +/* Author(s): */ +/* - John Eaton, jt_eaton@opencores.org */ +/* */ +/**********************************************************************/ +/* */ +/* Copyright (C) <2010> */ +/* */ +/* This source file may be used and distributed without */ +/* restriction provided that this copyright statement is not */ +/* removed from the file and that any derivative work contains */ +/* the original copyright notice and the associated disclaimer. */ +/* */ +/* This source file is free software; you can redistribute it */ +/* and/or modify it under the terms of the GNU Lesser General */ +/* Public License as published by the Free Software Foundation; */ +/* either version 2.1 of the License, or (at your option) any */ +/* later version. */ +/* */ +/* This source is distributed in the hope that it will be */ +/* useful, but WITHOUT ANY WARRANTY; without even the implied */ +/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */ +/* PURPOSE. See the GNU Lesser General Public License for more */ +/* details. */ +/* */ +/* You should have received a copy of the GNU Lesser General */ +/* Public License along with this source; if not, download it */ +/* from http://www.opencores.org/lgpl.shtml */ +/* */ +/**********************************************************************/ + Index: trunk/projects/Testbench/ip/uart_model/bin/Makefile =================================================================== --- trunk/projects/Testbench/ip/uart_model/bin/Makefile (nonexistent) +++ trunk/projects/Testbench/ip/uart_model/bin/Makefile (revision 88) @@ -0,0 +1,2 @@ +include ../../../bin/Makefile.root + Index: trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/impact_bat =================================================================== --- trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/impact_bat (revision 87) +++ trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/impact_bat (nonexistent) @@ -1,6 +0,0 @@ -setMode -bs -setCable -port svf -file ../debug/bitstream.svf -addDevice -p 1 -file Board_Design_jtag.bit -program -p 1 -closeCable -quit Index: trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/fpga_load =================================================================== --- trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/fpga_load (revision 87) +++ trunk/projects/fpgas/ip/Basys_soc_mrisc/syn/Basys_soc_mrisc_io_mouse_mouse/debug/fpga_load (nonexistent) @@ -1,6 +0,0 @@ -bsdl path ../bsdl;../target/bsdl; -cable usbblaster -detect -part 1 -svf bitstream.svf - Index: trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml =================================================================== --- trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml (revision 87) +++ trunk/projects/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_kim_2.xml (revision 88) @@ -763,9 +763,11 @@ + flashcs_n_out + @@ -2535,10 +2537,7 @@ - - flashcs_n_out - - + flashrp_n_out

/trunk/projects/fpgas/ip/Nexys2_T6502/soc/design.soc

/trunk/projects/fpgas/ip/Nexys2_T6502/doc/geda/drawing/filelist File deleted \ No newline at end of file

/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/doc/geda/drawing/filelist File deleted \ No newline at end of file

/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/syn/Nexys2_soc_mrisc_io_mouse_mouse/debug/fpga_load File deleted

/trunk/projects/fpgas/ip/Nexys2_soc_mrisc/syn/Nexys2_soc_mrisc_io_mouse_mouse/debug/impact_bat File deleted

/trunk/projects/fpgas/ip/Basys_mrisc/syn/Basys_mrisc_loop/debug/impact_bat File deleted

/trunk/projects/fpgas/ip/Basys_mrisc/syn/Basys_mrisc_loop/debug/fpga_load File deleted

/trunk/projects/pic_micro/bin/repeater

trunk/projects/pic_micro/bin/repeater Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_ind_mem.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +ind_mem + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_ind_mem + + + destination + ../verilog/top.ind_mem + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_ind_mem + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.ind_mem + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.ind_mem + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity1.xml (revision 88) @@ -0,0 +1,457 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +sanity1 + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_sanity1 + + + destination + ../verilog/top.sanity1 + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_sanity1 + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + 12'h000 + 12'h000 + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.sanity1 + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.sanity1 + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf1.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +rf1 + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf1 + + + destination + ../verilog/top.rf1 + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf1 + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.rf1 + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.rf1 + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_sanity2.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +sanity2 + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_sanity2 + + + destination + ../verilog/top.sanity2 + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_sanity2 + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.sanity2 + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.sanity2 + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf2.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +rf2 + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf2 + + + destination + ../verilog/top.rf2 + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf2 + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.rf2 + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.rf2 + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_loop.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +loop + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_loop + + + destination + ../verilog/top.loop + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_loop + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.loop + verilogSourceTop + + + + + ../verilog/top.out + verilogFragment + + + + + ../verilog/tb.test_define.loop + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/xml/mrisc_cpu_rf3.xml (revision 88) @@ -0,0 +1,456 @@ + + + + +opencores.org +pic_micro +mrisc_cpu +rf3 + + + + + + + + + + + verilog_maker + 104.0 + none + ./tools/bin/build_verilog + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf3 + + + destination + ../verilog/top.rf3 + + + + + + + leaf_maker + 105.0 + none + ./tools/bin/build_leaf + design + + + component + mrisc_cpu + + + variant + mrisc_cpu_rf3 + + + + + + + + + + + + + 0 + 0 + 0 + "NONE" + + 40 + 200000 + + + + + + + + sim + :: + Verilog + + + fs-sim + + + + + + + + + + + + + + + + + + fs-sim + + + ../verilog/top.rf3 + verilogSourceTop + + + + + ../verilog/top.io + verilogFragment + + + + + ../verilog/tb.test_define.rf3 + verilogFragment + + + + + + + + + + +clk +wire + + + +reset +wire + + + + + +inst_addr +wire + +100 + + +inst_data +wire + +110 + + +portain +wire + +70 + + +portbin +wire + +70 + + +portcin +wire + +70 + + +portaout +wire + +70 + + +portbout +wire + +70 + + +portcout +wire + +70 + + +trisa +wire + +70 + + +trisb +wire + +70 + + +trisc +wire + +70 + + +porta_we +wire + + + +portb_we +wire + + + +portc_we +wire + + + + + + + + + + + + + + + + + + clk + + + + + + + reset + + + + + + + 1'b1 + + + + + 1'b0 + + + + + inst_addr + + + + + + + inst_data + + + + + + portain + + + + + portbin + + + + + portcin + + + + + portaout + + + + + portbout + + + + + + portcout + + + + + + trisa + + + + + trisb + + + + + trisc + + + + + porta_we + + + + + portb_we + + + + + portc_we + + + + + 1'b1 + + + + + + + 1'b0 + + + + + + 12'h000 + + + + + + + + + + + + + + + + + + + + + + + + +dut + +opencores.org +pic_micro +mrisc_cpu + + + + + + +cg + +opencores.org +Testbench +clock_gen + + + + PERIODPERIOD + TIMEOUTTIMEOUT + + + + + +u1 + +opencores.org +cde +cde_sram + + + + WORDSROM_WORDS + ADDRROM_ADDR + WIDTHROM_WIDTH + INIT_FILEROM_FILE + + + + + + + + + + + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf1 =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf1 (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf1 (revision 88) @@ -0,0 +1,34 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + + + while(porta == 8'hFF) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + if(porta == 8'h01) + begin + + end + else + if(porta == 8'hff) + begin + $display("Test FAILED in test %d !!!", portb); + end + else + $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.ind_mem =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.ind_mem (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.ind_mem (revision 88) @@ -0,0 +1,34 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + + repeat(40) @(posedge clk); + + while(portaout == 8'h00) @(posedge clk); + + if(portaout == 8'h01) + begin + + end + else + if(portaout == 8'hff) + begin + $display("Test FAILED in test %d !!!", portb); + end + else + $display("Test status UNKNOWN (%h test: %d) !!!", portaout, portbout); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity1 =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity1 (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity1 (revision 88) @@ -0,0 +1,31 @@ + + +initial + begin + $display ("\n\nMini-RISC. Version 1.0\n\n"); + $display ("========== Starting Sanity 1 Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + while(inst_addr != GOOD & inst_addr != BAD) @(posedge clk); + + if(inst_addr == GOOD) + begin + end + else + if(inst_addr == BAD) + begin + $display("Sanity1 test FAILED !!!"); + end + else + $display("Sanity1 test status UNKNOWN !!!"); + + + repeat(4) @(posedge clk); + $display("=============================================\n\n\n"); + + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf2 =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf2 (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf2 (revision 88) @@ -0,0 +1,34 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + + + while(porta == 8'hFF) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + if(porta == 8'h01) + begin + + end + else + if(porta == 8'hff) + begin + $display("Test FAILED in test %d !!!", portb); + end + else + $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.loop =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.loop (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.loop (revision 88) @@ -0,0 +1,12 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + repeat(4000) @(posedge clk); +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity2 =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity2 (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.sanity2 (revision 88) @@ -0,0 +1,32 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + + + while(porta == 8'hFF) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + if(porta == 8'h01) + begin + end + else + if(porta == 8'hff) + begin + $display("Test FAILED in test %d !!!", portb); + end + else + $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf3 =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf3 (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/tb.test_define.rf3 (revision 88) @@ -0,0 +1,34 @@ + +initial + begin + $display ("\n\nMini-RISC. Sanity 2 Version 1.0\n\n"); + $display ("========== Starting Test ========== \n"); + repeat(10) @(posedge clk); + cg.reset_off; + + + while(porta == 8'hFF) @(posedge clk); + while(porta == 8'h00) @(posedge clk); + + if(porta == 8'h01) + begin + + end + else + if(porta == 8'hff) + begin + $display("Test FAILED in test %d !!!", portb); + end + else + $display("Test status UNKNOWN (%h test: %d) !!!", porta, portb); + + + repeat(4) @(posedge clk); + $display("\n=============================================\n\n\n"); + + + +cg.exit; + end + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.io =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.io (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.io (revision 88) @@ -0,0 +1,46 @@ +wire [7:0] porta; // I/O Port A +wire [7:0] portb; // I/O Port B +wire [7:0] portc; // I/O Port C + + + +// IO buffers for IO Ports +assign porta = trisa ? 8'bz : portaout; +assign portain = porta; + +assign portb = trisb ? 8'bz : portbout; +assign portbin = portb; + +assign portc = trisc ? 8'bz : portcout; +assign portcin = portc; + +// Pullups for IO Ports +pullup ua0(porta[0]); +pullup ua1(porta[1]); +pullup ua2(porta[2]); +pullup ua3(porta[3]); +pullup ua4(porta[4]); +pullup ua5(porta[5]); +pullup ua6(porta[6]); +pullup ua7(porta[7]); + +pullup ub0(portb[0]); +pullup ub1(portb[1]); +pullup ub2(portb[2]); +pullup ub3(portb[3]); +pullup ub4(portb[4]); +pullup ub5(portb[5]); +pullup ub6(portb[6]); +pullup ub7(portb[7]); + +pullup uc0(portc[0]); +pullup uc1(portc[1]); +pullup uc2(portc[2]); +pullup uc3(portc[3]); +pullup uc4(portc[4]); +pullup uc5(portc[5]); +pullup uc6(portc[6]); +pullup uc7(portc[7]); + + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.out =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.out (nonexistent) +++ trunk/projects/pic_micro/ip/mrisc_cpu/rtl/verilog/top.out (revision 88) @@ -0,0 +1,49 @@ + +assign portain = portaout; +assign portbin = portbout; +assign portcin = portcout; + +wire [7:0] porta; +wire [7:0] portb; +wire [7:0] portc; + + +// IO buffers for IO Ports +assign porta = trisa ? 8'bz : portaout; + + +assign portb = trisb ? 8'bz : portbout; + + +assign portc = trisc ? 8'bz : portcout; + + +// Pullups for IO Ports +pullup ua0(porta[0]); +pullup ua1(porta[1]); +pullup ua2(porta[2]); +pullup ua3(porta[3]); +pullup ua4(porta[4]); +pullup ua5(porta[5]); +pullup ua6(porta[6]); +pullup ua7(porta[7]); + +pullup ub0(portb[0]); +pullup ub1(portb[1]); +pullup ub2(portb[2]); +pullup ub3(portb[3]); +pullup ub4(portb[4]); +pullup ub5(portb[5]); +pullup ub6(portb[6]); +pullup ub7(portb[7]); + +pullup uc0(portc[0]); +pullup uc1(portc[1]); +pullup uc2(portc[2]); +pullup uc3(portc[3]); +pullup uc4(portc[4]); +pullup uc5(portc[5]); +pullup uc6(portc[6]); +pullup uc7(portc[7]); + + Index: trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc =================================================================== --- trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc (revision 87) +++ trunk/projects/pic_micro/ip/mrisc_cpu/soc/design.soc (revision 88) @@ -27,30 +27,134 @@ // from http://www.opencores.org/lgpl.shtml // // // --> + + - - + mrisc_cpu mrisc_cpu + + + mrisc_cpu + TB.dut + + + + +mrisc_cpu +mrisc_cpu_rf1 +rf1 + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_rf2 +rf2 + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_rf3 +rf3 + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_ind_mem +ind_mem + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_loop +loop + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_sanity1 +sanity1 + + + mrisc_cpu + TB.dut.dut + + + + +mrisc_cpu +mrisc_cpu_sanity2 +sanity2 + + + mrisc_cpu + TB.dut.dut + + + + + + + + + +rf1 +mrisc_cpu_rf1 + + ROM_FILE"../../../../../sw/rf1/rf1.abs12" + ROM_WORDS583 + ROM_ADDR11 + ROM_WIDTH12 + + + + + + sanity1 -mrisc_cpu +mrisc_cpu_sanity1 ROM_FILE"../../../../../sw/sanity1/sanity1.abs12" ROM_WORDS180 @@ -59,13 +163,12 @@ GOOD12'h0aa BAD12'h0af - -"../../bench/verilog/models/clock_gen.v" - + + rf3 -mrisc_cpu +mrisc_cpu_rf3 ROM_FILE"../../../../../sw/rf3/rf3.abs12" ROM_WORDS218 @@ -72,13 +175,11 @@ ROM_ADDR11 ROM_WIDTH12 - -"../../bench/verilog/models/clock_gen.v" - + sanity2 -mrisc_cpu +mrisc_cpu_sanity2 ROM_FILE"../../../../../sw/sanity2/sanity2.abs12" ROM_WORDS302 @@ -85,16 +186,12 @@ ROM_ADDR11 ROM_WIDTH12 - -"../../bench/verilog/models/clock_gen.v" - + - - rf2 -mrisc_cpu +mrisc_cpu_rf2 ROM_FILE"../../../../../sw/rf2/rf2.abs12" ROM_WORDS719 @@ -101,26 +198,11 @@ ROM_ADDR11 ROM_WIDTH12 - -"../../bench/verilog/models/clock_gen.v" - + -rf1 -mrisc_cpu - - ROM_FILE"../../../../../sw/rf1/rf1.abs12" - ROM_WORDS583 - ROM_ADDR11 - ROM_WIDTH12 - - -"../../bench/verilog/models/clock_gen.v" - - - ind_mem -mrisc_cpu +mrisc_cpu_ind_mem ROM_FILE"../../../../../sw/ind_mem/ind_mem.abs12" ROM_WORDS51 @@ -127,13 +209,11 @@ ROM_ADDR11 ROM_WIDTH12 - -"../../bench/verilog/models/clock_gen.v" - + loop -mrisc_cpu +mrisc_cpu_loop ROM_FILE"../../../../../sw/loop/loop.abs12" ROM_WORDS21 @@ -140,24 +220,11 @@ ROM_ADDR11 ROM_WIDTH12 - -"../../bench/verilog/models/clock_gen.v" - - - - mrisc_cpu - TB.dut - - - - - - - +

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