URL
https://opencores.org/ocsvn/socwire/socwire/trunk
Subversion Repositories socwire
Compare Revisions
- This comparison shows the changes necessary to convert path
/socwire
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/branches/Switch/cell.vhd
0,0 → 1,171
---====================== Start Software License ========================--- |
--== ==-- |
--== This license governs the use of this software, and your use of ==-- |
--== this software constitutes acceptance of this license. Agreement ==-- |
--== with all points is required to use this software. ==-- |
--== ==-- |
--== 1. This source file may be used and distributed without ==-- |
--== restriction provided that this software license statement is not ==-- |
--== removed from the file and that any derivative work contains the ==-- |
--== original software license notice and the associated disclaimer. ==-- |
--== ==-- |
--== 2. This source file is free software; you can redistribute it ==-- |
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==-- |
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==-- |
--== This implies modification and/or derivative work of this Software. ==-- |
--== ==-- |
--== 3. This source is distributed in the hope that it will be useful, ==-- |
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==-- |
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==-- |
--== ==-- |
--== Your rights under this license are terminated immediately if you ==-- |
--== breach it in any way. ==-- |
--== ==-- |
---======================= End Software License =========================--- |
|
|
---====================== Start Copyright Notice ========================--- |
--== ==-- |
--== Filename ..... cell.vhd ==-- |
--== Download ..... http://www.ida.ing.tu-bs.de ==-- |
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==-- |
|
|
--== Copyright .... Copyright (c) 2008 IDA ==-- |
--== Project ...... SoCWire Switch ==-- |
--== Version ...... 1.00 ==-- |
--== Conception ... 11 November 2008 ==-- |
--== Modified ..... N/A ==-- |
--== ==-- |
---======================= End Copyright Notice =========================--- |
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
|
ENTITY cell IS |
PORT( |
--== General Inputs ==-- |
|
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
|
--== Vertical Connectivity ==-- |
|
op_eop : IN STD_LOGIC; |
op_active : IN STD_LOGIC; |
op_taken_in : IN STD_LOGIC; |
op_taken_out : OUT STD_LOGIC; |
|
--== Horizontal Connectivity ==-- |
|
enable : IN STD_LOGIC; |
connect : IN STD_LOGIC; |
ip_eop : IN STD_LOGIC; |
op_wanted : IN STD_LOGIC; |
ip_taken_in : IN STD_LOGIC; |
ip_taken_out : OUT STD_LOGIC; |
connected : OUT STD_LOGIC |
); |
END cell; |
|
|
ARCHITECTURE rtl OF cell IS |
|
---=======================--- |
--== Signal Declarations ==-- |
---=======================--- |
|
SIGNAL rst_int : STD_LOGIC; |
SIGNAL rst_held : STD_LOGIC; |
SIGNAL connected_int : STD_LOGIC; |
SIGNAL connect_cell : STD_LOGIC; |
SIGNAL connected_i : STD_LOGIC; |
|
BEGIN |
|
---=======================--- |
--== Delayed reset logic ==-- |
---=======================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') OR (rst_int = '1') THEN |
rst_held <= '0'; |
ELSE |
rst_held <= (connected_int AND op_eop) OR rst_held; |
END IF; |
END IF; |
END PROCESS; |
|
rst_int <= enable AND connected_int AND (op_eop OR rst_held); |
|
---==============================--- |
--== Determine connection logic ==-- |
---==============================--- |
|
connect_cell <= NOT(ip_taken_in) AND NOT(op_taken_in) AND op_wanted AND |
op_active AND NOT(rst_int) AND connect; |
|
---====================--- |
--== Connection logic ==-- |
---====================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') OR (rst_int = '1') THEN |
connected_int <= '0'; |
ELSIF (enable = '1') THEN |
connected_int <= connect_cell OR connected_int; |
END IF; |
END IF; |
END PROCESS; |
|
---===================--- |
--== Connected logic ==-- |
---===================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') OR (op_eop = '1') THEN |
connected_i <= '0'; |
ELSIF (enable = '1') THEN |
connected_i <= connect_cell OR connected_i; |
END IF; |
END IF; |
END PROCESS; |
|
connected <= connected_i; |
|
---=====================--- |
--== Input taken logic ==-- |
---=====================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') OR (ip_eop = '1') THEN |
ip_taken_out <= '0'; |
ELSIF (enable = '1') THEN |
ip_taken_out <= connect_cell OR ip_taken_in; |
END IF; |
END IF; |
END PROCESS; |
|
---======================--- |
--== Output taken logic ==-- |
---======================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') OR (rst_int = '1') THEN |
op_taken_out <= '0'; |
ELSIF (enable = '1') THEN |
op_taken_out <= connect_cell OR op_taken_in; |
END IF; |
END IF; |
END PROCESS; |
|
END rtl; |
/branches/Switch/entrance.vhd
0,0 → 1,182
---====================== Start Software License ========================--- |
--== ==-- |
--== This license governs the use of this software, and your use of ==-- |
--== this software constitutes acceptance of this license. Agreement ==-- |
--== with all points is required to use this software. ==-- |
--== ==-- |
--== 1. This source file may be used and distributed without ==-- |
--== restriction provided that this software license statement is not ==-- |
--== removed from the file and that any derivative work contains the ==-- |
--== original software license notice and the associated disclaimer. ==-- |
--== ==-- |
--== 2. This source file is free software; you can redistribute it ==-- |
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==-- |
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==-- |
--== This implies modification and/or derivative work of this Software. ==-- |
--== ==-- |
--== 3. This source is distributed in the hope that it will be useful, ==-- |
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==-- |
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==-- |
--== ==-- |
--== Your rights under this license are terminated immediately if you ==-- |
--== breach it in any way. ==-- |
--== ==-- |
---======================= End Software License =========================--- |
|
|
---====================== Start Copyright Notice ========================--- |
--== ==-- |
--== Filename ..... entrance.vhd ==-- |
--== Download ..... http://www.ida.ing.tu-bs.de ==-- |
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==-- |
|
|
--== Copyright .... Copyright (c) 2008 IDA ==-- |
--== Project ...... SoCWire Switch ==-- |
--== Version ...... 1.00 ==-- |
--== Conception ... 11 November 2008 ==-- |
--== Modified ..... N/A ==-- |
--== ==-- |
---======================= End Copyright Notice =========================--- |
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
USE IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
ENTITY entrance IS |
GENERIC( |
--== Number Of Ports ==-- |
|
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32 |
); |
PORT( |
--== General Interface ==-- |
|
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
|
--== Input Interface ==-- |
|
nwrite : IN STD_LOGIC; |
full : OUT STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0); |
|
--== Connection Interface ==-- |
|
full_in : IN STD_LOGIC; |
connect : OUT STD_LOGIC; |
wanted : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0) |
); |
END entrance; |
|
|
ARCHITECTURE rtl OF entrance IS |
|
---=========================--- |
--== Function Declarations ==-- |
---=========================--- |
|
FUNCTION ports2bus(nports : NATURAL RANGE 2 TO 32) RETURN NATURAL IS |
BEGIN |
CASE nports IS |
WHEN 2 => RETURN 1; |
WHEN 3 TO 4 => RETURN 2; |
WHEN 5 TO 8 => RETURN 3; |
WHEN 9 TO 16 => RETURN 4; |
WHEN 17 TO 32 => RETURN 5; |
END CASE; |
END ports2bus; |
|
---=====================--- |
--== Type Declarations ==-- |
---=====================--- |
|
TYPE states IS |
(wait4hdr, |
transfer |
); |
|
---=======================--- |
--== Signal Declarations ==-- |
---=======================--- |
|
SIGNAL state : states; |
SIGNAL ditch_data : STD_LOGIC; |
SIGNAL hw_addr : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL wanted_int : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL full_i : STD_LOGIC; |
|
BEGIN |
|
---===========================--- |
--== Create Hardware Address ==-- |
---===========================--- |
|
G0 : FOR i IN 0 TO nports-1 GENERATE |
hw_addr(i) <= '1' WHEN (din(ports2bus(nports)-1 DOWNTO 0) = i) ELSE '0'; |
END GENERATE G0; |
|
|
---================================--- |
--== Desired connection selection ==-- |
---================================--- |
|
wanted_int <= hw_addr WHEN (state = wait4hdr) ELSE (others => '0'); |
|
---============================--- |
--== Desired connection logic ==-- |
---============================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') THEN |
wanted <= (OTHERS => '0'); |
ELSIF (state = wait4hdr) THEN |
wanted <= wanted_int; |
END IF; |
END IF; |
END PROCESS; |
|
|
---=================--- |
--== State Machine ==-- |
---=================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') THEN |
state <= wait4hdr; |
ditch_data <= '0'; |
connect <= '0'; |
ELSE |
CASE state IS |
|
WHEN wait4hdr => |
IF (nwrite = '0') THEN |
ditch_data <= '1'; |
connect <= '1'; |
state <= transfer; |
END IF; |
|
WHEN transfer => |
ditch_data <= '0'; |
IF (nwrite = '0') AND (full_i = '0') AND (din(datawidth) = '1') THEN |
connect <= '0'; |
state <= wait4hdr; |
END IF; |
|
END CASE; |
END IF; |
END IF; |
END PROCESS; |
|
---========================--- |
--== Drive output signals ==-- |
---========================--- |
|
full_i <= '0' WHEN (ditch_data = '1') OR (full_in = '0') ELSE '1'; |
full <= full_i; |
|
END rtl; |
/branches/Switch/switch.vhd
0,0 → 1,232
---====================== Start Software License ========================--- |
--== ==-- |
--== This license governs the use of this software, and your use of ==-- |
--== this software constitutes acceptance of this license. Agreement ==-- |
--== with all points is required to use this software. ==-- |
--== ==-- |
--== 1. This source file may be used and distributed without ==-- |
--== restriction provided that this software license statement is not ==-- |
--== removed from the file and that any derivative work contains the ==-- |
--== original software license notice and the associated disclaimer. ==-- |
--== ==-- |
--== 2. This source file is free software; you can redistribute it ==-- |
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==-- |
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==-- |
--== This implies modification and/or derivative work of this Software. ==-- |
--== ==-- |
--== 3. This source is distributed in the hope that it will be useful, ==-- |
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==-- |
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==-- |
--== ==-- |
--== Your rights under this license are terminated immediately if you ==-- |
--== breach it in any way. ==-- |
--== ==-- |
---======================= End Software License =========================--- |
|
|
---====================== Start Copyright Notice ========================--- |
--== ==-- |
--== Filename ..... switch.vhd ==-- |
--== Download ..... http://www.ida.ing.tu-bs.de ==-- |
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==-- |
|
|
--== Copyright .... Copyright (c) 2008 IDA ==-- |
--== Project ...... SoCWire Switch ==-- |
--== Version ...... 1.00 ==-- |
--== Conception ... 11 November 2008 ==-- |
--== Modified ..... N/A ==-- |
--== ==-- |
---======================= End Copyright Notice =========================--- |
|
|
|
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
|
ENTITY switch IS |
GENERIC( |
--== Number Of Ports ==-- |
|
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32 |
); |
PORT( |
--== General Interface (Sync Rst) ==-- |
|
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
|
--== Input Interface ==-- |
|
nwrite : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
full : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
din : IN STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
|
--== Output Interface ==-- |
|
empty : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
nread : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
dout : OUT STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
|
--== Activity Interface ==-- |
|
active : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0) |
); |
END switch; |
|
|
ARCHITECTURE rtl OF switch IS |
|
---==========================--- |
--== Component Declarations ==-- |
---==========================--- |
|
COMPONENT entrance |
GENERIC(--== Number Of Ports ==-- |
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32 |
); |
PORT(--== General Interface ==-- |
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
--== Input Interface ==-- |
nwrite : IN STD_LOGIC; |
full : OUT STD_LOGIC; |
din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0); |
--== Connection Interface ==-- |
full_in : IN STD_LOGIC; |
connect : OUT STD_LOGIC; |
wanted : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0) |
); |
END COMPONENT; |
|
COMPONENT matrix |
GENERIC(--== Number Of Ports ==-- |
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32 |
); |
PORT(--== General Inputs ==-- |
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
--== Input Interface ==-- |
nwrite : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
full : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
din : IN STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
--== Output Interface ==-- |
empty : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
nread : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
dout : OUT STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
--== Vertical Inputs ==-- |
op_eop : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
op_active : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
op_wanted : IN STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
--== Horizontal Inputs ==-- |
ip_eop : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
connect : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0) |
); |
END COMPONENT; |
|
|
---=======================--- |
--== Signal Declarations ==-- |
---=======================--- |
|
SIGNAL connect : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL wanted : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL op_eop : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL ip_eop : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL full_ii : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL din_i : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
SIGNAL full_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL nwrite_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL empty_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL nread_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL dout_i : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
SIGNAL active_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
|
BEGIN |
|
---================================--- |
--== Create port active signals. ==-- |
---================================--- |
|
active_i <= active(nports-1 DOWNTO 0); |
|
---===============================================================--- |
--== Detect EOP's & EEP's has they enter and leave switch matrix ==-- |
---===============================================================--- |
|
G0 : FOR i IN 0 TO nports-1 GENERATE |
ip_eop(i) <= NOT(nwrite_i(i)) AND NOT(full_ii(i)) AND din_i((datawidth+1)*(i+1)-1); |
op_eop(i) <= NOT(empty_i(i)) AND NOT(nread_i(i)) AND dout_i((datawidth+1)*(i+1)-1); |
END GENERATE G0; |
|
|
---================================================--- |
--== Switch Matrix entrance & Hardware Addressing ==-- |
---================================================--- |
|
G1 : FOR i IN 0 TO nports-1 GENERATE |
entr0 : entrance |
GENERIC MAP |
(--== Number Of Ports ==-- |
datawidth => datawidth, |
nports => nports |
) |
PORT MAP |
(--== General Interface ==-- |
clk => clk, |
rst => rst, |
--== Input Interface ==-- |
nwrite => nwrite_i(i), |
full => full_i(i), |
din => din_i((datawidth+1)*(i+1)-1 DOWNTO (datawidth+1)*i), |
--== Connection Interface ==-- |
full_in => full_ii(i), |
connect => connect(i), |
wanted => wanted(nports*(i+1)-1 DOWNTO nports*i) |
); |
END GENERATE G1; |
|
---=================--- |
--== Switch Matrix ==-- |
---=================--- |
|
matrix0 : matrix |
GENERIC MAP |
(--== Number Of Ports ==-- |
datawidth => datawidth, |
nports => nports |
) |
PORT MAP |
(--== General Inputs ==-- |
clk => clk, |
rst => rst, |
--== Input Interface ==-- |
nwrite => nwrite_i, |
full => full_ii, |
din => din_i, |
--== Output Interface ==-- |
empty => empty_i, |
nread => nread_i, |
dout => dout_i, |
--== Vertical Inputs ==-- |
op_eop => op_eop, |
op_active => active_i, |
op_wanted => wanted, |
--== Horizontal Inputs ==-- |
ip_eop => ip_eop, |
connect => connect |
); |
|
|
din_i((datawidth+1)*nports-1 DOWNTO 0) <= din; |
full <= full_i; |
nwrite_i(nports-1 DOWNTO 0) <= nwrite; |
empty <= empty_i(nports-1 DOWNTO 0); |
nread_i(nports-1 DOWNTO 0) <= nread; |
dout <= dout_i((datawidth+1)*nports-1 DOWNTO 0); |
|
|
END rtl; |
/branches/Switch/matrix.vhd
0,0 → 1,199
---====================== Start Software License ========================--- |
--== ==-- |
--== This license governs the use of this software, and your use of ==-- |
--== this software constitutes acceptance of this license. Agreement ==-- |
--== with all points is required to use this software. ==-- |
--== ==-- |
--== 1. This source file may be used and distributed without ==-- |
--== restriction provided that this software license statement is not ==-- |
--== removed from the file and that any derivative work contains the ==-- |
--== original software license notice and the associated disclaimer. ==-- |
--== ==-- |
--== 2. This source file is free software; you can redistribute it ==-- |
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==-- |
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==-- |
--== This implies modification and/or derivative work of this Software. ==-- |
--== ==-- |
--== 3. This source is distributed in the hope that it will be useful, ==-- |
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==-- |
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==-- |
--== ==-- |
--== Your rights under this license are terminated immediately if you ==-- |
--== breach it in any way. ==-- |
--== ==-- |
---======================= End Software License =========================--- |
|
|
---====================== Start Copyright Notice ========================--- |
--== ==-- |
--== Filename ..... matrix.vhd ==-- |
--== Download ..... http://www.ida.ing.tu-bs.de ==-- |
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==-- |
|
|
--== Copyright .... Copyright (c) 2008 IDA ==-- |
--== Project ...... SoCWire Switch ==-- |
--== Version ...... 1.00 ==-- |
--== Conception ... 11 November 2008 ==-- |
--== Modified ..... N/A ==-- |
--== ==-- |
---======================= End Copyright Notice =========================--- |
LIBRARY IEEE; |
USE IEEE.STD_LOGIC_1164.ALL; |
|
ENTITY matrix IS |
GENERIC( |
--== Number Of Ports ==-- |
|
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32 |
); |
PORT( |
--== General Inputs ==-- |
|
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
|
--== Input Interface ==-- |
|
nwrite : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
full : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
din : IN STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
|
--== Output Interface ==-- |
|
empty : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
nread : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
dout : OUT STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0); |
|
--== Vertical Inputs ==-- |
|
op_eop : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
op_active : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
op_wanted : IN STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
|
--== Horizontal Inputs ==-- |
|
ip_eop : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
connect : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0) |
); |
END matrix; |
|
ARCHITECTURE rtl OF matrix IS |
|
---=========================--- |
--== Constant Declarations ==-- |
---=========================--- |
|
CONSTANT all_ones : STD_LOGIC_VECTOR(nports-1 DOWNTO 0) := (OTHERS => '1'); |
CONSTANT all_zeros : STD_LOGIC_VECTOR(nports-1 DOWNTO 0) := (OTHERS => '0'); |
|
---==========================--- |
--== Component Declarations ==-- |
---==========================--- |
|
COMPONENT cell |
PORT(--== General Inputs ==-- |
clk : IN STD_LOGIC; |
rst : IN STD_LOGIC; |
--== Vertical Connectivity ==-- |
op_eop : IN STD_LOGIC; |
op_active : IN STD_LOGIC; |
op_taken_in : IN STD_LOGIC; |
op_taken_out : OUT STD_LOGIC; |
--== Horizontal Connectivity ==-- |
enable : IN STD_LOGIC; |
connect : IN STD_LOGIC; |
ip_eop : IN STD_LOGIC; |
op_wanted : IN STD_LOGIC; |
ip_taken_in : IN STD_LOGIC; |
ip_taken_out : OUT STD_LOGIC; |
connected : OUT STD_LOGIC |
); |
END COMPONENT; |
|
|
---=======================--- |
--== Signal Declarations ==-- |
---=======================--- |
|
TYPE MULTIPLEX IS ARRAY(0 TO datawidth+1) OF STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
|
SIGNAL enable : STD_LOGIC_VECTOR(nports-1 DOWNTO 0); |
SIGNAL op_taken : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL ip_taken : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL connected : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL full_mux : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL empty_mux : STD_LOGIC_VECTOR(nports*nports-1 DOWNTO 0); |
SIGNAL dout_mux : MULTIPLEX; |
|
|
BEGIN |
|
---===========================================--- |
--== Data multiplexing and handshake routing ==-- |
---===========================================--- |
|
GH : FOR h IN 0 TO nports-1 GENERATE |
GV : FOR v IN 0 TO nports-1 GENERATE |
full_mux(nports*h + v) <= nread(v) WHEN connected(nports*h + v) = '1' ELSE '1'; |
empty_mux(nports*h + v) <= nwrite(v) WHEN connected(nports*v + h) = '1' ELSE '1'; |
GI : FOR i IN 0 TO (datawidth) GENERATE |
dout_mux(i)(nports*h + v) <= din((datawidth+1)*v + i) WHEN connected(nports*v + h) = '1' ELSE '0'; |
END GENERATE GI; |
|
END GENERATE GV; |
full(h) <= '1' WHEN (full_mux(nports*(h+1)-1 DOWNTO nports*h)) = all_ones ELSE '0'; |
empty(h) <= '1' WHEN (empty_mux(nports*(h+1)-1 DOWNTO nports*h)) = all_ones ELSE '0'; |
GJ : FOR j IN 0 TO (datawidth) GENERATE |
dout((datawidth+1)*h + j) <= '0' WHEN (dout_mux(j)(nports*(h+1)-1 DOWNTO nports*h)) = all_zeros ELSE '1'; |
END GENERATE GJ; |
END GENERATE GH; |
|
|
---=========================================--- |
--== Connection cell pipeline enable logic ==-- |
---=========================================--- |
|
PROCESS(clk) |
BEGIN |
IF RISING_EDGE(clk) THEN |
IF (rst = '1') THEN |
enable(nports-2 DOWNTO 0) <= (OTHERS => '0'); |
enable(nports-1) <= '1'; |
ELSE |
enable <= enable(nports-2 DOWNTO 0) & enable(nports-1); |
END IF; |
END IF; |
END PROCESS; |
|
---===================--- |
--== Connection Cell ==-- |
---===================--- |
|
G0 : FOR h IN 0 TO nports-1 GENERATE |
G1 : FOR v IN 0 TO nports-1 GENERATE |
U0 : cell |
PORT MAP |
(--== General Inputs ==-- |
clk => clk, |
rst => rst, |
--== Vertical Connectivity ==-- |
op_eop => op_eop(h), |
op_active => op_active(h), |
op_taken_in => op_taken(h*nports + (v+nports-1) MOD nports), |
op_taken_out => op_taken(h*nports + v), |
--== Horizontal Connectivity ==-- |
enable => enable((v + h) MOD nports), |
connect => connect(v), |
ip_eop => ip_eop(v), |
op_wanted => op_wanted(v*nports + h), |
ip_taken_in => ip_taken(v*nports + (h+nports-1) MOD nports), |
ip_taken_out => ip_taken(v*nports + h), |
connected => connected(v*nports + h) |
); |
END GENERATE G1; |
END GENERATE G0; |
|
|
END rtl; |
/branches/Switch/Thumbs.db
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
branches/Switch/Thumbs.db
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: branches/Switch/socwire_switch.vhd
===================================================================
--- branches/Switch/socwire_switch.vhd (nonexistent)
+++ branches/Switch/socwire_switch.vhd (revision 10)
@@ -0,0 +1,278 @@
+---====================== Start Software License ========================---
+--== ==--
+--== This license governs the use of this software, and your use of ==--
+--== this software constitutes acceptance of this license. Agreement ==--
+--== with all points is required to use this software. ==--
+--== ==--
+--== 1. This source file may be used and distributed without ==--
+--== restriction provided that this software license statement is not ==--
+--== removed from the file and that any derivative work contains the ==--
+--== original software license notice and the associated disclaimer. ==--
+--== ==--
+--== 2. This source file is free software; you can redistribute it ==--
+--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
+--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
+--== This implies modification and/or derivative work of this Software. ==--
+--== ==--
+--== 3. This source is distributed in the hope that it will be useful, ==--
+--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
+--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
+--== ==--
+--== Your rights under this license are terminated immediately if you ==--
+--== breach it in any way. ==--
+--== ==--
+---======================= End Software License =========================---
+
+
+---====================== Start Copyright Notice ========================---
+--== ==--
+--== Filename ..... socwire_switch.vhd ==--
+--== Download ..... http://www.ida.ing.tu-bs.de ==--
+--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
+--== Authors .......Björn Osterloh, Karel Kotarowski ==--
+--== Contact .......Björn Osterloh (b.osterloh@tu-bs.de) ==--
+--== Copyright .... Copyright (c) 2008 IDA ==--
+--== Project ...... SoCWire Switch ==--
+--== Version ...... 1.00 ==--
+--== Conception ... 11 November 2008 ==--
+--== Modified ..... N/A ==--
+--== ==--
+---======================= End Copyright Notice =========================---
+
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE WORK.ALL;
+
+
+ENTITY SoCWire_switch IS
+ GENERIC(
+ datawidth : NATURAL RANGE 8 TO 8192:=16;
+ nports : NATURAL RANGE 2 TO 32:=32;
+ speed : NATURAL RANGE 1 TO 100:=10;
+ after64 : NATURAL RANGE 1 TO 6400:=6400; -- Spacewire Standard 6400 = 6.4 us
+ after128 : NATURAL RANGE 1 TO 12800:=12800; -- Spacewire Standard 12800 = 12.8 us
+ disconnect_detection : NATURAL RANGE 1 TO 850:=850 -- Spacewire Standard 850 = 850 ns
+ );
+ PORT(
+ --== General Interface (Sync Rst, 50MHz Clock) ==--
+
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+
+ --== Serial Receive Interface ==--
+
+ rx : IN STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
+ rx_valid : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+
+ --== Serial Transmit Interface ==--
+
+ tx : OUT STD_LOGIC_VECTOR((datawidth+2)*nports-1 DOWNTO 0);
+ tx_valid : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+
+ --== Active Interface ==--
+
+ active : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0)
+ );
+END SoCWire_switch;
+
+
+ARCHITECTURE rtl OF SoCWire_switch IS
+
+---=====================================---
+--== Signal Declarations (Link Enable) ==--
+---=====================================---
+
+SIGNAL socw_en : STD_LOGIC;
+SIGNAL socw_dis : STD_LOGIC;
+
+---================================---
+--== Signal Declarations (Active) ==--
+---================================---
+
+SIGNAL active_i : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+
+---=====================================================---
+--== Signal Declarations (Data : CODEC to Switch Core) ==--
+---=====================================================---
+
+SIGNAL dat_full : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+SIGNAL dat_nwrite : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+SIGNAL dat_din : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
+
+---=====================================================---
+--== Signal Declarations (Data : Switch Core to CODEC) ==--
+---=====================================================---
+
+SIGNAL dat_nread : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+SIGNAL dat_empty : STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+SIGNAL dat_dout : STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
+
+
+---=============================================---
+--== Component Instantiations for leaf modules ==--
+---=============================================---
+
+COMPONENT socwire_codec
+ GENERIC(
+ datawidth : NATURAL RANGE 8 TO 8192;
+ speed : NATURAL RANGE 1 TO 100;
+ after64 : NATURAL RANGE 1 TO 6400;
+ after128 : NATURAL RANGE 1 TO 12800;
+ disconnect_detection : NATURAL RANGE 1 TO 850
+ );
+
+ PORT(
+ --== General Interface (Sync Rst, 50MHz Clock) ==--
+
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+
+ --== Link Enable Interface ==--
+
+ socw_en : IN STD_LOGIC;
+ socw_dis : IN STD_LOGIC;
+
+ --== Serial Receive Interface ==--
+
+ rx : IN STD_LOGIC_VECTOR(datawidth+1 downto 0);
+ rx_valid : IN STD_LOGIC;
+
+ --== Serial Transmit Interface ==--
+
+ tx : OUT STD_LOGIC_VECTOR(datawidth+1 downto 0);
+ tx_valid : OUT STD_LOGIC;
+
+ --== Data Input Interface ==--
+
+ dat_full : OUT STD_LOGIC;
+ dat_nwrite : IN STD_LOGIC;
+ dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
+
+ --== Data Output Interface ==--
+
+ dat_nread : IN STD_LOGIC;
+ dat_empty : OUT STD_LOGIC;
+ dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
+
+ --== Active Interface ==--
+
+ active : OUT STD_LOGIC
+ );
+END COMPONENT;
+
+
+COMPONENT switch
+ GENERIC(
+ datawidth : NATURAL RANGE 8 TO 8192;
+ nports : NATURAL RANGE 2 TO 32
+ );
+ PORT(
+ --== General Interface (Sync Rst) ==--
+
+ clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+
+ --== Input Interface ==--
+
+ nwrite : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+ full : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+ din : IN STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
+
+ --== Output Interface ==--
+
+ empty : OUT STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+ nread : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0);
+ dout : OUT STD_LOGIC_VECTOR((datawidth+1)*nports-1 DOWNTO 0);
+
+ --== Activity Interface ==--
+
+ active : IN STD_LOGIC_VECTOR(nports-1 DOWNTO 0)
+ );
+END COMPONENT;
+
+
+BEGIN
+
+ ---=====================================---
+ --== Enable All CODEC's for Auto-Start ==--
+ ---=====================================---
+
+ socw_en <= '1';
+ socw_dis <= '0';
+
+
+ ---=====================---
+ --== SoCWire CODEC's ==--
+ ---=====================---
+
+ G0 : FOR i IN 0 TO nports-1 GENERATE
+ socw_codec : socwire_codec
+ GENERIC MAP
+ (
+ datawidth => datawidth,
+ speed => speed,
+ after64=> after64,
+ after128=>after128,
+ disconnect_detection=>disconnect_detection
+ )
+ PORT MAP
+ (--== General Interface (Sync Rst, 50MHz Clock) ==--
+ rst => rst,
+ clk => clk,
+ --== Link Enable Interface ==--
+ socw_en => socw_en,
+ socw_dis => socw_dis,
+ --== Serial Receive Interface ==--
+ rx => rx((i+1)*(datawidth+2)-1 DOWNTO i*(datawidth+2)),
+ rx_valid => rx_valid(i),
+ --== Serial Transmit Interface ==--
+ tx => tx((i+1)*(datawidth+2)-1 DOWNTO i*(datawidth+2)),
+ tx_valid => tx_valid(i),
+ --== Data Input Interface ==--
+ dat_full => dat_full(i),
+ dat_nwrite => dat_nwrite(i),
+ dat_din => dat_din((i+1)*(datawidth+1)-1 DOWNTO i*(datawidth+1)),
+ --== Data Output Interface ==--
+ dat_nread => dat_nread(i),
+ dat_empty => dat_empty(i),
+ dat_dout => dat_dout((i+1)*(datawidth+1)-1 DOWNTO i*(datawidth+1)),
+ --== Active Interface ==--
+ active => active_i(i)
+ );
+ END GENERATE G0;
+
+
+ ---==============================---
+ --== SoCWire Data Switch Core ==--
+ ---==============================---
+
+ socw_switch : switch
+ GENERIC MAP
+ (
+ datawidth => datawidth,
+ nports => nports
+ )
+ PORT MAP
+ (--== General Interface (Sync Rst) ==--
+ clk => clk,
+ rst => rst,
+ --== Input Interface ==--
+ nwrite => dat_empty,
+ full => dat_nread,
+ din => dat_dout,
+ --== Output Interface ==--
+ empty => dat_nwrite,
+ nread => dat_full,
+ dout => dat_din,
+ --== Activity Interface ==--
+ active => active_i
+ );
+
+ ---======================================---
+ --== Shared Internal & External Signals ==--
+ ---======================================---
+
+ active <= active_i;
+
+END rtl;