URL
https://opencores.org/ocsvn/socwire/socwire/trunk
Subversion Repositories socwire
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- This comparison shows the changes necessary to convert path
/socwire
- from Rev 23 to Rev 24
- ↔ Reverse comparison
Rev 23 → Rev 24
/trunk/Testbench/switch_tb.vhd
9,7 → 9,7
--== Project ...... SoCWire Switch Testbench ==-- |
--== Version ...... 1.00 ==-- |
--== Conception ... 22 April 2009 ==-- |
--== Modified ..... N/A ==-- |
--== Modified ..... holgerm : minor bug fix marked with holgerm ==-- |
--== ==-- |
---======================= End Copyright Notice =========================--- |
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41,7 → 41,12
GENERIC( |
datawidth : NATURAL RANGE 8 TO 8192; |
nports : NATURAL RANGE 2 TO 32; |
speed : NATURAL RANGE 1 TO 100 |
speed : NATURAL RANGE 1 TO 100; |
-- holgerm |
after64 : NATURAL RANGE 1 TO 6400:=6400; -- Spacewire Standard 6400 = 6.4 us |
after128 : NATURAL RANGE 1 TO 12800:=12800; -- Spacewire Standard 12800 = 12.8 us |
disconnect_detection : NATURAL RANGE 1 TO 850:=850 -- Spacewire Standard 850 = 850 ns |
-- holgerm |
); |
PORT( |
--== General Interface (Sync Rst, 50MHz Clock) ==-- |
126,8 → 131,18
SIGNAL dat_din_P2 : STD_LOGIC_VECTOR (datawidth downto 0); |
SIGNAL dat_din_P3 : STD_LOGIC_VECTOR (datawidth downto 0); |
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-- holgerm |
-- compile with "vsim -novopt switch_tb" otherwise optimization will delete these signals |
SIGNAL dat_empty_P0 : STD_LOGIC; |
SIGNAL dat_empty_P1 : STD_LOGIC; |
SIGNAL dat_empty_P2 : STD_LOGIC; |
SIGNAL dat_empty_P3 : STD_LOGIC; |
SIGNAL dat_dout_P0 : STD_LOGIC_VECTOR (datawidth downto 0); |
SIGNAL dat_dout_P1 : STD_LOGIC_VECTOR (datawidth downto 0); |
SIGNAL dat_dout_P2 : STD_LOGIC_VECTOR (datawidth downto 0); |
SIGNAL dat_dout_P3 : STD_LOGIC_VECTOR (datawidth downto 0); |
-- holgerm |
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BEGIN |
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-- Component Declaration for the Unit Under Test (UUT) |
137,7 → 152,12
( |
datawidth =>datawidth, |
nports => nports, |
speed => speed |
speed => speed, |
-- holgerm |
after64 =>after64, |
after128 =>after128, |
disconnect_detection =>disconnect_detection |
-- holgerm |
) |
PORT MAP |
(--== General Interface (Sync Rst) ==-- |
200,6 → 220,19
dat_din(17 downto 9) <=dat_din_P1; |
dat_din(26 downto 18)<=dat_din_P2; |
dat_din(35 downto 27)<=dat_din_P3; |
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-- holgerm |
-- compile with "vsim -novopt switch_tb" otherwise optimization will delete these signals |
dat_empty_P0 <= dat_empty(0); |
dat_empty_P1 <= dat_empty(1); |
dat_empty_P2 <= dat_empty(2); |
dat_empty_P3 <= dat_empty(3); |
dat_dout_P0 <= dat_dout(8 downto 0); |
dat_dout_P1 <= dat_dout(17 downto 9); |
dat_dout_P2 <= dat_dout(26 downto 18); |
dat_dout_P3 <= dat_dout(35 downto 27); |
-- holgerm |
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tb : PROCESS |
231,8 → 264,8
wait for 10 ns; |
dat_din_P0<="100000000"; -- EOP |
wait for 10 ns; |
dat_nwrite_P0<='1'; |
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dat_nwrite_P0<='1'; |
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-- Send Packet from Port 2 to Port 3 |
dat_nwrite_P2<='0'; |
dat_din_P2<="000000011"; -- Port 3 |
243,36 → 276,36
wait for 10 ns; |
dat_din_P2<="100000000"; -- EOP |
wait for 10 ns; |
dat_nwrite_P2<='1'; |
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dat_nwrite_P2<='1'; |
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-- Send Packet from Port 0 and Port 1 to Port 2 and Port 3 |
dat_nwrite_P0<='0'; |
dat_din_P0<="000000010"; -- Port 2 |
dat_din_P0<="000000010"; -- Port 2 |
dat_nwrite_P1<='0'; |
dat_din_P1<="000000011"; -- Port 3 |
wait for 10 ns; |
dat_din_P0<="000001110"; -- Data 0 |
dat_din_P0<="000001110"; -- Data 0 |
dat_din_P1<="000001010"; -- Data 0 |
wait for 10 ns; |
dat_din_P0<="000001111"; -- Data 1 |
dat_din_P1<="000001011"; -- Data 1 |
dat_din_P1<="000001011"; -- Data 1 |
wait for 10 ns; |
dat_din_P0<="100000000"; -- EOP |
dat_din_P0<="100000000"; -- EOP |
dat_din_P1<="100000000"; -- EOP |
wait for 10 ns; |
dat_nwrite_P0<='1'; |
dat_nwrite_P0<='1'; |
dat_nwrite_P1<='1'; |
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wait for 1000 ms; --wait very long |
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END PROCESS; |