URL
https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk
Subversion Repositories spacewire_light
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewire_light/trunk/syn/spwamba_gr-xc3s1500
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/leon3mp.ucf
22,10 → 22,9
|
# Timing constraints between 200 MHz SpaceWire clock and system clock. |
NET "spw_clkl" TNM_NET = "spwclk"; |
TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 3 ns DATAPATHONLY; |
TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 3 ns DATAPATHONLY; |
NET "clkm" MAXSKEW = 1 ns; |
NET "spw_clkl" MAXSKEW = 1 ns; |
TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 4 ns DATAPATHONLY; |
TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 4 ns DATAPATHONLY; |
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns; |
|
## Input to DCM for 200 MHz SpaceWire clock can not be optimally routed. |
PIN "spwclk0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; |
/Makefile
5,7 → 5,7
-include .config |
|
# Change this to your local GRLIB directory. |
GRLIB = /data/leon3/grlib-gpl-1.0.22-b4095 |
GRLIB = /data/leon3/grlib-gpl-1.1.0-b4104 |
|
TOP=leon3mp |
BOARD=gr-xc3s-1500 |
37,6 → 37,8
$(RTLDIR)/spwxmit_fast.vhd \ |
$(RTLDIR)/spwrecvfront_generic.vhd \ |
$(RTLDIR)/spwrecvfront_fast.vhd \ |
$(RTLDIR)/syncdff.vhd \ |
$(RTLDIR)/spwram.vhd \ |
$(RTLDIR)/spwambapkg.vhd \ |
$(RTLDIR)/spwamba.vhd \ |
$(RTLDIR)/spwahbmst.vhd \ |
/leon3mp.vhd
679,6 → 679,7
ahbi => ahbmi, |
ahbo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE), |
tick_in => spw_tick_in, |
tick_out => open, |
spw_di => spw_di, |
spw_si => spw_si, |
spw_do => spw_do, |