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    /spacewiresystemc/trunk/rtl/DEBUG_VERILOG
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Rev 27 → Rev 40

/clock_reduce.v
34,39 → 34,260
module clock_reduce(
input clk,
input reset_n,
input [2:0] clock_sel,
 
output reg clk_reduced
output clk_reduced,
output clk_100_reduced
);
 
 
reg [10:0] counter;
reg [10:0] counter_100;
 
assign clk_reduced = clk_reduced_p | clk_reduced_n;
assign clk_100_reduced = clk_100_reduced_p | clk_100_reduced_n;
 
 
reg clk_reduced_i;
reg clk_100_reduced_i;
 
 
reg clk_reduced_p;
reg clk_100_reduced_p;
 
reg clk_reduced_n;
reg clk_100_reduced_n;
 
always@(*)
begin
 
clk_reduced_p = 1'b0;
if(clk_reduced_i)
begin
clk_reduced_p = 1'b1;
end
end
 
 
always@(*)
begin
 
clk_reduced_n = 1'b1;
if(!clk_reduced_i)
begin
clk_reduced_n = 1'b0;
end
end
 
always@(*)
begin
 
clk_100_reduced_p = 1'b0;
if(clk_100_reduced_i)
begin
clk_100_reduced_p = 1'b1;
end
end
 
 
always@(*)
begin
 
clk_100_reduced_n = 1'b1;
if(!clk_100_reduced_i)
begin
clk_100_reduced_n = 1'b0;
end
end
 
always@(posedge clk)
begin
 
if(!reset_n)
begin
 
counter <= 11'd0;
clk_reduced <= 1'b0;
counter_100 <= 11'd0;
clk_reduced_i <= 1'b0;
clk_100_reduced_i <= 1'b0;
end
else
begin
if(counter >=11'd0 && counter <=11'd24 )
case(clock_sel)
3'd0://2mhz - 500 ns
begin
clk_reduced <= 1'b1;
counter <= counter + 11'd1;
if(counter >=11'd0 && counter <=11'd99 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd100 && counter <=11'd199 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
else if(counter >=11'd25 && counter <=11'd49 )
3'd1://5mhz
begin
clk_reduced <= 1'b0;
counter <= counter + 11'd1;
if(counter >=11'd0 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd40 && counter <=11'd79 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd2://10mhz
begin
if(counter >=11'd0 && counter <=11'd19 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd20 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd3://50mhz
begin
if(counter >=11'd0 && counter <=11'd3 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd4 && counter <=11'd7)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd4://100mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd4)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd5://150mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd3)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd6://200mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter == 11'd2)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd7://300mhz
begin
if(counter ==11'd0 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter ==11'd1)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
endcase
if(counter_100 >=11'd0 && counter_100 <=11'd1 )
begin
clk_100_reduced_i <= 1'b1;
counter_100 <= counter_100 + 11'd1;
end
else if(counter_100 >=11'd2 && counter_100 <=11'd4)
begin
clk_100_reduced_i <= 1'b0;
counter_100 <= counter_100 + 11'd1;
end
else
begin
clk_reduced <= 1'b1;
counter <= 11'd0;
clk_100_reduced_i <= 1'b1;
counter_100 <= 11'd0;
end
 
end
 
end
/debounce.v
38,17 → 38,32
output reg PB_down
);
 
reg aux_pb;
reg [15:0] counter;
//assign PB_state = (counter >= 400)?PB_state:1'b1;
always@(*)
begin
 
PB_state = 1'b1;
if(CLK)
begin
if(aux_pb)
PB_state = 1'b0;
end
else if(!CLK)
begin
if(aux_pb)
PB_state = 1'b0;
end
end
 
always@(posedge CLK)
begin
 
if(PB)
begin
PB_state<= 1'b1;
aux_pb <= 1'b0;
counter <= 16'd0;
PB_down <= 1'b0;
end
57,7 → 72,7
if(counter >= 400)
begin
PB_state<= 1'b0;
aux_pb <= 1'b1;
PB_down <= 1'b1;
end
else
/detector_tokens.v
35,50 → 35,49
input rx_sin,
input rx_resetn,
//input clock_sys,
output reg rx_buffer_write,
//output reg rx_buffer_write,
output reg [13:0] info
);
reg rx_error;
wire rx_got_bit;
wire rx_error;
reg rx_got_bit;
reg rx_got_null;
reg rx_got_nchar;
reg rx_got_time_code;
reg rx_got_fct;
reg [4:0] counter_neg;
//reg [3:0] counter_control;
//reg [3:0] counter_data;
//reg [5:0] counter_bit_found;
wire [5:0] counter_neg;
 
reg [1:0] state_data_process;
reg [1:0] next_state_data_process;
reg control_bit_found;
 
wire posedge_clk;
wire negedge_clk;
 
reg bit_c_0;//N
reg bit_c_1;//P
reg bit_c_2;//N
reg bit_c_3;//P
reg bit_c_ex;//P
wire bit_c_0;//N
wire bit_c_1;//P
wire bit_c_2;//N
wire bit_c_3;//P
wire bit_c_ex;//P
 
reg bit_d_0;//N
reg bit_d_1;//P
reg bit_d_2;//N
reg bit_d_3;//P
reg bit_d_4;//N
reg bit_d_5;//P
reg bit_d_6;//N
reg bit_d_7;//P
reg bit_d_8;//N
reg bit_d_9;//P
//reg bit_d_ex;//P
wire bit_d_0;//N
wire bit_d_1;//P
wire bit_d_2;//N
wire bit_d_3;//P
wire bit_d_4;//N
wire bit_d_5;//P
wire bit_d_6;//N
wire bit_d_7;//P
wire bit_d_8;//N
wire bit_d_9;//P
 
reg is_control;
wire is_control;
reg is_data;
 
reg last_is_control;
reg last_is_data;
reg last_is_timec;
//reg last_is_timec;
 
reg last_was_control;
reg last_was_data;
86,60 → 85,45
 
reg [3:0] control;
reg [3:0] control_r;
reg [3:0] control_p_r;
reg [9:0] data;
reg [9:0] timecode;
 
reg [9:0] dta_timec;
reg [9:0] dta_timec_p;
 
reg [3:0] control_l_r;
reg [9:0] data_l_r;
 
//reg parity_error;
//wire check_c_d;
reg parity_rec_c;
reg parity_rec_d;
 
reg rx_data_take;
reg rx_data_take_0;
reg rx_error_c;
reg rx_error_d;
 
//wire [13:0] info_w;
reg first_time;
reg ready_control;
reg ready_data;
 
wire ready_control;
wire ready_data;
//CLOCK RECOVERY
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
reg parity_rec_c_gen;
reg parity_rec_d_gen;
 
assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
reg ready_control_p;
reg ready_data_p;
 
assign ready_control = is_control;
assign ready_data = (counter_neg == 5'd5)?is_data:1'b0;
reg ready_control_p_r;
reg ready_data_p_r;
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
wire posedge_p;
 
if(!rx_resetn)
begin
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
first_time <= 1'b0;
end
else
begin
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
first_time <= 1'b1;
reg f_time;
//CLOCK RECOVERY
assign posedge_clk = posedge_p;
assign negedge_clk = (f_time)?!posedge_p:1'b0;
 
end
assign rx_error = rx_error_c | rx_error_d;
 
end
buf (posedge_p,rx_din ^ rx_sin);
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
146,180 → 130,109
 
if(!rx_resetn)
begin
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
bit_c_ex <= 1'b0;
f_time <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
bit_c_ex <= bit_c_3;
f_time <= 1'b1;
end
 
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
always@(*)
begin
 
if(!rx_resetn)
rx_got_bit = 1'b0;
 
if(rx_din | rx_sin)
begin
bit_d_0 <= 1'b0;
bit_d_2 <= 1'b0;
bit_d_4 <= 1'b0;
bit_d_6 <= 1'b0;
bit_d_8 <= 1'b0;
rx_got_bit = 1'b1;
end
else
begin
bit_d_0 <= rx_din;
bit_d_2 <= bit_d_0;
bit_d_4 <= bit_d_2;
bit_d_6 <= bit_d_4;
bit_d_8 <= bit_d_6;
end
end
 
 
always@(posedge negedge_clk or negedge rx_resetn)
always@(*)
begin
 
if(!rx_resetn)
ready_control = 1'b0;
ready_data = 1'b0;
 
if(is_control && counter_neg[5:0] == 6'd4 && !posedge_p)
begin
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
ready_control = 1'b1;
ready_data = 1'b0;
end
else
else if(is_control && counter_neg[5:0] == 6'd32 && !posedge_p)
begin
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
ready_control = 1'b0;
ready_data = 1'b1;
end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
bit_capture_data capture_d(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_d_0(bit_d_0),//N
.bit_d_1(bit_d_1),//P
.bit_d_2(bit_d_2),//N
.bit_d_3(bit_d_3),//P
.bit_d_4(bit_d_4),//N
.bit_d_5(bit_d_5),//P
.bit_d_6(bit_d_6),//N
.bit_d_7(bit_d_7),//P
.bit_d_8(bit_d_8),//N
.bit_d_9(bit_d_9)//P
);
 
bit_capture_control capture_c(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_c_0(bit_c_0),
.bit_c_1(bit_c_1),
.bit_c_2(bit_c_2),
.bit_c_3(bit_c_3)
);
 
counter_neg cnt_neg(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.is_control(is_control),
.counter_neg(counter_neg)
);
 
always@(*)
begin
 
if(!rx_resetn)
next_state_data_process = state_data_process;
 
case(state_data_process)
2'd0:
begin
is_control <= 1'b0;
is_data <= 1'b0;
control_bit_found <= 1'b0;
counter_neg <= 5'd0;
end
else
begin
if(counter_neg == 5'd0)
if(ready_control_p_r || ready_data_p_r)
begin
control_bit_found <= rx_din;
is_control <= 1'b0;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
next_state_data_process = 2'd1;
end
else if(counter_neg == 5'd1 && control_bit_found)
else
begin
is_control <= 1'b1;
is_data <= 1'b0;
counter_neg <= counter_neg + 5'd1;
next_state_data_process = 2'd0;
end
else if(counter_neg == 5'd1 && !control_bit_found)
begin
is_control <= 1'b0;
is_data <= 1'b1;
counter_neg <= counter_neg + 5'd1;
end
else
begin
 
if(is_control)
begin
control_bit_found <= rx_din;
if(counter_neg == 5'd2)
begin
counter_neg <= 5'd1;
is_control <= 1'b0;
is_data <= 1'b0;
end
end
else if(is_data)
begin
if(counter_neg == 5'd5)
begin
control_bit_found <= rx_din;
counter_neg <= 5'd1;
is_data <= 1'b0;
is_control <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
end
 
end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
2'd1:
begin
rx_error <= 1'b0;
end
else
next_state_data_process = 2'd0;
end
default:
begin
if(last_is_control)
begin
if(last_was_control)
begin
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
begin
rx_error <= 1'b1;
end
end
else if(last_was_timec)
begin
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
begin
rx_error <= 1'b1;
end
end
else if(last_was_data)
begin
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
begin
rx_error <= 1'b1;
end
end
 
end
else if(last_is_data)
begin
if(last_was_control)
begin
if(!(data[8]^control[1]^control[0]) != data[9])
begin
rx_error <= 1'b1;
end
end
else if(last_was_timec)
begin
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
begin
rx_error <= 1'b1;
end
end
else if(last_was_data)
begin
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
begin
rx_error <= 1'b1;
end
end
end
end
 
next_state_data_process = 2'd0;
end
endcase
end
 
always@(posedge negedge_clk or negedge rx_resetn)
376,45 → 289,73
begin
if(!rx_resetn)
begin
rx_buffer_write <= 1'b0;
rx_data_take_0 <= 1'b0;
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
else
begin
rx_data_take_0 <= rx_data_take;
rx_buffer_write <= rx_data_take_0;
 
if(counter_neg[5:0] == 6'd4 && is_control)
begin
ready_control_p_r <= 1'b1;
end
else if(counter_neg[5:0] == 6'd32)
begin
ready_data_p_r <= 1'b1;
end
else
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
end
end
 
always@(posedge ready_control or negedge rx_resetn )
always@(posedge posedge_clk or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_r <= 4'd0;
parity_rec_c <= 1'b0;
parity_rec_c_gen <= 1'b0;
end
else
begin
if(counter_neg == 5'd2)
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
else if(counter_neg == 5'd1 && control == 4'd7)
control_r <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
else
control_r <= control_r;
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
parity_rec_c <= bit_c_3;
 
if(last_is_control)
begin
parity_rec_c_gen <= !(bit_c_2^control[0]^control[1]);
end
else if(last_is_data)
begin
parity_rec_c_gen <= !(bit_c_2^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
end
end
end
 
always@(posedge ready_data or negedge rx_resetn )
always@(posedge posedge_clk or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec <= 10'd0;
parity_rec_d <= 1'b0;
parity_rec_d_gen <= 1'b0;
end
else
begin
if(counter_neg == 5'd5)
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
else
dta_timec <= dta_timec;
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
parity_rec_d <= bit_d_9;
 
if(last_is_control)
begin
parity_rec_d_gen <= !(bit_d_8^control[0]^control[1]);
end
else if(last_is_data)
begin
parity_rec_d_gen <= !(bit_d_8^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
end
end
end
 
423,127 → 364,96
 
if(!rx_resetn)
begin
control <= 4'd0;
control_l_r <= 4'd0;
control_l_r <= 4'd0;
control <= 4'd0;
data <= 10'd0;
 
data <= 10'd0;
data_l_r <= 10'd0;
//rx_data_flag <= 9'd0;
//rx_buffer_write <= 1'b0;
//rx_data_take <= 1'b0;
last_is_control <= 1'b0;
last_is_data <= 1'b0;
//last_is_timec <= 1'b0;
 
timecode <= 10'd0;
// rx_time_out <= 8'd0;
// rx_tick_out <= 1'b0;
state_data_process <= 2'd0;
info <= 14'd0;
 
last_is_control <=1'b0;
last_is_data <=1'b0;
last_is_timec <=1'b0;
 
last_was_control <=1'b0;
last_was_data <=1'b0;
last_was_timec <=1'b0;
info <= 14'd0;
//rx_error <= 1'b0;
//rx_got_null <= 1'b0;
//rx_got_nchar <= 1'b0;
//rx_got_time_code <= 1'b0;
//rx_got_fct <= 1'b0;
//meta_hold_setup <= 1'b0;
//meta_hold_setup_n <= 1'b0;
//meta_hold_setup_n_n<= 1'b0;
 
rx_error_c <= 1'b0;
rx_error_d <= 1'b0;
end
else
begin
 
//meta_hold_setup_n_n <= meta_hold_setup;
//meta_hold_setup_n <= meta_hold_setup_n_n;
state_data_process <= next_state_data_process;
 
if(ready_control)
case(state_data_process)
2'd0:
begin
control <= control_r;
control_l_r <= control;
 
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
if(ready_control_p_r)
begin
control <= control_p_r;
control_l_r <= control;
 
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
last_is_control <= 1'b1;
last_is_data <= 1'b0;
//last_is_timec <= 1'b0;
 
end
else if(ready_data)
begin
if(control[2:0] != 3'd7)
end
else if(ready_data_p_r)
begin
data <= dta_timec;
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
if(control[2:0] != 3'd7)
begin
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <=1'b0;
last_is_data <=1'b1;
//last_is_timec <=1'b0;
end
else if(control[2:0] == 3'd7)
begin
last_is_control <= 1'b0;
last_is_data <= 1'b0;
//last_is_timec <= 1'b1;
end
end
else if(control[2:0] == 3'd7)
else
begin
timecode <= dta_timec;
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
 
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
end
else if(last_is_data)
2'd1:
begin
if(ready_control_p_r)
begin
 
data_l_r <= data;
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
if(parity_rec_c_gen != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
else
rx_error_c <= rx_error_c;
 
rx_data_take <= 1'b1;
//rx_tick_out <= 1'b0;
//meta_hold_setup <= 1'b0;
end
else if(last_is_timec)
begin
//rx_tick_out <= 1'b1;
rx_data_take <= 1'b1;
end
else if(ready_data_p_r)
begin
 
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
if(parity_rec_d_gen != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
else
rx_error_d <= rx_error_d;
//meta_hold_setup <= 1'b0;
 
end
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
end
else if(last_is_control)
default:
begin
 
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
rx_data_take <= 1'b0;
 
if((control[2:0] == 3'd6) == 1'b1 )
begin
data <= 10'b0100000001;
end
else if( (control[2:0] == 3'd5 ) == 1'b1 )
begin
data <= 10'b0100000000;
end
 
end
else
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
endcase
end
end
end
endmodule
/write_axi.v
32,6 → 32,7
//-FHDR------------------------------------------------------------------------
module write_axi(
input clock_recovery,
input clock_50,
input reset_n,
input [13:0] data_rec,
output reg [13:0] data_stand
38,7 → 39,7
);
 
 
always@(posedge clock_recovery or negedge reset_n )
always@(posedge clock_50 or negedge reset_n )
begin
 
if(!reset_n)
47,7 → 48,10
end
else
begin
data_stand <= data_rec;
if(clock_recovery)
data_stand <= data_rec;
else
data_stand <= data_stand;
end
end
 

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