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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

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  • This comparison shows the changes necessary to convert path 
    /spacewiresystemc/trunk/rtl/RTL_VB
    from Rev 39 to Rev 40
    ↔ Reverse comparison
  •

Rev 39 → Rev 40

/fifo_rx.v
42,12 → 42,10
output reg f_full,f_empty,
output reg open_slot_fct,
output reg overflow_credit_error,
output reg [DWIDTH-1:0] data_out,
output [DWIDTH-1:0] data_out,
output reg [AWIDTH-1:0] counter
);
 
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
 
59,11 → 57,59
reg [1:0] state_data_read;
reg [1:0] next_state_data_read;
 
reg [1:0] state_open_slot;
reg [1:0] next_state_open_slot;
 
reg [10:0] counter_wait;
 
/****************************************/
 
always@(*)
begin
next_state_open_slot = state_open_slot;
 
case(state_open_slot)
2'd0:
begin
if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
begin
next_state_open_slot = 2'd1;
end
else
begin
next_state_open_slot = 2'd0;
end
end
2'd1:
begin
if(counter_wait != 11'd300)
next_state_open_slot = 2'd1;
else
next_state_open_slot = 2'd2;
end
2'd2:
begin
if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
begin
next_state_open_slot = 2'd2;
end
else
begin
next_state_open_slot = 2'd0;
end
end
default:
begin
next_state_open_slot = 2'd0;
end
endcase
end
 
/****************************************/
 
always@(*)
begin
next_state_data_write = state_data_write;
 
case(state_data_write)
140,85 → 186,60
endcase
end
 
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
state_open_slot <= 2'd0;
open_slot_fct<= 1'b0;
counter_wait <= 11'd0;
end
else
begin
state_open_slot <= next_state_open_slot;
 
case(state_open_slot)
2'd0:
begin
if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
begin
open_slot_fct<= 1'b1;
counter_wait <= counter_wait + 11'd1;
end
else
begin
open_slot_fct<= 1'b0;
end
end
2'd1:
begin
if(counter_wait != 11'd300)
counter_wait <= counter_wait + 11'd1;
else
counter_wait <= counter_wait;
open_slot_fct<= 1'b1;
end
2'd2:
begin
counter_wait <= 11'd0;
open_slot_fct<= 1'b0;
end
default:
begin
open_slot_fct<= open_slot_fct;
end
endcase
 
end
end
//Write pointer
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
state_data_write <= 2'd0;
wr_ptr <= {(AWIDTH){1'b0}};
mem[0] <= {(DWIDTH){1'b0}};
mem[1] <= {(DWIDTH){1'b0}};
mem[2] <= {(DWIDTH){1'b0}};
mem[3] <= {(DWIDTH){1'b0}};
mem[4] <= {(DWIDTH){1'b0}};
mem[5] <= {(DWIDTH){1'b0}};
mem[6] <= {(DWIDTH){1'b0}};
mem[7] <= {(DWIDTH){1'b0}};
mem[8] <= {(DWIDTH){1'b0}};
mem[9] <= {(DWIDTH){1'b0}};
mem[10] <= {(DWIDTH){1'b0}};
 
mem[11] <= {(DWIDTH){1'b0}};
mem[12] <= {(DWIDTH){1'b0}};
mem[13] <= {(DWIDTH){1'b0}};
mem[14] <= {(DWIDTH){1'b0}};
mem[15] <= {(DWIDTH){1'b0}};
mem[16] <= {(DWIDTH){1'b0}};
mem[17] <= {(DWIDTH){1'b0}};
mem[18] <= {(DWIDTH){1'b0}};
mem[19] <= {(DWIDTH){1'b0}};
mem[20] <= {(DWIDTH){1'b0}};
mem[21] <= {(DWIDTH){1'b0}};
 
mem[22] <= {(DWIDTH){1'b0}};
mem[23] <= {(DWIDTH){1'b0}};
mem[24] <= {(DWIDTH){1'b0}};
mem[25] <= {(DWIDTH){1'b0}};
mem[26] <= {(DWIDTH){1'b0}};
mem[27] <= {(DWIDTH){1'b0}};
mem[28] <= {(DWIDTH){1'b0}};
mem[29] <= {(DWIDTH){1'b0}};
mem[30] <= {(DWIDTH){1'b0}};
mem[31] <= {(DWIDTH){1'b0}};
mem[32] <= {(DWIDTH){1'b0}};
 
 
mem[33] <= {(DWIDTH){1'b0}};
mem[34] <= {(DWIDTH){1'b0}};
mem[35] <= {(DWIDTH){1'b0}};
mem[36] <= {(DWIDTH){1'b0}};
mem[37] <= {(DWIDTH){1'b0}};
mem[38] <= {(DWIDTH){1'b0}};
mem[39] <= {(DWIDTH){1'b0}};
mem[40] <= {(DWIDTH){1'b0}};
mem[41] <= {(DWIDTH){1'b0}};
mem[42] <= {(DWIDTH){1'b0}};
mem[43] <= {(DWIDTH){1'b0}};
 
mem[44] <= {(DWIDTH){1'b0}};
mem[45] <= {(DWIDTH){1'b0}};
mem[46] <= {(DWIDTH){1'b0}};
mem[47] <= {(DWIDTH){1'b0}};
mem[48] <= {(DWIDTH){1'b0}};
mem[49] <= {(DWIDTH){1'b0}};
mem[50] <= {(DWIDTH){1'b0}};
mem[51] <= {(DWIDTH){1'b0}};
mem[52] <= {(DWIDTH){1'b0}};
mem[53] <= {(DWIDTH){1'b0}};
mem[54] <= {(DWIDTH){1'b0}};
 
mem[55] <= {(DWIDTH){1'b0}};
mem[56] <= {(DWIDTH){1'b0}};
mem[57] <= {(DWIDTH){1'b0}};
mem[58] <= {(DWIDTH){1'b0}};
mem[59] <= {(DWIDTH){1'b0}};
mem[60] <= {(DWIDTH){1'b0}};
mem[61] <= {(DWIDTH){1'b0}};
mem[62] <= {(DWIDTH){1'b0}};
mem[63] <= {(DWIDTH){1'b0}};
 
state_data_write <= 2'd0;
end
else
begin
228,14 → 249,11
case(state_data_write)
2'd0:
begin
mem[wr_ptr]<=data_in;
wr_ptr <= wr_ptr;
end
2'd1:
begin
if(wr_en)
mem[wr_ptr]<=data_in;
else
mem[wr_ptr]<=mem[wr_ptr];
wr_ptr <= wr_ptr;
end
2'd2:
begin
243,7 → 261,6
end
default:
begin
mem[wr_ptr]<=mem[wr_ptr];
wr_ptr <= wr_ptr;
end
endcase
253,85 → 270,58
 
//FULL - EMPTY COUNTER
 
always@(posedge clock or negedge reset)
always@(posedge clock or negedge reset)
begin
if (!reset)
begin
if (!reset)
f_full <= 1'b0;
f_empty <= 1'b0;
overflow_credit_error<=1'b0;
counter <= {(AWIDTH){1'b0}};
end
else
begin
if(state_data_write == 2'd2)
begin
overflow_credit_error<=1'b0;
counter <= {(AWIDTH){1'b0}};
credit_counter <= 6'd55;
counter <= counter + 6'd1;
end
else
begin
 
if (state_data_write == 2'd2)
begin
if(credit_counter == 6'd0)
credit_counter <= credit_counter;
else
credit_counter <= credit_counter - 6'd1;
end
else if(state_data_read == 2'd2)
begin
if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
begin
if(credit_counter < 6'd48)
credit_counter <= credit_counter + 6'd8;
else
credit_counter <= credit_counter + 6'd7;
end
else
credit_counter <= credit_counter;
end
else
begin
if(credit_counter > 6'd55)
begin
overflow_credit_error <= 1'b1;
end
else
overflow_credit_error <= 1'b0;
end
 
if (state_data_write == 2'd2)
begin
if(counter == 6'd63)
counter <= counter;
else
counter <= counter + 6'd1;
end
else if(state_data_read == 2'd2)
begin
if(counter == 6'd0)
counter <= counter;
else
counter <= counter - 6'd1;
end
if(counter > 6'd0 && state_data_read == 2'd2)
counter <= counter - 6'd1;
else
begin
counter <= counter;
end
end
end
 
always@(*)
begin
if(counter > 6'd56)
begin
overflow_credit_error <= 1'b1;
end
else
overflow_credit_error <= 1'b0;
 
f_full = 1'b0;
f_empty = 1'b0;
if(counter == 6'd56)
begin
f_full <= 1'b1;
end
else
begin
f_full <= 1'b0;
end
 
if(counter == 6'd63)
begin
f_full = 1'b1;
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
end
end
 
if(counter == 6'd0)
begin
f_empty = 1'b1;
end
 
end
 
//Read pointer
always@(posedge clock or negedge reset)
begin
338,13 → 328,11
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
open_slot_fct<= 1'b0;
state_data_read <= 2'd0;
end
else
begin
 
state_data_read <= next_state_data_read;
 
case(state_data_read)
352,46 → 340,25
begin
if(rd_en)
begin
data_out <= data_out;
open_slot_fct<= open_slot_fct;
rd_ptr <= rd_ptr+ 6'd1;
end
else
begin
open_slot_fct<= open_slot_fct;
data_out <= mem[rd_ptr];
rd_ptr <= rd_ptr;
end
end
2'd1:
begin
if(rd_ptr == 6'd7 || rd_ptr == 6'd15 || rd_ptr == 6'd23 || rd_ptr == 6'd31 || rd_ptr == 6'd39 || rd_ptr == 6'd47 || rd_ptr == 6'd55 || rd_ptr == 6'd63)
begin
open_slot_fct<= 1'b1;
end
else
begin
open_slot_fct<= 1'b0;
end
 
if(rd_en)
begin
data_out <= mem[rd_ptr];
end
else
begin
data_out <= data_out;
end
rd_ptr <= rd_ptr;
end
2'd2:
begin
open_slot_fct<= open_slot_fct;
data_out <= data_out;
rd_ptr <= rd_ptr;
end
default:
begin
rd_ptr <= rd_ptr;
data_out <= data_out;
 
end
endcase
 
399,4 → 366,15
end
end
 
 
mem_data mem_dta_fifo_rx(
 
.clock(clock),
.reset(reset),
 
.data_in(data_in),
.wr_ptr(wr_ptr),
.rd_ptr(rd_ptr),
.data_out(data_out)
);
endmodule
/fifo_tx.v
38,23 → 38,24
 
(
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in,
input [DWIDTH-1:0] data_in/* synthesis syn_noprune */,
output reg f_full,write_tx,f_empty,
output reg [DWIDTH-1:0] data_out,
output reg [AWIDTH-1:0] counter
output [DWIDTH-1:0] data_out/* synthesis syn_noprune */,
output reg [AWIDTH-1:0] counter/* synthesis syn_noprune */
);
reg [AWIDTH-1:0] wr_ptr/* synthesis syn_noprune */;
reg [AWIDTH-1:0] rd_ptr/* synthesis syn_noprune */;
 
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
reg [AWIDTH-1:0] wr_ptr;
reg [AWIDTH-1:0] rd_ptr;
 
reg [1:0] state_data_write;
reg [1:0] next_state_data_write;
 
reg [1:0] state_data_read;
reg [1:0] next_state_data_read;
 
//reg [AWIDTH-1:0] counter_writer/* synthesis syn_noprune */;
//reg [AWIDTH-1:0] counter_reader/* synthesis syn_noprune */;
 
 
/****************************************/
 
always@(*)
104,7 → 105,7
case(state_data_read)
2'd0:
begin
if(rd_en && !f_empty)
if(counter > 6'd0)
begin
next_state_data_read = 2'd1;
end
115,17 → 116,28
end
2'd1:
begin
if(rd_en)
if(rd_en && !f_empty)
begin
next_state_data_read = 2'd1;
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd2;
next_state_data_read = 2'd1;
end
end
2'd2:
begin
if(rd_en)
begin
next_state_data_read = 2'd2;
end
else
begin
next_state_data_read = 2'd3;
end
end
2'd3:
begin
next_state_data_read = 2'd0;
end
default:
140,77 → 152,6
begin
if (!reset)
begin
mem[0] <= {(DWIDTH){1'b0}};
mem[1] <= {(DWIDTH){1'b0}};
mem[2] <= {(DWIDTH){1'b0}};
mem[3] <= {(DWIDTH){1'b0}};
mem[4] <= {(DWIDTH){1'b0}};
mem[5] <= {(DWIDTH){1'b0}};
mem[6] <= {(DWIDTH){1'b0}};
mem[7] <= {(DWIDTH){1'b0}};
mem[8] <= {(DWIDTH){1'b0}};
mem[9] <= {(DWIDTH){1'b0}};
mem[10] <= {(DWIDTH){1'b0}};
 
mem[11] <= {(DWIDTH){1'b0}};
mem[12] <= {(DWIDTH){1'b0}};
mem[13] <= {(DWIDTH){1'b0}};
mem[14] <= {(DWIDTH){1'b0}};
mem[15] <= {(DWIDTH){1'b0}};
mem[16] <= {(DWIDTH){1'b0}};
mem[17] <= {(DWIDTH){1'b0}};
mem[18] <= {(DWIDTH){1'b0}};
mem[19] <= {(DWIDTH){1'b0}};
mem[20] <= {(DWIDTH){1'b0}};
mem[21] <= {(DWIDTH){1'b0}};
 
mem[22] <= {(DWIDTH){1'b0}};
mem[23] <= {(DWIDTH){1'b0}};
mem[24] <= {(DWIDTH){1'b0}};
mem[25] <= {(DWIDTH){1'b0}};
mem[26] <= {(DWIDTH){1'b0}};
mem[27] <= {(DWIDTH){1'b0}};
mem[28] <= {(DWIDTH){1'b0}};
mem[29] <= {(DWIDTH){1'b0}};
mem[30] <= {(DWIDTH){1'b0}};
mem[31] <= {(DWIDTH){1'b0}};
mem[32] <= {(DWIDTH){1'b0}};
 
 
mem[33] <= {(DWIDTH){1'b0}};
mem[34] <= {(DWIDTH){1'b0}};
mem[35] <= {(DWIDTH){1'b0}};
mem[36] <= {(DWIDTH){1'b0}};
mem[37] <= {(DWIDTH){1'b0}};
mem[38] <= {(DWIDTH){1'b0}};
mem[39] <= {(DWIDTH){1'b0}};
mem[40] <= {(DWIDTH){1'b0}};
mem[41] <= {(DWIDTH){1'b0}};
mem[42] <= {(DWIDTH){1'b0}};
mem[43] <= {(DWIDTH){1'b0}};
 
mem[44] <= {(DWIDTH){1'b0}};
mem[45] <= {(DWIDTH){1'b0}};
mem[46] <= {(DWIDTH){1'b0}};
mem[47] <= {(DWIDTH){1'b0}};
mem[48] <= {(DWIDTH){1'b0}};
mem[49] <= {(DWIDTH){1'b0}};
mem[50] <= {(DWIDTH){1'b0}};
mem[51] <= {(DWIDTH){1'b0}};
mem[52] <= {(DWIDTH){1'b0}};
mem[53] <= {(DWIDTH){1'b0}};
mem[54] <= {(DWIDTH){1'b0}};
 
mem[55] <= {(DWIDTH){1'b0}};
mem[56] <= {(DWIDTH){1'b0}};
mem[57] <= {(DWIDTH){1'b0}};
mem[58] <= {(DWIDTH){1'b0}};
mem[59] <= {(DWIDTH){1'b0}};
mem[60] <= {(DWIDTH){1'b0}};
mem[61] <= {(DWIDTH){1'b0}};
mem[62] <= {(DWIDTH){1'b0}};
mem[63] <= {(DWIDTH){1'b0}};
 
wr_ptr <= {(AWIDTH){1'b0}};
state_data_write <= 2'd0;
end
222,12 → 163,11
case(state_data_write)
2'd0:
begin
mem[wr_ptr]<=mem[wr_ptr];
wr_ptr <= wr_ptr;
end
2'd1:
begin
mem[wr_ptr]<=data_in;
wr_ptr <= wr_ptr;
end
2'd2:
begin
235,7 → 175,6
end
default:
begin
mem[wr_ptr]<=mem[wr_ptr];
wr_ptr <= wr_ptr;
end
endcase
247,6 → 186,8
begin
if (!reset)
begin
f_full <= 1'b0;
f_empty <= 1'b0;
counter <= {(AWIDTH){1'b0}};
end
else
254,45 → 195,37
 
if(state_data_write == 2'd2)
begin
if(counter == 6'd63)
counter <= counter;
else
counter <= counter + 6'd1;
counter <= counter + 6'd1;
end
else if(state_data_read == 2'd2)
else
begin
if(counter == 6'd0)
counter <= counter;
if(counter > 6'd0 && state_data_read == 2'd3)
counter <= counter - 6'd1;
else
counter <= counter - 6'd1;
counter <= counter;
end
 
if(counter == 6'd63)
begin
f_full <= 1'b1;
end
else
begin
counter <= counter;
f_full <= 1'b0;
end
 
if(counter == 6'd0)
begin
f_empty <= 1'b1;
end
else
begin
f_empty <= 1'b0;
end
end
end
 
 
always@(*)
begin
 
f_full = 1'b0;
f_empty = 1'b0;
 
if(counter == 6'd63)
begin
f_full = 1'b1;
end
 
if(counter == 6'd0)
begin
f_empty = 1'b1;
end
 
end
 
//Read pointer
always@(posedge clock or negedge reset)
begin
299,7 → 232,6
if (!reset)
begin
rd_ptr <= {(AWIDTH){1'b0}};
data_out <= 9'd0;
write_tx <= 1'b0;
state_data_read <= 2'd0;
end
306,44 → 238,49
else
begin
state_data_read <= next_state_data_read;
 
case(state_data_read)
2'd0:
begin
if(rd_en)
write_tx<= 1'b0;
end
2'd1:
begin
if(rd_en && !f_empty)
begin
write_tx<= 1'b0;
rd_ptr <= rd_ptr + 6'd1;
end
else
begin
data_out <= mem[rd_ptr];
rd_ptr <= rd_ptr;
end
 
if(counter > 6'd0)
begin
write_tx<= 1'b1;
end
else
write_tx<= 1'b0;
end
write_tx<= 1'b1;
end
2'd1:
2'd2:
begin
write_tx<= 1'b0;
data_out <= mem[rd_ptr];
end
2'd2:
2'd3:
begin
write_tx<= 1'b0;
data_out <= mem[rd_ptr];
end
default:
begin
rd_ptr <= rd_ptr;
data_out <= data_out;
end
endcase
end
end
 
mem_data mem_dta_fifo_tx(
 
.clock(clock),
.reset(reset),
 
.data_in(data_in),
.wr_ptr(wr_ptr),
.rd_ptr(rd_ptr),
.data_out(data_out)
);
 
endmodule
/fsm_spw.v
77,6 → 77,14
 
reg got_bit_internal;
 
reg get_rx_got_fct_a, get_rx_got_fct_b;
reg get_rx_error_a, get_rx_error_b;
reg get_rx_got_null_a, get_rx_got_null_b;
 
reg get_rx_got_nchar_a, get_rx_got_nchar_b;
reg get_rx_got_time_code_a, get_rx_got_time_code_b;
reg get_rx_credit_error_a, get_rx_credit_error_b;
 
//
assign fsm_state = state_fsm;
 
106,7 → 114,7
begin
next_state_fsm = ready;
end
else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
else if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | rx_got_time_code)
begin
next_state_fsm = error_reset;
end
115,11 → 123,11
ready:
begin
 
if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a)
begin
next_state_fsm = error_reset;
end
else if(((!link_disable) & (link_start |(auto_start & rx_got_null)))==1'b1)
else if(((!link_disable) & (link_start |(auto_start & get_rx_got_null_a)))==1'b1)
begin
next_state_fsm = started;
end
128,11 → 136,11
started:
begin
 
if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
begin
next_state_fsm = error_reset;
end
else if((rx_got_null & rx_got_bit)== 1'b1)
else if((get_rx_got_null_a & rx_got_bit)== 1'b1)
begin
next_state_fsm = connecting;
end
141,11 → 149,11
connecting:
begin
 
if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
if(get_rx_error_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
begin
next_state_fsm = error_reset;
end
else if(rx_got_fct)
else if(get_rx_got_fct_a)
begin
next_state_fsm = run;
end
154,7 → 162,7
run:
begin
 
if(rx_error | rx_credit_error | link_disable | after850ns == 12'd85)
if(get_rx_error_a | get_rx_credit_error_a | link_disable | after850ns == 12'd85)
begin
next_state_fsm = error_reset;
end
175,13 → 183,47
 
rx_resetn <= 1'b0;
 
enable_tx<= 1'b0;
send_null_tx<= 1'b0;
send_fct_tx<= 1'b0;
enable_tx <= 1'b0;
send_null_tx <= 1'b0;
send_fct_tx <= 1'b0;
 
get_rx_got_fct_a <= 1'b0;
get_rx_got_fct_b <= 1'b0;
get_rx_error_a <= 1'b0;
get_rx_error_b <= 1'b0;
get_rx_got_null_a <= 1'b0;
get_rx_got_null_b <= 1'b0;
 
 
get_rx_got_nchar_a <= 1'b0;
get_rx_got_nchar_b <= 1'b0;
get_rx_got_time_code_a <= 1'b0;
get_rx_got_time_code_b <= 1'b0;
get_rx_credit_error_a <= 1'b0;
get_rx_credit_error_b <= 1'b0;
 
end
else
begin
 
get_rx_got_fct_b <= rx_got_fct;
get_rx_got_fct_a <= get_rx_got_fct_b;
 
get_rx_error_b <= rx_error;
get_rx_error_a <= get_rx_error_b;
 
get_rx_got_null_b <= rx_got_null;
get_rx_got_null_a <= get_rx_got_null_b;
 
get_rx_got_nchar_b <= rx_got_nchar;
get_rx_got_nchar_a <= get_rx_got_nchar_b;
 
get_rx_got_time_code_b <= rx_got_time_code;
get_rx_got_time_code_a <= get_rx_got_time_code_b;
 
get_rx_credit_error_b <= rx_credit_error;
get_rx_credit_error_a <= get_rx_credit_error_b;
 
state_fsm <= next_state_fsm;
 
case(state_fsm)
/rx_spw.v
42,650 → 42,286
output rx_error,
 
output reg rx_got_bit,
output reg rx_got_null,
output reg rx_got_nchar,
output reg rx_got_time_code,
output reg rx_got_fct,
output reg rx_got_fct_fsm,
output rx_got_null,
output rx_got_nchar,
output rx_got_time_code,
output rx_got_fct,
output rx_got_fct_fsm,
 
output reg [8:0] rx_data_flag,
output reg rx_buffer_write,
output [8:0] rx_data_flag,
output rx_buffer_write,
 
output [7:0] rx_time_out,
output reg rx_tick_out
output rx_tick_out
);
 
 
reg [5:0] counter_neg;
reg control_bit_found;
reg data_bit_found;
wire [5:0] counter_neg/* synthesis syn_replicate = 0 */;
 
wire posedge_clk;
wire negedge_clk;
 
reg [1:0] state_data_process;
reg [1:0] next_state_data_process;
wire bit_c_0;//N
wire bit_c_1;//P
wire bit_c_2;//N
wire bit_c_3;//P
 
reg bit_c_0;//N
reg bit_c_1;//P
reg bit_c_2;//N
reg bit_c_3;//P
wire bit_d_0;//N
wire bit_d_1;//P
wire bit_d_2;//N
wire bit_d_3;//P
wire bit_d_4;//N
wire bit_d_5;//P
wire bit_d_6;//N
wire bit_d_7;//P
wire bit_d_8;//N
wire bit_d_9;//P
 
reg bit_d_0;//N
reg bit_d_1;//P
reg bit_d_2;//N
reg bit_d_3;//P
reg bit_d_4;//N
reg bit_d_5;//P
reg bit_d_6;//N
reg bit_d_7;//P
reg bit_d_8;//N
reg bit_d_9;//P
wire [1:0] state_data_process;
 
reg is_control;
reg parity_received;
wire is_control/* synthesis dont_replicate */;
wire last_is_control;
wire last_is_data;
wire last_is_timec;
 
reg last_is_control;
reg last_is_data;
reg last_is_timec;
wire [2:0] control_p_r/* synthesis dont_replicate */;
wire [7:0] timecode/* synthesis dont_replicate */;
 
reg [3:0] control;
reg [3:0] control_r;
reg [3:0] control_p_r;
reg [9:0] data;
reg [9:0] timecode;
wire [2:0] control_l_r/* synthesis dont_replicate */;
 
reg [3:0] control_l_r;
wire [8:0] dta_timec_p/* synthesis dont_replicate */;
 
reg [9:0] dta_timec;
reg [9:0] dta_timec_p;
 
reg ready_control;
reg ready_data;
 
reg ready_control_p;
reg ready_data_p;
wire ready_control_p_r;
wire ready_data_p_r;
 
reg ready_control_p_r;
reg ready_data_p_r;
wire parity_rec_c;
wire parity_rec_d;
 
reg parity_rec_c;
reg parity_rec_d;
wire parity_rec_c_gen;
wire parity_rec_d_gen;
 
reg rx_error_c;
reg rx_error_d;
wire rx_error_c;
wire rx_error_d;
 
reg posedge_p;
wire posedge_p/* synthesis syn_replicate = 0 */;
 
reg f_time;
//CLOCK RECOVERY
assign posedge_clk = posedge_p;
assign negedge_clk = !posedge_p;
assign negedge_clk = (f_time)?!posedge_p:1'b0;
 
assign rx_time_out = timecode[7:0];
assign rx_time_out = timecode;
 
assign rx_error = rx_error_c | rx_error_d;
buf (posedge_p,rx_din ^ rx_sin);
 
always@(*)
begin
 
rx_got_bit = 1'b0;
 
if(rx_din | rx_sin)
begin
rx_got_bit = 1'b1;
end
end
 
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
 
if(counter_neg[5:0] == 6'd4 && !posedge_p)
begin
ready_control = 1'b1;
end
else if(counter_neg[5:0] == 6'd32 && !posedge_p)
begin
ready_data = 1'b1;
end
end
 
 
always@(*)
begin
ready_control_p = 1'b0;
ready_data_p = 1'b0;
 
if(counter_neg[5:0] == 6'd4 && posedge_p)
begin
ready_control_p = 1'b1;
end
else if(counter_neg[5:0] == 6'd32 && posedge_p)
begin
ready_data_p = 1'b1;
end
end
 
always@(*)
begin
posedge_p = 1'b0;
 
if(rx_din ^ rx_sin)
begin
posedge_p = 1'b1;
end
else
begin
posedge_p = 1'b0;
end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
f_time <= 1'b0;
end
else
begin
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
f_time <= 1'b1;
end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
always@(*)
begin
 
if(!rx_resetn)
begin
bit_d_0 <= 1'b0;
bit_d_2 <= 1'b0;
bit_d_4 <= 1'b0;
bit_d_6 <= 1'b0;
bit_d_8 <= 1'b0;
rx_got_bit = 1'b0;
 
end
else
if(rx_din | rx_sin)
begin
bit_d_0 <= rx_din;
bit_d_2 <= bit_d_0;
bit_d_4 <= bit_d_2;
bit_d_6 <= bit_d_4;
bit_d_8 <= bit_d_6;
rx_got_bit = 1'b1;
end
end
 
always@(posedge posedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
end
else
begin
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
end
 
end
 
always@(posedge negedge_clk or negedge rx_resetn)
always@(*)
begin
ready_control = 1'b0;
ready_data = 1'b0;
 
if(!rx_resetn)
if(is_control && counter_neg == 6'd4 && !posedge_p)
begin
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
ready_control = 1'b1;
ready_data = 1'b0;
end
else
else if(!is_control && counter_neg == 6'd32 && !posedge_p)
begin
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
ready_control = 1'b0;
ready_data = 1'b1;
end
end
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
rx_got_fct <= 1'b0;
end
else
begin
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
begin
rx_got_fct <= 1'b1;
end
else
begin
rx_got_fct <= 1'b0;
end
end
end
rx_buffer_fsm buffer_fsm(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
.last_is_control(last_is_control),
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
.rx_got_null(rx_got_null),
.rx_got_nchar(rx_got_nchar),
.rx_got_time_code(rx_got_time_code)
);
 
if(!rx_resetn)
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
else
begin
if(last_is_data == 1'b1 )
begin
rx_got_nchar <= 1'b1;
end
else if(last_is_timec == 1'b1)
begin
rx_got_time_code <= 1'b1;
end
else if(last_is_control == 1'b1)
begin
rx_got_null <= 1'b1;
end
else
begin
rx_got_null <= 1'b0;
rx_got_nchar <= 1'b0;
rx_got_time_code <= 1'b0;
end
end
end
rx_data_buffer_data_w buffer_data_flag(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_fct_fsm <= 1'b0;
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
.state_data_process(state_data_process),
.control(control_p_r),
.last_is_timec(last_is_timec),
.last_is_data(last_is_data),
.last_is_control(last_is_control),
 
end
else
begin
.rx_buffer_write(rx_buffer_write),
.rx_tick_out(rx_tick_out)
);
 
if(ready_control || ready_control_p)
begin
if(is_control)
ready_control_p_r <= 1'b1;
else
ready_control_p_r <= 1'b0;
end
else
begin
ready_control_p_r <= 1'b0;
end
 
if(ready_data || ready_data_p)
begin
if(!is_control)
ready_data_p_r <= 1'b1;
else
ready_data_p_r <= 1'b0;
end
else
begin
ready_data_p_r <= 1'b0;
end
rx_control_data_rdy control_data_rdy(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
 
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
rx_got_fct_fsm <= 1'b1;
else
rx_got_fct_fsm <= rx_got_fct_fsm;
end
end
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
 
always@(posedge ready_control or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_r <= 4'd0;
parity_rec_c <= 1'b0;
end
else
begin
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
parity_rec_c <= bit_c_3;
end
end
.control(control_p_r),
.control_l_r(control_l_r[2:0]),
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
if(!rx_resetn)
begin
control_p_r <= 4'd0;
end
else
begin
control_p_r <= control_r;
end
end
.is_control(is_control),
.counter_neg(counter_neg),
.last_is_control(last_is_control),
 
.rx_error(rx_error),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.rx_got_fct_fsm(rx_got_fct_fsm)
);
 
 
always@(posedge ready_data or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec <= 10'd0;
parity_rec_d <= 1'b0;
end
else
begin
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
parity_rec_d <= bit_d_9;
end
end
rx_data_control_p data_control(
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
 
.bit_c_3(bit_c_3),
.bit_c_2(bit_c_2),
.bit_c_1(bit_c_1),
.bit_c_0(bit_c_0),
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
if(!rx_resetn)
begin
dta_timec_p <= 10'd0;
end
else
begin
dta_timec_p <= dta_timec;
end
end
 
always@(posedge ready_data_p or negedge rx_resetn )
begin
 
if(!rx_resetn)
begin
rx_error_d <= 1'b0;
end
else
begin
if(last_is_control)
begin
if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
end
else if(last_is_data)
begin
if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
begin
rx_error_d <= 1'b1;
end
end
end
end
 
always@(posedge ready_control_p or negedge rx_resetn )
begin
 
if(!rx_resetn)
begin
rx_error_c <= 1'b0;
end
else
begin
if(last_is_control)
begin
if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
end
else if(last_is_data)
begin
if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
begin
rx_error_c <= 1'b1;
end
end
end
.bit_d_9(bit_d_9),
.bit_d_8(bit_d_8),
.bit_d_0(bit_d_0),
.bit_d_1(bit_d_1),
.bit_d_2(bit_d_2),
.bit_d_3(bit_d_3),
.bit_d_4(bit_d_4),
.bit_d_5(bit_d_5),
.bit_d_6(bit_d_6),
.bit_d_7(bit_d_7),
end
.last_is_control(last_is_control),
.last_is_data(last_is_data),
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
else
begin
.is_control(is_control),
.counter_neg(counter_neg),
 
if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)
begin
if(last_is_timec == 1'b1)
begin
rx_tick_out <= 1'b1;
end
else if(last_is_data == 1'b1)
begin
rx_buffer_write <= 1'b1;
end
else if(last_is_control == 1'b1)
begin
if(control[2:0] == 3'd6)
begin
rx_buffer_write <= 1'b1;
end
else if(control[2:0] == 3'd5)
begin
rx_buffer_write <= 1'b1;
end
end
end
else
begin
rx_buffer_write <= 1'b0;
rx_tick_out <= 1'b0;
end
end
end
.dta_timec_p(dta_timec_p),
.parity_rec_d(parity_rec_d),
.parity_rec_d_gen(parity_rec_d_gen),
 
.control_p_r(control_p_r),
.control_l_r(control_l_r),
.parity_rec_c(parity_rec_c),
.parity_rec_c_gen(parity_rec_c_gen)
);
 
always@(posedge negedge_clk or negedge rx_resetn)
begin
 
if(!rx_resetn)
begin
is_control <= 1'b0;
control_bit_found <= 1'b0;
counter_neg[5:0] <= 6'd1;
end
else
begin
bit_capture_data capture_d(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_d_0(bit_d_0),//N
.bit_d_1(bit_d_1),//P
.bit_d_2(bit_d_2),//N
.bit_d_3(bit_d_3),//P
.bit_d_4(bit_d_4),//N
.bit_d_5(bit_d_5),//P
.bit_d_6(bit_d_6),//N
.bit_d_7(bit_d_7),//P
.bit_d_8(bit_d_8),//N
.bit_d_9(bit_d_9)//P
);
 
control_bit_found <= rx_din;
bit_capture_control capture_c(
.negedge_clk(negedge_clk),
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.bit_c_0(bit_c_0),
.bit_c_1(bit_c_1),
.bit_c_2(bit_c_2),
.bit_c_3(bit_c_3)
);
 
case(counter_neg)
6'd1:
begin
counter_neg[5:0] <= 6'd2;
end
6'd2:
begin
if(control_bit_found == 1'b1)
begin
is_control <= 1'b1;
end
else
begin
is_control <= 1'b0;
end
counter_neg cnt_neg(
.negedge_clk(negedge_clk),
.rx_resetn(rx_resetn),
.rx_din(rx_din),
.is_control(is_control),
.counter_neg(counter_neg)
);
 
counter_neg[5:0] <= 6'd4;
end
6'd4:
begin
if(is_control == 1'b1)
begin
counter_neg[5:0] <= 6'd2;
is_control <= 1'b0;
end
else
begin
counter_neg[5:0] <= 6'd8;
end
end
6'd8:
begin
counter_neg[5:0] <= 6'd16;
end
6'd16:
begin
counter_neg[5:0] <= 6'd32;
end
6'd32:
begin
is_control <= 1'b0;
counter_neg[5:0] <= 6'd2;
end
default:
begin
is_control <= is_control;
counter_neg[5:0] <= counter_neg[5:0];
end
endcase
rx_data_receive rx_dtarcv (
.posedge_clk(posedge_clk),
.rx_resetn(rx_resetn),
.ready_control_p_r(ready_control_p_r),
.ready_data_p_r(ready_data_p_r),
.ready_control(ready_control),
.ready_data(ready_data),
 
end
end
.parity_rec_c(parity_rec_c),
.parity_rec_d(parity_rec_d),
 
always@(*)
begin
.parity_rec_c_gen(parity_rec_c_gen),
.parity_rec_d_gen(parity_rec_d_gen),
 
next_state_data_process = state_data_process;
.control_p_r(control_p_r),
.dta_timec_p(dta_timec_p),
 
case(state_data_process)
2'd0:
begin
if(ready_control_p_r || ready_data_p_r)
begin
next_state_data_process = 2'd1;
end
else
begin
next_state_data_process = 2'd0;
end
end
2'd1:
begin
next_state_data_process = 2'd0;
end
default:
begin
next_state_data_process = 2'd0;
end
endcase
end
.control_l_r(control_l_r),
.state_data_process(state_data_process),
 
.last_is_control(last_is_control),
.last_is_data(last_is_data),
.last_is_timec(last_is_timec),
 
always@(posedge negedge_clk or negedge rx_resetn )
begin
.rx_error_c(rx_error_c),
.rx_error_d(rx_error_d),
.rx_got_fct(rx_got_fct),
 
if(!rx_resetn)
begin
control_l_r <= 4'd0;
control <= 4'd0;
data <= 10'd0;
.rx_data_flag(rx_data_flag),
 
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
.timecode(timecode)
);
 
rx_data_flag <= 9'd0;
timecode <= 10'd0;
 
state_data_process <= 2'd0;
end
else
begin
 
state_data_process <= next_state_data_process;
 
case(state_data_process)
2'd0:
begin
 
if(ready_control_p_r)
begin
control <= control_p_r;
control_l_r <= control;
 
if(control_p_r[2:0] == 3'd6)
begin
rx_data_flag <= 9'd257;
end
else if(control_p_r[2:0] == 3'd5)
begin
rx_data_flag <= 9'd256;
end
else
begin
rx_data_flag <= rx_data_flag;
end
 
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
 
end
else if(ready_data_p_r)
begin
if(control[2:0] != 3'd7)
begin
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
end
else if(control[2:0] == 3'd7)
begin
timecode <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
end
end
else
begin
timecode <= timecode;
end
end
2'd1:
begin
rx_data_flag <= rx_data_flag;
timecode <= timecode;
end
default:
begin
rx_data_flag <= rx_data_flag;
timecode <= timecode;
end
endcase
end
end
 
endmodule
/spw_ulight_con_top_x.v
30,11 → 30,14
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
 
`timescale 1ns/1ns
 
module spw_ulight_con_top_x(
input ppll_100_MHZ,
input ppllclk,
input reset_spw_n_b,
input top_sin,
input top_din,
77,11 → 80,11
wire [8:0] datarx_flag_w;
wire buffer_write_w;
wire [7:0] time_out_axi;
//wire [7:0] time_out_axi;
wire [13:0] monitor_x_axi;
wire [13:0] data_x;
wire rx_buffer_write_mon_x;
//wire [13:0] monitor_x_axi;
//wire [13:0] data_x;
//wire rx_buffer_write_mon_x;
 
wire credit_error_rx_w,top_send_fct_now_w;
89,7 → 92,7
wire [8:0] top_tx_data_w;
wire tx_reset_n;
 
assign tx_reset_n = (!reset_spw_n_b)?1'b0:1'b1;
assign tx_reset_n = (!reset_spw_n_b | top_fsm != 6'd16)?1'b0:1'b1;
 
//assign time_out = time_out_w;
assign datarx_flag = datarx_flag_axi;
/top_spw_ultra_light.v
86,7 → 86,6
 
wire got_fct_flag_fsm;
 
 
FSM_SPW FSM(
.pclk(pclk),
.resetn(resetn),
/tx_spw.v
50,1447 → 50,95
input gotfct_tx,
input send_fct_now,
//
output reg tx_dout_e,
output reg tx_sout_e,
//
output reg ready_tx_data,
output reg ready_tx_timecode
output ready_tx_data,
output ready_tx_timecode,
 
output tx_dout_e,
output tx_sout_e
 
);
wire [13:0] timecode_s;
 
localparam [6:0] tx_spw_start = 7'b0000000,
tx_spw_null = 7'b0000001,
tx_spw_fct = 7'b0000010,
tx_spw_null_c = 7'b0000100,
tx_spw_fct_c = 7'b0001000,
tx_spw_data_c = 7'b0010000,
tx_spw_data_c_0 = 7'b0100000,
tx_spw_time_code_c = 7'b1000000;
wire [5:0] last_type;
wire txdata_flagctrl_tx_last;
 
localparam [5:0] NULL = 6'b000001,
FCT = 6'b000010,
EOP = 6'b000100,
EEP = 6'b001000,
DATA = 6'b010000,
TIMEC = 6'b100000;
wire [8:0] tx_data_in;
wire [8:0] tx_data_in_0;
wire process_data;
wire process_data_0;
 
wire last_timein_control_flag_tx;
 
localparam [7:0] null_s = 8'b01110100;
localparam [2:0] fct_s = 3'b100;
localparam [3:0] eop_s = 4'b0101;
localparam [3:0] eep_s = 4'b0110;
localparam [13:0] timecode_ss = 14'b01110000000000;
wire [7:0] tx_tcode_in;
wire tcode_rdy_trnsp;
 
wire fct_counter_p;
wire [2:0] fct_flag_p;
 
wire get_data;
wire get_data_0;
 
reg [6:0] state_tx;
reg [6:0] next_state_tx;
wire char_sent;
wire fct_sent;
 
reg [2:0] state_fct_send;
reg [2:0] next_state_fct_send;
wire tx_dout;
wire tx_sout;
 
reg [2:0] state_fct_receive;
reg [2:0] next_state_fct_receive;
tx_fsm_m tx_fsm(
.pclk_tx(pclk_tx),
.enable_tx(enable_tx),
.send_null_tx(send_null_tx),
.send_fct_tx(send_fct_tx),
 
reg [2:0] state_data_fifo;
reg [2:0] next_state_data_fifo;
.get_data(get_data),
.get_data_0(get_data_0),
 
reg [13:0] timecode_s;
.tx_data_in(tx_data_in),
.tx_data_in_0(tx_data_in_0),
.process_data(process_data),
.process_data_0(process_data_0),
 
reg [5:0] last_type;
reg [8:0] txdata_flagctrl_tx_last;
reg [8:0] tx_data_in;
reg [8:0] tx_data_in_0;
reg process_data;
reg process_data_0;
reg last_process_data;
 
reg [7:0] last_timein_control_flag_tx;
reg [7:0] tx_tcode_in;
reg tcode_rdy_trnsp;
 
reg [2:0] fct_send;
reg [2:0] fct_flag;
 
reg [5:0] fct_counter_receive;
 
reg block_decrement;
reg char_sent;
 
reg fct_sent;
 
reg last_tx_dout;
reg last_tx_sout;
 
reg tx_dout;
reg tx_sout;
 
reg tx_dout_null;
reg tx_dout_fct;
reg tx_dout_timecode;
reg tx_dout_data;
 
reg [3:0] global_counter_transfer;
 
 
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
tx_dout <= 1'b0;
end
else
begin
case(state_tx)
tx_spw_start:
begin
if(send_null_tx && enable_tx)
begin
tx_dout <= !(null_s[6]^null_s[0]^null_s[1]);
end
else
begin
tx_dout <= 1'b0;
end
end
tx_spw_null,tx_spw_null_c:
begin
if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^fct_s[0]^fct_s[1]);
end
else if(last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^eop_s[0]^eop_s[1]);
end
else if(last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^eep_s[0]^eep_s[1]);
end
else if(last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(null_s[6]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= null_s[6];
end
else if(global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= null_s[5];
end
else if(global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= null_s[4];
end
else if(global_counter_transfer[3:0] == 4'd4)
begin
tx_dout <= null_s[3];
end
else if(global_counter_transfer[3:0] == 4'd5)
begin
tx_dout <= null_s[2];
end
else if(global_counter_transfer[3:0] == 4'd6)
begin
tx_dout <= null_s[1];
end
else if(global_counter_transfer[3:0] == 4'd7)
begin
tx_dout <= null_s[0];
end
end
tx_spw_fct,tx_spw_fct_c:
begin
if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^fct_s[0]^fct_s[1]);
end
else if(last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^eop_s[0]^eop_s[1]);
end
else if(last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^eep_s[0]^eep_s[1]);
end
else if (last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(fct_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= fct_s[2];
end
else if(global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= fct_s[1];
end
else if(global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= fct_s[0];
end
end
tx_spw_data_c:
begin
if(!tx_data_in[8] && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^null_s[0]^null_s[1]);
end
else if(!tx_data_in[8] && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^fct_s[0]^fct_s[1]);
end
else if(!tx_data_in[8] && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^eop_s[0]^eop_s[1]);
end
else if(!tx_data_in[8] && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^eep_s[0]^eep_s[1]);
end
else if(!tx_data_in[8] && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(!tx_data_in[8] && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in[8]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^null_s[0]^null_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^fct_s[0]^fct_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^eop_s[0]^eop_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^eep_s[0]^eep_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^null_s[0]^null_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^fct_s[0]^fct_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^eop_s[0]^eop_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^eep_s[0]^eep_s[1]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= tx_data_in[8];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= tx_data_in[0];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= tx_data_in[1];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd4)
begin
tx_dout <= tx_data_in[2];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd5)
begin
tx_dout <= tx_data_in[3];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd6)
begin
tx_dout <= tx_data_in[4];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd7)
begin
tx_dout <= tx_data_in[5];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd8)
begin
tx_dout <= tx_data_in[6];
end
else if(!tx_data_in[8] && global_counter_transfer[3:0] == 4'd9)
begin
tx_dout <= tx_data_in[7];
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= eep_s[2];
end
else if( tx_data_in[8] && tx_data_in[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= eep_s[1];
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= eep_s[0];
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= eop_s[2];
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= eop_s[1];
end
else if(tx_data_in[8] && tx_data_in[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= eop_s[0];
end
end
tx_spw_data_c_0:
begin
if(!tx_data_in_0[8] && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^null_s[0]^null_s[1]);
end
else if(!tx_data_in_0[8] && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^fct_s[0]^fct_s[1]);
end
else if(!tx_data_in_0[8] && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^eop_s[0]^eop_s[1]);
end
else if(!tx_data_in_0[8] && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^eep_s[0]^eep_s[1]);
end
else if(!tx_data_in_0[8] && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(!tx_data_in_0[8] && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(tx_data_in_0[8]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^null_s[0]^null_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^fct_s[0]^fct_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^eop_s[0]^eop_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^eep_s[0]^eep_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eop_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^null_s[0]^null_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^fct_s[0]^fct_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^eop_s[0]^eop_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^eep_s[0]^eep_s[1]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(eep_s[2]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= tx_data_in_0[8];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= tx_data_in_0[0];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= tx_data_in_0[1];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd4)
begin
tx_dout <= tx_data_in_0[2];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd5)
begin
tx_dout <= tx_data_in_0[3];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd6)
begin
tx_dout <= tx_data_in_0[4];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd7)
begin
tx_dout <= tx_data_in_0[5];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd8)
begin
tx_dout <= tx_data_in_0[6];
end
else if(!tx_data_in_0[8] && global_counter_transfer[3:0] == 4'd9)
begin
tx_dout <= tx_data_in_0[7];
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= eep_s[2];
end
else if( tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= eep_s[1];
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b01 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= eep_s[0];
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= eop_s[2];
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= eop_s[1];
end
else if(tx_data_in_0[8] && tx_data_in_0[1:0] == 2'b00 && global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= eop_s[0];
end
end
tx_spw_time_code_c:
begin
if(last_type == NULL && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^null_s[0]^null_s[1]);
end
else if(last_type == FCT && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^fct_s[0]^fct_s[1]);
end
else if (last_type == EOP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^eop_s[0]^eop_s[1]);
end
else if( last_type == EEP && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^eep_s[0]^eep_s[1]);
end
else if( last_type == DATA && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^txdata_flagctrl_tx_last[0]^txdata_flagctrl_tx_last[1]^txdata_flagctrl_tx_last[2]^txdata_flagctrl_tx_last[3]^ txdata_flagctrl_tx_last[4]^txdata_flagctrl_tx_last[5]^txdata_flagctrl_tx_last[6]^txdata_flagctrl_tx_last[7]);
end
else if( last_type == TIMEC && global_counter_transfer[3:0] == 4'd0)
begin
tx_dout <= !(timecode_s[12]^last_timein_control_flag_tx[7]^last_timein_control_flag_tx[6]^last_timein_control_flag_tx[5]^last_timein_control_flag_tx[4]^last_timein_control_flag_tx[3]^last_timein_control_flag_tx[2]^last_timein_control_flag_tx[1]^last_timein_control_flag_tx[0]);
end
else if( global_counter_transfer[3:0] == 4'd1)
begin
tx_dout <= timecode_s[12];
end
else if( global_counter_transfer[3:0] == 4'd2)
begin
tx_dout <= timecode_s[11];
end
else if( global_counter_transfer[3:0] == 4'd3)
begin
tx_dout <= timecode_s[10];
end
else if( global_counter_transfer[3:0] == 4'd4)
begin
tx_dout <= timecode_s[9];
end
else if( global_counter_transfer[3:0] == 4'd5)
begin
tx_dout <= timecode_s[8];
end
else if( global_counter_transfer[3:0] == 4'd6)
begin
tx_dout <= timecode_s[0];
end
else if( global_counter_transfer[3:0] == 4'd7)
begin
tx_dout <= timecode_s[1];
end
else if( global_counter_transfer[3:0] == 4'd8)
begin
tx_dout <= timecode_s[2];
end
else if(global_counter_transfer[3:0] == 4'd9)
begin
tx_dout <= timecode_s[3];
end
else if(global_counter_transfer[3:0] == 4'd10)
begin
tx_dout <= timecode_s[4];
end
else if(global_counter_transfer[3:0] == 4'd11)
begin
tx_dout <= timecode_s[5];
end
else if( global_counter_transfer[3:0] == 4'd12)
begin
tx_dout <= timecode_s[6];
end
else if(global_counter_transfer[3:0] == 4'd13)
begin
tx_dout <= timecode_s[7];
end
end
default:
begin
end
endcase
end
end
 
//strobe
always@(*)
begin
 
tx_sout = last_tx_sout;
 
if(tx_dout == last_tx_dout)
begin
tx_sout = !last_tx_sout;
end
else if(tx_dout != last_tx_dout)
begin
tx_sout = last_tx_sout;
end
end
 
always@(*)
begin
next_state_fct_send = state_fct_send;
 
case(state_fct_send)
3'd0:
begin
if(send_fct_now)
begin
next_state_fct_send = 3'd1;
end
else if(fct_sent)
begin
next_state_fct_send = 3'd3;
end
else
next_state_fct_send = 3'd0;
end
3'd1:
begin
next_state_fct_send = 3'd2;
end
3'd2:
begin
if(send_fct_now)
begin
next_state_fct_send = 3'd2;
end
else
begin
next_state_fct_send = 3'd0;
end
end
3'd3:
begin
next_state_fct_send = 3'd4;
end
3'd4:
begin
if(fct_sent)
begin
next_state_fct_send = 3'd4;
end
else
begin
next_state_fct_send = 3'd0;
end
end
default:
begin
next_state_fct_send = 3'd0;
end
endcase
end
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_flag <= 3'd7;
state_fct_send<= 3'd0;
end
else
begin
state_fct_send <= next_state_fct_send;
 
case(state_fct_send)
3'd0:
begin
fct_flag <= fct_flag;
end
3'd1:
begin
if(fct_flag < 3'd7)
fct_flag <= fct_flag + 3'd1;
else
fct_flag <= fct_flag;
end
3'd2:
begin
fct_flag <= fct_flag;
end
3'd3:
begin
if(fct_flag > 3'd0)
fct_flag <= fct_flag - 3'd1;
else
fct_flag <= fct_flag;
end
3'd4:
begin
fct_flag <= fct_flag;
end
default:
begin
fct_flag <= fct_flag;
end
endcase
end
end
 
 
always@(*)
begin
next_state_fct_receive = state_fct_receive;
 
case(state_fct_receive)
3'd0:
begin
if(gotfct_tx)
begin
next_state_fct_receive = 3'd1;
end
else if(char_sent)
begin
next_state_fct_receive = 3'd3;
end
else
next_state_fct_receive = 3'd0;
end
3'd1:
begin
 
next_state_fct_receive = 3'd2;
end
3'd2:
begin
if(gotfct_tx)
begin
next_state_fct_receive = 3'd2;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
3'd3:
begin
next_state_fct_receive = 3'd4;
end
3'd4:
begin
if(char_sent)
begin
next_state_fct_receive = 3'd4;
end
else
begin
next_state_fct_receive = 3'd0;
end
end
default:
begin
next_state_fct_receive = 3'd0;
end
endcase
end
 
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
fct_counter_receive<= 6'd0;
state_fct_receive <= 3'd0;
end
else
begin
 
state_fct_receive <= next_state_fct_receive;
 
case(state_fct_receive)
3'd0:
begin
fct_counter_receive <= fct_counter_receive;
end
3'd1:
begin
if(fct_counter_receive < 6'd48)
begin
fct_counter_receive <= fct_counter_receive + 6'd8;
end
else
begin
fct_counter_receive <= fct_counter_receive + 6'd7;
end
end
3'd2:
begin
fct_counter_receive <= fct_counter_receive;
end
3'd3:
begin
if(fct_counter_receive == 6'd0)
fct_counter_receive <= fct_counter_receive;
else
fct_counter_receive <= fct_counter_receive - 6'd1;
end
3'd4:
begin
fct_counter_receive <= fct_counter_receive;
end
default:
begin
fct_counter_receive <= fct_counter_receive;
end
endcase
end
end
 
always@(*)
begin
next_state_tx = state_tx;
 
case(state_tx)
tx_spw_start:
begin
if(send_null_tx && enable_tx)
begin
next_state_tx = tx_spw_null;
end
else
begin
next_state_tx = tx_spw_start;
end
end
tx_spw_null:
begin
if(send_null_tx && send_fct_tx && enable_tx)
begin
if(global_counter_transfer == 4'd7)
next_state_tx = tx_spw_fct;
else
next_state_tx = tx_spw_null;
end
else
next_state_tx = tx_spw_null;
end
tx_spw_fct:
begin
if(send_fct_tx && global_counter_transfer == 4'd3)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
next_state_tx = tx_spw_fct;
end
tx_spw_null_c:
begin
if(global_counter_transfer == 4'd7)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else if(process_data && !gotfct_tx && fct_counter_receive > 6'd0)
begin
next_state_tx = tx_spw_data_c;
end
else if(process_data_0 && !gotfct_tx && fct_counter_receive > 6'd0)
begin
next_state_tx = tx_spw_data_c_0;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
tx_spw_fct_c:
begin
if(global_counter_transfer == 4'd3)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
begin
next_state_tx = tx_spw_fct_c;
end
end
tx_spw_data_c:
begin
 
if(!tx_data_in[8])
begin
if(global_counter_transfer == 4'd9)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else if(process_data_0 && !gotfct_tx && fct_counter_receive > 6'd0)
begin
next_state_tx = tx_spw_data_c_0;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
next_state_tx = tx_spw_data_c;
end
else if(tx_data_in[8])
begin
if(global_counter_transfer == 4'd3)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
next_state_tx = tx_spw_data_c;
end
.tx_tcode_in(tx_tcode_in),
.tcode_rdy_trnsp(tcode_rdy_trnsp),
.ready_tx_data(ready_tx_data),
.ready_tx_timecode(ready_tx_timecode),
 
end
tx_spw_data_c_0:
begin
.fct_great_than_zero(fct_counter_p),
 
if(!tx_data_in_0[8])
begin
if(global_counter_transfer == 4'd9)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else if(process_data && !gotfct_tx && fct_counter_receive > 6'd0)
begin
next_state_tx = tx_spw_data_c;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
next_state_tx = tx_spw_data_c_0;
end
else if(tx_data_in_0[8])
begin
if(global_counter_transfer == 4'd3)
begin
if(tickin_tx && !ready_tx_timecode && tcode_rdy_trnsp)
begin
next_state_tx = tx_spw_time_code_c;
end
else if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
next_state_tx = tx_spw_data_c_0;
end
.gotfct_tx(gotfct_tx),
.send_fct_now(send_fct_now),
 
end
tx_spw_time_code_c:
begin
if(global_counter_transfer == 4'd13)
begin
if(fct_flag > 3'd0 && !send_fct_now)
begin
next_state_tx = tx_spw_fct_c;
end
else if(process_data && !gotfct_tx && fct_counter_receive > 6'd0 )
begin
next_state_tx = tx_spw_data_c;
end
else if(process_data_0 && !gotfct_tx && fct_counter_receive > 6'd0)
begin
next_state_tx = tx_spw_data_c_0;
end
else
begin
next_state_tx = tx_spw_null_c;
end
end
else
begin
next_state_tx = tx_spw_time_code_c;
end
end
default:
begin
next_state_tx = tx_spw_start;
end
endcase
end
.tx_dout_e(tx_dout_e),
.tx_sout_e(tx_sout_e)
 
);
 
always@(posedge pclk_tx or negedge enable_tx)
begin
if(!enable_tx)
begin
tx_data_send tx_data_snd(
.pclk_tx(pclk_tx),
.send_null_tx(send_null_tx),
.enable_tx(enable_tx),
 
timecode_s <= 14'b01110000000000;
.get_data(get_data),
.get_data_0(get_data_0),
 
ready_tx_data <= 1'b0;
ready_tx_timecode <= 1'b0;
.timecode_tx_i(timecode_tx_i),
.tickin_tx(tickin_tx),
 
last_type <= NULL;
.data_tx_i(data_tx_i),
.txwrite_tx(txwrite_tx),
 
global_counter_transfer <= 4'd0;
txdata_flagctrl_tx_last <= 9'd0;
tx_data_in <= 9'd0;
tx_data_in_0 <= 9'd0;
.fct_counter_p(fct_counter_p),
 
process_data <= 1'b0;
process_data_0 <= 1'b0;
.tx_data_in(tx_data_in),
.tx_data_in_0(tx_data_in_0),
 
last_timein_control_flag_tx <= 8'd0;
.process_data(process_data),
.process_data_0(process_data_0),
 
char_sent<= 1'b0;
fct_sent <= 1'b0;
 
last_tx_dout <= 1'b0;
last_tx_sout <= 1'b0;
 
state_tx <= tx_spw_start;
 
tx_dout_e <= 1'b0;
tx_sout_e <= 1'b0;
 
tx_tcode_in <= 8'd0;
tcode_rdy_trnsp <= 1'b0;
 
end
else
begin
state_tx <= next_state_tx;
 
case(state_tx)
tx_spw_start:
begin
 
if(send_null_tx && enable_tx)
begin
global_counter_transfer <= global_counter_transfer + 4'd1;
end
else
begin
global_counter_transfer <= 4'd0;
end
end
tx_spw_null:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
 
 
if(tickin_tx && global_counter_transfer == 4'd5)
begin
tx_tcode_in <= timecode_tx_i;
tcode_rdy_trnsp <= 1'b1;
end
else
tx_tcode_in <= tx_tcode_in;
 
 
if(global_counter_transfer == 4'd7)
begin
last_type <= NULL;
global_counter_transfer <= 4'd0;
end
else
begin
last_type <= last_type;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
tx_spw_fct:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
 
if(global_counter_transfer == 4'd3)
begin
last_type <=FCT;
global_counter_transfer <= 4'd0;
fct_sent <= 1'b0;
end
else
begin
if(fct_flag > 3'd0)
fct_sent <= 1'b1;
else
fct_sent <= fct_sent;
 
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
tx_spw_null_c:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
if(global_counter_transfer == 4'd7)
begin
fct_sent <= 1'b0;
last_type <= NULL;
global_counter_transfer <= 4'd0;
end
else
begin
 
if(process_data_0)
begin
process_data_0 <= process_data_0;
end
else
begin
if(txwrite_tx)
begin
tx_data_in <= data_tx_i;
process_data <= 1'b1;
end
else
begin
tx_data_in <= tx_data_in;
process_data <= 1'b0;
end
process_data_0 <= 1'b0;
end
 
char_sent <= 1'b0;
fct_sent <= 1'b0;
ready_tx_timecode <= 1'b0;
last_type <= last_type;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
tx_spw_fct_c:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
 
if(global_counter_transfer == 4'd3)
begin
char_sent <= 1'b0;
last_type <=FCT;
fct_sent <= 1'b0;
global_counter_transfer <= 4'd0;
end
else
begin
char_sent <= 1'b0;
process_data <= process_data;
process_data_0 <= process_data_0;
 
fct_sent <= 1'b1;
 
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
tx_spw_data_c:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
 
if(!tx_data_in[8])
begin
 
if(global_counter_transfer == 4'd9)
begin
fct_sent <= 1'b0;
char_sent <= 1'b1;
last_type <= DATA;
global_counter_transfer <= 4'd0;
end
else
begin
 
if(global_counter_transfer < 4'd3)
begin
ready_tx_data <= 1'b1;
end
else
begin
fct_sent <= 1'b0;
ready_tx_data <= 1'b0;
 
if(global_counter_transfer == 4'd3)
begin
txdata_flagctrl_tx_last <= tx_data_in;
end
else
txdata_flagctrl_tx_last <= txdata_flagctrl_tx_last;
 
if(txwrite_tx)
begin
tx_data_in_0 <= data_tx_i;
process_data_0 <= 1'b1;
end
else
begin
tx_data_in_0 <= tx_data_in_0;
process_data_0 <= 1'b0;
end
end
process_data <= 1'b0;
char_sent <= 1'b0;
ready_tx_timecode <= 1'b0;
global_counter_transfer <= global_counter_transfer + 4'd1;
 
end
 
end
else if(tx_data_in[8])
begin
 
if(global_counter_transfer == 4'd3)
begin
char_sent <= 1'b1;
fct_sent <= 1'b0;
if(tx_data_in[1:0] == 2'b00)
begin
last_type <=EOP;
end
else if(tx_data_in[1:0] == 2'b01)
begin
last_type <=EEP;
end
 
ready_tx_data <= 1'b0;
global_counter_transfer <= 4'd0;
end
else
begin
fct_sent <= 1'b0;
char_sent <= 1'b0;
process_data <= 1'b0;
process_data_0 <= 1'b0;
txdata_flagctrl_tx_last <= txdata_flagctrl_tx_last;
ready_tx_data <= 1'b1;
ready_tx_timecode <= 1'b0;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
 
end
tx_spw_data_c_0:
begin
 
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
 
if(!tx_data_in_0[8])
begin
 
if(global_counter_transfer == 4'd9)
begin
fct_sent <= 1'b0;
char_sent <= 1'b1;
last_type <= DATA;
global_counter_transfer <= 4'd0;
end
else
begin
 
if(global_counter_transfer < 4'd3)
begin
ready_tx_data <= 1'b1;
end
else
begin
ready_tx_data <= 1'b0;
 
if(global_counter_transfer == 4'd3)
begin
txdata_flagctrl_tx_last <= tx_data_in_0;
end
else
txdata_flagctrl_tx_last <= txdata_flagctrl_tx_last;
 
if(txwrite_tx)
begin
tx_data_in <= data_tx_i;
process_data <= 1'b1;
end
else
begin
tx_data_in <= tx_data_in;
process_data <= 1'b0;
end
end
 
fct_sent <= 1'b0;
process_data_0 <= 1'b0;
char_sent <= 1'b0;
ready_tx_timecode <= 1'b0;
global_counter_transfer <= global_counter_transfer + 4'd1;
 
end
 
end
else if(tx_data_in_0[8])
begin
 
if(global_counter_transfer == 4'd3)
begin
fct_sent <= 1'b0;
char_sent <= 1'b1;
 
if(tx_data_in_0[1:0] == 2'b00)
begin
last_type <=EOP;
end
else if(tx_data_in_0[1:0] == 2'b01)
begin
last_type <=EEP;
end
 
ready_tx_data <= 1'b0;
global_counter_transfer <= 4'd0;
end
else
begin
fct_sent <= 1'b0;
process_data <= 1'b0;
process_data_0 <= 1'b0;
txdata_flagctrl_tx_last <= txdata_flagctrl_tx_last;
ready_tx_data <= 1'b1;
ready_tx_timecode <= 1'b0;
char_sent <= 1'b0;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
end
 
end
tx_spw_time_code_c:
begin
last_tx_dout <= tx_dout;
last_tx_sout <= tx_sout;
 
tx_dout_e <= tx_dout;
tx_sout_e <= tx_sout;
if(global_counter_transfer == 4'd13)
begin
fct_sent <= 1'b0;
ready_tx_timecode <= 1'b1;
global_counter_transfer <= 4'd0;
end
else
begin
if(process_data_0)
begin
 
process_data_0 <= process_data_0;
end
else
begin
if(txwrite_tx)
begin
tx_data_in <= data_tx_i;
process_data <= 1'b1;
end
else
begin
tx_data_in <= tx_data_in;
process_data <= 1'b0;
end
process_data_0 <= 1'b0;
end
fct_sent <= 1'b0;
char_sent <= 1'b0;
ready_tx_timecode <= 1'b0;
global_counter_transfer <= global_counter_transfer + 4'd1;
end
 
 
if(global_counter_transfer != 4'd13)
begin
timecode_s <= {timecode_ss[13:10],2'd2,tx_tcode_in[7:0]};
end
else
begin
last_timein_control_flag_tx <= tx_tcode_in;
last_type <= TIMEC;
end
 
end
default:
begin
fct_sent <= 1'b0;
char_sent <= 1'b0;
last_type <= last_type;
global_counter_transfer <= global_counter_transfer;
tx_dout_e <= tx_dout_e;
tx_sout_e <= tx_sout_e;
end
endcase
end
end
 
.tx_tcode_in(tx_tcode_in),
.tcode_rdy_trnsp(tcode_rdy_trnsp)
);
endmodule

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