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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

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  • This comparison shows the changes necessary to convert path 
    /spacewiresystemc/trunk/rtl
    from Rev 8 to Rev 12
    ↔ Reverse comparison
  •

Rev 8 → Rev 12

/RTL_VB/fsm_spw.v
82,7 → 82,7
assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;
 
//
assign send_null_tx = (next_state_fsm == started | next_state_fsm == connecting | next_state_fsm == run)?1'b1:1'b0;
assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
 
//
assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
268,7 → 268,7
end
else
begin
if(after850ns < 12'd85 && (auto_start | link_start))
if(after850ns < 12'd85 && state_fsm == run)
after850ns <= after850ns + 12'd1;
else
after850ns <= 12'd0;
/RTL_VB/rx_spw.v
117,15 → 117,15
assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];
assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];
 
assign control[0:0] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:control[0:0];
assign control[1:1] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:control[1:1];
assign control[2:2] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:control[2:2];
assign control[3:3] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:control[3:3];
assign control[0:0] = (counter == 5'd3)?rx_din:control[0:0];
assign control[1:1] = (counter == 5'd2)?rx_din:control[1:1];
assign control[2:2] = (counter == 5'd1)?rx_din:control[2:2];
assign control[3:3] = (counter == 5'd0)?rx_din:control[3:3];
 
assign rx_got_fct = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
assign rx_got_nchar = (!rx_resetn)?1'b0:(!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
assign rx_got_time_code = (!rx_resetn)?1'b0:(counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
assign rx_got_null = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
assign rx_got_fct = (counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
assign rx_got_nchar = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
assign rx_got_time_code = (counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
assign rx_got_null = (counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
 
assign rx_error = (parity_error)?1'b1:
/RTL_VB/tx_spw.v
110,6 → 110,11
 
assign ready_tx_timecode = (enable_time_code & global_counter_transfer == 14)?1'b1:1'b0;
 
/*
assign ready_tx_data = (enable_n_char & global_counter_transfer == 4'd9 & !data_tx_i[8])?1'b1:
(enable_n_char & global_counter_transfer == 4'd3 & data_tx_i[8])?1'b1:1'b0;
*/
 
always@(*)
begin
tx_dout = 1'b0;
436,7 → 441,8
else if((enable_null | enable_fct | enable_n_char) && tx_dout != last_tx_dout)
begin
tx_sout = last_tx_sout;
end
end
end
 
//slots open in another side
496,10 → 502,10
begin
if(send_null_tx && enable_tx)
begin
if(!hold_null)
//if(!hold_null)
next_state_tx = tx_spw_null;
enable_null = 1'b1;
//enable_null = 1'b1;
end
else
begin
535,7 → 541,8
enable_fct = 1'b0;
if(send_fct_tx && fct_counter > 6'd0)
begin
next_state_tx = tx_spw_full;
//if(global_counter_transfer == 4'd7)
next_state_tx = tx_spw_full;
end
 
end
548,6 → 555,13
enable_n_char = 1'b0;
enable_time_code = 1'b0;
 
/*
hold_null <= 1'b0;
hold_fct <= 1'b0;
hold_data <= 1'b0;
hold_time_code <= 1'b0;
*/
 
if(tickin_tx && !hold_null && !hold_fct && !hold_data)
begin
enable_time_code = 1'b1;

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