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Rev 13 → Rev 14

/RTL_VB/rx_spw.v
54,285 → 54,308
output rx_tick_out
);
 
wire [4:0] counter;
 
reg [4:0] counter_pos;
reg [4:0] counter_neg;
 
wire posedge_clk;
wire negedge_clk;
 
wire [3:0] control;
wire [9:0] data;
wire [9:0] timecode;
reg bit_c_0;//N
reg bit_c_1;//P
reg bit_c_2;//N
reg bit_c_3;//P
 
reg [3:0] control_l_a;
reg [9:0] data_l_a;
reg [9:0] timecode_l_a;
reg bit_d_0;//N
reg bit_d_1;//P
reg bit_d_2;//N
reg bit_d_3;//P
reg bit_d_4;//N
reg bit_d_5;//P
reg bit_d_6;//N
reg bit_d_7;//P
reg bit_d_8;//N
reg bit_d_9;//P
 
reg [2:0] control_l_r;
reg [9:0] data_l_r;
reg [9:0] timecode_l_r;
reg is_control;
reg is_data;
 
reg parity_error;
reg last_is_control;
reg last_is_data;
reg last_is_timec;
 
reg control_found;
reg data_found;
reg time_code_found;
 
reg last_was_control;
reg last_was_data;
reg last_was_time_code;
wire data_control_up;
reg last_was_timec;
 
assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1:
(counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:
(counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0;
reg [3:0] control;
reg [9:0] data;
reg [9:0] timecode;
 
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
reg [3:0] control_l_r;
reg [9:0] data_l_r;
 
assign counter = counter_pos + counter_neg;
reg parity_error;
wire check_c_d;
 
assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9];
assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8];
assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0];
assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1];
assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2];
assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3];
assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4];
assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5];
assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6];
assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7];
//CLOCK RECOVERY
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
 
assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0];
assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1];
assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2];
assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3];
assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4];
assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5];
assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6];
assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7];
assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];
assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];
assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
 
assign control[0:0] = (counter == 5'd3)?rx_din:control[0:0];
assign control[1:1] = (counter == 5'd2)?rx_din:control[1:1];
assign control[2:2] = (counter == 5'd1)?rx_din:control[2:2];
assign control[3:3] = (counter == 5'd0)?rx_din:control[3:3];
assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
 
assign rx_got_fct = (counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
assign rx_got_nchar = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
assign rx_got_time_code = (counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
assign rx_got_null = (counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
 
assign rx_error = (parity_error)?1'b1:
((counter == 5'd9 | counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0;
assign rx_error = parity_error;
 
assign rx_data_flag = (rx_got_nchar)?data[8:0]:data_l_a[8:0];
assign rx_buffer_write = (rx_got_nchar & data_control_up)?1'b1:1'b0;
assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
 
assign rx_time_out = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0];
assign rx_tick_out = (rx_got_time_code & data_control_up)?1'b1:1'b0;
assign rx_buffer_write = ( (control[2:0] == 3'd5 & is_control) == 1'b1 | (control[2:0] != 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
assign rx_data_flag = ( (control[2:0] == 3'd6 & is_control) == 1'b1 )?9'b100000001:
( (control[2:0] == 3'd5 & is_control) == 1'b1 )?9'b100000000:
( (control[2:0] != 3'd7 & is_data) == 1'b1)?data[8:0]:9'd0;
 
assign rx_time_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?timecode[7:0]:8'd0;
assign rx_tick_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
 
always@(posedge posedge_clk or negedge rx_resetn or posedge last_was_control)
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn | last_was_control)
 
if(!rx_resetn)
begin
counter_pos <= 5'd0;
bit_c_1 <= 1'b0;
bit_c_3 <= 1'b0;
 
bit_d_1 <= 1'b0;
bit_d_3 <= 1'b0;
bit_d_5 <= 1'b0;
bit_d_7 <= 1'b0;
bit_d_9 <= 1'b0;
end
else
begin
if(counter == 5'd4 & control[2:2])
begin
counter_pos <= 5'd0;
end
else if(counter == 5'd9)
begin
counter_pos <= 5'd0;
end
else
begin
counter_pos <= counter_pos + 5'd1;
end
bit_c_1 <= rx_din;
bit_c_3 <= bit_c_1;
 
bit_d_1 <= rx_din;
bit_d_3 <= bit_d_1;
bit_d_5 <= bit_d_3;
bit_d_7 <= bit_d_5;
bit_d_9 <= bit_d_7;
 
end
 
end
 
//
always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control)
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn | last_was_control )
 
if(!rx_resetn)
begin
counter_neg <= 5'd0;
bit_c_0 <= 1'b0;
bit_c_2 <= 1'b0;
 
bit_d_0 <= 1'b0;
bit_d_2 <= 1'b0;
bit_d_4 <= 1'b0;
bit_d_6 <= 1'b0;
bit_d_8 <= 1'b0;
 
is_control <= 1'b0;
is_data <= 1'b0;
 
counter_neg <= 5'd0;
 
end
else
begin
if(counter == 5'd4 & control[2:2])
 
bit_c_0 <= rx_din;
bit_c_2 <= bit_c_0;
 
bit_d_0 <= rx_din;
bit_d_2 <= bit_d_0;
bit_d_4 <= bit_d_2;
bit_d_6 <= bit_d_4;
bit_d_8 <= bit_d_6;
 
if(counter_neg == 5'd1)
begin
counter_neg <= 5'd0;
if(bit_c_0)
begin
is_control <= 1'b1;
is_data <= 1'b0;
end
else
begin
is_control <= 1'b0;
is_data <= 1'b1;
end
 
counter_neg <= counter_neg + 5'd1;
 
end
else if(counter == 5'd9)
begin
counter_neg <= 5'd0;
end
else
begin
counter_neg <= counter_neg + 5'd1;
end
if(is_control)
begin
if(counter_neg == 5'd2)
begin
counter_neg <= 5'd1;
is_control <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
else if(is_data)
begin
if(counter_neg == 5'd5)
begin
counter_neg <= 5'd1;
is_data <= 1'b0;
end
else
counter_neg <= counter_neg + 5'd1;
end
else
begin
counter_neg <= counter_neg + 5'd1;
end
end
end
end
 
//parity error
always@(*)
begin
 
parity_error = 1'b0;
 
if(control_found && last_was_control)
if(last_is_control)
begin
if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3])
if(last_was_control)
begin
parity_error = 1'b1;
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
begin
parity_error = 1'b1;
end
end
end
else if(control_found && last_was_data)
begin
if(!(data_l_a[8]^control_l_r[0]^control_l_r[1]) != data_l_a[9])
else if(last_was_timec)
begin
parity_error = 1'b1;
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
begin
parity_error = 1'b1;
end
end
end
else if(control_found && last_was_time_code)
begin
if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9])
else if(last_was_data)
begin
parity_error = 1'b1;
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
begin
parity_error = 1'b1;
end
end
end
else if(data_found && last_was_control)
else if(last_is_data)
begin
if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3])
if(last_was_control)
begin
parity_error = 1'b1;
if(!(data[8]^control[1]^control[0]) != data[9])
begin
parity_error = 1'b1;
end
end
end
else if(data_found && last_was_data)
begin
if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9])
else if(last_was_timec)
begin
parity_error = 1'b1;
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
begin
parity_error = 1'b1;
end
end
end
else if(data_found && last_was_time_code)
begin
if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7]) != data_l_r[9])
else if(last_was_data)
begin
parity_error = 1'b1;
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
begin
parity_error = 1'b1;
end
end
end
else if(time_code_found && last_was_data)
begin
if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9])
begin
parity_error = 1'b1;
end
end
else if(time_code_found && last_was_control)
begin
if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7]) != control_l_a[3])
begin
parity_error = 1'b1;
end
end
end
 
//
always@(*)
always@(posedge check_c_d or negedge rx_resetn )
begin
 
last_was_control = 1'b0;
last_was_data = 1'b0;
last_was_time_code= 1'b0;
 
if(counter == 5'd4 & control[2:2])
if(!rx_resetn)
begin
last_was_control = 1'b1;
end
else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7)
begin
last_was_data = 1'b1;
end
else if(counter == 5'd9 && control_l_a[2:0] == 3'd7)
begin
last_was_time_code= 1'b1;
end
control <= 4'd0;
control_l_r <= 4'd0;
 
end
data <= 10'd0;
data_l_r <= 10'd0;
 
//
always@(posedge data_control_up or negedge rx_resetn)
begin
timecode <= 10'd0;
 
if(!rx_resetn)
begin
control_found <= 1'b0;
data_found <= 1'b0;
time_code_found <= 1'b0;
end
else
begin
control_found <= last_was_control;
data_found <= last_was_data;
time_code_found <= last_was_time_code;
end
last_is_control <=1'b0;
last_is_data <=1'b0;
last_is_timec <=1'b0;
 
end
last_was_control <=1'b0;
last_was_data <=1'b0;
last_was_timec <=1'b0;
 
//
always@(posedge last_was_control or negedge rx_resetn)
begin
if(!rx_resetn)
begin
control_l_a <= 4'd4;
control_l_r <= 3'd4;
end
else
begin
control_l_a <= control;
control_l_r <= control_l_a[2:0];
end
end
if((control[2:0] != 3'd7 & is_data) == 1'b1)
begin
 
always@(posedge last_was_data or negedge rx_resetn)
begin
if(!rx_resetn)
begin
data_l_a <= 10'd0;
data_l_r <= 10'd0;
end
else
begin
data_l_a <= data;
data_l_r <= data_l_a;
end
end
data <= {bit_d_9,bit_d_8,bit_d_7,bit_d_6,bit_d_5,bit_d_4,bit_d_3,bit_d_2,bit_d_1,bit_d_0};
data_l_r <= data;
 
always@(posedge last_was_time_code or negedge rx_resetn)
begin
if(!rx_resetn)
begin
timecode_l_a <= 10'd0;
timecode_l_r <= 10'd0;
last_is_control <=1'b0;
last_is_data <=1'b1;
last_is_timec <=1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
else if((control[2:0] == 3'd7 & is_data) == 1'b1)
begin
 
timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
 
last_is_control <= 1'b0;
last_is_data <= 1'b0;
last_is_timec <= 1'b1;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
begin
 
control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
control_l_r <= control[3:0];
/*
if(last_is_data & last_was_data)
begin
data <= 10'd0;
data_l_r <= 10'd0;
timecode <= 10'd0;
end
*/
last_is_control <= 1'b1;
last_is_data <= 1'b0;
last_is_timec <= 1'b0;
last_was_control <= last_is_control;
last_was_data <= last_is_data ;
last_was_timec <= last_is_timec;
end
end
else
begin
timecode_l_a <= timecode;
timecode_l_r <= timecode_l_a;
end
end
 
 
endmodule

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