URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
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- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/rtl
- from Rev 18 to Rev 19
- ↔ Reverse comparison
Rev 18 → Rev 19
/RTL_VB/rx_spw.v
47,11 → 47,11
output rx_got_time_code, |
output rx_got_fct, |
|
output [8:0] rx_data_flag, |
output rx_buffer_write, |
output reg [8:0] rx_data_flag, |
output reg rx_buffer_write, |
|
output [7:0] rx_time_out, |
output rx_tick_out |
output reg [7:0] rx_time_out, |
output reg rx_tick_out |
); |
|
|
97,6 → 97,8
reg parity_error; |
wire check_c_d; |
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reg rx_data_take; |
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//CLOCK RECOVERY |
assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0; |
assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0; |
113,14 → 115,6
assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0; |
assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0; |
|
assign rx_buffer_write = ( (control[2:0] == 3'd5 & is_control) == 1'b1 | (control[2:0] != 3'd7 & is_data) == 1'b1)?1'b1:1'b0; |
assign rx_data_flag = ( (control[2:0] == 3'd6 & is_control) == 1'b1 )?9'b100000001: |
( (control[2:0] == 3'd5 & is_control) == 1'b1 )?9'b100000000: |
( (control[2:0] != 3'd7 & is_data) == 1'b1)?data[8:0]:9'd0; |
|
assign rx_time_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?timecode[7:0]:8'd0; |
assign rx_tick_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?1'b1:1'b0; |
|
always@(posedge posedge_clk or negedge rx_resetn) |
begin |
|
293,10 → 287,15
control <= 4'd0; |
control_l_r <= 4'd0; |
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data <= 10'd0; |
data_l_r <= 10'd0; |
data <= 10'd0; |
data_l_r <= 10'd0; |
rx_data_flag <= 9'd0; |
rx_buffer_write <= 1'b0; |
rx_data_take <= 1'b0; |
|
timecode <= 10'd0; |
rx_time_out <= 8'd0; |
rx_tick_out <= 1'b0; |
|
last_is_control <=1'b0; |
last_is_data <=1'b0; |
309,11 → 308,20
end |
else |
begin |
|
rx_buffer_write <= rx_data_take; |
rx_data_flag <= data[8:0]; |
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rx_time_out <= timecode; |
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if((control[2:0] != 3'd7 & is_data) == 1'b1) |
begin |
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data <= {bit_d_9,bit_d_8,bit_d_7,bit_d_6,bit_d_5,bit_d_4,bit_d_3,bit_d_2,bit_d_1,bit_d_0}; |
data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7}; |
data_l_r <= data; |
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rx_data_take <= 1'b1; |
rx_tick_out <= 1'b0; |
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last_is_control <=1'b0; |
last_is_data <=1'b1; |
326,6 → 334,8
begin |
|
timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7}; |
rx_tick_out <= 1'b1; |
rx_data_take <= 1'b0; |
|
last_is_control <= 1'b0; |
last_is_data <= 1'b0; |
339,15 → 349,24
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0}; |
control_l_r <= control[3:0]; |
|
/* |
if(last_is_data & last_was_data) |
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if((control[2:0] == 3'd6 & is_control) == 1'b1 ) |
begin |
data <= 10'd0; |
data_l_r <= 10'd0; |
timecode <= 10'd0; |
data <= 10'b0100000001; |
rx_data_take <= 1'b1; |
end |
*/ |
else if( (control[2:0] == 3'd5 & is_control) == 1'b1 ) |
begin |
data <= 10'b0100000000; |
rx_data_take <= 1'b1; |
end |
else |
begin |
rx_data_take <= 1'b0; |
end |
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rx_tick_out <= 1'b0; |
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last_is_control <= 1'b1; |
last_is_data <= 1'b0; |
last_is_timec <= 1'b0; |
/RTL_VB/tx_spw.v
96,7 → 96,6
reg enable_time_code; |
|
reg [2:0] fct_send; |
reg [2:0] fct_send_last; |
reg [2:0] fct_flag; |
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reg [5:0] fct_counter; |
106,6 → 105,7
reg last_tx_sout; |
|
reg block_sum; |
reg block_sum_fct_send; |
|
reg [3:0] global_counter_transfer; |
|
467,26 → 467,30
end |
|
//slots open in our side |
always@(posedge send_fct_now or negedge enable_tx) |
always@(*) |
begin |
|
if(!enable_tx) |
fct_send = {3{1'b0}}; |
|
if(send_fct_now) |
begin |
fct_send <= {3{1'b1}}; |
end |
else |
begin |
if(block_sum_fct_send) |
begin |
|
if(fct_send == 3'd7) |
begin |
fct_send <= 3'd1; |
end |
else |
begin |
fct_send <= fct_send + 3'd1; |
if(fct_flag == 3'd7) |
begin |
fct_send = 3'd0; |
end |
else |
begin |
fct_send = fct_flag + 3'd1; |
|
end |
end |
end |
|
end |
|
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584,8 → 588,7
eep_s <= 4'h6; |
timecode_s <= 14'b01110000000000; |
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fct_flag <= 3'd0; |
fct_send_last <= 3'd0; |
fct_flag <= 3'd7; |
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first_time <= 1'b1; |
ready_tx_data <= 1'b0; |
605,6 → 608,7
fct_counter_receive <= 6'd0; |
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block_sum <= 1'b0; |
block_sum_fct_send <= 1'b0; |
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last_tx_dout <= 1'b0; |
last_tx_sout <= 1'b0; |
623,7 → 627,7
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ready_tx_data <= 1'b0; |
ready_tx_timecode <= 1'b0; |
|
// |
if(gotfct_tx && !block_sum) |
begin |
fct_counter_receive <= fct_counter; |
635,21 → 639,18
end |
else |
block_sum <= block_sum; |
|
// |
if(fct_send_last != fct_send) |
if(send_fct_now && !block_sum_fct_send) |
begin |
if(fct_send == 3'd1 && fct_send_last == 3'd7) |
begin |
fct_flag <= fct_flag + 3'd1; |
end |
else |
begin |
fct_flag <= fct_flag + (fct_send - fct_send_last); |
end |
|
fct_send_last <= fct_send; |
fct_flag <= fct_send; |
block_sum_fct_send<= 1'b1; |
end |
else if(!send_fct_now) |
begin |
block_sum_fct_send<= 1'b0; |
end |
else |
block_sum_fct_send <= block_sum_fct_send; |
|
if(first_time) |
begin |
691,6 → 692,18
begin |
hold_fct <= 1'b1; |
global_counter_transfer <= global_counter_transfer + 4'd1; |
// |
if(send_fct_now && !block_sum_fct_send) |
begin |
fct_flag <= fct_send; |
block_sum_fct_send<= 1'b1; |
end |
else if(!send_fct_now) |
begin |
block_sum_fct_send<= 1'b0; |
end |
else |
block_sum_fct_send <= block_sum_fct_send; |
end |
else |
begin |
716,25 → 729,23
else |
block_sum <= block_sum; |
|
|
if(global_counter_transfer == 4'd13) |
begin |
ready_tx_timecode <= 1'b1; |
end |
|
// |
if(fct_send_last != fct_send) |
if(send_fct_now && !block_sum_fct_send) |
begin |
if(fct_send == 3'd1 && fct_send_last == 3'd7) |
begin |
fct_flag <= fct_flag + 3'd1; |
end |
else |
begin |
fct_flag <= fct_flag + (fct_send - fct_send_last); |
end |
|
fct_send_last <= fct_send; |
fct_flag <= fct_send; |
block_sum_fct_send<= 1'b1; |
end |
else if(!send_fct_now) |
begin |
block_sum_fct_send<= 1'b0; |
end |
else |
block_sum_fct_send <= block_sum_fct_send; |
|
if(global_counter_transfer < 4'd13) |
begin |
752,22 → 763,18
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ready_tx_timecode <= 1'b0; |
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//if(fct_counter > 6'd0) |
// fct_counter_receive <= fct_counter; |
// |
if(fct_send_last != fct_send) |
if(send_fct_now && !block_sum_fct_send) |
begin |
if(fct_send == 3'd1 && fct_send_last == 3'd7) |
begin |
fct_flag <= fct_flag + 3'd1; |
end |
else |
begin |
fct_flag <= fct_flag + (fct_send - fct_send_last); |
end |
|
fct_send_last <= fct_send; |
fct_flag <= fct_send; |
block_sum_fct_send<= 1'b1; |
end |
else if(!send_fct_now) |
begin |
block_sum_fct_send<= 1'b0; |
end |
else |
block_sum_fct_send <= block_sum_fct_send; |
|
if(!data_tx_i[8]) |
begin |