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URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

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  • This comparison shows the changes necessary to convert path 
    /spacewiresystemc/trunk/testbench
    from Rev 12 to Rev 40
    ↔ Reverse comparison
  •

Rev 12 → Rev 40

/module_tb.v
4,6 → 4,7
module module_tb;
 
reg CLK_SIM;
reg CLK_SYS_RX;
 
`ifdef VERILOG_A
 
40,6 → 41,20
wire TX_CLOCK_OUT;
wire TX_CLOCK_OUT_SC;
 
integer i;
integer time_clk_ns;
 
assign SPILL_ENABLE = 1'b1;
 
initial
begin
$dumpfile("module_tb.vcd");
$dumpvars(0,module_tb);
$global_init;
i=0;
time_clk_ns = 500;
end
 
assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
assign SPW_SC_FSM_OUT = SPW_SC_FSM;
51,7 → 66,7
initial CLK = 1'b0;
always #(10) CLK = ~CLK;
 
SpwTCR DUT_TCR (
SPW_TOP DUT_TCR (
.CLOCK(CLOCK),
.RESETn(RESETn),
.LINK_START(LINK_START),
77,8 → 92,7
.Sout(Sout)
);
 
 
always@(posedge CLK , negedge CLK)
always@(posedge CLK)
$global_reset;
 
always@(posedge CLK)
86,6 → 100,9
 
always@(posedge CLK)
$receive_rx_spw;
//
always@(posedge CLK)
$run_sim;
 
//FLAG USED TO FINISH SIMULATION PROGRAM
always@(posedge CLK)
96,11 → 113,14
`endif
 
`ifdef VERILOG_B
`endif
assign TOP_SIN = TOP_SOUT;
assign TOP_DIN = TOP_DOUT;
 
integer time_clk_ns;
 
reg PCLK;
reg PCLK_FIFO;
reg PPLLCLK;
 
wire RESETN;
122,7 → 142,7
wire TOP_SEND_FCT_NOW;
 
wire [8:0] DATARX_FLAG;
wire BUFFER_WRITE;
wire BUFFER_READ;
 
wire [7:0] TIME_OUT;
wire TICK_OUT;
134,11 → 154,21
wire TOP_TX_READY_TICK;
 
wire [5:0] TOP_FSM;
wire [5:0] COUNTER_FIFO_RX;
wire [5:0] COUNTER_FIFO_TX;
 
wire TX_CLOCK_RECOVERY_VLOG;
wire [3:0] SPW_SC_FSM;
wire [3:0] SPW_SC_FSM_OUT;
 
wire [31:0] counter;
wire [3:0] global_counter_actual;
wire [13:0] data_took_is;
wire din_out;
wire sin_out;
 
wire F_FULL,F_EMPTY,F_FULL_RX,F_EMPTY_RX;
 
assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
145,7 → 175,7
integer i;
 
initial
begin
begin
$dumpfile("module_tb.vcd");
$dumpvars(0,module_tb);
$global_init;
156,6 → 186,9
initial PCLK = 1'b0;
always #(5) PCLK = ~PCLK;
 
initial PCLK_FIFO = 1'b0;
always #(10) PCLK_FIFO = ~PCLK_FIFO;
 
initial PPLLCLK = 1'b0;
always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
 
162,11 → 195,13
initial CLK_SIM = 1'b0;
always #(1) CLK_SIM = ~CLK_SIM;
 
initial CLK_SYS_RX = 1'b0;
always #(4) CLK_SYS_RX = ~CLK_SYS_RX;
top_spw_ultra_light DUT_ULIGHT(
.pclk(PCLK),
spw_ulight_con_top_x DUT_ULIGHT(
.ppll_100_MHZ(PCLK),
.ppllclk(PPLLCLK),
.resetn(RESETN),
.reset_spw_n_b(RESETN),
 
.top_sin(TOP_SIN),
.top_din(TOP_DIN),
181,11 → 216,8
.top_tx_tick(TOP_TX_TICK),
.top_tx_time(TOP_TX_TIME),
 
.credit_error_rx(CREDIT_ERROR_RX),
.top_send_fct_now(TOP_SEND_FCT_NOW),
 
.datarx_flag(DATARX_FLAG),
.buffer_write(BUFFER_WRITE),
.read_rx_fifo_en(BUFFER_READ),
 
.time_out(TIME_OUT),
.tick_out(TICK_OUT),
193,25 → 225,30
.top_dout(TOP_DOUT),
.top_sout(TOP_SOUT),
 
.top_tx_ready(TOP_TX_READY),
.f_full(F_FULL),
.f_empty(F_EMPTY),
.f_full_rx(F_FULL_RX),
.f_empty_rx(F_EMPTY_RX),
.top_tx_ready_tick(TOP_TX_READY_TICK),
 
.top_fsm(TOP_FSM)
.top_fsm(TOP_FSM),
.counter_fifo_tx(COUNTER_FIFO_TX),
.counter_fifo_rx(COUNTER_FIFO_RX)
);
 
 
//
always@(posedge PCLK)
always@(posedge PCLK_FIFO)
$write_tx_fsm_spw_ultra_light;
 
//
always@(posedge PCLK or posedge TOP_TX_READY)
always@(posedge PCLK_FIFO)
$write_tx_data_spw_ultra_light;
 
always@(posedge PCLK)
always@(posedge PCLK_FIFO)
$write_tx_time_code_spw_ultra_light;
 
//
always@(posedge BUFFER_WRITE)
always@(posedge PCLK_FIFO)
$receive_rx_data_spw_ultra_light;
always@(posedge TICK_OUT)
232,5 → 269,7
$finish();
end
 
`endif
 
 
endmodule

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