URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/testbench
- from Rev 5 to Rev 7
- ↔ Reverse comparison
Rev 5 → Rev 7
/module_tb.v
135,6 → 135,13
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wire [5:0] TOP_FSM; |
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wire TX_CLOCK_RECOVERY_VLOG; |
wire [3:0] SPW_SC_FSM; |
wire [3:0] SPW_SC_FSM_OUT; |
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assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT; |
assign SPW_SC_FSM_OUT = SPW_SC_FSM; |
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integer i; |
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initial |
194,30 → 201,31
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// |
always@(posedge PCLK) |
$write_tx_fsm_spw_ultra_light; |
// |
always@(posedge PCLK) |
$write_tx_fsm_spw_ultra_light; |
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// |
always@(posedge PCLK) |
$write_tx_data_spw_ultra_light; |
// |
always@(posedge PCLK) |
$write_tx_data_spw_ultra_light; |
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always@(posedge PCLK) |
$write_tx_time_code_spw_ultra_light; |
always@(posedge PCLK) |
$write_tx_time_code_spw_ultra_light; |
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// |
always@(posedge PCLK) |
$receive_rx_data_spw_ultra_light; |
// |
always@(posedge BUFFER_WRITE) |
$receive_rx_data_spw_ultra_light; |
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always@(posedge PCLK) |
$receive_rx_time_code_spw_ultra_light; |
always@(posedge TICK_OUT) |
$receive_rx_time_code_spw_ultra_light; |
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// |
always@(posedge PCLK , negedge PCLK) |
$global_reset; |
// |
always@(posedge CLK_SIM) |
$run_sim; |
// |
always@(posedge PCLK , negedge PCLK) |
$global_reset; |
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// |
always@(posedge CLK_SIM) |
$run_sim; |
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//FLAG USED TO FINISH SIMULATION PROGRAM |
always@(posedge CLK_SIM) |