URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/vpi
- from Rev 10 to Rev 12
- ↔ Reverse comparison
Rev 10 → Rev 12
/vpi_test_stress/env_global_spw.cpp
2,9 → 2,9
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#include "../../systemC/link_sc.h" |
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int counter; |
int counter=0; |
int data_iteration_vlog=0; |
int position; |
int position=0; |
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#include <stdio.h> |
#include <iostream> |
46,11 → 46,11
#define SEND_TIME_CODE 0 |
#define WAIT_500_CYCLES 1 |
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unsigned int state_test; |
unsigned int state_test=0; |
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unsigned int state_test_rx; |
unsigned int state_test_rx=0; |
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unsigned int counter_null; |
unsigned int counter_null=0; |
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#include "run_sim.h" |
#include "global_init.h" |
/vpi_test_stress/run_sim.h
5,11 → 5,13
vpiHandle DIN = vpi_handle_by_name("module_tb.TOP_DIN", NULL); |
vpiHandle SIN = vpi_handle_by_name("module_tb.TOP_SIN", NULL); |
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//vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); |
vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); |
//vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL); |
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vpiHandle i = vpi_handle_by_name("module_tb.i", NULL); |
vpiHandle tx_clock = vpi_handle_by_name("module_tb.time_clk_ns", NULL); |
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dout_value.format = vpiIntVal; |
sout_value.format = vpiIntVal; |
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19,7 → 21,7
fsm_value.format = vpiIntVal; |
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v_generate.format=vpiIntVal; |
//fsm_value.format = vpiIntVal; |
fsm_value.format = vpiIntVal; |
//message_value.format = vpiIntVal; |
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if(SC_TOP->finish_simulation() == 1) |
43,9 → 45,16
SC_TOP->set_rx_sin(sout_value.value.integer); |
SC_TOP->set_rx_din(dout_value.value.integer); |
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//fsm_value.value.integer = SC_TOP->get_spw_fsm(); |
//vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); |
fsm_value.value.integer = SC_TOP->get_spw_fsm(); |
vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); |
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vpi_get_value(tx_clock, &sout_value); |
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if(sout_value.value.integer != SC_TOP->verilog_frequency()) |
{ |
sin_value.value.integer = SC_TOP->verilog_frequency(); |
vpi_put_value(tx_clock, &sin_value, NULL, vpiNoDelay); |
} |
//fsm_value.value.integer = SC_TOP->clock_tx(); |
//vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay); |
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/vpi_test_stress/write_fsm_spw_ultra_light.h
11,9 → 11,6
link_enable_value.value.integer = SC_TOP->verilog_linkenable(); |
vpi_put_value(LINKSTART, &link_enable_value, NULL, vpiNoDelay); |
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//if(SC_TOP->verilog_linkenable()) |
// printf("TESTE\n"); |
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auto_start_value.value.integer = SC_TOP->verilog_autostart(); |
vpi_put_value(AUTOSTART, &auto_start_value, NULL, vpiNoDelay); |
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/vpi_test_stress/write_tx_data_spw_ultra_light.h
8,6 → 8,7
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if(SC_TOP->reset_set()) |
{ |
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if(SC_TOP->start_tx_test()) |
{ |
switch(state_test) |
16,17 → 17,18
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value_to_tx.value.integer = 0; |
vpi_put_value(TX_WRITE, &value_to_tx, NULL, vpiNoDelay); |
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value_to_tx.value.integer = SC_TOP->take_data(position); |
vpi_put_value(TX_DATA, &value_to_tx, NULL, vpiNoDelay); |
state_test = 59; |
break; |
case 59: |
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value_to_tx.value.integer = SC_TOP->take_data(position); |
vpi_put_value(TX_DATA, &value_to_tx, NULL, vpiNoDelay); |
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vpi_get_value(TX_READY, &value_to_tx); |
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if(value_to_tx.value.integer == 0) |
{ |
value_to_tx.value.integer = 1; |
value_to_tx.value.integer =1; |
vpi_put_value(TX_WRITE, &value_to_tx, NULL, vpiNoDelay); |
state_test = WAIT_DATA; |
} |