URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
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- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/rtl/RTL_VB/fsm_spw.v
82,7 → 82,7
assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1; |
|
// |
assign send_null_tx = (next_state_fsm == started | next_state_fsm == connecting | next_state_fsm == run)?1'b1:1'b0; |
assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0; |
|
// |
assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0; |
268,7 → 268,7
end |
else |
begin |
if(after850ns < 12'd85 && (auto_start | link_start)) |
if(after850ns < 12'd85 && state_fsm == run) |
after850ns <= after850ns + 12'd1; |
else |
after850ns <= 12'd0; |
/rtl/RTL_VB/rx_spw.v
117,15 → 117,15
assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8]; |
assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9]; |
|
assign control[0:0] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:control[0:0]; |
assign control[1:1] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:control[1:1]; |
assign control[2:2] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:control[2:2]; |
assign control[3:3] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:control[3:3]; |
assign control[0:0] = (counter == 5'd3)?rx_din:control[0:0]; |
assign control[1:1] = (counter == 5'd2)?rx_din:control[1:1]; |
assign control[2:2] = (counter == 5'd1)?rx_din:control[2:2]; |
assign control[3:3] = (counter == 5'd0)?rx_din:control[3:3]; |
|
assign rx_got_fct = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0; |
assign rx_got_nchar = (!rx_resetn)?1'b0:(!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0; |
assign rx_got_time_code = (!rx_resetn)?1'b0:(counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0; |
assign rx_got_null = (!rx_resetn)?1'b0:(counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0; |
assign rx_got_fct = (counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0; |
assign rx_got_nchar = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0; |
assign rx_got_time_code = (counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0; |
assign rx_got_null = (counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0; |
assign rx_got_bit = (posedge_clk)?1'b1:1'b0; |
|
assign rx_error = (parity_error)?1'b1: |
/rtl/RTL_VB/tx_spw.v
110,6 → 110,11
|
assign ready_tx_timecode = (enable_time_code & global_counter_transfer == 14)?1'b1:1'b0; |
|
/* |
assign ready_tx_data = (enable_n_char & global_counter_transfer == 4'd9 & !data_tx_i[8])?1'b1: |
(enable_n_char & global_counter_transfer == 4'd3 & data_tx_i[8])?1'b1:1'b0; |
*/ |
|
always@(*) |
begin |
tx_dout = 1'b0; |
436,7 → 441,8
else if((enable_null | enable_fct | enable_n_char) && tx_dout != last_tx_dout) |
begin |
tx_sout = last_tx_sout; |
end |
end |
|
end |
|
//slots open in another side |
496,10 → 502,10
begin |
if(send_null_tx && enable_tx) |
begin |
if(!hold_null) |
//if(!hold_null) |
next_state_tx = tx_spw_null; |
|
enable_null = 1'b1; |
//enable_null = 1'b1; |
end |
else |
begin |
535,7 → 541,8
enable_fct = 1'b0; |
if(send_fct_tx && fct_counter > 6'd0) |
begin |
next_state_tx = tx_spw_full; |
//if(global_counter_transfer == 4'd7) |
next_state_tx = tx_spw_full; |
end |
|
end |
548,6 → 555,13
enable_n_char = 1'b0; |
enable_time_code = 1'b0; |
|
/* |
hold_null <= 1'b0; |
hold_fct <= 1'b0; |
hold_data <= 1'b0; |
hold_time_code <= 1'b0; |
*/ |
|
if(tickin_tx && !hold_null && !hold_fct && !hold_data) |
begin |
enable_time_code = 1'b1; |
/systemC/link_sc.h
37,6 → 37,7
virtual bool verilog_linkenable(); |
virtual bool verilog_autostart(); |
virtual bool verilog_linkdisable(); |
virtual float verilog_frequency(); |
|
//tests |
virtual bool start_tx_test(); |
/testbench/module_tb.v
150,6 → 150,7
$dumpvars(0,module_tb); |
$global_init; |
i=0; |
time_clk_ns = 500; |
end |
|
initial PCLK = 1'b0; |
156,7 → 157,7
always #(5) PCLK = ~PCLK; |
|
initial PPLLCLK = 1'b0; |
always #(100) PPLLCLK = ~PPLLCLK; |
always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK; |
|
initial CLK_SIM = 1'b0; |
always #(1) CLK_SIM = ~CLK_SIM; |
198,15 → 199,12
.top_fsm(TOP_FSM) |
); |
|
|
|
|
// |
always@(posedge PCLK) |
$write_tx_fsm_spw_ultra_light; |
|
// |
always@(posedge PCLK) |
always@(posedge PCLK or posedge TOP_TX_READY) |
$write_tx_data_spw_ultra_light; |
|
always@(posedge PCLK) |
/vpi/vpi_test_stress/env_global_spw.cpp
2,9 → 2,9
|
#include "../../systemC/link_sc.h" |
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int counter; |
int counter=0; |
int data_iteration_vlog=0; |
int position; |
int position=0; |
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#include <stdio.h> |
#include <iostream> |
46,11 → 46,11
#define SEND_TIME_CODE 0 |
#define WAIT_500_CYCLES 1 |
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unsigned int state_test; |
unsigned int state_test=0; |
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unsigned int state_test_rx; |
unsigned int state_test_rx=0; |
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unsigned int counter_null; |
unsigned int counter_null=0; |
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#include "run_sim.h" |
#include "global_init.h" |
/vpi/vpi_test_stress/run_sim.h
5,11 → 5,13
vpiHandle DIN = vpi_handle_by_name("module_tb.TOP_DIN", NULL); |
vpiHandle SIN = vpi_handle_by_name("module_tb.TOP_SIN", NULL); |
|
//vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); |
vpiHandle DTA = vpi_handle_by_name("module_tb.SPW_SC_FSM", NULL); |
//vpiHandle TX_CLOCK_OUT = vpi_handle_by_name("module_tb.TX_CLOCK_OUT", NULL); |
|
vpiHandle i = vpi_handle_by_name("module_tb.i", NULL); |
vpiHandle tx_clock = vpi_handle_by_name("module_tb.time_clk_ns", NULL); |
|
|
dout_value.format = vpiIntVal; |
sout_value.format = vpiIntVal; |
|
19,7 → 21,7
fsm_value.format = vpiIntVal; |
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v_generate.format=vpiIntVal; |
//fsm_value.format = vpiIntVal; |
fsm_value.format = vpiIntVal; |
//message_value.format = vpiIntVal; |
|
if(SC_TOP->finish_simulation() == 1) |
43,9 → 45,16
SC_TOP->set_rx_sin(sout_value.value.integer); |
SC_TOP->set_rx_din(dout_value.value.integer); |
|
//fsm_value.value.integer = SC_TOP->get_spw_fsm(); |
//vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); |
fsm_value.value.integer = SC_TOP->get_spw_fsm(); |
vpi_put_value(DTA, &fsm_value, NULL, vpiNoDelay); |
|
vpi_get_value(tx_clock, &sout_value); |
|
if(sout_value.value.integer != SC_TOP->verilog_frequency()) |
{ |
sin_value.value.integer = SC_TOP->verilog_frequency(); |
vpi_put_value(tx_clock, &sin_value, NULL, vpiNoDelay); |
} |
//fsm_value.value.integer = SC_TOP->clock_tx(); |
//vpi_put_value(TX_CLOCK_OUT, &fsm_value, NULL, vpiNoDelay); |
|
/vpi/vpi_test_stress/write_fsm_spw_ultra_light.h
11,9 → 11,6
link_enable_value.value.integer = SC_TOP->verilog_linkenable(); |
vpi_put_value(LINKSTART, &link_enable_value, NULL, vpiNoDelay); |
|
//if(SC_TOP->verilog_linkenable()) |
// printf("TESTE\n"); |
|
auto_start_value.value.integer = SC_TOP->verilog_autostart(); |
vpi_put_value(AUTOSTART, &auto_start_value, NULL, vpiNoDelay); |
|
/vpi/vpi_test_stress/write_tx_data_spw_ultra_light.h
8,6 → 8,7
|
if(SC_TOP->reset_set()) |
{ |
|
if(SC_TOP->start_tx_test()) |
{ |
switch(state_test) |
16,17 → 17,18
|
value_to_tx.value.integer = 0; |
vpi_put_value(TX_WRITE, &value_to_tx, NULL, vpiNoDelay); |
|
value_to_tx.value.integer = SC_TOP->take_data(position); |
vpi_put_value(TX_DATA, &value_to_tx, NULL, vpiNoDelay); |
state_test = 59; |
break; |
case 59: |
|
value_to_tx.value.integer = SC_TOP->take_data(position); |
vpi_put_value(TX_DATA, &value_to_tx, NULL, vpiNoDelay); |
|
vpi_get_value(TX_READY, &value_to_tx); |
|
if(value_to_tx.value.integer == 0) |
{ |
value_to_tx.value.integer = 1; |
value_to_tx.value.integer =1; |
vpi_put_value(TX_WRITE, &value_to_tx, NULL, vpiNoDelay); |
state_test = WAIT_DATA; |
} |
/work/SpaceWrireTestSuit.glade
Cannot display: file marked as a binary type.
svn:mime-type = application/xml
/work/final_spw.so
Cannot display: file marked as a binary type.
svn:mime-type = application/x-sharedlib
/work/run_stress_test.sh
1,4 → 1,3
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g++ -c -ldl -fpic ../vpi/vpi_test_stress/env_global_spw.cpp -std=c++11 -Wwrite-strings -fpermissive |
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g++ -shared -oenv_global_spw.vpi env_global_spw.o -lvpi -std=c++11 -Wwrite-strings -fpermissive |