URL
https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk
Subversion Repositories spi_master_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/spi_master_slave/trunk
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/bench/readme.txt
File deleted
/bench/spi_master_atlys_test.vhd
File deleted
/bench/spi_loopback_test.vhd
File deleted
/bench/spi_loopback_test_dbg.wcfg
File deleted
/bench/spi_test_ct.wcfg
File deleted
/rtl/spi_loopback_test.vhd
0,0 → 1,305
-------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: Jonny Doin |
-- |
-- Create Date: 22:59:18 04/25/2011 |
-- Design Name: spi_master_slave |
-- Module Name: spi_master_slave/spi_loopback_test.vhd |
-- Project Name: SPI_interface |
-- Target Device: Spartan-6 |
-- Tool versions: ISE 13.1 |
-- Description: Testbench to simulate the master and slave SPI interfaces. Each module can be tested |
-- in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave' |
-- module, simulating the internal working of each design. |
-- In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for |
-- both modules, and also a different clock domain for each parallel interface. |
-- Different values for PREFETCH for each interface can be tested, to model the best value |
-- for the pipelined memory / bus that is attached to the di/do ports. |
-- To test the parallel interfaces, a simple ROM memory is simulated for each interface, with |
-- 8 words of data to be sent, synchronous to each clock and flow control signals. |
-- |
-- |
-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave' |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Revision 0.10 - Implemented FIFO simulation for each interface. |
-- Additional Comments: |
-- |
-- Notes: |
-- This testbench has been automatically generated using types std_logic and |
-- std_logic_vector for the ports of the unit under test. Xilinx recommends |
-- that these types always be used for the top-level I/O of a design in order |
-- to guarantee that the testbench will bind correctly to the post-implementation |
-- simulation model. |
-------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
USE ieee.numeric_std.ALL; |
|
library work; |
use work.all; |
|
ENTITY spi_loopback_test IS |
GENERIC ( |
N : positive := 32; -- 32bit serial word length is default |
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) |
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase. |
PREFETCH : positive := 2 -- prefetch lookahead cycles |
); |
END spi_loopback_test; |
|
ARCHITECTURE behavior OF spi_loopback_test IS |
|
--========================================================= |
-- Component declaration for the Unit Under Test (UUT) |
--========================================================= |
|
COMPONENT spi_loopback |
PORT( |
m_clk_i : IN std_logic; |
m_rst_i : IN std_logic; |
m_spi_miso_i : IN std_logic; |
m_di_i : IN std_logic_vector(31 downto 0); |
m_wren_i : IN std_logic; |
s_clk_i : IN std_logic; |
s_spi_ssel_i : IN std_logic; |
s_spi_sck_i : IN std_logic; |
s_spi_mosi_i : IN std_logic; |
s_di_i : IN std_logic_vector(31 downto 0); |
s_wren_i : IN std_logic; |
m_spi_ssel_o : OUT std_logic; |
m_spi_sck_o : OUT std_logic; |
m_spi_mosi_o : OUT std_logic; |
m_di_req_o : OUT std_logic; |
m_do_valid_o : OUT std_logic; |
m_do_o : OUT std_logic_vector(31 downto 0); |
m_do_transfer_o : OUT std_logic; |
m_wren_o : OUT std_logic; |
m_wren_ack_o : OUT std_logic; |
m_rx_bit_reg_o : OUT std_logic; |
m_state_dbg_o : OUT std_logic_vector(5 downto 0); |
m_core_clk_o : OUT std_logic; |
m_core_n_clk_o : OUT std_logic; |
m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0); |
s_spi_miso_o : OUT std_logic; |
s_di_req_o : OUT std_logic; |
s_do_valid_o : OUT std_logic; |
s_do_o : OUT std_logic_vector(31 downto 0); |
s_do_transfer_o : OUT std_logic; |
s_wren_o : OUT std_logic; |
s_wren_ack_o : OUT std_logic; |
s_rx_bit_reg_o : OUT std_logic; |
s_state_dbg_o : OUT std_logic_vector(5 downto 0) |
); |
END COMPONENT; |
|
--========================================================= |
-- constants |
--========================================================= |
constant fifo_memory_size : integer := 16; |
|
--========================================================= |
-- types |
--========================================================= |
type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0); |
|
--========================================================= |
-- signals to connect the instances |
--========================================================= |
-- internal clk and rst |
signal m_clk : std_logic := '0'; -- clock domain for the master parallel interface. Must be faster than spi bus sck. |
signal s_clk : std_logic := '0'; -- clock domain for the slave parallel interface. Must be faster than spi bus sck. |
signal rst : std_logic := 'U'; |
-- spi bus wires |
signal spi_sck : std_logic; |
signal spi_ssel : std_logic; |
signal spi_miso : std_logic; |
signal spi_mosi : std_logic; |
-- master parallel interface |
signal di_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U'); |
signal do_valid_m : std_logic; |
signal do_transfer_m : std_logic; |
signal di_req_m : std_logic; |
signal wren_m : std_logic := '0'; |
signal wren_o_m : std_logic := 'U'; |
signal wren_ack_o_m : std_logic := 'U'; |
signal rx_bit_reg_m : std_logic; |
signal state_m : std_logic_vector (5 downto 0); |
signal core_clk_o_m : std_logic; |
signal core_n_clk_o_m : std_logic; |
signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0'); |
-- slave parallel interface |
signal di_s : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal do_s : std_logic_vector (N-1 downto 0); |
signal do_valid_s : std_logic; |
signal do_transfer_s : std_logic; |
signal di_req_s : std_logic; |
signal wren_s : std_logic := '0'; |
signal wren_o_s : std_logic := 'U'; |
signal wren_ack_o_s : std_logic := 'U'; |
signal rx_bit_reg_s : std_logic; |
signal state_s : std_logic_vector (5 downto 0); |
-- signal sh_reg_s : std_logic_vector (N-1 downto 0); |
|
--========================================================= |
-- Clock period definitions |
--========================================================= |
constant m_clk_period : time := 10 ns; -- 100MHz master parallel clock |
constant s_clk_period : time := 10 ns; -- 100MHz slave parallel clock |
|
BEGIN |
|
--========================================================= |
-- Component instantiation for the Unit Under Test (UUT) |
--========================================================= |
|
Inst_spi_loopback: spi_loopback |
port map( |
----------------MASTER----------------------- |
m_clk_i => m_clk, |
m_rst_i => rst, |
m_spi_ssel_o => spi_ssel, |
m_spi_sck_o => spi_sck, |
m_spi_mosi_o => spi_mosi, |
m_spi_miso_i => spi_miso, |
m_di_req_o => di_req_m, |
m_di_i => di_m, |
m_wren_i => wren_m, |
m_do_valid_o => do_valid_m, |
m_do_o => do_m, |
----- debug ----- |
m_do_transfer_o => do_transfer_m, |
m_wren_o => wren_o_m, |
m_wren_ack_o => wren_ack_o_m, |
m_rx_bit_reg_o => rx_bit_reg_m, |
m_state_dbg_o => state_m, |
m_core_clk_o => core_clk_o_m, |
m_core_n_clk_o => core_n_clk_o_m, |
m_sh_reg_dbg_o => sh_reg_m, |
----------------SLAVE----------------------- |
s_clk_i => s_clk, |
s_spi_ssel_i => spi_ssel, |
s_spi_sck_i => spi_sck, |
s_spi_mosi_i => spi_mosi, |
s_spi_miso_o => spi_miso, |
s_di_req_o => di_req_s, |
s_di_i => di_s, |
s_wren_i => wren_s, |
s_do_valid_o => do_valid_s, |
s_do_o => do_s, |
----- debug ----- |
s_do_transfer_o => do_transfer_s, |
s_wren_o => wren_o_s, |
s_wren_ack_o => wren_ack_o_s, |
s_rx_bit_reg_o => rx_bit_reg_s, |
s_state_dbg_o => state_s |
-- s_sh_reg_dbg_o => sh_reg_s |
); |
|
--========================================================= |
-- Clock generator processes |
--========================================================= |
m_clk_process : process |
begin |
m_clk <= '0'; |
wait for m_clk_period/2; |
m_clk <= '1'; |
wait for m_clk_period/2; |
end process m_clk_process; |
|
s_clk_process : process |
begin |
s_clk <= '0'; |
wait for s_clk_period/2; |
s_clk <= '1'; |
wait for s_clk_period/2; |
end process s_clk_process; |
|
--========================================================= |
-- rst_i process |
--========================================================= |
rst <= '0', '1' after 20 ns, '0' after 100 ns; |
|
--========================================================= |
-- Master interface process |
--========================================================= |
master_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789", |
X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until m_clk'event and m_clk = '1'; |
di_m <= (others => '0'); |
wren_m <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
wait until di_req_m = '1'; -- wait shift register request for data |
-- load next fifo contents into shift register |
for cnt in 0 to (fifo_memory_size/2)-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '1'; -- write data into spi master |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '0'; -- remove write enable signal |
wait until di_req_m = '1'; -- wait shift register request for data |
end loop; |
wait until spi_ssel = '1'; |
wait for 2000 ns; |
for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
di_m <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '1'; -- write data into spi master |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wait until m_clk'event and m_clk = '1'; -- sync fifo data load at next rising edge |
wren_m <= '0'; -- remove write enable signal |
wait until di_req_m = '1'; -- wait shift register request for data |
end loop; |
wait; |
end process master_tx_fifo_proc; |
|
|
--========================================================= |
-- Slave interface process |
--========================================================= |
slave_tx_fifo_proc: process is |
variable fifo_memory : fifo_memory_type := |
(X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394", |
X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678"); |
variable fifo_head : integer range 0 to fifo_memory_size-1; |
begin |
-- synchronous rst_i |
wait until rst = '1'; |
wait until s_clk'event and s_clk = '1'; |
di_s <= (others => '0'); |
wren_s <= '0'; |
fifo_head := 0; |
wait until rst = '0'; |
wait until di_req_s = '1'; -- wait shift register request for data |
-- load next fifo contents into shift register |
for cnt in 0 to fifo_memory_size-1 loop |
fifo_head := cnt; -- pre-compute next pointer |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
di_s <= fifo_memory(fifo_head); -- place data into tx_data input bus |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '1'; -- write data into shift register |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wait until s_clk'event and s_clk = '1'; -- sync fifo data load at next rising edge |
wren_s <= '0'; -- remove write enable signal |
wait until di_req_s = '1'; -- wait shift register request for data |
end loop; |
wait; |
end process slave_tx_fifo_proc; |
|
END ARCHITECTURE behavior; |
/syn/spi_master_atlys.xise
File deleted
/syn/spi_master_atlys_top_bitgen.xwbt
0,0 → 1,8
INTSTYLE=ise |
INFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.ncd |
OUTFILE=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.bit |
FAMILY=Spartan6 |
PART=xc6slx45-2csg324 |
WORKINGDIR=C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn |
LICENSE=WebPack |
USER_INFO=205970357_0_0_751 |
/syn/spi_master_atlys_top.twr
0,0 → 1,112
-------------------------------------------------------------------------------- |
Release 13.1 Trace (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
|
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n |
3 -fastpaths -xml spi_master_atlys_top.twx spi_master_atlys_top.ncd -o |
spi_master_atlys_top.twr spi_master_atlys_top.pcf -ucf spi_master_atlys.ucf |
|
Design file: spi_master_atlys_top.ncd |
Physical constraint file: spi_master_atlys_top.pcf |
Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07) |
Report level: verbose report |
|
Environment Variable Effect |
-------------------- ------ |
NONE No environment variables were set |
-------------------------------------------------------------------------------- |
|
INFO:Timing:2698 - No timing constraints found, doing default enumeration. |
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths |
option. All paths that are not constrained will be reported in the |
unconstrained paths section(s) of the report. |
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on |
a 50 Ohm transmission line loading model. For the details of this model, |
and for more information on accounting for different loading conditions, |
please see the device datasheet. |
|
|
|
Data Sheet report: |
----------------- |
All values displayed in nanoseconds (ns) |
|
Setup/Hold to clock gclk_i |
------------+------------+------------+------------+------------+------------------+--------+ |
|Max Setup to| Process |Max Hold to | Process | | Clock | |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | |
------------+------------+------------+------------+------------+------------------+--------+ |
btn_i<0> | 3.278(R)| SLOW | -1.955(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<1> | 2.687(R)| SLOW | -1.446(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<2> | 2.472(R)| SLOW | -1.378(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<3> | 2.485(R)| SLOW | -1.363(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<4> | 3.029(R)| SLOW | -1.604(R)| FAST |gclk_i_BUFGP | 0.000| |
btn_i<5> | 2.674(R)| SLOW | -1.430(R)| SLOW |gclk_i_BUFGP | 0.000| |
sw_i<0> | 4.100(R)| SLOW | -2.174(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<1> | 5.263(R)| SLOW | -2.981(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<2> | 5.340(R)| SLOW | -2.970(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<3> | 4.839(R)| SLOW | -2.685(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<4> | 3.689(R)| SLOW | -2.001(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<5> | 4.210(R)| SLOW | -2.310(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<6> | 4.396(R)| SLOW | -2.450(R)| FAST |gclk_i_BUFGP | 0.000| |
sw_i<7> | 4.807(R)| SLOW | -2.644(R)| FAST |gclk_i_BUFGP | 0.000| |
------------+------------+------------+------------+------------+------------------+--------+ |
|
Clock gclk_i to Pad |
------------+-----------------+------------+-----------------+------------+------------------+--------+ |
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | |
------------+-----------------+------------+-----------------+------------+------------------+--------+ |
dbg_o<4> | 10.189(R)| SLOW | 4.245(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<5> | 10.661(R)| SLOW | 4.525(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<7> | 10.584(R)| SLOW | 4.515(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<8> | 10.546(R)| SLOW | 4.517(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<9> | 10.444(R)| SLOW | 4.424(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<10> | 11.747(R)| SLOW | 5.263(R)| FAST |gclk_i_BUFGP | 0.000| |
dbg_o<11> | 10.850(R)| SLOW | 4.663(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<0> | 9.978(R)| SLOW | 4.140(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<1> | 9.999(R)| SLOW | 4.146(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<2> | 9.969(R)| SLOW | 4.128(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<3> | 9.554(R)| SLOW | 3.890(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<4> | 10.087(R)| SLOW | 4.246(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<5> | 16.607(R)| SLOW | 8.007(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<6> | 11.948(R)| SLOW | 5.282(R)| FAST |gclk_i_BUFGP | 0.000| |
led_o<7> | 11.126(R)| SLOW | 4.792(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<0> | 9.589(R)| SLOW | 3.927(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<1> | 9.834(R)| SLOW | 4.096(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<2> | 9.806(R)| SLOW | 4.063(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<3> | 9.369(R)| SLOW | 3.801(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<4> | 9.464(R)| SLOW | 3.837(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<5> | 9.704(R)| SLOW | 4.008(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<6> | 9.672(R)| SLOW | 3.966(R)| FAST |gclk_i_BUFGP | 0.000| |
m_do_o<7> | 9.539(R)| SLOW | 3.912(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<0>| 11.606(R)| SLOW | 5.188(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<1>| 11.499(R)| SLOW | 5.055(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<2>| 11.467(R)| SLOW | 5.046(R)| FAST |gclk_i_BUFGP | 0.000| |
m_state_o<3>| 11.607(R)| SLOW | 5.144(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_miso_o | 13.517(R)| SLOW | 5.528(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_mosi_o | 13.405(R)| SLOW | 5.552(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_sck_o | 11.665(R)| SLOW | 5.240(R)| FAST |gclk_i_BUFGP | 0.000| |
spi_ssel_o | 12.854(R)| SLOW | 5.876(R)| FAST |gclk_i_BUFGP | 0.000| |
------------+-----------------+------------+-----------------+------------+------------------+--------+ |
|
Clock to Setup on destination clock gclk_i |
---------------+---------+---------+---------+---------+ |
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
---------------+---------+---------+---------+---------+ |
gclk_i | 5.299| | | | |
---------------+---------+---------+---------+---------+ |
|
|
Analysis completed Wed Aug 10 22:57:08 2011 |
-------------------------------------------------------------------------------- |
|
Trace Settings: |
------------------------- |
Trace Settings |
|
Peak Memory Usage: 180 MB |
|
|
|
/syn/spi_master_atlys_top.syr
0,0 → 1,798
Release 13.1 - xst O.40d (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
--> Parameter TMPDIR set to xst/projnav.tmp |
|
|
Total REAL time to Xst completion: 1.00 secs |
Total CPU time to Xst completion: 0.09 secs |
|
--> Parameter xsthdpdir set to xst |
|
|
Total REAL time to Xst completion: 1.00 secs |
Total CPU time to Xst completion: 0.09 secs |
|
--> Reading design: spi_master_atlys_top.prj |
|
TABLE OF CONTENTS |
1) Synthesis Options Summary |
2) HDL Parsing |
3) HDL Elaboration |
4) HDL Synthesis |
4.1) HDL Synthesis Report |
5) Advanced HDL Synthesis |
5.1) Advanced HDL Synthesis Report |
6) Low Level Synthesis |
7) Partition Report |
8) Design Summary |
8.1) Primitive and Black Box Usage |
8.2) Device utilization summary |
8.3) Partition Resource Summary |
8.4) Timing Report |
8.4.1) Clock Information |
8.4.2) Asynchronous Control Signals Information |
8.4.3) Timing Summary |
8.4.4) Timing Details |
8.4.5) Cross Clock Domains Report |
|
|
========================================================================= |
* Synthesis Options Summary * |
========================================================================= |
---- Source Parameters |
Input File Name : "spi_master_atlys_top.prj" |
Input Format : mixed |
Ignore Synthesis Constraint File : NO |
|
---- Target Parameters |
Output File Name : "spi_master_atlys_top" |
Output Format : NGC |
Target Device : xc6slx45-2-csg324 |
|
---- Source Options |
Top Module Name : spi_master_atlys_top |
Automatic FSM Extraction : YES |
FSM Encoding Algorithm : Gray |
Safe Implementation : No |
FSM Style : LUT |
RAM Extraction : No |
ROM Extraction : No |
Shift Register Extraction : NO |
Resource Sharing : YES |
Asynchronous To Synchronous : NO |
Shift Register Minimum Size : 2 |
Use DSP Block : Auto |
Automatic Register Balancing : No |
|
---- Target Options |
LUT Combining : Area |
Reduce Control Sets : Auto |
Add IO Buffers : YES |
Global Maximum Fanout : 100000 |
Add Generic Clock Buffer(BUFG) : 16 |
Register Duplication : YES |
Optimize Instantiated Primitives : NO |
Use Clock Enable : Auto |
Use Synchronous Set : Auto |
Use Synchronous Reset : Auto |
Pack IO Registers into IOBs : Auto |
Equivalent register Removal : YES |
|
---- General Options |
Optimization Goal : Speed |
Optimization Effort : 2 |
Power Reduction : NO |
Keep Hierarchy : No |
Netlist Hierarchy : As_Optimized |
RTL Output : Yes |
Global Optimization : AllClockNets |
Read Cores : YES |
Write Timing Constraints : NO |
Cross Clock Analysis : NO |
Hierarchy Separator : / |
Bus Delimiter : <> |
Case Specifier : Maintain |
Slice Utilization Ratio : 100 |
BRAM Utilization Ratio : 100 |
DSP48 Utilization Ratio : 100 |
Auto BRAM Packing : NO |
Slice Utilization Ratio Delta : 5 |
|
========================================================================= |
|
|
========================================================================= |
* HDL Parsing * |
========================================================================= |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work |
Parsing entity <spi_slave>. |
Parsing architecture <rtl> of entity <spi_slave>. |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 347: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 355: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 364: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" into library work |
Parsing entity <spi_master>. |
Parsing architecture <rtl> of entity <spi_master>. |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 503: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 511: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 519: Case choice must be a locally static expression |
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master.vhd" Line 528: Case choice must be a locally static expression |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work |
Parsing entity <grp_debouncer>. |
Parsing architecture <rtl> of entity <grp_debouncer>. |
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work |
Parsing entity <spi_master_atlys_top>. |
Parsing architecture <behavioral> of entity <spi_master_atlys_top>. |
|
========================================================================= |
* HDL Elaboration * |
========================================================================= |
|
Elaborating entity <spi_master_atlys_top> (architecture <behavioral>) from library <work>. |
|
Elaborating entity <spi_master> (architecture <rtl>) with generics from library <work>. |
|
Elaborating entity <spi_slave> (architecture <rtl>) with generics from library <work>. |
|
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>. |
|
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>. |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 456. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 517. Case statement is complete. others clause is never selected |
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 567. Case statement is complete. others clause is never selected |
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spi_master_slave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 174: Net <dbg[3]> does not have a driver. |
|
========================================================================= |
* HDL Synthesis * |
========================================================================= |
|
Synthesizing Unit <spi_master_atlys_top>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd". |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sh_reg_dbg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <sck_ena_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <do_transfer_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <wren_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <rx_bit_reg_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_clk_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 181: Output port <core_n_ce_o> of the instance <Inst_spi_master_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <sh_reg_dbg_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <do_transfer_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <wren_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 202: Output port <rx_bit_next_o> of the instance <Inst_spi_slave_port> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 221: Output port <strb_o> of the instance <Inst_sw_debouncer> is unconnected or connected to loadless signal. |
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 230: Output port <strb_o> of the instance <Inst_btn_debouncer> is unconnected or connected to loadless signal. |
WARNING:Xst:2935 - Signal 'dbg<3:0>', unconnected in block 'spi_master_atlys_top', is tied to its initial value (0000). |
Found 1-bit register for signal <samp_ce_gen_proc.clk_cnt>. |
Found 1-bit register for signal <fsm_ce>. |
Found 1-bit register for signal <fsm_ce_gen_proc.clk_cnt>. |
Found 1-bit register for signal <clear>. |
Found 8-bit register for signal <led_o>. |
Found 4-bit register for signal <m_wr_st_reg>. |
Found 3-bit register for signal <s_wr_st_reg>. |
Found 3-bit register for signal <s_rd_st_reg>. |
Found 1-bit register for signal <spi_wren_reg_m>. |
Found 8-bit register for signal <spi_di_reg_m>. |
Found 1-bit register for signal <spi_rst_reg>. |
Found 1-bit register for signal <spi_ssel_reg>. |
Found 8-bit register for signal <sw_reg>. |
Found 6-bit register for signal <btn_reg>. |
Found 1-bit register for signal <spi_wren_reg_s>. |
Found 8-bit register for signal <spi_di_reg_s>. |
Found 8-bit register for signal <s_do_1_reg>. |
Found 8-bit register for signal <s_do_2_reg>. |
Found 8-bit register for signal <s_do_3_reg>. |
Found 1-bit register for signal <samp_ce>. |
Found finite state machine <FSM_2> for signal <s_rd_st_reg>. |
----------------------------------------------------------------------- |
| States | 7 | |
| Transitions | 20 | |
| Inputs | 2 | |
| Outputs | 3 | |
| Clock | gclk_i (rising_edge) | |
| Reset | spi_ssel_o (positive) | |
| Reset type | synchronous | |
| Reset State | st_reset | |
| Power Up State | st_reset | |
| Encoding | Gray | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
Found finite state machine <FSM_0> for signal <m_wr_st_reg>. |
----------------------------------------------------------------------- |
| States | 11 | |
| Transitions | 36 | |
| Inputs | 11 | |
| Outputs | 10 | |
| Clock | gclk_i (rising_edge) | |
| Reset | clear (positive) | |
| Reset type | synchronous | |
| Reset State | st_reset | |
| Power Up State | st_reset | |
| Encoding | Gray | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM <s_wr_st_reg>. |
Found finite state machine <FSM_1> for signal <s_wr_st_reg>. |
----------------------------------------------------------------------- |
| States | 8 | |
| Transitions | 20 | |
| Inputs | 5 | |
| Outputs | 9 | |
| Clock | gclk_i (rising_edge) | |
| Reset | spi_ssel_o (positive) | |
| Reset type | synchronous | |
| Reset State | st_reset | |
| Power Up State | st_reset | |
| Encoding | Gray | |
| Implementation | LUT | |
----------------------------------------------------------------------- |
Found 1-bit adder for signal <samp_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_1_OUT<0>> created at line 273. |
Found 1-bit adder for signal <fsm_ce_gen_proc.clk_cnt[0]_PWR_4_o_add_3_OUT<0>> created at line 287. |
Found 8-bit comparator equal for signal <_n0380> created at line 359 |
Found 6-bit comparator equal for signal <_n0400> created at line 362 |
Summary: |
inferred 2 Adder/Subtractor(s). |
inferred 71 D-type flip-flop(s). |
inferred 2 Comparator(s). |
inferred 5 Multiplexer(s). |
inferred 3 Finite State Machine(s). |
Unit <spi_master_atlys_top> synthesized. |
|
Synthesizing Unit <spi_master>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_master.vhd". |
N = 8 |
CPOL = '0' |
CPHA = '0' |
PREFETCH = 3 |
SPI_2X_CLK_DIV = 1 |
Found 1-bit register for signal <spi_2x_ce_gen_proc.clk_cnt>. |
Found 1-bit register for signal <core_clk>. |
Found 1-bit register for signal <core_n_clk>. |
Found 1-bit register for signal <core_ce>. |
Found 1-bit register for signal <core_n_ce>. |
Found 1-bit register for signal <rx_bit_reg>. |
Found 1-bit register for signal <do_valid_A>. |
Found 1-bit register for signal <do_valid_B>. |
Found 1-bit register for signal <do_valid_C>. |
Found 1-bit register for signal <do_valid_D>. |
Found 1-bit register for signal <do_valid_o_reg>. |
Found 1-bit register for signal <di_req_o_A>. |
Found 1-bit register for signal <di_req_o_B>. |
Found 1-bit register for signal <di_req_o_C>. |
Found 1-bit register for signal <di_req_o_D>. |
Found 1-bit register for signal <di_req_o_reg>. |
Found 8-bit register for signal <di_reg>. |
Found 1-bit register for signal <wren>. |
Found 4-bit register for signal <state_reg>. |
Found 8-bit register for signal <sh_reg>. |
Found 1-bit register for signal <ssel_ena_reg>. |
Found 8-bit register for signal <do_buffer_reg>. |
Found 1-bit register for signal <do_transfer_reg>. |
Found 1-bit register for signal <di_req_reg>. |
Found 1-bit register for signal <wr_ack_reg>. |
Found 1-bit register for signal <sck_ena_reg>. |
Found 1-bit register for signal <spi_clk_reg>. |
Found 1-bit register for signal <spi_2x_ce>. |
Found 1-bit adder for signal <spi_2x_ce_gen_proc.clk_cnt[0]_PWR_7_o_add_1_OUT<0>> created at line 328. |
Found 4-bit subtractor for signal <GND_7_o_GND_7_o_sub_12_OUT<3:0>> created at line 526. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_20_o> created at line 519 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_21_o> created at line 519 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_7_o_LessThan_22_o> created at line 528 |
Found 4-bit comparator greater for signal <GND_7_o_state_reg[3]_LessThan_23_o> created at line 528 |
Summary: |
inferred 2 Adder/Subtractor(s). |
inferred 52 D-type flip-flop(s). |
inferred 4 Comparator(s). |
inferred 13 Multiplexer(s). |
Unit <spi_master> synthesized. |
|
Synthesizing Unit <spi_slave>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/spi_slave.vhd". |
N = 8 |
CPOL = '0' |
CPHA = '0' |
PREFETCH = 3 |
Found 4-bit register for signal <state_reg>. |
Found 1-bit register for signal <do_valid_B>. |
Found 1-bit register for signal <do_valid_C>. |
Found 1-bit register for signal <do_valid_D>. |
Found 1-bit register for signal <do_valid_o_reg>. |
Found 1-bit register for signal <di_req_o_A>. |
Found 1-bit register for signal <di_req_o_B>. |
Found 1-bit register for signal <di_req_o_C>. |
Found 1-bit register for signal <di_req_o_D>. |
Found 1-bit register for signal <di_req_o_reg>. |
Found 8-bit register for signal <di_reg>. |
Found 1-bit register for signal <wren>. |
Found 8-bit register for signal <sh_reg>. |
Found 8-bit register for signal <do_buffer_reg>. |
Found 1-bit register for signal <do_transfer_reg>. |
Found 1-bit register for signal <di_req_reg>. |
Found 1-bit register for signal <wr_ack_reg>. |
Found 1-bit register for signal <tx_bit_reg>. |
Found 1-bit register for signal <do_valid_A>. |
Found 4-bit subtractor for signal <GND_8_o_GND_8_o_sub_6_OUT<3:0>> created at line 362. |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_9_o> created at line 355 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_10_o> created at line 355 |
Found 4-bit comparator greater for signal <state_reg[3]_GND_8_o_LessThan_11_o> created at line 364 |
Found 4-bit comparator greater for signal <GND_8_o_state_reg[3]_LessThan_12_o> created at line 364 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 43 D-type flip-flop(s). |
inferred 4 Comparator(s). |
inferred 22 Multiplexer(s). |
Unit <spi_slave> synthesized. |
|
Synthesizing Unit <grp_debouncer_1>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
N = 8 |
CNT_VAL = 200 |
Found 8-bit register for signal <reg_A>. |
Found 8-bit register for signal <reg_B>. |
Found 8-bit register for signal <reg_out>. |
Found 8-bit register for signal <cnt_reg>. |
Found 9-bit adder for signal <n0024> created at line 162. |
Found 8-bit comparator not equal for signal <n0008> created at line 184 |
Found 8-bit comparator not equal for signal <n0010> created at line 190 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 32 D-type flip-flop(s). |
inferred 2 Comparator(s). |
Unit <grp_debouncer_1> synthesized. |
|
Synthesizing Unit <grp_debouncer_2>. |
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spi_master_slave/spi_master_slave/trunk/syn/grp_debouncer.vhd". |
N = 6 |
CNT_VAL = 200 |
Found 6-bit register for signal <reg_A>. |
Found 6-bit register for signal <reg_B>. |
Found 6-bit register for signal <reg_out>. |
Found 8-bit register for signal <cnt_reg>. |
Found 9-bit adder for signal <n0024> created at line 162. |
Found 6-bit comparator not equal for signal <n0008> created at line 184 |
Found 6-bit comparator not equal for signal <n0010> created at line 190 |
Summary: |
inferred 1 Adder/Subtractor(s). |
inferred 26 D-type flip-flop(s). |
inferred 2 Comparator(s). |
Unit <grp_debouncer_2> synthesized. |
|
========================================================================= |
HDL Synthesis Report |
|
Macro Statistics |
# Adders/Subtractors : 7 |
1-bit adder : 3 |
4-bit subtractor : 2 |
9-bit adder : 2 |
# Registers : 72 |
1-bit register : 48 |
4-bit register : 2 |
6-bit register : 4 |
8-bit register : 18 |
# Comparators : 14 |
4-bit comparator greater : 8 |
6-bit comparator equal : 1 |
6-bit comparator not equal : 2 |
8-bit comparator equal : 1 |
8-bit comparator not equal : 2 |
# Multiplexers : 40 |
1-bit 2-to-1 multiplexer : 13 |
4-bit 2-to-1 multiplexer : 12 |
8-bit 2-to-1 multiplexer : 15 |
# FSMs : 3 |
|
========================================================================= |
|
========================================================================= |
* Advanced HDL Synthesis * |
========================================================================= |
|
WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1710 - FF/Latch <di_reg_3> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1710 - FF/Latch <di_reg_5> (without init value) has a constant value of 0 in block <Inst_spi_slave_port>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
|
Synthesizing (advanced) Unit <grp_debouncer_1>. |
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>. |
Unit <grp_debouncer_1> synthesized (advanced). |
|
Synthesizing (advanced) Unit <grp_debouncer_2>. |
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>. |
Unit <grp_debouncer_2> synthesized (advanced). |
|
Synthesizing (advanced) Unit <spi_master>. |
The following registers are absorbed into counter <spi_2x_ce_gen_proc.clk_cnt_0>: 1 register on signal <spi_2x_ce_gen_proc.clk_cnt_0>. |
Unit <spi_master> synthesized (advanced). |
|
Synthesizing (advanced) Unit <spi_master_atlys_top>. |
The following registers are absorbed into counter <samp_ce_gen_proc.clk_cnt_0>: 1 register on signal <samp_ce_gen_proc.clk_cnt_0>. |
The following registers are absorbed into counter <fsm_ce_gen_proc.clk_cnt_0>: 1 register on signal <fsm_ce_gen_proc.clk_cnt_0>. |
Unit <spi_master_atlys_top> synthesized (advanced). |
|
========================================================================= |
Advanced HDL Synthesis Report |
|
Macro Statistics |
# Adders/Subtractors : 2 |
4-bit subtractor : 2 |
# Counters : 5 |
1-bit up counter : 3 |
8-bit up counter : 2 |
# Registers : 205 |
Flip-Flops : 205 |
# Comparators : 14 |
4-bit comparator greater : 8 |
6-bit comparator equal : 1 |
6-bit comparator not equal : 2 |
8-bit comparator equal : 1 |
8-bit comparator not equal : 2 |
# Multiplexers : 46 |
1-bit 2-to-1 multiplexer : 20 |
4-bit 2-to-1 multiplexer : 12 |
8-bit 2-to-1 multiplexer : 14 |
# FSMs : 3 |
|
========================================================================= |
|
========================================================================= |
* Low Level Synthesis * |
========================================================================= |
WARNING:Xst:1293 - FF/Latch <spi_di_reg_s_2> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_3> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <spi_di_reg_s_5> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
INFO:Xst:2261 - The FF/Latch <di_reg_2> in Unit <spi_slave> is equivalent to the following 2 FFs/Latches, which will be removed : <di_reg_3> <di_reg_5> |
WARNING:Xst:1710 - FF/Latch <di_reg_2> (without init value) has a constant value of 0 in block <spi_slave>. This FF/Latch will be trimmed during the optimization process. |
Optimizing FSM <FSM_2> on signal <s_rd_st_reg[1:3]> with Gray encoding. |
-------------------------------------- |
State | Encoding |
-------------------------------------- |
st_reset | 000 |
st_wait_spi_do_valid_1 | 001 |
st_wait_spi_n_do_valid_1 | 011 |
st_wait_spi_do_valid_2 | 010 |
st_wait_spi_n_do_valid_2 | 110 |
st_wait_spi_do_valid_3 | 111 |
st_wait_spi_n_do_valid_3 | 101 |
-------------------------------------- |
Optimizing FSM <FSM_0> on signal <m_wr_st_reg[1:4]> with Gray encoding. |
---------------------------------- |
State | Encoding |
---------------------------------- |
st_reset | 0000 |
st_wait_spi_idle | 0001 |
st_wait_new_switch | 0011 |
st_send_spi_data_sw | 0110 |
st_wait_spi_ack_sw | 0111 |
st_send_spi_data_1 | 0010 |
st_wait_spi_ack_1 | 0100 |
st_wait_spi_di_req_2 | 0101 |
st_wait_spi_ack_2 | 1100 |
st_wait_spi_di_req_3 | 1101 |
st_wait_spi_ack_3 | 1111 |
---------------------------------- |
Optimizing FSM <FSM_1> on signal <s_wr_st_reg[1:3]> with Gray encoding. |
------------------------------------ |
State | Encoding |
------------------------------------ |
st_reset | 000 |
st_wait_spi_start | 001 |
st_wait_spi_di_req_2 | 011 |
st_wait_spi_ack_2 | unreached |
st_wait_spi_do_valid_1 | 010 |
st_wait_spi_di_req_3 | 110 |
st_wait_spi_ack_3 | 111 |
st_wait_spi_end | 101 |
------------------------------------ |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_7 hinder the constant cleaning in the block spi_master_atlys_top. |
You should achieve better results by setting this init to 1. |
INFO:Xst:2261 - The FF/Latch <spi_di_reg_s_0> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <spi_di_reg_s_4> <spi_di_reg_s_6> <spi_di_reg_s_7> |
|
Optimizing unit <spi_master_atlys_top> ... |
|
Optimizing unit <grp_debouncer_1> ... |
|
Optimizing unit <grp_debouncer_2> ... |
|
Optimizing unit <spi_master> ... |
|
Optimizing unit <spi_slave> ... |
WARNING:Xst:1293 - FF/Latch <fsm_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <samp_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <fsm_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce_gen_proc.clk_cnt_0> has a constant value of 0 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Inst_spi_master_port/spi_2x_ce> has a constant value of 1 in block <spi_master_atlys_top>. This FF/Latch will be trimmed during the optimization process. |
INFO:Xst:2261 - The FF/Latch <Inst_spi_slave_port/di_reg_7> in Unit <spi_master_atlys_top> is equivalent to the following 3 FFs/Latches, which will be removed : <Inst_spi_slave_port/di_reg_6> <Inst_spi_slave_port/di_reg_4> <Inst_spi_slave_port/di_reg_0> |
INFO:Xst:2261 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is equivalent to the following FF/Latch, which will be removed : <Inst_spi_master_port/core_ce> |
INFO:Xst:3203 - The FF/Latch <Inst_spi_master_port/core_clk> in Unit <spi_master_atlys_top> is the opposite to the following 2 FFs/Latches, which will be removed : <Inst_spi_master_port/core_n_clk> <Inst_spi_master_port/core_n_ce> |
|
Mapping all equations... |
Building and optimizing final netlist ... |
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1. |
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s) |
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s) |
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s) |
|
Final Macro Processing ... |
|
========================================================================= |
Final Register Report |
|
Macro Statistics |
# Registers : 217 |
Flip-Flops : 217 |
|
========================================================================= |
|
========================================================================= |
* Partition Report * |
========================================================================= |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
========================================================================= |
* Design Summary * |
========================================================================= |
|
Top Level Output File Name : spi_master_atlys_top.ngc |
|
Primitive and Black Box Usage: |
------------------------------ |
# BELS : 205 |
# GND : 1 |
# INV : 4 |
# LUT1 : 14 |
# LUT2 : 4 |
# LUT3 : 28 |
# LUT4 : 17 |
# LUT5 : 55 |
# LUT6 : 47 |
# MUXCY : 14 |
# MUXF7 : 4 |
# VCC : 1 |
# XORCY : 16 |
# FlipFlops/Latches : 217 |
# FD : 83 |
# FD_1 : 1 |
# FDC : 8 |
# FDE : 111 |
# FDR : 10 |
# FDRE : 4 |
# Clock Buffers : 2 |
# BUFG : 1 |
# BUFGP : 1 |
# IO Buffers : 62 |
# IBUF : 14 |
# OBUF : 48 |
|
Device utilization summary: |
--------------------------- |
|
Selected Device : 6slx45csg324-2 |
|
|
Slice Logic Utilization: |
Number of Slice Registers: 217 out of 54576 0% |
Number of Slice LUTs: 169 out of 27288 0% |
Number used as Logic: 169 out of 27288 0% |
|
Slice Logic Distribution: |
Number of LUT Flip Flop pairs used: 274 |
Number with an unused Flip Flop: 57 out of 274 20% |
Number with an unused LUT: 105 out of 274 38% |
Number of fully used LUT-FF pairs: 112 out of 274 40% |
Number of unique control sets: 23 |
|
IO Utilization: |
Number of IOs: 63 |
Number of bonded IOBs: 63 out of 218 28% |
|
Specific Feature Utilization: |
Number of BUFG/BUFGCTRLs: 2 out of 16 12% |
|
--------------------------- |
Partition Resource Summary: |
--------------------------- |
|
No Partitions were found in this design. |
|
--------------------------- |
|
|
========================================================================= |
Timing Report |
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. |
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT |
GENERATED AFTER PLACE-and-ROUTE. |
|
Clock Information: |
------------------ |
-----------------------------------+------------------------+-------+ |
Clock Signal | Clock buffer(FF name) | Load | |
-----------------------------------+------------------------+-------+ |
gclk_i | BUFGP | 189 | |
Inst_spi_master_port/spi_clk_reg | BUFG | 28 | |
-----------------------------------+------------------------+-------+ |
|
Asynchronous Control Signals Information: |
---------------------------------------- |
No asynchronous control signals found in this design |
|
Timing Summary: |
--------------- |
Speed Grade: -2 |
|
Minimum period: 5.283ns (Maximum Frequency: 189.286MHz) |
Minimum input arrival time before clock: 2.083ns |
Maximum output required time after clock: 7.830ns |
Maximum combinational path delay: No path found |
|
Timing Details: |
--------------- |
All values displayed in nanoseconds (ns) |
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'gclk_i' |
Clock period: 5.283ns (frequency: 189.286MHz) |
Total number of paths / destination ports: 1727 / 266 |
------------------------------------------------------------------------- |
Delay: 5.283ns (Levels of Logic = 4) |
Source: sw_reg_5 (FF) |
Destination: btn_reg_0 (FF) |
Source Clock: gclk_i rising |
Destination Clock: gclk_i rising |
|
Data Path: sw_reg_5 to btn_reg_0 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDE:C->Q 3 0.525 1.196 sw_reg_5 (sw_reg_5) |
LUT6:I1->O 2 0.254 0.834 _n038082 (_n038081) |
LUT6:I4->O 3 0.250 0.766 _n038083 (_n0380) |
LUT5:I4->O 6 0.254 0.876 _n0418_inv1_rstpot (_n0418_inv1_rstpot) |
LUT3:I2->O 1 0.254 0.000 btn_reg_0_dpot (btn_reg_0_dpot) |
FDE:D 0.074 btn_reg_0 |
---------------------------------------- |
Total 5.283ns (1.611ns logic, 3.672ns route) |
(30.5% logic, 69.5% route) |
|
========================================================================= |
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg' |
Clock period: 4.344ns (frequency: 230.203MHz) |
Total number of paths / destination ports: 214 / 36 |
------------------------------------------------------------------------- |
Delay: 2.172ns (Levels of Logic = 2) |
Source: Inst_spi_slave_port/state_reg_1_1 (FF) |
Destination: Inst_spi_slave_port/tx_bit_reg (FF) |
Source Clock: Inst_spi_master_port/spi_clk_reg rising |
Destination Clock: Inst_spi_master_port/spi_clk_reg falling |
|
Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 2 0.525 1.156 Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1) |
LUT6:I1->O 1 0.254 0.000 Inst_spi_slave_port/tx_bit_next3_F (N14) |
MUXF7:I0->O 1 0.163 0.000 Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next) |
FD_1:D 0.074 Inst_spi_slave_port/tx_bit_reg |
---------------------------------------- |
Total 2.172ns (1.016ns logic, 1.156ns route) |
(46.8% logic, 53.2% route) |
|
========================================================================= |
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i' |
Total number of paths / destination ports: 14 / 14 |
------------------------------------------------------------------------- |
Offset: 2.083ns (Levels of Logic = 1) |
Source: sw_i<7> (PAD) |
Destination: Inst_sw_debouncer/reg_A_7 (FF) |
Destination Clock: gclk_i rising |
|
Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7 |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
IBUF:I->O 1 1.328 0.681 sw_i_7_IBUF (sw_i_7_IBUF) |
FD:D 0.074 Inst_sw_debouncer/reg_A_7 |
---------------------------------------- |
Total 2.083ns (1.402ns logic, 0.681ns route) |
(67.3% logic, 32.7% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i' |
Total number of paths / destination ports: 41 / 31 |
------------------------------------------------------------------------- |
Offset: 7.663ns (Levels of Logic = 4) |
Source: Inst_spi_master_port/ssel_ena_reg (FF) |
Destination: spi_miso_o (PAD) |
Source Clock: gclk_i rising |
|
Data Path: Inst_spi_master_port/ssel_ena_reg to spi_miso_o |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDE:C->Q 5 0.525 1.271 Inst_spi_master_port/ssel_ena_reg (Inst_spi_master_port/ssel_ena_reg) |
LUT5:I0->O 1 0.254 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1) |
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2) |
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF) |
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o) |
---------------------------------------- |
Total 7.663ns (4.195ns logic, 3.468ns route) |
(54.7% logic, 45.3% route) |
|
========================================================================= |
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg' |
Total number of paths / destination ports: 25 / 14 |
------------------------------------------------------------------------- |
Offset: 7.830ns (Levels of Logic = 4) |
Source: Inst_spi_slave_port/state_reg_0 (FF) |
Destination: spi_miso_o (PAD) |
Source Clock: Inst_spi_master_port/spi_clk_reg rising |
|
Data Path: Inst_spi_slave_port/state_reg_0 to spi_miso_o |
Gate Net |
Cell:in->out fanout Delay Delay Logical Name (Net Name) |
---------------------------------------- ------------ |
FDC:C->Q 22 0.525 1.442 Inst_spi_slave_port/state_reg_0 (Inst_spi_slave_port/state_reg_0) |
LUT5:I3->O 1 0.250 0.682 Inst_spi_slave_port/spi_miso_o2 (Inst_spi_slave_port/spi_miso_o1) |
LUT6:I5->O 2 0.254 0.834 Inst_spi_slave_port/spi_miso_o3 (Inst_spi_slave_port/spi_miso_o2) |
LUT3:I1->O 1 0.250 0.681 Inst_spi_slave_port/spi_miso_o4 (spi_miso_o_OBUF) |
OBUF:I->O 2.912 spi_miso_o_OBUF (spi_miso_o) |
---------------------------------------- |
Total 7.830ns (4.191ns logic, 3.639ns route) |
(53.5% logic, 46.5% route) |
|
========================================================================= |
|
Cross Clock Domains Report: |
-------------------------- |
|
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg |
--------------------------------+---------+---------+---------+---------+ |
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
--------------------------------+---------+---------+---------+---------+ |
Inst_spi_master_port/spi_clk_reg| 3.706| | 2.262| | |
gclk_i | 4.633| | 2.169| | |
--------------------------------+---------+---------+---------+---------+ |
|
Clock to Setup on destination clock gclk_i |
--------------------------------+---------+---------+---------+---------+ |
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| |
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| |
--------------------------------+---------+---------+---------+---------+ |
Inst_spi_master_port/spi_clk_reg| 4.416| 3.782| | | |
gclk_i | 5.283| | | | |
--------------------------------+---------+---------+---------+---------+ |
|
========================================================================= |
|
|
Total REAL time to Xst completion: 8.00 secs |
Total CPU time to Xst completion: 7.33 secs |
|
--> |
|
Total memory usage is 178696 kilobytes |
|
Number of errors : 0 ( 0 filtered) |
Number of warnings : 29 ( 0 filtered) |
Number of infos : 22 ( 0 filtered) |
|
/syn/spi_master_atlys_top.xst
0,0 → 1,51
set -tmpdir "xst/projnav.tmp" |
set -xsthdpdir "xst" |
run |
-ifn spi_master_atlys_top.prj |
-ifmt mixed |
-ofn spi_master_atlys_top |
-ofmt NGC |
-p xc6slx45-2-csg324 |
-top spi_master_atlys_top |
-opt_mode Speed |
-opt_level 2 |
-power NO |
-iuc NO |
-keep_hierarchy No |
-netlist_hierarchy As_Optimized |
-rtlview Yes |
-glob_opt AllClockNets |
-read_cores YES |
-write_timing_constraints NO |
-cross_clock_analysis NO |
-hierarchy_separator / |
-bus_delimiter <> |
-case Maintain |
-slice_utilization_ratio 100 |
-bram_utilization_ratio 100 |
-dsp_utilization_ratio 100 |
-lc Area |
-reduce_control_sets Auto |
-fsm_extract YES -fsm_encoding Gray |
-safe_implementation No |
-fsm_style LUT |
-ram_extract No |
-rom_extract No |
-shreg_extract NO |
-auto_bram_packing NO |
-resource_sharing YES |
-async_to_sync NO |
-shreg_min_size 2 |
-use_dsp48 Auto |
-iobuf YES |
-max_fanout 100000 |
-bufg 16 |
-register_duplication YES |
-register_balancing No |
-optimize_primitives NO |
-use_clock_enable Auto |
-use_sync_set Auto |
-use_sync_reset Auto |
-iob Auto |
-equivalent_register_removal YES |
-slice_utilization_ratio_maxmargin 5 |
/syn/spi_master_atlys_top_guide.ncd
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII |
XILINX-XDM V1.6 |
###3956:XlxV32DM 3fe8 f5ceNqdWm1v4jgX/SvRaj8ubfyapFlVIpB20FDoAp2n/RTREDpoKbBAZzra/fHPdYghJontVmrA957jY99rJ7ZDf+c+/xe54e+j7Mdit1ivrhx0QZ3fcdjCKA1b2T9vix/TZbbaJ9vsZbHbZ1sovK7B9xy2Xpbr5+kyWW/2QdharPa7/a9lhjA5Gc5ilzmtjfOe8t3ynbJWunshmLaw0/rptJbrl0Uqqjvr+dxprZfO98XLd6f1njkrp7V3EBT3juu0jm3P3jbLRTrdQ08PdbYOdUr9cKbbbOrouu1Azdbr3oEezLL9dLF0WovtQWtTfC/TQmaz/pkVvrWz2yyS12kuNd0vf+2S/XoDjs3FKp3VgherlwZgk84dkaQtfCzTaXhKBDhexcd6ycND82BstoiFtTmAYdp7gEEu1YyfpRLipZ8JINUH8J7Nwsvo4eb27uExecRPRDUpCy/v213kHb5cUhQwlQUmC7woEMkhksM8WfBlISgK3JUF2QTHsiB1uNThUodLHV/W8mUtX9byZS1f9tCXPfSljn/Ukf0JZH8CWSuQtQJZKyhqYRfJApYFIgtUFpgscFnwZOGoU7SOkSsLUhlJZSSVkVRGUhlJZSR1sCwQKcikIJOCTFZnsrocFCzHAnPMD4WipzC0slBwCXUPFEqKbwoTaNzvdeLkEflP2FVMoqIUnUzsKqgwmWrykolUMlLJREX5EyaKSWhaNoMS6D0hXzVVtByQMHFaNstcX1VSc4HVXAizHECg1g3UumBixSRINc9QqpqlhoirNARmWRlMcmaqdWkprQQpnQRTqYue6JlZrouVNBPyhJhqllF6btJyCEyty9RecTVerkrxczJVUVZGYWp4qumrZqCYWK2r5NlTG/LUhtSJJMxAMbFKxkg1sWpS1eSKqQyZOuuEiVTzjExVkysmUeueNcRUlJdQ6irtUnWKUnWKUnUSUqz0Spi+apYySYlKJioKTw1XMamKMhUtR0TVAaW+KuUryaGQHPf0UPEhGSh0UYhIiC5c2EUgfDV8mNw/TK5mzy/J+k+ErtxrEpILJD6ATOHxTSXnNdntp/sMeARoZWSnIM8h+8P9A9aUP2jATwZzXWkEZSQQCMIhv+oNhNjzfpUs/mSiCRT6hXP3E3ye8BHwFc0usxk0mXvpyfuazNY17t3J/RwGecskbzls03nYdtLpdvvLSb9PFysHotnuF6sX5+di/71AXt/end96q90+ER2cZc/rt1WabS/vUijsk/SwuUzSX3+617/R7EOKEJ1BEIdtSFEbw0XgonAxuDhcPRq2YYsFpb/gekRhhMMIyBGQIyBHQI6AHAE56rEw6g87X73D1+MT7Paju9tR0p5MRr3oYRKPQwoeoRf9FYRi/5Zv4gTvodfvJpP26DaGj84XHzzjpDe4GQL3MQ2jbLlz3AsCG/VhlltXomYiPp4Pdqc9Gj3R6cG4uUnGo6L8pT3qwkTOy71hlPSgB1nJHIDI/GTDmIIjODj6DxN2KnLR06KcDEfJXXzH/YMH9hRFP0bxLbRdNDCO+yLeBKZbB4cdSF0HUteB1HUgdR1IXUeIdtrd5Fsv/l/yLR6Ne8MBC/NoAI3h6hG4BlD4Kup9/a/fnnS+iPZvbiDQq/GoN+hNii/3avw06OQpv2qL4n//Qe3+Vxp2oCNQHJIAPu7uepNJ3J1CcTyBvEf9GBgQOjTwlxd2RnEbYDAeedh5EsKzsLN+3RwHYXow81EIijJkLy2K+WOhr1h3igVzCeRhPw5fcEFgXUhIFxLShbnUhZC7PVd8IPGBxQehYTefPF2YjF2YFPHNzXA0SfrxN9FU/DgZtZODbxbe9odRu5/0h7e9jgv3qmInm2n6N4wJq3W7Df4mPm7wkwY/bfCz+m7iejepd9N6d4M2r3d79W6/3h2o2UYwnxX7AjKKKq46H6rx4RofqTZR0yquumoq0qqLzc88+NxBzh303MEqsiw45/AKh7tVVzUyXo2MVyPj1ch4tVe8phNe1eVXXZVwqtW8ajheNRyvGo5XDcerhuNVw/Gq4Xg1/aqG41XCqXL8ajh+NRy/Go5fDcevhuNXw/Gr4fjVcPyarlbCCSqcoBpOUA0nqIYTVMMJquEE1XCCajhBNZygGk4QoLCHw54L18APYaG5FKt4cCiJBXyaFw9rt5eXxSkfSuN4ItbpKB4l+bYkiXqDbm9we1n3uumyB6vhl148EnuQp6Tdvx12hoNxgjENBXTcyST3YqEeT+LBJLkfDe+TMQADsZMRtKKJZPJ0HyM/bBKFxU+Fcj7Pnb3BJB4NIAP3/WTUHtzGsIMR/sGwGx94h8qj+CYexQPYg4v9AyyWNdtI7IWWm0tbJrJmYmsmsWZSayazZvJr7Fswl297kabMmgoD+S1xrbTf11uhbUtF9lRsTyX2VGpPZfZUbk/1rvGzNTXZ7q2G7ciGP5TWVRhlu7elGFstjPQw1sNED1M9zPQw18PeNZzza+AiQyJwLQ4T09XjIrVaCWyQwGYJYpAgZglqkKBmCWaQYGYJbpDg140zVc5pVw8jPYz1MNHDVA8zPcz1sIdqHwACaotnKdah8nilkUBaCXQtT4YaCayVwNfyNKeRIFoJci1PfhoJeGBoUHheTBtRmD0aEOlArAOJDqQ6kDXHEmlHPTqOulYCaSXkqHOdBNZKyFH3dBJEKyFH3ddJ6EY90o56pBv1SDfqkW7UI92oR7pRjxJW/5gU4DrfaulxZMBhxKgelze7VoYYZMjxsaOVoQYZKntjRyN2NEOKmaFTzK5TkobtaNSO1rBSFLSmJVDCSA9jPUz0MNXDDLEDXDqRbtbb/SXm9f673XdRd7aANfCfZJ10TcR18mO6XMySrhzfc2K63mZJuvxbproJl7dAVk/Le5RvEPUEZCJgE4GYCNREYCYCNxFO++R6Asw5PY4MODbgxIBTA84MODfgHpprcDEz20ZGZGR0MTIwoC84MHPk6/0PcJGhd6LlhpsXbrrnt/k8/3cwcUvY8ZAlD1vyiCWPWvKYJY9b8rzrpkeOwktcOxqyo2E7GrGjUTsas6NxO5qnoe2309WuIMo3JAaaXP/njezDCtJuWmpODHnrmKQio1Qkt0omqS4mBkZ+UzfpbN+T50V+oGzq0okhdzhuPXEHYLaa5lqekWJYTnffDc+OI0EeJ/RCyCSEjocKvRA2CcnNcmAQal7GCwI1tUQtY2cmIWYZOzcJccvYm7cPB0Lz9qHAkQHHBpwYcGrAmQHnBtxrutuEjd+TNEvwRZv1HyZmIjkQCTMRX7JVstmu0wuxm01X+4tOXs//aD3YR1xEn62Kit5+oiq+6H62Kvl8rLSI1ftwVfzpmnJIP16TFjn6eE1WpOjjNfmn4wwObTauKGALqmarWaLk/xDVtGHe7bLlcXVq4uT/bFcsO76ZI9dDayqxpzJzJ5FFJ9HxfYM1lZhbxhYtY/v04OPbDmPLxKJlYh/z8f2xPZU3TlZJhQ27kYLMFGymkKZd3c9tIvqq2dWdGHIPETQRs1VTTwQm93GlLfluOf2RFa9xWK27+hZHz6t9iVPind6taHHv+ONfLX56E1YPK/usc/hw5DcQIhOhW051HUFs5bUaZ8/KWsLZq8pz3vnp3YaG7GjYjkbsaNSOxuxo3I4Gx3ZipsFDwIaFrFjYikWsWNSKxaxY3IrlNbOU0/rUhlVzbFTJxUncRIhMhK78BaqJoLsXYZe/yt7zH17mBoKy3NYzkhsLzm3DXX/iyAf9rImnvd3PztvUjsb0rSFDa+ha/6g6o3F9a/hajxNDb06/NmtlqEGG2uWGGWSYXdDcELRnaMY7/vaXamin35jqYUNtrIeJHqZ6mOlhroe9hhVZOSx4Roqcx7ZMbM0k1kxqDAWZQzmdKExi2CyGrfNy/GcRY7PE3CyxTjI5/o/KXM+EG2Ae/h9ATwxm###5648:XlxV32DM 3fff 15f8eNqNW2tz2ziy/Sv7MYnrOsSTZLjrGpGUHVWsx5XkjFNbWyjZkjO+69guU7OTrXLlt98G0CAIiYI1ldin+zT6ATQBUMqMHputap7vVfOw+s9GPT+9bD8229V2o1423xUhd8UoakHftGAHLLY/1c39Vj1ufm5p8pYFo/RNE3V+jNEF2cSMIGMq3jBQz6vbfytxwNFfL0rThx15A+uIkOyA3ebxwNxpyg12Nf+l1pubpz8fbzcvH6nsUY5vAWzV7aMt4va/f0/OjjQkxxrSYw3ZsYb8WENxrKE8o+nbhg9/bvX8rI+1VKPJV5Uc4/nn04v2fKQlOdqSHm3JjrbkR1uKoy3l0ZbpGV0da6letscsVmsMf8hNj/180/z5oBc0xpIoS6Msi7I8yoooK6NsekZue1icGF1wjIaK76K0ns+YAxp3QN90wOIO2JsOeNwBf9OBiDsQbzqQcQfy7FBTuu5NoiyJsjTKsijLo6yIsjLKpqTvCdfMQLfkYZLESBojWYyEDY9ESHformM2sIiHA4hYAIEBaCSAeCOAjAWQGIBFAsg3AqSxACkG4JEAZv8l+SEeuvwwRyIcjXAswvEIJyKcjHCH+7qM9XUZ6+sy1tdlrK9LvfmtI2RsxUu98a0jZHywjA2WbwxOY4PjfVRG+qiM9FEZ6aMy0kdlpI/KSB+VkT4qoY9uD3BP5toZpUmcpnGaxWkep0WclnE67b/KIH3gHHQsibI0yrIoy6OsiLIyyqayuJwO6mGdFpdXS/FxQBygDjAHuAPCAOmMpTOWzlg6Y9kxloQV48FMVeP6cjQZqulsOZpOFiujHE/rq8vh2uDlaDxcLAfj2Y0Rvw7nCzCEwatnUsDvCUn0D6J/UP2D6R9c/xC0mGTwN0+LyXD5+3T+hRRTUUxPebKmxTSBv/DiOoUX9imDv2A+layYXi3zYsbU7HJQDWuStNjlKIvZoPoyrBn8ron+Od8tg4hiVi9UeTmtvqiLSa3K0aQeTS7gGevVq/nwXHtqORNwPJws7zrKq8XgYhi4/lpVva47euN6d4wOPb6YQzNofT2dLFU1Hw6WQ3U1uVoMazUbTRY2NMycmsOcgKvbVrH8NhuurHRRq1FtTWf12K0PzKvRjCZqsFiMLiYKFg/T0Mrh9XI4gUYznoh1/HU0/D2YlK/DymRPPK3DLb5Nqu6QbrFuiOjQNiM1mFefcY4D/fwcKvmiqul4thxc3Fg8WSyhTwnXUj00BUwuxmoxvZpXQ6s+nw8uFmo5VeXwUl2OFnqpvmirTseCQvfK8vP8imTF7FKVMMtfBuXlUFWD+fwbvK/PIEzeR8Gcz2wKL0/bp+rpxzNhpwMBaZ1OxY667FdXTi1C9bfRZLSEmYYntld/mhxkyE6Iui8y78+T9+fJfZ60o5an5dX5xelUP4FOSdnpaHx13bVD1aneAfaVSa+235b2almvlvelQPuUrE/ZO1z0KWWfMu1TZn3KvDvTTgmdRYr/pcUCdsAFjFrADrhgebG4HFXDS9jIPexouYfi1sNLvV06SXpCArFqpfPz1qjkrZFpBy8FQ8rOkMpnVFEPfUaVz6gKMqp8RpV2v24l/YzxNlp1fg595gTX7a2b2idQ+wRqPzu1z6X2udRBLrXPpQ5Krc/P27zO0xKWCA3HwTSO9TS2TBkwZYepAqbqMHXA1O0MX/s1B0g9ZB5yD8WNh63366AXrn0vXAdFXHd64fpj6cOWPmzpw5Y+bOnDlt2wZRC29GHLIGzZCVv5sJUPW/mwlQ9b+bBVN2wVhK182CoIW3XC1j5s7cPWPmztw9Y+bN0NWwdhax+2DsLC2sIzPYe2mlfq82g416fft7RY/LF63qjEAbIplu3FQB/Fd0bGE8+czXxXA9eQ4Rx2Dav+CuHMGQdXk7tQN4enrasYwxPWkRezobleLfFKMBrPIPfR0npZBneJpTu0TQKXo3JBi9+HpLheFdf1Z5v/IjMYMq2sdvF5MBuiVo+7Mcg5XRfXI7iyXf/PdV3+LTklf1ssrywYLKrRSBbX6xs1WsOg9Q9V3j+u7x+/Q7ZaGq/+7+nl6+aluX96dKr7R68qvmXFv/4J91Kqkk2L7GfzyHDF7lqEn+doiiY53P4NIoliqUVMsdyiVHFuECWKWx0VSqAuV8LqGFPS6liqpNVxolKr41RlyV2L8JskSwmVUYtyldnwgqnc6kSq8jTXSBJFEmphDu86iYZMQykMTJkiqdVmoM2YgXmqSG60PAEPObeQAswsFIomaJADNM44TAC1ITjMACVWC1NAqdXCHMA8WAjDmNVCxZQzC8GA2xBQDhU2MFRB9XuvhmBgU+dQBRSloYRhsAYWwsLYKiR4YFlqYQpLYzxIcMZyYSEMy60HcMYTOwymhCd2WA6rR80SILTNAc3kNfYzOGvOQWNgCuVxW0iagT+bRqqH2MlMc6Ebw0LoBxs7S1KAJqOMJ0rAShkIrcOsNqNKSGubZQCNNqcMOgqhVDJhRAKGh/U/9y/b2ah8+gkOEiVlAhfyfsJWxovVy2aVFTfbR3X/9+TMIdIi2iLWIt4icXZrkX6O4F7oJBJINJBYIPFAEkZaGQm/eCAdwU5+6nnS5Qnymedpl6fI555nZ7CLeQGf+MQb8K4D9xGv9Lzo8v4T2n0dNASqVOIh8ZB6yDzkHgpR3D5sVi+39hd+VpsWtz/WD/ePG1ncNt8ZPE3F+ua7eoLZyhGRDtQLi7BFtEWsRbxFokWyRWmLshbl0AoGQStMYRHXKJEdkRjR2YYSDSQWSDyQRCDJQEoDKQuk3Eiy+H778G91f4u/lX6lmcGqdcWP+ie0R6DT7XnBiz/uv//BivtmkxUPm7WZbYdIi2iLWIt4i0SLZItSmEODcA6dRAKJBhILJB5IIpBkINlZutFSg49XRyBdgXYF1hV4VxBdQXaF9GzVCirpYNLBtINZB/MOFh0sOziFYH9u4eiDvZdkToA9WX+gZwQG+y8VKHC9lTszCYc3y1HQhwFnTtCbunOdgQNBUcglCDgGAikukSE8g91f/8OLjuR2hR4ld8MgVOZ8CH2CCGduJXzcnQXEzyQKEuLniRPAee7MUjigciyAwI1CJG1mVgq9QlIiwST0jUckOEdU6BMJzajUJ5VwgmacWQoMxxlnBBg3RwwuBcLNEYNihcQxTLtOHQOHtUjRtT5shSuSwzknMvTG4d4mcuoEOBdzN4ZzfddCQcBJ5+rRxcpEOoGCkDoBbmVJhhODkv8HNHtK2qdkzhcHHaYp4H4kiYtPISTBNAWDZFyfCjj5petTuAGBgF0hRAaCSxP6VDJcZhgMAnMCjGE4RsKsSeaaB6WwmkDpfMACSYbTI/UVwT0SAODSilXA7RUErELfskCBgoSLiMAqZCpAcBllMCcC7qwgUH3pvGsR5rWrYLsKsauQ1lueKIoIngFEzJlr1N7hjQISuWsRriZSQp/QgJi+3+Zw42uxm7w9Fd1XsX2VsG4JvFBwZA1Gt8jCzdQZSgWPQeJxGKyj4vsqaX3AQ5mmyBocBIOV0pdnA1Moe6Uh3IbhqM4QS8Coh9Rgv7EYth14lC3W7wzc2sBuAC8YHLF+2YAdsCNgupaHdxsicRx0E0mZxYIDlhbDDkMwLwHZkszGhH0CMNqkMDZDG+gwkqMfuCaTPLU41y8zaAP50sTmABdmwDliWCqCeqiVEtSb1xjUUxhLUQ/vcJShHlaRMoEYxjKJWAK2OcCjAxjHQr3wvmcfQxRwZdAJPP3w8mex0O9GqIeJpxydS/2ilCAGe2EL188cvAlanOk3KLTJIHlcHAmPBJV2kVPYA2nK7UKhgMkgD7apcLwRunxGoYspjkch5KGnqXC8EbCVDZ+btkUMi8/SFHEGr3HWR65f3nDxc+hVhoufp/rVO0EMb4C5rS/P9BuerS/XL18JjoXFh6bOix9q/YR3Y4TEQ+oh85B7KDyUHqZna4TtzRdFEoo0FFko8lAUoShD0V1xfyj7b2l1SV2JBBINJHjnSbyIOQcqsq+i+yqbP+Gg+usFtOYidr4Yq/PzNSG3vWpsEH3aHaZZlBVRVkbZrD9b2p8txWwP5EPdxhxjeZQVUTaNslmUzfsrPVCK+6irfx4cm8RpHvUdjxwfK6NsGmUPLPmBgG4Hi7I0yrIoK6NsTopHVjzd3dHiCcDz6mVdNPqJJ/iGFogkFGkoslDkoShCUYaifg/1okoCiQQSDSQWSDyQRCDJQEoxPA3rpGGdNKyThnXSsE4a1knDOmlYJw3qpEGdNKiTBnXSoE4a1EmDOmlQJwvrZGGdLKyThXWysE4W1snCOllYJwvqZEGdLKiTBXWyoE4W1MmCOq0Ed+nGH7WNP2obf9Q2/qht/FHb+KO28Udt44/aJjxqm/CobcKjtgmP2iY8apvwqG3Co7bpHrWwizTqZb13zN30qt0u0juI9g9qj5PeQax/kNt79eR3bwJNcBNogptAE94Emv2bQLN/E2j2bwLN/k2g6bsJ3PSqu1PUcyD3DqJ+d24i53GvS9Y/iPkt/TDLsqKBvXi7eoTXR/1/26zvjdUP/fk03dWol+2OFdmzIj1WdM+K9lixPSvWY8XPdhRiVyF3FenZJlDo78gCmezIdEdmOzLfkcWOLHfkNEiogZncUZAww2Ynw8Z2Eyh+rJrt5kWttg//bdT26Vk/Hj1qUDyfPn7/sbLsfQOP+10Hm65G8qm5b0mD8dNTrXixTUNYV3KtmhtlA/hp42HHddNsHpxri/Fu3yrAmx1q/s8uM1lE7ijai7XoJcS+HvJ8ftqStF+vzg8yFzvJNLu+G1d7v57v6/tzaQ7m0jIXQPxlvrlCQBygDjAHuAPCAelAenZjAH6LhQLpCrQrsK7Au4LoCrIrpEbItYDfbCUetx8VoYZ0WPe1Fm9Z2mGp/34JNazDuq+0ZMvyDuu+z8pbVnRY981V1rJSf9nV4k6H/4W3DE+n7XdpGaqUR6RFtEWsRbxFokWyRWlW/LyVzcNPLti6eK3no6/DwXI5L6fXnwj9tLgc/g4/pvDjajEbTupPbLEcLIevr1P4PakH8/rT5ddqPF1QwZLi9XKwrD6r6Rx2+0/wZzHX/8QIfyWf9D9pVNr7p4GGr6/07vghdsRbQch+EMZhyNVSDxgPx5/mA/N3PK2HMOaSyNep/EfyM9n575WS4vXN/JOIjU/4dSr+8e7drwH5AD/oya+BeP/+5J0WjfxuQD8Y3YcBe//+/Stf7QzhH94NhAbsZEDBwg/eZYDgWhQnxtUBZ7/sGGrj7XjT6djR1plJGJ1BV7XOqDb+bcCNHQjvrFvjBuxPDANVfRgQPZSuDg/V+epxEIiYOKQTh32AysCOGUemZRylsyPOBbNz2KZNUH6FgzUYwcwoS7r5YnoOTuz4V5rtDsAFA+GdiUPfn6DvMBtTCFr4EeK3X2ZCqJnCTj/o6TJrT96bGT/BxaThbFAWDPllKuDtgguzjK+wqVsrvZjW5DebJGEtc9Iue0eL06eNd7XcatdeCfIrbUNBps7KVwvuP2Dq7UCzioEoOsts5t90BUwGD3M2Lfjh107OTiv2tNgHPpZpx1fi+s/1PraMjZYjib2Jbgy36VDGUcf25B028gnm5zmGC6kXyqzC5v8BrYHhQg==###4796:XlxV32DM 3fff 12a4eNrNWltv5bYR/jN+sH1exKtuMLBGgyIF0gbtBn3IgwGRFIF9iVsELVr4+Pz2Di8jUhSlrDZZpFnY0hlxhvN9Q34cHWe8Xr8XT/e3Z/74TB+upBsXw+X+mcCPuDyzh4eHaxueNHhDrnHsM1/uxLUPd+CebsWVMncvn+4h5IcbTPQIdwzuONw9i8dn6Wag/HAU3NSGcT+Mwh1bDZM9Drs9k0f3m/rfDAbxR8jq4QHQMW/jSxaX5eGD/wA++eNghHDP1DlfYHY3V9dU5gozXXysECnM7uPBFI8h0QsOdFTf4iQ4zV4kmNrHwUwfroztp3BLnjgl8XdXKXe8XH4eXPDiZUY8pLrgEiubeIzZIZqrWFcjsXGPUzl4WAKXtojkxnlvjvHg4wdDsWP4K5dFbF+ae6wkkrrEeYwzF88hEF8FyiiMhJQr4BbrELZJBHvlUx4GMl2Y44ninL8QJVXfL0K/62C1r4PxHIbH4SFEJpjNB7tw5TLyG11ka5tdlqVVLqN8v6TtcluGLwvq2vYVr9W+waI+LrVIKwA3xGXZgJhh/Wm2GffndgtSLguXpU/l3H6tSr/YLkW6lacpjGdrPfd6e+dII83ZMrnSrFZhNX5wpXy8pT2w2KLwzSuP1TypNmmOHYfLVnce0aFfOWCpL5VdsFqYLBO0mp6tiOKP9xlZKINY2rh5c6LmtS9brSq+2T5X3q0ckuAE9ZBBPZY17CKQSxCYMPWyuq5MVEIVCznYQ4Bb3LWsKfxomfQN9SNK+JWpwoUVpwTOk1G0COyqGjxqTlAbkqp2cYeqG4ybfGFme8xm52zSGxjmFShneztsu/vdMHE4bNHglNui97gNYt2c4JBlVOZ+NWj002aDhEs5bNx0EsG2dm5hXaBIOjG934jl6vBbhpTiCSuvqcVOS4+npXe5X3GAB/mVTcchRAzB8xC32IcsJ+HGedv3rE+BIgsudgIlRaCPaUNi1LBuL5WupIxzi81TLo/IdbYGci8WT7+Y+pXSzahse8RdRbvtIMw8FDKdtLQ6NDsAf2nQBxzEjgbhhifzdlRWpN0By6qsD7jkAyrow7N0/KRHaaUg0fkOyDb62mOVdHaGrIZdKhWE/GpJ5CxdaVMfcVva2iuZKkNiPpkG4EMwX8kGihud2vjNG8PeO8LeG8TSsJQNhzsXl2fIcdY7HqaQ2o/LffH+sH269C2bFIIaXrLeKB+aVsbqleBSvIFkJ/eVmo1HaD2rnQ+Ml/n41WFwqR8G/uBzb3n+ZItbLR5B6bBdSd1l1bKuEs7WcqruDeUg64eWpZXXLkZJi2h1hl0Te8FyjXvwWV6JU9Xrnz7+8PyXb57/9s3w3d//8OfvP1Lx/uHDP0jfkPHDh/8IbYY/DmIgbx9JQwZG+4Ex+MioMUYNzBD+9hObwTLCRQ5yvGMzG9hMx/eP1lQcKBk/MtIPQpihye1ydA6lWYg9s3G5gW2g+7lBNobCHRvvwCIUhyxpO/CZMya1gcdUejPcdM4bbkQ7CD2P//6BMQvR3T/azMdz9IMi41+ZoEDUO1wbd71j3AyKjneWuccwDOcyYpDN7G74wLm/aT2Doo+5Qcb/ZYIDkZ27Yf7mO8bmgb3dEaCPSzX+ZGfwgo8TJDaN798yZmAQFYN5u+MwOcChQJ2GCQZO1XgH00n41IZPHTyDiwwXEy4qXHS4TH6iO9LAx2m8m4dpdvMIMv7IzATUk4YPZh7AxnuYm5OBh7ntxhlIYuO7cmUDJu3Q64FI+/ZPxtsRfrERYnTjj0YP3ZtSg5oGpQc1DwpY5IMSg2qG909idlX/lplu/BfjFmozjmDUNaOqGaeasa8Zu5qxrRnl1sgZqRmbipHamnGuGU3NWMHO5TbPV97ympHVjLRmJDVjUzFKWzPONeMW0avoRc3Ia0ZWM9KakdSMleRFZ2vGSvKiwjwYVc041Yx9zdjVjG3NKGvGGnWsFpPVYrJaTFaLOdXcp5r7VHWvLUVRW2CitsDEVDP2NWNXM9Z2h5A1o6gZq8nX9pGo7SNeW2CmxqepUWdqK1lvYyrSgkIPZphAZ+GUBiicK1BZfyBwPgh3WkM00rTjJ+3mBzOcMK0FBdGOt/FVO6LHT4aGC/NG4599smRx6SZwsX7Qq1XhYv0g0thlVM9gFCGNf06I43tU1G8YF6p582mxjrgkXXIcDkrWhixnOb4y5tN5B2guKsudGJyfHI4U6s5TDSdjixHaLkZYw4SXpwUmYyoEpl62V9nIVTaylo3XplU2rXOaQko2/DdjOm2RTi2LpszCfEYWsszCnsgiktJUSHELqRnmLHLfQAMAW6t7Ix0k2kL70sFCaju4QhPU9nBlg/N7LydfSuMmb2Cd6LhOWLgSGq/4mceriEnJeG3jFZPt/TjW4nWKVxWvOoBhsuS2pzEbOr5OJlbAH8qrUd1nVKArKtBPpytA7LYCP4cK0Lcnd2P1+GKts3aZFYgZX/TkzP4A9GY76BasLViZb6HB6jYcpDx6L6Dbh5+TB0wangGVfhKVTwLhQGSc2eTmfnyBDe2niaHcTsqmYT4xEX1gqbrELPEeFj2a3IN7D5k8ssSUf9bis85HA6nx5i5LrNWjf+58YSpJ0jNYceOTWw2T8Y9Y9gjejZ7cEnDpOKw6x9pB4iEBdIH97xIwnksvBtGapewDsQDnRXdjqI6nkgUgL9D1h1jBGnC8WDoGwoK1D1aQ0YDMmd3Scy8q0DrDuwlqvXZrT0Wtb89pfZR1MR6JvlpE/5NtM+2vaPx8rPH13TRtNf60nlVFnpovEXn9a0T+8Mxpv0Tt599A7WvpkM4N0BW1b0HtOai3AnWHl2BQVNJJuMILHfj8ktLHNbKn8L9e2Unn98ae/Eodyeh4RkYptB0qISBKksqkRI1qo0bBc9QoVAe4CRve+YYN798wlnCLcnQ2Ny+a2uPkcJNFCmJj0rNFO0nfo3XKpF5ylPo5zzbI05Q8sjm81PcqIVkEjUmB0UwezSt612dAvNh2fRRb0qEQgwlUyktWfpSBi3VAWj81yRlZjhPCVKaYDqQnistcMXW0CpIr5hylkapm0wabrA2e/k/a4Ol8G0yV2G2DTdiBdNJf1AbL8wpJ9fRbt8HivDBSrb9SG+wW0l4bTJUEqs1AVQtXoF11cIUXMdUPzq8mjqE0v1sbTD+nDWb8fBtM9fyV2uBQASdFcLO0wVRn1qTZVHdoFtU2eApq5ryCNlLFk4fXRh/RayPVJJ8EJZtqlptrbbDMp2HeJ8qsW6q1NljkHtx76OSRJab8MwSk56wNDkXAxJwyO0vRBvsZQhtMizY4TO7aYMZjG0w1zbHiYUZ1jwlM6dQIYhCtWcr+VBQ6ibqvjpdvqpOo+1ih4c1E3RMWrDRrgz3yoPWwgso2eM7a4On3bYMZO98GU9N8rTaY0S8Qec/LV2mDff3Pqr3hX6kNpsrstsFUTaDqBH4U/FD40fDDBufzS0r/1dtgquxRG8zFZ7TBVC9KaKptMNWoUQY1yqA6uD+5hQ1v4oanWubhknKI3LxoqsHJDc8jeRfD0rNFO6lG7YTNUmmDYd9l2Xp5Mk3yyObwUm9IQlJpgxnNo3lFVzYD4sVW2Si2VC1CbLM2ODvKTGqDqW5zRrI2mGWK6UAGFeSZYrpkg1Vkiml4lMbwRTp1/1AZbRBF2qMoSlhGPuZ4YdxrF7jp9Woi8B4VWkw4OPzqFv4vqW5JNTYuKQHrWfZxTcV1GRIgeSQTI824L/tl4vefw3j29uRSgCjjk7PA4/HF/QKyeDz53ACYDuyMe6gyvAgShCp41H9CEarPEFc9D1Bl8f5oJmymVY4U/I3duEPCMh55LhA8heLJzq+cNtldikue4YUlK4loYkm6w5KY3ZLQkyUhuyXR1ZIQLInBkpC8JMIgBTAgLwllm5LE1y9CDkqCbpWS6PgNg9EHJaEMe0BWL4mz5yUJf0BblYSEPJk6KImgeyWx/amKhPmrFeFTpSJhPFRE0FgRZ8kqQmxkwA3IKxL+frhCSiNSfYh03kPanUQqd5H2VaQSkc6IVK6R9oh0LpC2JVIWkZpDpHYPaXsSabuLtKsibRGpRaTtGumESG2BtCuR8oh0PkLKmj2k8iTSbhdpW0XaRaT+q3+PtFsjja9KbsAaaV8iFRGpPURK9pCKk0j7XaSyirRHpASR9mukGpGSAulUIpUBKW8OkdI9pPwk0mkXqaginRApRaTTGqlBpLRAqkqkbURKDpGyPaTsJFK1i5RXkSpEyhCpWiOdESkrkOoSaReR0kOkfA8pPYlU7yJlVaQakXJEqtdILSLla6ShM8+R9rHFYUdIzZ4iEd8vnICq7W6LU92ofryDalCSwJJB5djiuAErqGbTzU0R6mFRDd2F2pyDava7OVWDaghCxZ1qVt0cmxeoxU6dQ+8Ayx6hxgabZ73DK/FdVoLKZFdCxZ6GOTxtgWfetBoq4DGqJKZDKeJLgE8INKZbI4YuhObEsDZ2hy5hRwx0je7tLCYU7M705CxugHuG7YkzAX1PzpLIdFm0JWn4P+I0h6T150ize6RNJ0lrd0kzx6T1a9JsskfS7EIadjqzRdLagrSuJM1E0sghafYUabbZI60/SVq3S9p8TJpdkWabZA+k2WYhDZsm2yBpXUFaX5I2x5et6Yi0tjlHGtkjrTtJ2m4vZftD0tpmTRpJ9kgaWUjD/ssSJK0vSJtK0vD7kfaQNHKONLpHWnuStN22zE7HpJE1aTTZI2l0IQ1bOWcKpE0FaaogTcZvMDg7JI3WSPsfFKUWrA==###4076:XlxV32DM 3fff fd4eNqdm8uO5KgShl9mdmdj7jhT9SolYWxLvZla9LI17364RNgQBmZIjWqqHElivt8QEQTunb0O8f7FtHktr/ePED7+/mdTpwh/8PCz/PlLSPlienv/LaR/7fr9l/DHS/k9/CHVS1sV/thDR/Lq4JeQC3R0bOEPVna0547YyeF76/t/2P63MHEk/M+XMPwVent/h7EFOwwo26PpK1pig/BZuof4k01yCZ8FS/zjO/7vnzgKn3DCx3/+Fkq9pGbvNBwp8yDYot8/IAOOZhPmoYKDMbdFkz3R1KRovifasY9FE7Vo8raDaPISzaNoEkXzRLSdisZBtH0ompwTTfVEk5Oi7R3R+LKNRZO1aOq2g2jqEm1H0RSKttei7anX+B+KJrJo7LhF+yWErERTu6UqeHjiy0FlWE7AUVHPleiZBtCeO64hQ24fkcIQIuVXtNxIv8Vhsx6xQbhdsAuZUO1BUSWg+hHqqjuoJ5sjTfdvksqWa8ntI2kYQSYNloKUqwNIQ4Oa9KSkKpPyZUhqeqTLJOnZJWVN0hNJDZKeNemJpKYmXRdKqoGUDUl70/c450jT/dukS4s0tU+kOHuDpSTVC5KS2bsySmqAVA5J1x7p5DpN92+SirNJypB0RVJWkzIkXQkpp6QWSNWQ1PVI90lS3iU9mqQcSR2S8pqUI6kjpIKSrplUjJ/p1iP1k6SiS7o3SQWSbkgqalKBpBshlZTUAen4mfoe6TZJKrukvkkqkdQjqaxJJZJ6Qqoo6Qak65B075G6SVLVJd2apApJdyRVNalC0r0mFQ9SD/mWHpGKnkc6J9ep6JIezXUqkFSgRxI1qdiAVBCPJDQl3YF0OHtFzyOdk+s03b+9KRFNUo2k6JGCpSLFeCqIRxKPdPAAUjsk7Xmkc3Kdim42eKomKWaDAj2SqLJBLtH3CuKRhKWkJ5CaIWnPI52T6zTdv03a9L2pfSJFjxQsFSmuU1F7JClpNmgW8EhiQCrV1k3x5xZqHkAbteV8c/uAGoeQUKOlQGUMFmpsUKEqmjoY2DcLPkQ9uqhzKzUPoL2p0y1UxRH1AFTFO6gHQaW5g4HdrmBD1LOLuk2idpOHc2uiCkQ9EVV0UE+CSpMHA3tUMdrOyJxKN1HdJKrsPlXeRIXsIQ4BUGUbNTSoUWlMNbBH5ecQlXVR10nUflC1TVSFqAxR66BqBKIygkqDqsFN6jFE5V1UO4naj6pLE1UjKkfUOqqq66lygkqjqsFd6j5EFV1UM4naD6usiWoQVSBqHVadRVRBUGlYNbhN9UNU2UXVk6j9uCqbqBZRJaJWcVUdC6JKgrpSVNynbkNU1UVVk6hr1y21n+qKqApR1+qpLieiKoLqKCpsVLkbououqpxEdV1U1UR1iKoR1VUeGEvNsUGFymnp3cBOlY2ryGqmiiwF71SRDzZVRc7Dbfvrc1xFVmUVGQaU7amKHC25ipzvEcUUOTf5ipayiiw5Lb0b2PTKdSianhOtd8hzLJOi7V0fcYxF07Vo4raDaOISbUfRBIq2E9EOKhrun91INO3mROse8pyTonXL16ceiqZdLZq87SCavEQ7UDSJoh1EtJOKhlvxbSjaNida95DnmBStv/UxY9G2WjR120E0dYmG2yUoZ3xFSyWaWKhouKs/hqL5OdF0T7R9TjSxdJ39OhbN16Lp2w6iaRRNLCiaBtHEQkRjVDQsEJxD0fY50UxPND8pGuuK5sai7bVohR1EM5doDEUzKBqrRQP6O1GwUGtgo0qZNL2c6JjcvuiuZz9aUye3j0QGUyJdeunfwb1AnmBISqTpaaKFUgPTQ9JeSnRM7l700X3eokmKrtVgRqSPmvRAUpIRaVo/slBpYGZI2jtNPCY3L7rvQ88mKfpDY5D0rEkxzTX1aaI09DTR4mG4HZJ2TxMn9y6m7/iam2+DTszAaWK0lKQW9y7GElJ6mmjxLHwdknZPEye3LqbvrZq7NIOex6xIympShqQrIaUlQQtlBjasfpruaeLkzsX0K4LN4qfBiqBxSMprUo6kjpDSiqCFKgMb7kdN9zRRTJL2C4Lt2YsFQYNlXiNqUiwdGVLmNbQgaLHIMPa93dNEPknarwc2K0cG64HGI6msSXE3akjtXhuShFioMbDhi2D6mEpCnlsKSEIYd3NZiDZdZf4l3z2qLCSPKNtzFgK7iPjZVZxykIVoQ15qolVUC+UKdg5fauqXKyZfC9n7VdTmMdaOR5M7vuqzk6PJ66Um8qqPeywFPFgfHmO5/vtbk281ue7Jumyewjo8WXf4BoyrT9ZXfC/EkTdg3OOp4sn68GzSrV3UydeaXPepyuaRncOn6vDA2dVPddWISg6cHa2NWygNiOHRuuseOE/OX9ctjcvm6xIOD5wdHji7ujS+4vx15MDZ0dK4hf28cEPS7oHz5GtNrlsZl83XJRweODs8cHZ1ZXzFlwhcHbTYFu+jwqBVJtUCEhF3VcbX94/fkkf1aXw/exrur31Pv06X4NmW5tU9ZuGOPGYLewiWzxfCPRjGIxe+blMvbHFZg5S2vuPINOlvs9Cf+aC/4KChpB4HGkL/V7xB+P19unKDGa3xJO5732NBdltuc+gqmNdyDx/7Sq19jAHMnbc5tfZbEtmFTetrfcnXiiJDDqT4lMg/wTkAHc/XzORrZuEhsN5D8J89BN57CNtn/QnSn+fQn/usP0n7gxVn108mSXxS8ARlfoJB4bLSFe3pgQfFy7JhBMv2hV+TTUU7g8nG4beA3/KefMxtdy/5rstSVnLjt4tJmWNHNpeTkqOZVZPS3OZyUm5xUob5E+a7wWkJCasS3Wnp83z0MZULbUN+tC3vcH3e1zxc78t9reM1u67dGa95nt3ibsbeZNL/HDmPS6+LQyMfvnsU997idXHvNVyfxb1dvGZ5CfGpleS7K0l/MlOlj32ZciUZcOnbIwxeb3SaoOwtEU9Ky/s6Ku3VfS3jtb6uWVTaZy5v72ZRaZFejopLyHeXuPoMlBNQzxD0EQWvFzoJKCegrAbNYJoIU4BWfF2XIz9yOb7rcsRnLsfD+vSVCwlqob1yRcwV9sIVsa3op3Qilyvy4Io8uCIPrsiXrmjDymJo5XWwLmVgS1YTrCy1La2xh+T6PL+t4Sm8v4/shmzRWARrjq+msMpgPUovnKwqWM/U1iJg4cgK/+Zrt7diHyLdz6eet9Ia8HZWRvlkDXh7egC+tEYvKxKeuK0Jz2cQh6MofTJzhbn04FvRdcD2GbC0Buw97RvjOEiKBrttJW83/d/9muotB/7ZctC95cA+Wg5XxuV1Nb19YS8j85XWeUjrvC4jK2ZkXtWLq7DfiyVk3kEu9tqC2BuKDZt0pcqYmEUuXJZba5flbO2ynKpdlvPosuDavCsn7ULUxGBbBM8YJRvBM8bUMPaVeF6Huwb7KIQq3/a8YhxiHp5X1hjZU9vKM9++WKXJKFtB0D4KmKoMgprc4RHU4sCuG/1mK77yHzSJSyn8RKsqrGH1h59gtbawhtXvk5td18IanU2chVlisObVn/zjatBsCrey7oUV3Ypi9rbeDiRLg/eL/kqkLnhhjY5CJutWdAyeKSzFABLnrnrtOHeh6qJsMXchqzpZnVVV6VFYl/762Mepy5Y7C/M6Ge40zJtkuPMwH6cFYwu4IF26opAhPCIoZgj+UftQZzELDJmXNNS7h2+zWDF8xmas6LNRLmPJfPUrjvRRnMVXyQ5drSDmSVJ21CuGbWniOrxj/ESVd8Sip3+UwHSZPSmijSZr2pBs6aFdz48zzj9y5LisYs+lw/ZXyM/zPzWIvjl+dn0nu+uvaAnilKspfgb96WtJxsJraOpjTdbn1RbLo7FLWXys4WMdP04JAdb1kllFcwrQ6xX7bVp38ZXrMtg4CDaurCF4hV+SReZTZAyymSbJIqXK/zjjT2BbYKg2Le34L5deTL1iFo2LG+qMai2ygGYEqgPPSgKPumeDz88Qd3wn2bMtZI9XeBCBYakMUyIXMmxZzxht1vb3v7iln3Mrk5wgy0k3aQ4n7frZgj/IgnfX8nuchOMLlf8HwagjEw==###4556:XlxV32DM 3fff 11b4eNq1W81y5KoOfpnzAObPhu6a/X2KVBmwq2ZzZpHl1Lz7RSCBjE3Sic8sErqFLRAIfZJQb/PzZ9CP6fGP0ttDifhM3036npq5kbfn85dSK9D/eB1i+gAvTb9Tv36oNT7/VTo8RFie/6iwPUyI6YM2j3mZ0ocoHtty4CgVDLS0EXb4bmGANJAvA4k1DfFQfKANB5K2DCSWGQcSNND6/LlnRj/FtBaGiyWGomPoNTFcTgw1MhRjhjqEnqGhpZj7pchzBobdmq+05m0P+GLDYhg+wkIjmH6EObLFbhylfH64+FJcLr7sRbO0VvP3Fl/1DOtumu8t/toz3Glp9GnxN7b4plv8saa7TtODoBHUNzW9bMZpsXUnSpC0Nvobi/0uLBDk7x86vZpW4y39/Xk3wjGqSVSTqOU8Z2p8pCk9f8DBSyyBj1OlD0iJe3rFZ/aBXgmF/Z4fNvSwKA9Hm/mHRga2+a20yLnPEyNPY8s69kLvSWTn8iuwuApeWR/plP2AXUrt2z7lme3EMFGXRBXwzgzrsiRWbn/stkhYWoGtxFZhq6F929e8bGubJPCMMo+0EXXNi7nteXYrTVqRsGsVVtPMN5x5zDNPf8DPt22AUdIfLIJEfmnmZQMKq62RcZitDmNomAATK9NOE4xT7nVtgXDFNa24jUzQNLEo8hRcEylPYc864DyRdSGLKe+AKtv9FixKaDO1sH6LCidUqEWMt13iPiZqOg5Ju8VjfsjH/PtfZZLOq/DM58KsRffF5J6/osvKH2Nu9gJbezkJaS54MmD9nonl2h1lMmdL+PCAIdeRUYu+txB4cBf/fbbvgo4kTLupfjm/qpD3tLMwfGrfdjjHwu/tJdjQtxiBHAWRPd+nciaImUVmpPMiTO2tzCytZN6bPSncY00yr7Q3Efcmsr3J5zoZupAF+8JO/RJiKd9FXgwvJ927G4gbbsIljuHrOycnM1AIu99iOw8Uwm632C4924Bs4/fZvkuBKgP8yy4Lm+mR6DPb/XfY/Pp80SWxVF0yQM928wesbmlnbBduTz172uDTBp82+HRV631rc+F2Zq9zNOyMSOEbuZ0CSTYcxszktIDAJDRyxbe03jomLdfwR1q+oZb7puW9Jveaq+Ng01ZzY9M0oTjwr8tUtoCotNRlCkjlG+ZEo7eNT8c7HdzueO8oePgrx1vEeXC87XTLMC8je7/fYmtH9n67xdYNNGWJd2DEVxhx/HgLT9CdxOHHO/j2/NXxhs0qULFga7F1/Hg79rTBpw0+bfDperzJH4FefryDJfrCjrfwrpEZyHnyFePMj3dgZHa8xd5ruZ6Kls/yL4HYNAIxfQsWxEDLnbrFVg603MlbbNVAy524BWJk+SZ1BLGZ6PIIYr49fw1iE4KWwFZiqy5BbELQEthKbBUHsbXN5QBiZMsncQAx3cgcxCYiTwcQs43MtNwIALEF/kjLBdryjWt5Ud2gStMyE6s9ZibW+RgsrwuFthTR5iFToHWVG7L2FDF7FjGfRi+BMstiTF0WQ/Sj13j63ZD/Ah8gyHkLsNpS+UYOsE5ZT7RkVAq8pNoZlYI0qTmVImipDaNStC0if1YlqsquRfJE0srPj2R6q/WRuC87cy74ygeS/Shy2xeyVXFqZMipZee/fPeQiYiyfYftjKp9TwtKRm7bG9mlx/bG1kOOcGdsYW47Y+ufY+sY62MBZiOmDTvaeGlFwW62AdN2VIPqjdRdPqwp2N4rmN6u82H6o9UEPWuZGSnlyHCHG6bQSDVK61Gc8KkYJWf6QaZJP4+CiaNgagQd/pZgshOspswoUrkvmPxYMD0Cr/WWYKIXzJNg4cuCDfKvTV4ujxmhprsVRaBrBKqY80CgESUPJKkPSCzzFqf2Sk0PST0zas2ObZJRgYPKjA0xliydWOEuP0yZqmZV0462hNgmGJVsuCYfAKgojazSTOyNlvXcGbXad1GFkSypFwWjUqpR6oVRKdUoNsWo4C3IzJdwXh6SZQWoTFmQ7DVIhS2GxtKwGI/PDqXUVUryMKQ5eDWirqKgdwzl+zbd+kJ+pQhmGXmBuZZVkIw8A3nj7lcmGyDHgzcl0XuSCltMEUhTvSnQcnFGRYU++dSj4tENcUfzUMDy6/A4EzweUVF+gopHMPQdGMavgiEHwYyKHRjOBzCchmDoP7VJXwOPDhVHQbuzd2xsTkddo+L6XfDQz0uUl0d5RtkCt9ySZxuCofu7mDFKU7j5ljxhiIHLd/dHvLQ/o/yIu5dJI1udFA9t41LtKaUd5XKJgemVCwwEasNATm0YSClHOR8w0LOHLzBw4hjIqQ0DdaOiNHOPDvmNCwycOAbW4Gm7wkCxXWEgUBsGcmrFQEnRq7QDDMT0r1ywtdg6joGy8UYpLUkpKaspj/krUece6B1XMdC2visMBPIFBgKZYeDOyFcYiGlwuWBrsXUMA2EqCeWS25CAkDBQIwYKjoHLIQb/FYpeH9JVCGW/or1KXvXh2wGhcn7klNMiOEroM19ncrf+kK5rOaT+nIzi9/ufGB2fTxFn65//U4bzBpbKsRt+VlkS+I2+2OIAuNY7tz5iO90uYmGJl7dEt53o3nDR5Uj0g8TbANrW7ZbE/cUnVXN4cUvitZd45xKLTzY7Hjd7H6DgGm+JHnq2uKJ+uiV66EQPjos+vbLZ+zS6cbqRrXhHPfz9A/Q8VxsApVQbVJADRWN5eor/4JVWC2IoTw8MKlCaek+xRZ7XJJgDckNKNAhAdjSbuc5GtL5WLmE8AWZ6ssKo8VubesuymnqPvu08b2zo1gR2ikFCNvKuDJkvQ7aILd6rJ+6l9dhiDUrSo9zuE7t3p5AMehHC5jx4aHQUOlShaXv2icOeqXf4+8QT4ybXQtCMDc7Y4IwNztjgjA3O2OCMDc64prYJ7OEpDut0UwNn+hweA+9WTILnvpBRPCybgctYA7goIDY0hIsGcVFxXNQFAD8PEU0rwurAc/9yGlVQGrUH2wOq/lS5pgNuhdc+aMMj7s4QZF40H8T9j9e2j6FW8tHp8oZVxYmuJHFU/XkwsuuhRi6XQc1XMSjd6rACRcVigtF4L9WGSt3XRdYI9Axr4kVL11ZRatdHogjo6/RfbJLrA/daN+pOhYVKXW/SuIJx7P/oXOE1X0XYVE3Ddstd79aLWVpxuW19BFkD7Xh/25JlU+hwp0OWqMnDTnqCHxx9CPnDG/zjProu5hreKK3DNjTzrOluOz9t8GmDTxt8mkxjDSLymC2GrGV2Fgsuob+EI0Uz8isIbkApdl6qrfU1TC13UlDv53KMmNlWbC2hKfXO2FsD11ysR70Ge1utIOessZfKPaWmS0rtGTxrim/BMqB0nqSj6kxYviKd3Uk6LVpfg+5yDwdzsDtKt7Fbunx3R70z9tZINqsd9RrsPd7aUa/G3np7h/d/pYzRbliwqCdWxmgjFixKBZGbTZ6XI3yaEZ80LxdaB4EVS/zp5/A67BR6+XLFeFU3vH58NzAqqRbr2Qct5iGeEopqZXaJGSB/MDjryQcnOFq3V0uop1csi7L9UqDrK4T5xlokPaZ6XFE8EfTEikRAXylppGoCQtGBV5Z7YpKSFvBO7zrmEsziEsJrzBWsJZgHxwo3vUws6/y6s1xELQ+D53jZA56vnOAo72Td1cmqnDLvC2qvGdxHm8uk5Cnz7i4z7346elTFw/rgYlpdpuDD9MnFdJ+LD6/l4uc+F78+v3JDrfIQl0n5cE5i719K+uqPkr5am0Fu43R0vxDtqtxx/QOUE1+jri/cu9KNIt7rcs2DDEa4JZcb5eZDeFUu/aoLdJXU1noZpCfiLbnWUY4+xFflkqM7lFcuH7S2gyTE9n253jXV4wB7nttV5EzphVtJtc/FU4NjAZ4ZqFFpF2xt89QU1WHBh2zU4TF0WigNAX01m139xszfIn+L/C3yb+X0nnisPEFMHl0mVxOuqFoMPuBsbJ3NzF6p+WpNxUaZzPLVG5t7/TkM/kSjUOtPZwJbg5b3p5opkK/5sIpqzuADTnGuU9Str9576BgYldxTrVZGrT85CYx7c0cV/XRFG+ZwFoObHzY0FVOnolpfuymJnlHJl9TKMmr9WQ6VkGYq+o5JyTeoqwvJVwqEmRYxcx7U1vGiOd1B6QelXrz2rofWeIJWObrU5tB7hFZvcl3mZdHecopG6Rc4tWiPmwTdmfgPaq44MgwtSU4tXWKPOd+fxu/Zso9mkPQHdQKmUgoJI/99DpCrhletzdSThmcqabiuV2STaopZdgKprW5RY9RRWNTjsDnGompxrWacFNPiens3KXb/pz2jUuSj+SRa3aLYQeOFAT/Rks471PmF+4mq09orZb8swOuScb+2cLqtWl+or1gRQXxfThH6gouPvL6l9/r0ORDzcrKDO6/V3rgL0E73SbWaxDtdtIvA4jB1iMOuf2fcrT0L1pwcua7u9GPjxVzXk4yKcrMCDe7e7hQlYJLiypHTp4pQyx2eV82QVOvgwmddbm1yXwNag213+vG4MtebHM4/Hv8wG3gIzs3/AbT2xyk=###5000:XlxV32DM 3fff 1370eNq1W8vS46gOfpl5AHMzdlL9Kl2FAVf1Znoxy65594OEBDK2k/8yZ5FKImwMQvp0tdoe02Mun+nPX8bah4nb829j40Mt8/MvE/PDxVR+WPeYvS4/knpk//wVbbmnkPPDqP1Z/rv2X2v4P/f/Bv77/n+C/0v5//xtDDz/+e8/TsEP/ecH/CjU5081hUK3KlW6NuEBpB92NeUCGANSGzN+KfeoGegWHmb+4KXRP3HO8l2m3GHKuIvhmYZnGM44axLDjoYdDKcyrNLeFxotkCM+k8h4lwHyBs+aYZ+2LHFaHvvy/KF2j9+w5PL9c6+bXMVVjq5ydFV5dPmUq5KhR5QNIItyffLUyRGm1EgVF8PedwWL332lwg/kWMRVrpoXr3FmHKcDWC0xuayNDsDyAUxrH6vTIdlq5qBF/sO0sIbyAf7uYnSm0cL+WM/OiVFHo4UF0eG9Gy/UIvPLB5axCGrhffmUvdq6qZ+FJ3WWBamVL0VUJjraQv5300o/1GN56Mf652/jirTb8ESNmJcq9Wpai9iaJsZhfh7UICxHNQjrUQ1CPKpB8KwG9N89n78jqsOvHQT7udkNjtYL7QyJtDPso3Y6K7TTDNpmB+10g3YKbbWDtqrjMkHbm9oi28pxyRVmWqEi/FAp0goLx+sKQ9kh6v+vIlAVB/xScaAqDIhUmbkpiFamU4Xcbiz65QfKLR7jFA4KWcZALfD4uwABtYmk0oJ6FEWmsghW9GAqi2BDBaSSCP672bXIzWMtDAosVRtJ1Sqkqh73b2JGYcrW2F2eCYTYCQYJqRMsEnIneCTsnQCSWuS9PkTNKFuVP/LkCoPo5JbTybFsqduTK8IKTLRywpUm3NQorEXq6oTzQVhVPAqrCkdhVRsKX6AnFu5OD3dlvFY7PnFOQj3coB4vjJW+MFbakdwBEw+GhyWmrGw0OEzuhsYyEG6aoE4JQ6NtYpHSwtB0BSm3dwuifadWlN40obRLQUzUTRNyj1YlLK6yViAkrgkR0m1l5oeeHvmhPUtzJGkOEiPtAdMOmLjcYeIRCucOhbEL9oZQ1OV6g7NJU/8PZ5lU/w9nmXSfFhwVNKLP36keaVrxITnVL/EsWFkWzwJJ3MWzEvwXz9rgv67o7QSI/943Uu5JKPeg0/5epwdVdmdVLt++mgtc33xlLuaTBrr0NWfOXp4YqFG3Ci6qAQrYKuhtXMfBKBDjbhDG4TrltJulafNpWolYr6e1OC5hZHPMNncCLv0CuI5AJdmm8hFWANgEkO12OLjN8wrOQLZdHtzJrr8BtnrQR2ArHDYjh8ko6PStg5vHaUkezPStg/Pjwe3MNn+aNw0H97nzisfzmseoSfGD5//TeXU/7HBebrS5ms5r/9Z5LeO0JAZGf+u81tFes4eA7tCXzuvlMS13we28fPSYzN0xfeR0/MjGSGxUXz+df8AQ1wg0evY+wIut2wWDXn6gNwwXUBQ3Kb6Ho7hyGOQfxKmPCW/GuZX8k3IphnFl3u7VOCuHZxpu3o1zWgw7Gm7ezTzpvtju3cyTZfJ6CqMXWKLC8BlMQf029D3Tt6Pvhb59d5LclnijjjY6Tcg4JWZ3NLuj2R3N7mh2R7M7mr2F5wgKuPSZ2e8a+xuLZ2a/Z/ZvuY/hqvYN+bcw/zxxf+6BvGspDhidabQwf5/w3kmMOhotC814cHvuCwXW54yc51gK7imczwkXt/LiTF1cWnGv7Zgs79XwXnfHt1jeq2t73fpYnW7B9bbdONorJg5+Jo17dWJ0ptGy11Q5EcWoo9Gy14Sc2ENfKEZrlQORqa5GayixW1u4EkGm6eyaeK+K9urs1sdakOla7mUXQaZzVlA5yHRdakSQ6UwS1BZkUnjxMxnaZs1oVNcf8j71SCt1kV48KBl68SDrRcgfcDTsxCdy4rfuxP+O1VuV+Y7l+dq3H/Mdfsh3zB0iY4W0WN1u6cLPRxe+uux6cPnN0cU/+NsFdcc4NASyifFbxsuMznUzJubkJfprLzG9CW/z4IUMKaMh/E3bnbvv3Fdzt2M2SL3P3W4VP92l+3ryF9x0HYfbYev7XRzeF9oD8hYUw+H3oHhXgtpxulkeinsj5nU7pGHEC0oGqrwL6hGRmNqQyEkqI1A9JaAmSmzHCVFl72sjlDQNJX0f62nVCiuIdDWtDTN2eEEo4tGZRhvMIPjwqKPRI9zwqKVRhh3X/Qoj06urSK8mzqPasowCIRoARjPAZAKY+BpgVtYOkowjnLgBTuKQPgV4epVIs2MizY1BtzkF3bexdqEvNebO612K1oVR9k26TtGaVxs/aYIdNEEfQm/csrnysf15PVbAlB1gZyYlb870baVoPgX1nDN/l4tWA/7tQ3JBgow9bYyc6de+9I0TrSILNQhs0b+fkPYs6mpjp0vnemo2/VCfqvwGXZ02VF9ynlVM/XqRCrTi8u4sq6TE1b3WFMm3watBL3dZc1IxiLsGZ5m20MEwkycHPzoOWZM7uXkwKm6CyhBjTRRUhhYVxcQ9TW4WQW0eTPSC2qEkHHyVjiVQk1GmSJ1yjCU7YUm6wBI7OB9uQI95cEb84NxI5+Q6+XeT85M5wUPyr2f9LnGGCOF5m+XrCcKW5jPoMrorTySdwmijX6i4GzyReYiv/cFzEViQw63nccaCeB1YX+r+PGDF60R8YcU2ZhQ4ERNPKUFn3lQAXta9Dg5HEc31JvHynbyLwbjksqAR9w9u58THN/W8cV/hJmWhpm+kLCr4FCAzNeT8ARLUUMFmL0YdjTKSVGzkUU+jDZO41mxqAFxHGZsM17sNxuSBPKnmkxkCZ4ypbTaCyoX0KmJExfAPzp5C3cwAXH50TG3YbwjNc4X+SVA5VK/KDK5XmRVyCnAC3Ve1bBfKqMxYzIu4a6G7GOpV0vykKKyJtUaQm+2xKQtys1SGY2T4QfsOvG/LvrINByOZnZgKycgPMnrVVYTzQXhXGIoa+BC4Y2wA4J4viqOD46UQiK/8gWC+VXiGiTsrOYSAH2KnopFCCfeh+F8pgM2awWZRzdc1/3fnbR3dIp8H/4/IgyYv+qjJPh01eZl61Sx3c7NgJatbm2XjytahoLWsx4LWko/GbQnPC6umT372OvrZ69z87KPZW9fB7K1mMHtrMXubDXnwsBfDTRCnooTz146nuuTwfXFrrJFcYaXDPISUwMVyBf1UtVH6rQiWCfdxp1zPMKd6hjVvYomxzPC5oOJYz8MKstzpymZWmS9432XC8UzXwDs9FVDM/snGlm+daRrs38r2zxxyKrCe7fkrVLFGEYVpIv41fqVUfeKMc6LuNaCUywBgdRvLlFcsY6HmIlwf6jhaE/JM7ol4ZwS5J+DtIsjNCjg2KUhusYRLUZBbLNGaEHDdfgW6lgYIlAAT7UkYIMf2FajCbBnNqe60iy3X1c59qBnflpRBakt+c0MDUlvS2+yC2pLdTs7LyW5no6C2ZHdqTzOyyyhwiBTaQXGyuyd1Q75KAIcsMjRJUltmpqWQQ75KAIcsMjFpFdTWZeRqzmWH9jXOuThVbY6fbrrXhk6btwHTepfN7QHUVcvG9KZlw7zJ985DvrcA+X3TRpwuTdupVyMMcVs8mbbrFJJ/24s1j6GdG0M7e27g+GVqInxzk79LJvmTAcAc7wUs2ufn4qzb7tzL9JJJN50d5pxcV+8MAW+8xB3IVX+VQo6nmNbO/0mn41sbqA47t3etESZ/Z+cOB/xVCOvPO9fDzo8bttcW8HMnjHh0Fdma9L19LnfFf38qxqv5un6S39RP0qt6iZvsXQbTn/w1r77WHvWBegklAW2xM0WbCoOKQSnCRT82/PHTYFHCcTkcfhyyjuwJQOO1yDpyNAl07Hyf7KFkn/p00lMI4i5HdwmPQYthS8PCcxBrueh8h02ih2DJU5BZyRIb0c0t3VoD3J5WDWRzKU8Lm1/6mGh4z4LaXAWnBLW5ChyKI7W5Cs0FmYJwFZwX1OYqcASMJ9fr4hNnSKfIy251cU4vwFgrMPUUwhSvCkxTFAUmOXsvcTOrkNpK3FZe20rcnO1FyWseTrU7uEdPyy7j1A7aXLAydvZwkNo8HJME9Vh7Ympr5bfy2ubh9Py4lwniKJv2J8stqWVmcG0giaDY8dHk+KgPtu37j7aoSsdoOThG5PhwPVv6P3rwf8ybllX12v9B/6i6KsJrmG+9hlMw5b5WmflmpOzsndewfctrQJW69Brcyaa49Xrn+vnBhq8bhLcv3o8Q9R5nJbD3grWzskbD0UQ2ojTde6UKuSGHmXZBbcjRWluy6chhJkltpek8CSojh83yaQ05uLiNGxHI0TCTm56cHQEPxjpyTJJ6ao5BakOOyQlqi40meW1HDjlvfwOj7FFBy/ojM0AYAgj9uhodn59rZfdvAiTEibcAUQOg+wDpHUAAoGwGQ6NLREgnvfD5Q3HE1z2fyzpDnm41d/5o2Vw/v9fL8irnVaSXU+95Ouji1MlCF7Ogdl2U1K6LSVB7o9oiqKyLZgqCyrpYjxfS7DnJUi6rM5CbvjXVR2rTt11SWd8a0CCV9a0BDVJ70UZe2/VNY81Wyf4PfDMNNM5IjUvvcgUnVWi9YaQB58xAjmP2G2P/nHtF97KQu4qXN+RbG83GWkwNXcvrqTBm3Yds7Ele7VCIfBGN6qBuOuojhTK6ZoA+9PKWsKjBDZne1lIfTjGSUUNtmaNPUSkO9i66DafM8aw+1R7z9nWGoij8rlRhl7C+2qydLt6hYsMXrHi/trKELq6dWoH7WfUaxQNa765pTn2wPRbR7YWrYHssYlfufQ3Uvxpsj0n0uolRS6Mcm2i/ihk5NjG5dZxZ2eDGzAByQ67+QmQSLbf9jbUkWm37K5VJtNj2l96SaLHVWgkqI5cip7/2qobmxxc7X1++XRgyHEGGFZBxmZObnx9/l+qQtXv9UtVWg635Ml9xclr19LF+z/zmLaHw6q2T6g1d5y9O/Z7z/KHXGf4HAdriew==###5056:XlxV32DM 3fff 13a8eNq9W0uS5CwOvswcwIDBdmb0fk7REbwc0Zu/F73s6LsPEhLI2M6qzpqZRZXTwsZ6gJA+hJ6ezx/RPabHv8ycH0btcL+0e63gfi33z5/GBLj++WWnWH7o39/ghzH++V0pB3STCt1Uelye5Wrh+l1NOzTbub8WDZADkOcg3prprRmaY2nWs+zUUbOD5oxvG9FsqdlCc0JWLX/TFlYD0H2hqyIc0AvnE72zPv/8CXPWD/VY4O/3P8bah7PuWVQxPxZbrkk91LQ9f8YJNPEjmqYoH0FRc7+3cG/7vWNFk35JrdS6PJ/47ekBbdNv/KTx6fmPmeND2aV8POaHjQm4KWyZVNnJy4ENPR/ZqPbsbOjpFRtg7W7myk/RHfxA3cWpkN00d3LR2nfQ3C+jJkEtNi9/Rf27F9RitAjjxExBUIutyh886wS12L/8wbOboJZBU/6KndwEdtLlX2n0bKqFTOW6qQ42Wlg5R9PY4xzw23EO+LXPgejrJdROcr3seElTeyWY8krhAMm6k2E2JYNdpNph2vChnPpDoTyUa8957+RUyHsdd7vqZGB215Vs66XyuCOPP9VU31Go9PpShMGocBbDtX87GmzInbAgobMRQVkKjV36Vo6uOJSKVeA6yxHs6wiex/GrZhq/qvO9Ej+Vf7Pg/Z9gUBmHXgPNi6RO/Qbq1x1Mr+Kl6ZXHAe/5Q6ARezUB0zR+yC1iAtphwvXBpM3gUPXZoRa9uVHCXD9sTvJN9Fn/od4cTh3Za5hrr+4r1sAxeOjVspLMh9a4NEI+GmEfjBAW7l9/0ghV6cLL3S9mRUvrKM9av2e/pPsw9koWXb+kez32urNu7BdnwtEI6GGkEaLiD81fM0KdICcj+EGwqOv3li8ZIY29kmn9l4wwj71urJvls0ZIn3FHuxmN0Pye+2+5o+spEUcJY/3w9r41Stxg6koO3RcqRI0QI1QxCx1+QJiBD9Qwreoa30lI+gYUCDmhP9vbqL8aXey9vx59QsTQyS1+nFOu8SN0DPEjNrf4sQU72NyC0hbtILmFsrMDWTdgaXnsK0ji6LrRdaVroKuna6JrhOv33WNAtLOAngScIAAzGCzwVyx9xdJXLH3F0lcsfcXSVyx9pYi4W1SxYlEUq9839WvmILD6dVO/6m3I3R5Q+6l3B9rfFYqSBbUof59Q94l1r0n3CnWfq8Gajms8mDP2nwW1aD5jmL8HZmatzKQNNcVDofwg2dYm28SvbCzbRLLZPfW22t0q41boDmQrC5KIcZFaZEsKZYss21Rlg9YiW5rwnchSTDXW3bF/SYVYFzOcfWFmXGUmoqIzP5wjy+ZYtpz5lYVkKxSWbetttTsv42zoTsTvTlA5fp8TZWzQa5Utyjh+5XeyjOO9oFIcX9KwaiDIIWovoGdlq2m+l4Ci6q1S62D8vmsaKZVqRCKHkxcTObVDgmDgj7ODlbKDRSZyFMhHETnju0W+i3DMU7ypUrxygDeer7qFIjt03Ka34omHrBYjfY8RybqTm7n/BA2z8ijQRgKtHwmkkaNLgeYvCaSr/6oC6UlQu0CaLa/ZjVWBVHGdqixv+uFYIE8CbSJ/qyIckxLbkhLORXpe05KRebPjKsbL53YKwmwWy6cblsdznqxFnoyCHLXLy6X3J+3qj7WreNGDH2KhrAJBKrxVLAMfIDyDF1Foi/jKJMcYktta2MYYkvta2Mfp3MxaRt5Cufb60GQqa2cylWdTrZcR/iXYUC7bB2n0MXvmpPlHmk9J8zFXPqbIp8zYyQT5mBmPCTEPuXGkwVUdsl6Fy5gX9t9a2phOA8DQAPgrffEkULOM1H6Y1IagGYbglpmF/MYMLzLlUaaWaez/H5k0qv/gtCZiIU/vyKRxAZEyeU5qMvl1bdX/ViZ7csSaWdAnFj4lkxllMtyh+T/JtJxWy5lZmN+Q6ZfS7IbKIGxhVh2RREXvBwOEvJ9exBscgintBJVDL6WtoHLo1VfdMpmLqIW8SbcKP3rsVWc8PU2e2DRe5t7WAimljaByIKVUFFQOoJQKgsoBlF7IlYPJkcPih5BOnMMPsVpoCozw+aqvRTcedW8Ty4IWn+jLgtKTILfUSKldkFtq1HIg4L4sIKgayG1A33APZoN7mI54bz3dm3q/iCBJ240/oqvUu0MyxxT2kBopDaqzZJgU6lfxB3RAPwz+qOmPtrp/oKrJcvqjVO5tLZdRKgkq5zJKe0HlHEZpwX7LYfQU+xBEoRJamFMb+NGTGEXbJhAx1yGBkbO1PXJGao2GHVFzFZ2eXXo8jdT6bJ1mkEFV/uqzW4+ykVqf9RRlT6RBejiI4BvJGHxDIlNigvLyQ7XgLlDEECQ4f0TZR3g9XgHoA3Ke0gkSBwD9Ayxcy5V9xLGLr8NPBKPsDZ7NGzLax79HkHTNGI+A9r+NlX3jHs8mwKPlAB4JlAijkSvsGDV+5PHz2JlR7gY8tu5LosdB9GCl6O4D0eNRdH0H3fovib7cYLfWfkn0PIq+S9Ht34lubgBTu31J9PUGMbXzF0Q3Fco5QqZC9PlO9IPE8w0oadf3Jf6lGxKjKnryDSgVKumYhdISVWoQlHICHdKMQUEHLWzRu+WHlUiKO9xSyD2w0A1LKp6HuPGNm9TbOnCjGc+BJ1u8oRtwowhcSAnJC5NrvFIceuWSgbJiqR4QtLUcPglrNHBbr46umq4LXQ1dV7r2RFKApmo9AraCXtGqaWpCN/MccmHdQCY1kyAKjGDRYzPHlji2xLElji1xbIljSxxb4rhhow3wU0aGGZrxQZjTLTDowLNaBCKqG/apFrYpgXGQ5ESsNzCPldfJSOtklOukHXaj3bB7vVztTg8Y0D6G6TT9fDhlU3Jq38zpeXN3u7LbaZtAJzGx7bAN4g77H6eJX6OlS/BKvw9eGQiz9hp4StBds8k1bUIwiJU6uc/XqgRd+0LbAqUOXc3DAX6I+creA57s85XHOVI5P2jQGVIpP/gTbAl91KN8pyNniQZNOiFnP0kBn9/Fn7U/e2vK/eOpDiV8ZrXK24iQtZ2s01Ycw5kIxX2wU2XTdgO96Zc7VTdDw+SVge2tJgOo6uonwXgzx/OgI1H5pFFSU+lQ+QQdjH4UqpDSJvZ30tapwrcpmySkDT1hVA25UHFmRdydzZ7J7PmiNskOtUkvClzc81SN9DOmjs1RXI21Q6IiBV67QOuok51rXURJDA/JIc6ek78rvLCn7eZVXW83zx/sdE7P+1qnwoEbaq9a1YE9DaXlpvZqOtZeVY7OyMq4D9757fzUvPdqYMf1HUxFW8bm7SbXS5FfH8ZgR/itGLFzovAB1FUrwjCq8L6TAXxOkBzqTQlqi4esFVSGavQWBJWhGr2tgspQjWafi1TeJatDCKleFKtVuxK5FavNaRXU5oON6EJsdllBbT5Y+xIuPnJZAJUiTHzeaTbuPBsXAqerhVeYdqKiaw1c0UX3ME1FHrt6UdrlbxLYXtS1za2oiwjb81jdtbmhumszNxspW1kfiogguRNjcGUM2PhxEFot5sSL+kP92VkqJ4N3I7pNwG3MAx/79gnM1M/DXN88y7WNcs3TX871azl7Xe0LJ6T9mNRtkRk7zHrgJzx/+OqifSZ11XjPLBvNec/QlufUxgMUiPmH5uDEzwR7lTaPs5m3maCpbyXpbRHkBg7qdRXkBg62aY7kXszLngLJrW6iTX9kcNlaWmK2LkEP0fzSqbIuwjBO6a2QKUtfBE0g047deyeojOQ1r4NURvL0ughqQ/I22QMnAnqTUnIUAE59HbdwyWWs00XcNiyS1YVfLgnhnSVBuPhVAq6CeoCTY6f3BaQIlWFfumRZsFSSWG4isZTMYdwh4LjB+tQhYLjB+qahKvYDkO9YznqP9mFB0VWGZPeX4Medn8nmJcy3cwi9ihBauIwgQ2iNC8NVFuSWl/DHLSQz+tSG7+X3hHUvgb38gbD5KOy4pcTAnnPvCbuM/TGil94TdnsJ5aW/E3bcu2Uoz9n3hD35Ccbw4nvCxpfgXfw7Ye9qJdz8hrC/dG6g24APNUDrgDXpVjVFhWDfdGa4DzxZ7YuKnWRVBEBKUwXBYCoiuEXFfXonEIyK/jRteBkq9tOimuKX5eIOvR8QOMs4od4PgBYNtd/YOzG8NYbX3tcBnmrvHJDCbDqZujKtK14gs+mxr+VdURBZgCGZZcgyhs/iYQFpZkYiJ45CcoNIchNaAqwNSTWTBFgtb8bq/Yhppq4hAbtlXrAhgabFvSR6wQ4HfJyixUqLJLqDJmE8CxHH0xLi+IR/3lYqyZMXsmRphpM/wQ4RacNHwvzZkz/mg5M/Y36s7g4m9AhXnAUKnAWFwzmqpnygi2CRlY/khoM0+BnJPYZMuyD3GLIdCAqHA2FcCIBkjiEhhT9ZVpNlzeujW244urU8XyOu8TKWByA21Gzx+gzX6awKQ7wf5RbqgxxqvuQHBkA3oMiwrSgq8E5QuSpTZO5WgJE9G7e9WEFk4/YylbYy7bad2nL0siiU+QC5dAe2nCHLzTcnuUaTxefNka6703YUdzaYax/ObokQUz+PcSmYR+5JuwHoUi0kLRNb3Q2HcDpRNC9vpZq9xP8TGSZ6nqsoEpbNN2qqKpLiLnGz02kgBkYGjKB6rhfjexo81fwCyRNDL6g+9LTi9a1oQOD3QfWHa8oIY7G6trWBXatEn4KgdqRKCWpHwJygdqxrFVTGxXo2VhgQgNvWn+2AW59IICNP5o51BdUnaMe6ghITtB3XDErUI3VHrMRhS23DUKnrqPxztTJvFava9LwoydDDqcUDphVmfzp1wuV5vEP1cb3ufHe85cInolzXkTcf93s7ow4yow6dKqK0Ki8o20euPAo89hiWhbaOTHBujtSGNnAtFFIJ2ygzUwPQUELFBx+PxXQCjOZulsOjS93uDjDLVfLVKdm282jjTV4d00nNn9l5RBDJXe08+vMBpe36BGJPTg6+NAywXXy+KL2ZcfV0V97dn47jOf055zd9Nkw7LO6Otp88ItffgLNh4ebWhVrRE/wHVTXQmA==###4816:XlxV32DM 3fff 12b8eNq1W0mS3DoOvUwfgLPIzPhXcQQHMcKb9sLLH757cwBIiJKyqrLcC1uVEAVOwMMDKD3//BY6PthD/PuP8v4R5fNH+VekLhSpBKl6lqup1x/lX7krXX+mPpzt80f2RaqERE3mIWUojVltrNNsLLfSOvbWeoo588/WlZS+9c5J7xp61+VJXe5yvbcnf0QLd+zzz5+ghHrwh3vIh//3v1LrhzHm+R+p1MNu5Zp46cU9f2ZfHn7+Kj3W60/OAlzrMpTm+0OWXqogTcHWBDu0zPOGqjc46yq5qdcgTG1Y14L92/qXZYD/lSo+Yi4DiftDaF5HVobIVR/azsvILOjvIyxLVa9lYr4O0VB9ruvj3neFOiZUaEGhef6MsimMaoyXxzLeqOfvvf42vdk2xeFZ+pce+9/W/gP2b9b+DU5oO3Qs+LFjIS87FqyKbZ+/bDtTLUWhXW3drqq5VLkBCyoLDhYU0IJMnvea0ZXdOVpWeJRtbTrLtajM7bYltw3cNvX23m4bclvDbV1vp6PTBHCarTlNMa42ph3nEZqnFds7OFO5P5yJ6z6BMm4GipqVi1Dm+sgP/eAczXwDM7fTzH/tsa3tPo04+LK2+z5/p/o7t2aZTbEr4szn72oyWfRm/uwrcvUVdfKVk4uU69ZcRYX6e6OmxcG0gl5NS0ZiWnKxGbWYlu6mZaZN5+fR1MTZ1IJI4cZ1efGJ7rs+fsV3Q1Wornw3bOsEhSa+S5zWL75CfTPUP/SVb4azb+5kAfWygFT/xbrEdV0iros/rQuDbvztuvyuZtyNPkX0z636dJtP9ZHgm6+3BuDvbS3bMwH8PQx/T3LeI/7eDay6ZAB/L3qnv2uuyW0Dt6e/t+WA0RA/jwbFgfi3MgAedQzFkdvQZ3QMQxdEx709FPQUx9pYNKki0jLczGu/ORNpGWVu8XX3RFoGuTcky45Iyxj3NqGdE2mBoL3OhxtGsabOtUfUUCPqVv8h1FiAGkeg5hhKDyE0wg0CD37AwyG2kphqRkydEBP6imyXhi5PSJGukYIjUhztXz0PSNEB5AopJpKQ6DS3StHoJHKY8tgMsu8WaU4CT3MUFE8D3BkRTwPMmohngEmJiDHA/Ak6lJ16+AJDEffRwT76EzM6buP2/DrcUwu4xv2fMqaG/9rvKzwC3ip1Yjb6I7hFtWXGXKywiLBr+UmxXygT5UYvYHhSqonHmvM7rmTZ2vEmL7lSj1Qv8Jla8wLUdauXBQWgVicv4fwjnB4L+lvugG11x4r0+U/tqf7xo/5XkDSIbntNTgCdAWbVlWmA3qyxAzoH665KG6DXfeuArn2e9wigax9hIKVpBfSqlwB64OS2gdvTn3SYo5n+1M0Qn1Lw1PQrb/EpQYjbwPv6eMX72vkkcIYTUG0KG6jq4tLl77JHuTuj1gycMaAzbgeiZnckavC7GiJhbDYeGZt1yNjgd3iStIfBRosTNLs7V3ZyunIZv14s3GawcHnyWW2uswF1Z+HXCNw9wh4Qmdh8A0lKThySSC5ORi8+JCdFoVrQw3mc4smLNP8cqVpncpiAXJzWIbuShwnUbsLzp29O+bMZbVXTo6zcXPfVrq6aazW15lZFUpodTLls4yALGsNMkyKx6F6B0kFChgtVKRIWKeKUdjcvffq9KRdzON2TGRvuA/LhNt2/m7SMeXO1tWhaOMppJNTJEfHwcx0YEQ90kCJM8Rxlxy9JnhjhuuMJzhZoVE2JbXHifTqxMR6cOBJmFNnKNbw9Wrp3R0v38Wjp3jw/KFks4dis9Eo/b9OwoPawGHpZi254Oq6Gbtm1oYsP2JNafJdR3+32eFkrie/VStxtrcSesGC7rpUcSyTpOL9eQlnTsDaNyzTMn9K8TX1uIfnzLh/7rdyGlQYHZQxL2aTHkkIR0+CJ1lw3ftTTSNnCQdHDHooenNzWcHt4oKJ9QRXGQRBXiDb1D8KNB7K0cZRhx426fpOW/mPL4PYwpbSqSMTVX2t0nfDWxnpRYin3B9QI70njEe25EYfKi8XKyyaLz+uHeBj0+QA+nwiLps5tFufWi3MXMPgVAymtFENKSygYHulPHqlpPm+W0PPZ6FmndfTAgtqtx8RPHviJzL7PoK1qggy+LlzPiTbM0jcJpeC2PRubjwxzEJsg0rHDGyfSYSQYS6pi3OAyN2fKlhm6ZRG2bKcw3bcgNjj91SLK82dKtOSFCYtwa8KCqxW3r6/WTFiEy4vegDhovqF31k5rB3UTfqQ0CpkgbhuR3HD1Jt7J/gzy38SV/LfHJvkffl4btF5iHG4Hz7WCSHmM7I7RZXcKMVaklplgf/LrWmY61jIjO1LkMCjysZYZjsy41zo12WgkyCTY0iD7+dIFCbLO39U4XTjFBndduZDPTxLomxTxonJR1n/Fmij6wIJ6aXOwYHch2IW73NudIEzkpeR5WbrdF0BLh+OJFgvVVex1p+ORzVxDpvy4OPxbJSz7OT+LZ8JS6Si0oSc1KfLsPlSUjgKeC0Q6eLalbUdhsBmT7NKOrmUXm8v1ciLqquJc+s0twhs9pYSCk6OHROKiQ+B1tLwpXCRicuiBRyYOSqju+sjEQQHW0QMXRZVW0oB1W4flS3c48+FG0uDsxrGIrUjPVQF7rhBL9o4ljl1QcrVEZb1QcBLFtyWK2yWKuxHFj7HjS7j1+gzGL7gVn2fAgtIa5xaYBFuY8GQSp0qUCp+rRKk7inpdKa1uRfDGxhumEdkbTKPoS4s+jJkhv6NPtdh+DdT7CUj8F4H69WEUe0nR7OlAGYF6f2/h8s1pTkjvUD5hsaZdVnDAmhIM8wYGUGUjsIMGPhbJho2UDFrkiDYRaqJ4nuJJZAgm7xSTBZFOTKbScVCy4aFKGeZ8w2Hgd5WOTMkyIh3kc6B6lQ76OlC9Sgd9dYmMYaA6x9MwCyyteDGNLVVOiqodt3VfukasbIIrEC2bCZ5bRH+7Hwowbkdo3nGD9kMssWSsEJf+BL1pOE0Y71lkAFr+WVJ9RbmwJnlCMr35G87N8yml/zxP0Vu4odyCfUttvGFVgn9Lbbop7AvxvtrJDKp+anlGoRx8FspwG2lPy/wtAdNV7nstfAtwjXAlDEO1EIitNbTW0FpDa2QveiNjIfarMZusT5MkxhAxSXkMliFLnzNH0RsRDxT6E2ROy9tEG5TpnfganTB3dGIwzOivUs1eDjmYPVShlfje2Rhbi37Il7eTPwn/4pUEfXhh6OMiWeND19XGdHpXIX9QVv+4SEbOglhnpnucqE3OfFgnpnukxQc0Ik6iQjUKKDpFUoualWxPDvx71gxSmiyzfcrh1IuNU69EnhnvypFDL9ZLcHWs43048NX+Ply90ymx9+30Xj4sWjAHC5Z3OP0zEdJZqUwipLMacppUx9dkEnAdqle9OHPJ8NxbjCysByNhw0P/kw8Y9rnUTr3MiVtN8IpTcu7eKoeNl0I23kOz9+S0Y57vy2Z8qdEBYae0B2bvsYTmMcHznoKeJ49UXpHkocJZpcXyE6fltjokUq3Bylr9gyBhbV4E9R/akQA7Urd2NAyC3RmEf3812xjJmdF4sa4NlUyITTGdkN3WCUmYkP5wQu5uQiG+RZ1HBu7IhHqWD1IyISwJVDGdkKnv6XBRXwoUOCUFUzJ/N/k1X01+92PWek52Ww78KtlNd0W6krHluxzXnUKZ8n8nx2Uvc1xzx1XD9o2amjB3XDWYb5Xq0npaNjLe9Mn16zn/KcPty/j5Zbsjzfga6Dvzmyy26j9kPm05q7zzz7q+/Ron7+xZWcuP8CTDRJIfkcpfmrkcyfDSrOaRXCrRyp8g0pGRznQ6zey1Z2ttLkdaK6eYkmCBYkJrIYtuU8o4JX/IyceAMk1aA5EiRSLFzDxpFSl85qvEuUqPnxHgNljYBgvbMM4JtF0Tzk0DuG3/n4TT3jmx2L6TwtnbhNN+S+1twum+pfY24fR/JeG0NwmnPSaclrS/TDgtJJwWEk4oiWh7SDgzaa2htYbWGlqPhNOSsdCEE0tT9emrhNNeJ5z2kHBaIiZBXNkWxP3DPviOdg4fsDhLD5jV8vYIwd7Xx81mHjfHvPB8tvB83t2HhGF+T/8vgzyN7myJ5i+O5Pzz3l3j+p7LZ87kjp/owHcH+ZY4mDNxcNeBT75a/NOh++G1F2XdDcLIbyEMW2v+I1/a2JentfKhLxwtqhOCItTJb0Ed43d8ZeOfnZ94fu3tb/56I8MN+MpvgW+LTJevEW/iyxN9Pb+LT67KtOIN+MvvgD+PWPpgUFXJh/oe45Mx8USl41CByQ7k1YMqcCsAdAWArmy8AnLGSbUdYVwhjNMXElG3Bd0WdFvQPd7vTfiKIRP0IxDmZpeNYSmICmU4I/bVR8YJKo+ZjBL5njZ07ONNzY2qGMeoPFHxOHxVg0na41c2zM/mMEj8ymYG3KpqvAipBjO0tO6gmJ07Cpr80CTJbmNNYlZtGZslD56oFCsV2lBpWYPUh4IUs+wT4bYM+WjOOBQ3hiLmvcFrR+23SZHX8sSJdJQLDW07Sm8xESnw2pLOZNuKxyVyYySHb/Sc+9J7Rx9SVcnuKm5GvvFdVtEnbupfRrynT94cXRr+nj51c3Rp2FvfoeF3N1UxPWHDwlyVU5qaMsolpakDO+qGVKyoC9mvEq6KFKzyNrXQ9zHSjnJBmWQ2U0x4J37uU/skVSL8OKiKaZWofXhwMEr4msv5v2uUYk93Rhne2XSx73dG6d/Tl++M0r2lL7M7o7RvGSUaX1VMjFJnPuXEKHXG9nu+NMq6IS2v3uF4eG/Hw//8D+l92r4=###5200:XlxV32DM 3fff 1438eNq1W0my3KoS3cxfgGgSUFV4K46gkSI8eR546Hh7/yRkQkol2de3nge2SgeUdNkcEq7el8cenl/3+Pz3hy77Y3non1/0tj+Mr7BalorDNvDtoZb4/FpKq75NuFUva6s94NJr59xqlwm32jk9//03QY4P9XAP/XA//zEAD+fX5/+MtY811WdRVcb6/J5T/fr5LWd8fC9re2sin9926I+IjyoQq9r6b/nZ5Ji4Pf8xNj+UqgLz9oBcsIXalFp6E1ucUkJ71I63lmpP8Yn9zCexKZBY/XmxP6zDH+bnF+x2XYkv2M5YEbslUQpUCrUUaqnZaUoRneuCMzrguS5KJ4aTWBfI64TFuui6FKd1ibQu+VProsHdrEsxfQI1qD9fFw3+Zl2K/rzYuS7YbVwXbGesC2yLKAUq5XUZU4qosBeACQt74eVCWcJewE5Y2ovDdYl1xJHXJdG6lM+sy/dq4zQFur8r399V6Pbk4p09+XfsyaU7ewpviT2badYkdn1LbDmLzSQ2vmH92pFKoPy29nXWG24ZJ8uuq4O6Iut3D10XgbUVEI/dizjyJi7Ts0ivUkRtoNpAtYFqD22WfZFRwRnGk1BnLWGh/E4zHKX3kbD0PmuoWm7xH2t5Ji3f7rScFPqbyaU7nLjcKG6GX3qGy8VisXX6NJt3baCiz6/4Xx2iEficbG0mKsx7DUKIGLivC/5QtnpeRY4Xei/r0Hceuv+1gbcIXB97n5Zu37uqjyqnxuqwPeu7nu/5OdzBnqQ3qM80qq3uiUCeADSgTMA3YJuAbcA+gRUBtUzAPF99jg44HiOWLlhaOvPnS1dnNaSzPHI2WX1Knsf+OilvJ3dgXgRaipebr8tl+6p1t5Bdf/gxGxrnK4f5jrNjTOJm8QMvml0jN7u8NKtEs2ZK1E/qBr2rJ/Vnttg7Ru/L85c9VPuhhyGeJrqyuD7R+nMTDScbXtnv6l0KRDnp+S12A4hbF2O6YzB+JX/r2eqq3FpabTQ1mGNtiAc37LeJC3drjGIxNTab9GzyYnMCPs6i3L5YmrlbAXv0oTvCUdZ2CG8HpoAwINxkr17AFuHuSlYBG4TboNYkxlpJNcWQ7qYsDmrtzCYkekaxF/D8da01/FP1ZnrCwpt53iGEQyzwmbvgW4e3rclQs7KIEH4VlbEfuk21nuic6jZLqxMf1Fna9oNjRbRO6d7nXwm0zv+uGplCn/xYq4IlDjOl+9q4zDDDgaW7PvZ4R0eX/cnRZTMcHfo3d+BWHKJg3c60gvySfd2rAKm5+m2IStA6AlLuypxtexFMEXVzl/6JzHw7uoFKe9C+Ire3nfxhTtxeObfn4Jf+ULohf3Az3e0IbwMvEZ5ZmV1eRqk+HuHNxpuydWsR/gscQz1EUifg6E08bOEdWZ2Qpq1AUb9+s5CNoFCEviBSpxDLVlFG8lzDN+pIrVpVrMmd7qOPn4sdFU834o0oBioe7gSiFsWWiodbmTvT2onGISWtUcREm3/rXwa0KFtJB1qUmduTjSxKvVjUd1qBA6nIZ1KR3YlUdNNadqIMBxObptVGd2VaZn/PtMqtaeUXwfvJtEiZ8zHmqnKMuWhcXfmFjdlG5y5tzL1ou4snG7sJ9vrU8D4aPhsbGUXTeS1twXJ2CH+gzn9lfS+zPul7YX2PRsgS+j4VujR9R5lS37UodlQ89F1YS2n63opn+JzmUJq+t+KTvlOfhJ47oefti6bn2ink6R55umdN30nT9cc24t+3Hk82oevItrap6gnp8jajSmpMfbLnlJ7E7A+EPqECXW7zhclNYp/tidiTyV2EuXgf5mYgfOXz7i73k9I7uR93l/tJ8Q2xtmmnpNl1l0Cb/Zdcnw3XNNseaXa3rHvL65YpLG+yb8Gum4peJTfS+tZ41Xm87FniCw2x9nq8y2lboZ+XYd3ehfXL/Y5bb+J7Cm/k9vRK3gcHLsIlk/EGT47OibgGT0bvmFG69UABGu0GxCk16Dw9Az3XmVzRbmEpQSZXOklnKYGkBJISSMok60V0UewAgoDFfsEJeLhHG/WEhR8f1BnNYhJqpvYNJUL9w0ZZlzl8J/ymo53D11E05r/1VCdvs5y73Gu4Y2KU9xrOH/YadsJiV8G7oNajOjVbkfuVho6NCe+vGsobCquXudBzc4gBudQQ4B/6wQEgLBQAjAgAlxzn1r9+ZBtRW97uOAi8kBuzXHOQ8vxznt8zh5ccBF72FV5fc5Abz/ABwk+Zy8Y1itRRy2dO+AMpxplPIN75RLniE63YUfErf27FQMWTPzPdaMWWioeZKV0OzKEQc4CgTgn8QPm9aP9OAj/cBV9t3kmJh7vgq+1bYu9inIa3xN6FEu3eSuDzRjCsxwT+wng4JPCDqH+ZwA/d3+Ps9meg5yoT+LuoDVQbqDZQ7ZHAD6IvMoHPThC/Fo4UBCxPrzaGpTcGL2B5TKVM1fJUnSNnVoImLQep5V11BZGI65FIRDgSp+iOxCnmo9+I/sgoYqgOrG/evpVOlEtPbRfRaHU2tctwokGx8InUi6FAuqZB5je0b3n+kg91GhgOzlLkO5Q5m5znHr4Q0yDdr0g032dvf+jMS696qC+qndwbgVbnWVoasSiBovIYVAc16kILt9k0uUGg1UPWf4iuAq3amhsjykmgtQ8ZHblOm0BrH7JvdYtAUfdC6wNMtAWJ3NRd2dnhDpe2kyttJ1cFPNTQVUO6GkTOQipl+I1Swp1SVl3sLoT9+35Qwm9F7O1Ql8o8tUmoO0Vs8jCQtrWp8SHIMCE3jOvzeAJE+8TTeQ8HkTobcErgRz5i0HyyETM7Svu7vEmlDFmdow9ThvSSGtT2N1yF3tOJK+QDSckv535sx+klQ+OXk5WcEyFnu5Tbk+LOc8Un43p5mauPnHYUfxKYLF9d2T81+Wk/CwSeivQy+e568uNpssthstOZig6XlF5Oxt0mJvsPjpz05eSH89D4/oDaPjf55zPHNO4Nlc9NfjkL5EPC9HIXQa9i8uE3mcD0cseB8xMp/FbB7xJ8dQLOZ3fj6oTKn5jRHzatRJATZfNqx8decQQbnPjGHNpZXJ81glvaEJGeNuwDR5pff/SNZImUXh/xCCHBcjqz8ohD3zkX2lEX2lEX2lEXOg4r4hjMctzBH9Ri4Bbz6GmQ/CnD7OTcL2czBWGwKz0mOYFywLUp8LztNG+bCLwcIHEAvdnQPtonTPPGxws6cwojFXFSNq4pFbnt1pnzAKmnR3OvTCQS/fkI4SPUNnSGcM4C1I9GCLfJ0aiy6qPC0hnK+diuAHWmzX9WE+6jyoq1YXZp4bVxtDZK93VDRtAbCg3tc4RcpU9qQ02Xg8mKvmh9ex/wbFDFR13vjXmBJV6w3vCC9cQL4Hl1yt/pQjjQgwtC0AnA8kJdJV0wh7i/HRPFgge0xLJMHJfn4UpI5wkfySB/NpFhz4licfEj2daGu4rZ7iWM2PU6sWBOLGG/nPweXcIhtE8naAPcbJbNO5tlu+fT+EaYdPmPx3c1rMsDUvuy9ecgaexbo3lJA3EAcuWjo9GnnZF9fjAfdJUZty/JCI5dBt4a6O25ttv+eKC/HN9ZLY/3auxrVoTSF+ad9IXKHN6qfg5fD54d615mvFbFCpTjml1MT0Wg4WDqwVJKwlJKwvaUxCkV0WSM/PDIxnIiQoZulh1IdiDZgWSPk7oyZB+OsReYTbYoYSmvgbcPlfhkJPYUM5PWS84Og5N95yAKXooYmUVVQMAjo2jH+Ecqhu4NuFmdOsk0Y6SMmqhx/mA58WI58dLYh13sXFGSxEFxJHzaao8tu5MoswzFm/6GMjMBkHWZxdhx/BBA5u8XJhLVuVNXYHRlm2Vz5+4kytRAFSVQphMAsi5TD8WcrKFEU/D67kvOFSiSx790afou56reyrneHniqt3Kut+eK6q2c6+3xnfpvcq7uJufqjjlXWf/60jTlXOmMDeiMDdx6eWmacq50rgd0rgfyXA9kX2TOdSRX3XXO1V3nXA8nYCBhmXP1L1ruSMvT39Fyf6vl6R298bdant8Se6vl5S2xt1q+/Sda7m+03B+13Iv6l1ruScs9abknLfcHLd9EbaDaQLWBag8t96Ivhz8NYHX211rur7XcH7TcCXhq+Q+gM8Cv9UftDx4E2v5XapnxjHgeeGIc7+PVN8Yj43g3qb4xvjK+Ir4OPDCOs1bfGPeM4wW9+sa4Yxxv5tW3jlu6PPy1/qghsb4xvjCO54X1jXDetNYfFa9vjG+Mb4hvAy+MF8TLwDPjGXGeH+uo//VHxR3339KB+tf6o+L1jXHDOO6i6xvjmnHcR9c3xnm8Hsfrx3g9j9fjeP0Yr+PxOhyvG+N1PF6H43VjvI7H63C8bujDSjcU6486//WNccs43nlc7cAN4wZxM3DNuEZcD1wxrhBXA18Yx5uRK48LAo2r/sATun3gG+Mb4jwu4PUCXC8Y6wWa9VmjPuuhz5r1WaM+66HPmvVZoz7roc+a9VmjPuuhz5r1WaM+66HPmvVZoz5rN3CeZ43zrMc8G5ZvUL4Z8g3LNyjfDPmG5RuUb4Z8w/INyjdDfmQ5EeXEISeynIhy4pATWU5EOXHKYX2IqA9x6Dmw3gLqLQy9BdZbQL2FobcQGcc0FcSBr4yviK8DD4zjVgbCwNkeAe0Rhj2CYxxvKsDwJ/THAhXH7RbAwNl+Ae0X5rjYfgHtF4b9AtsvoP3CsF/L9mjRHu3Q28LzX3D+y5j/wvNccJ7LmOfC9lLQXsqwl8x2kdEu8rD3jW9zetpZ4n0bhWtafUiLPz222aXSfaR2po5TpeVRI9kXFUt/JnpmwnHLiM819WftR3vue3tqy/WpfO9PrWJ/aqq/BaoP/Wn6uzUbfefpO93xtX8Hqbdj9/5ubaKnpu+oXuntAZVDXT98uoXr9adeIr33cu07bpZM5Znkrf0d+En932hcaiGcxps26i/1Z6Py6u/bu+/jxr9BbngkOb7Xg9DLbaB+7dwelWeqD70e/mVje8ZejlccupzevqZ1wh10r0/98u2JXISPdz1uMhdqWo2/pkRSg84etaTX0XgRzfbKEAhpf19LjAqEROW7RLoU2K6/N5HQRWpHzfbagUS2H67/4IsbqNOcLcHr8guPE44XKtQjpz7itjvuPKnd+ti4zV6lVc19UtrTt+fhiod6lLULa7v+zsX+DyoD3VI=###6556:XlxV32DM 3fff 1984eNrVWksS7bht3RIpfvW6ehlZgCSSw0xSGb3y3kMcHIiU/drulJ1yZUTdiw9BgMSPTD9/T3X8CCH+9vuR/Y92/jb/mGObY+ZYMP7lv1J1P9yP4ycwvHO//R7nP+OYoCMLKE3Q6RY34Cjyofz0o+iHcPQbR1+Uo/cOLL2x9BtLQVLsSpb4KPohLA9jmX48t3CMP54KhocxPJRhKhPlEcYRqCB5hC1GYRYWM9GNMGsBzIIxC4uZqEuYqRoT1ZhMfXExo/qiqk/+WSDVQ6Qekj8nLE+YLz+eSeVrneRjfpz3jyfp2KZeffM/hvx+bhn/8l/+KZM0/MQ/0EXooIhx/pZl+Nsw7gYMGXtXHlCBf+rEiMoDKpg8mgjfC2YVXqp6f5+LWfPKTEhA2sDsXMxUBZNbH5SIknl3g9u9cXPKDTRKfIDfvfGD3iY/7xoZFmOIlUz6l+EwhkKk1FjCIzjPT+gSq5VVBmMDQQ8VWLZV5MjfojgYbs6HnawIjgiOCO4VaGwCiQEfxxU2Hjn5cD+ayqMKmwItRTUVSBd68A+RKHOveu4yZ5JRAkVwRHBEcEAQNbhN94GSQVXNzu4RxJb95+/ygRMQj+PHuOYJuDLGeASOUcerKvxU+DFPBsbK37Xw/0g84peH/3sZ59SF20hm7E0xZPcC89BRT49gYCVAfYj6KDNscPkDzORDDKTEhfN5c2U3cKNyw0S34VY6zwYUGlVWJfYXFNlJgtE7RKLTA6QRAlGq22izagbrythsQksXDIgznwj3Vo9FjAnniPVkOsDoxyI2V/XA19a4aGUryIjtJigq9dkXcafT1BXPP5R42hMTCrEqkP4t+o2Y+oq25qKOVHYNqK+s+/jwenCwTQ7dHs8NUS5ykwkfQsDsFNV6cctX3DalLCSdcFfYnBxli/weW1Jdz+lw0ueuxQE7Ik/8VSnQadZIcAEy4qjDGIkaH9Rr4iIHt6XnbnGDO8ushxMnk2BNOhtPCRYVuoDqXFMra03hkdjSTkVOt9d/hAofYTTiXE4/Yh/4EDVl9SrpSgytUzsPlQ9JYYRO7RRqx1M72bTDCXV7J65NjtGwxT62yIbdywio1FykbqKzmkh5E2moKH2YSIMiJYp0UKRiInUTpasDed2CM5FuE+mBSMFECnqghEYhJ2OyKNlnBakC/fD0j4MpiR8H3IofumsEpyi9fCC0DjuqgkzygyATvcw/Tpm932s/iFzpuTSop8fkmv9gdYkJhj8QMSValEuOPEa47zkiwMwRm97PgwKEOQJhjjgVt8P/Msr/Mtr/IDxmSgGER+OijOAsSYlyvsn5JudbOcSkhHMEYTCCoRxl1AN5ev1IMz4KqozCQkbFGCq9ph6OMVDSwPcPOfVC4pL+kZ1iyCg8ZRQEGXVhU/OSPMECgWPlSMs0/q8h52CoObinCjnpfnHcmJUbE3Pc3VbGJeK0A5QpqJxbLEWs++jxVdRuq++NNE3VICNEa57p5HOtLYLDmZjQCndAMA23lR7Axuwo3pELGlUjZXfqd1OnF099HsVcCILjbd2o06JGjJko7QT1MOqyqDn32KmbUqNWEBwJRJN+WPUx/eFLz1yku114Y4BA0zVzEQZWbPRzY6DBs/NAH/3SaNB5uKbJOrL3YXXFhJD64uJHUuLgNLdQKR6qEIlDj4u/+FGMp6EOTGC1xjz67wSqn5HXBKJU1RMngHaPXtYE8HUiJhLGO70zWAHSnzUDNTjKmgKaV7putkCa0K81icLkA6H+Rh4vk1gpI9v0nUS1POo2iVhHl2+TwEzHODdtmp4vTtGBcW/qOKgo46bF42gLZVDfkrBhVUQZ+4qHCZp1poHsEbWXJCexqXeY3gtjsP0JN5bVfcE/C6r7UeZeTFYKR9YZ8GxittQulsJSpUQdRUz4K00ITssSQV2N+kJGQDuk5ldGgBgvfs+LFG+SeVhlfcCRiYBiIS8mmsJr7eqb5qr+YrS/VLFzhPb8RRVNbkCYIxAOpsgyCxDEzUe6ec/xpJdP9PJA9IemWScpId+AfEMVCKmodNS3oL1J+2qkWcjIyqTBcs9gdeJ5oD0Pnuf58LaFZUmZS+JSgHB4IsiShk7fHxOjU4xoYnTODu0H2aGnaDhtGmb4e9fkODL6CS9l3sicZmuodTsPj1pUImevy7TalThvM+215YqdsqFikTzYWTp1MJ2KTKcsakVLpx7Lf5lXaT1kXlry3soC7mDea3n/m+8erHCQAZ5FFQOx3uTasnwLhI5VIZhVpqRZy1owZ+4MjyMLUMVIxpi4IscCQqomWatiXCxvLpY3QIXmwqUnXdOQbLn1YCKaiVvJFvVUe8Ps2HJWbL9WN5mYP78jNNEyXYtgVNJa2ZNYZVDJ0J0EcS1UxYRvkv4wAzxN38C9Lj1DwA2Ge5vChejigbiujbhbcowUFnE58yRa0oayMHBP6H59uF8DxYdGvWNvZtyaR8hJZN5uBZcGx3hwmlC201J4WjLHm6ek0NnqQTMJQ95IjcRYXCQ1P40kyVt/aQYCtM3GzbHQz0qaptxvnnBN3KQF2bWbk7pbmZysDolVFuLrYYfwpodLzFcUNxPXaDDh1fcJH5swKzEiBJjw5MgCQYzAmW6dMKa3hGKXTdk1cjEJsIdPdtBw/pIlonbOEmtVFB4+KX/E1MR0FlrxrJ0kIU1MSGGex47BrdsfmJGYaOU858IQJw8M8tDd8dwLAxrwWoJiFqQVN5NPKUa2RNvmg3KetrioNXxY2TNSqGcsNiYsTojk1RClhYUBn4R5MlGRRzW/UGw9lpxrFhWteERdk1jONB1V0ylq8BIMWSoqIVZAUIFUQtgEQzUuY3OaWKB6mCO2Z2PgTuyvyiheRaYA58TWt0vscaUoi/SOsxfOzlmHs9k7Zy+c3XP2oiOqL8zeOHvREYhRe8mQprNucyZWMHGQd0cx/6A0ldJQCokgKg3VBz89NDeBNIm6aCYNZ8MkMvI31hXtuOCjmxjo1SJ3RlZ3MbAOrbqwWC5ei7t4r2IUfXqp7pHb+tMK/0JNeYZ9qZovYISFofunvE1+nAd/poWh54GeTSputBcqT51/K2lPv1nrK8m5cF5JWLcPnaeseXhiirb1z1tPjD/bYmKitLcbkIFyLxRbj/UFWFU4qyocay5J/BNHFFjOFiROPNCZS47grARzjzVmZyoUSZs5Ylt7yooAwQQQXuzgqQuOKoldQxl6BuJhjUcwSaPUvZ0YQTGgkeDujUdiv+H4jUWGAwr7zbLX9SJFfSOYdaLCSMG1NV9jF0P0DIlQCbi+YbCfIZsdElVgjG26g9NFdj7ErHDnWJ53m/DFUG4TCfaszHmwgy/uywjIvSCNOwm+19dnQSQHBQQJRtm4jcE+lNK0BdEC67w1qPjKNgS2LkVAJujrWBATAXmCP92CQIRa7WRboeWtiFAY0qjH2u0Svy5GJaSUj1+QxjCCuH88x4Ig4xYICpt74yarRRjR6BQWRKNv81rIHA+LdkQlioDVHk9aEBNhKE1ekHFbpMZBecoCvcUu27OZ1ohZGiRSYGVt1czjg1w3i/9jySnVx3gLuJuO0JmffT8QOIPlAYGcU7POc3hd0mALPB2EIXOELxrW8zzyAmlbKchGuRgf6JdRUov754g4AWke+ufM8WYQGuavH/P62sO1DP8oa149x37cBqsbTHsY6OZDW5bR3qYlSRzfwscSchjiurSKS+hmgdrq8643dIndMH40Eh1aAmju0Hg3hvUHW9ZtfclixLjnG4+t4bQ1DFN5M9C1QOr2h/UBj3uBTCvW5TueDaYGRsbt5d4usmCK6bCPYB+8uEHj1UZrzGaOheNgY5YNXGRrRT0uGrVs3HbiDWv0emvcPvbR7KPbh26AYE38uPrEmpc6u9OSCU+GGk3EzxWMRtbSTrtk6eYJTdci1ooq3XxKUfyi9h6SMuG9Lk5djo0ajEvQfD456/HB7BdTKtwdRqsPuiYd0dIc7aMzP9NLI7GC1qku8K61a+yNxhj3yonXx9h6zu4swM+OmNboArp/6gsE3tMjGs1RrKH39pbRsqUPQGSYQni0iMpY2IcFKW3R8qkCeASGOiNlyNM667a7menEIMZgPRK7+UC5UmA2h8w+9jc9KO/LApNUFWw9WGBU3tXbFX2CCY5NmZmQbKvs/NDgb01fqCgR96JmVN/Wak1636iOCwt0z9oGyJZdYgSXQp2+uG6tuMwRudJb58zimReN2kXDqFswmI8yRy5b8GY9Gnlx4XjvqI0k6QhrXM2Wthy8bNA7Ehxvu1JIltIltvLRmbIbWi2XqU6d67G5ut2WZJu0A9vt2N3uVoqRDcNGHxv33S/2MOxs2M2wcVnYLbtkGa2gS58owVoZJzP+ZMEia+7rTgrS62VUBrK9VbqpPKRvtqeTEXUjQoy2bEUbg9VuzNCNuMcGc+9tWsFkbknWm85hl2SdUyBDTKNvmJ2YnhjOpMJ1zd23I9ZYPYLJ3RYEV1z3eO94nrVslGaJb1i69oxwgnmikd4mRGhKhGc2/XgxTTJNFO571wArR2Vynwtk9TWIIrIvaQvOnBDN32qNr/NeVRfvPfXO4LbGntxXPJZgDSaChbndwXwNbRJH48TEMHxYgh/DYffTvLPxV+MFdXivrtsC4cIodKoYerPCAR4ovFfwfRHpHVAMyWBjg+HqJgamlDE4wm4e1ARHZSZINIG5WzMaHm6EYkz8YsJnM/b0pehtPoLdQ38A4mJryo2pQn1B3UB9gdSAPbDhLIGnMvAEBh4GoPcOGX/EY9XxKPBT1HpeRoTEYubKY03H5o69kYzFbTCcs2ivHWOxa5sauQJ7tRjLsUC6AnuDGEtYIM5meTVWl/nA72ZsQkyyR4exxI1a5QnXom4Mwu+jNw+MZ4tBzsK04wQZKH2hqOsNbL5FbYRI2HMrMDbTtbOwh7yxWz3l+XRBnAM6hD5a8X/rjbJnm0BudJT2WLToLYjLQWfQ50WrNxGe3W5/sWbsYRHjJYP4AIQ4Xzdi3CV7Vjb6gTcXPS7y7VZGI+21OszWAdd07fCaEPie1jXdu2ydfWtPY9mH12Uf3padF+27bHQyrdeheTnv6bDsw9uyyyK2ZbMf48dGjXUffHyoH8i17rQ5cTYJVfC0XX0oeapb+uvR4LQDWzWaSZTU1CPvkKIvexWSxoIgpcls3Ka8Q/jAmBC3IKjxsnVhU9lA8PnlBWW/QNqW5MtjIfvAhj09BizbIa7Mx3Ki7Jaw48WxPUpWmrBodFWJspewaN63x7i5yHHR6KrSK3paIIqerPy6rKF3rbe+eLMkb36xma9zYeDWVjA6H/Iqxr0w9KmqoAx7nYuLyqttOHgcJRMYjr6Aut6nr+6VRaygT2DB5nYLxYRp9kpW3xMkO3wp8WWet3eft4FuFhh3ZG4cbevqCwe+LNB3ita7gcQM99ix0To0WG8jROsC5tOID8yJtPo4eBlor1OAMYhROeI0OdsFXd94AxP7w/Ocoj8b2KdVmrpS/HHY4yf45MucaeazrmxPB+Q6gvwC+QXw+8t/ejtH/xnizDVS/u2/w2Q51zhBPC0ElQ/I76D6AR076PyAwg66PqC4g+4PKO2g5wPKO6h9QGUH9Q+o7qDxAZ0bKLsP6NpB/gO6d9DxAT07KHxAbQPd8QPqO9UXtNsrpx1Ud3vljynrbq/8MWXd7ZU/pqy7vfLHlHW3V/6Ysu72yh9T1t1e+WPKutsrf0xZd3vljynrx14fU9bdXuVjyrrbq3xMWXd7lY8p626v8jFl3e1VPvaqu73Kx17nbq/ysde526t87HXu9iofe527vcrHXudur/Kx17nbq3zsde72Kh97nbu9ysde526v8rHXudurfOx17vaqH3udu73qx17nbq/6sde526t+7HXu9qofe527verHXtdur/qx17Xbq37sde32qh97Xbu96sde126v+rHXtdurfux17faqH3tdu73qx17Xbq/6sde126t+7HXt9jo/9rp2e50fo1y7vc6P5q/dXudXvdqCACi8evqPEGdufdSfwQcXrnjGnmIa020dIc/DcITTuVnNj1kHnbMIHmmGWMF1bgaVEo54hJnPfOii0REjAaPPklKwj19ghw0jAaOTt3xPiWOa3vL5a7mmm6xpxBjblKp+MX8t8/9mfTGJLL9YX33pFMPW92vsgPWtNen61oyCOyZd+hvKE5Tu5a0Yf0t5AMfW3v6GeoP8ETX0OE3xCz5L/r/PR6VrxgeJEbLV6LkfP3vucNfzc7LHtktzcbHMCfMkr5joxvQR2yODtf4rGEW/owjdohcRppgj5iiCxT/EfUQf/8RcoI+nLHfukqz/TW4ZJpuqSHEa6c/O8Sf4zO34r5nrT/DZ1vwLTK59oia3z2P6WdrH3HK0BNX9LSYsZXx63K22cNu0aVQ5dsp/UoI/5vr3pfyVhDIeMhOcDY/tR4LyD3TwVzS/wkvijtxf7e1fydD+QAaP43v8nTX+CSn+6fkDnOX/2/n/tBWeP5Qi/pu1kP7N85d/9fz/wOv5N/D9n0SM/wH7i7Kv###1828:XlxV32DM 3fff 70ceNrNWluy2yAM3RIg4eB0HV1Ak9x89q9fd7r38rBjHAOWwMGdzrSOfY4khCQQFG/6qQ0goB5BghDCPt7xpgf9xEt4RmOf72A/4miflNY4hHdonzRaCWC/IGqH0cq+vdh3ToKZpL3rIMjB50G6CHKiMSeQ09gtVItYz+wf+zSgw6PXPVjNF4vf4ADs8yzlC1+sFfaBI2KwImY26c/LLNuYss/9q5wefNhfI355D8X6JVyKHnjjpHBWjtbCo1tsUIUxEqwg6L9n9Zuj9e/EuvIeT+fuA6XT9zaeQp436DqqTgQdfepE0HVGnVCELPxspXi34DO14qN5kqoWOzNu/+6WLSVdR2VL0NEnW4KuM7IFYDw5W94tOCNbSl44ZlXLr6pjl1W1rP/s8TfqJ+9tclGgQHTbX5VtOC8SFEir3yVTr/1VqTdirBhakfuWAn9d6a200WJMeyeWk7Su9k36SJJSK8cKq1iVG3y0nNmTpSzo25WpHR/06MqCDed1ZQrUf6D/0KrF9D+cXLXhM7v9CivO20UE/WdHQaP+A3YQ2PmE5KCej7SCF3QduIInur6PruCJzq/rCn5u/5e2oW8HGLLm87Urr3/oWMHzVpxzajSA7FZBCroOrCBBS78KEvSdV0FKq16vCvJuQ+8KYg7ffYTIhOiManhFzJJtm7l1jMhTrwxKR9HLQ8rKXZ+HqVSmrCVG37P+btKan8WiZXN097rfIdWegq4Da0/ihuejtSdxy9O19px715O2ofcZxPih3cPEszouvvq43NzkYFjrXkg5daOCjAW//6Vh0b/dx2JBrkhiNQmrGXKdz0aStcutOg1L9VjegpStkoHNzW8aq0hY420wpJEZRowZhsdKNgiGDWks3Q+QifM0diXXV1eFtx0OMuTTcmNkzN9Y8EcKuzfGNEeT5WMm+9ZjDPczkpTVM1Y3y33HSoYN0o/NMHw3y9dkW2g5EE5pafExnygLMhaJ/lDk/J6xIxmLRCww/ACMuQ7rriRjeTmliuu6YNiSxioyFhhyebVxPsOlyx+IdiNjbpBcG+dzK948hrMmWvwFLC3+wlohyFhNjKWRIXcsxIdkyJ1vinXYd7/hoy8LXpv5V5Yrk1z39rHLFSzufePn6MvKZrPDhgzbab4XuEvk1HJNFRdXpwh8rmriShb3sakk/MhaKlYdFxr0QoNe1aBXNekVh/tqL4NLNlO4cpVHXK6pqhzLjqamcqiN1Xy2aWBjZeVRmwjhcSWzaj02+2h+ZC779TouMiPkselD+NElmuJDbEbMZ48V8xT3ilxfxz0p19dxD1zHVQ3cugoSnx3wZyk+pahnqya2bGCrJt2qcscWn18d7fNy9SvbTeHWVc74hJGfkZfqqhufmNZx65nrGaLn8nLKXMcdq5i6YHFutPfNyXxNNGNVBXlsbhv4Y4aGWSrtUcsV97LpIrJZ9Pfvb6lv4iqu8P3bvrui+PEH8HZVP34C/roa/LaD/1XYBHsz9Lt77ugulEb7zl0n4TSQ9KFMEqtB240FTtehKd6E0O5az6MWOQ7/tFwJA3kDn2GH0HDyg6ukddUQXAV65SoQ6tu1rNZb6YOqr2Cv1/w1jc49u4vPZ7jamzYlIn6LT89e/bbY4JVLw/h0NH+G3Nht5fiGJvhJG3IjnrPn/pKTPt6KvZiTse//zCgyEUrRGeZnDJes9o/W8YyG/5Yj3ewtEpZLcfeUkzHN/9YyFyUWBZiIqe2x6pDINPOSsFk418xpdveyPD1r3vfORoKdiVF5piL6GGHPx5WzsNIyf1/Fgq8Yem3DP7T0MZo=###2804:XlxV32DM 3fff adceNq1W1ty5CoM3RJIYLsz67gLSJz05/zNV2r2fm2wsQAJgXtSU1PVnT7iIQFHQsLN7uHQPz26h3fO75+M2f723L5v/92Xd9vfFgQ0/oHWGI9+RnA7zLh1w4UWAvLpAC36IH/J2U0Ogtz2OcodbUBoo8QiwV6feawLvyNuIyd9ACKDXSrs/hn2zxXWEkQPehpAw6GBXrQ79KWhMaCnzCpP7707Zj6fUn///rb+A97MG37/Rre+OfvrD7qPN/j1H7r3twW+0eH7Jr5uC2Jxn6QDDN1uf9lGsy0Giqm6rc1wtcBjJ2fjMhLlKKJefLEVedz8aDNpv+xzu9SEm5qmqCacMzUhPr83mWXTVG0Gx87R5IZgjA2VsTm0xQdZSNrSiOjeRXqiYQC9DGCrLevWsGU5LKbfW9v70Ebz2CiPs2OW+bEkHmdAW9j+eQ95K+n3rIUk7zbrPh35tTpw9R70Np5eQ/B7ausvHej+sEYfutbX1LHjKXaOOxqtsG/jTtr3K3acN4Y9EsW9GOYiH6VLQvhj5lE3lkU/EsIHxIk2rEYMQZuk1YjW14JuabYN92THHu1DLcHYSpiHvVbE3rOwKqIuqbRL/fpDC9jo97T6WkmTX0TpNbDVIjKD7WCG5WSGRjs6w8TxfKZ2opWodQ3962Gv7PuGjZqcT4ZyG0O5g8ghYyhr1m98FPw0pdVa74lgzYNxkLXYhYin7Ez2RGkl0tM+Y9FatPeRkXqWOQDnJOcv7tj3QNhhIK3jYy5e2AH1Tl7ITvbhTOTPOc9q55Jur+FjPPsJ6PxLa9gcazi0E9eOJ04g5k6gy53Aetj7kKy3illtOH55tfHY01Cluh+luhsHDrKE8qhUzqsqSu+/2R0eVTVdjiAshSP4tTuC/EZjySe4NT5sM25RAUGctMyhtyPnRB+INnri0MlZ49A2c+10tBtCmwH0NICFEsuuKAwHhU2/n1iOtiPWEHfUkMOPj5jjWAw5WLCxVi/CDmskkX5qRXQxUXMPu1pvyzccDnmXEsf6S4jhr7PAZzaQT4BwsFOLZW3zFOTCwbd0nVfAkpCwi5MDaVgp6kCWTl6JRoLwRCOlSyjZr20hVn5zJ7rswa5Z3u62sHu/pFElpxdO9OmgPsu6b49OCo1j/6zaGaX02M6a2qFu4GVR6vZh+b12A2dC5a55n8NTOXRQ+TxA5TPx0GQq9yQGqhXlSp96yOgu3VWFBRDVtBAa/8hp3L2P0bgnNG5VGreEmK1K4y30xKETIVqVxnW0G0KbAfQ0gAUGCwkr023EeeLTS7dA2z4qKNpUkbsoc8bvqhsqH97+R6nd/zi1W0K//A5YCKlZ4txbidpTLFW2rVG7fn75bmr3xzjknT0lhCd3IP1auNC6/f41tdORcKcmqtQ+JmlUScve2/ee8zbd28NL9B7H/1m1M0rvsZ01tZPTu79H7w9C7/4GvaPu+TaWDI/1QraN0Pt1Ic8qanqJ3qfzavhK17wTev/M6X2yY/S+EHoHld5BRGPInEKKbM7rZF+jN/ODs4cmMFy5AYno270QoqdoNhXDEb2ONgPoaQALzZQQT/S2Sg3N5HpPJvozey1d1aFC+pKMnjoaJf/x1NENB+BW6qg+1oGQNagxJZAYH9QYv2xbcwT0k27pdgSWRpJoEpJEX+y86hgfSIwPrzoCrbXApH1Ym7BrG1RnYEzSqJLw0t1tkD7WwSvOgE/BI77kDByzTO3ozgCU32tn4IM4A1PGcu/+e+tScwZchzOAA84AEmfAqM7A+MWQeIXCqNu9sHh8yja7fYlEZa/EpXhmyoZnqACZul0Km66buQxb7VSgiOacCiQ0y6HzChAdDQPoZQDrGCxIMyTxPBKal4rUHkWRWt+Ve55nB7WqYywul1r/ubgcCWWiGpEiictRjcvLtjU6dh33irabkG26RZB3EI3NkVByryYutG7D3tg8r8LQY3PsrMKo6XhM0qiSUUP36bhdOdFLx2XlxF06LitCKB0DW4FRfa/p+JPQcV4jOH+1SiltykqopU1i8Q2fldKLuFoZSftCiUua0xWTf5ESyrzSFM07R6DI5pJonk83W7Nw5vbspAzQaDEGn48aLW8q80hsgZWfm1dvtduFnZk8udSvJwP40tF6q8jNlNlYwWGV66jLjC9fsDjd2dXXzU/49HG06MmOvSo2ZuHKXZgnqQZ5ySnpviu471j13nk0Xb9mStGyYQZ1M+UqEKgKmA1xXzlsX/UMMCXXOnoaQENnrc2Jdnn9kYie017JKoqE2qb2ziJVS5E3noRWlxu0CuoG9N206tWKXigqeuul9wrxzOecUly6GkKrWMSlbqdVz75MmKRM9lH3adVHKHLelnvgoqEtmxMGEe2KDG+77ZGRTAPYOjc9N3LT9eOpVh6sIS/KjMe45kdjXPOPY1xkc5BSNrkmwjLr2qbueyeHuLeS09A5TkLvuob/TQRav+/ozfFiZ3bYChXlUOT8pT7vOsllNvauy65lmXtP8jLLnIcy5lYEulpClY88O2x6qFJ/XLN0U+WiPJXJqdI2vLTbMWggtCXLDK/0veP7wHtHm+4vNBVZYbpWvscS7ujqUEq6m5lfeu84p/eOZ33cur93nKOaPvPXJGCX772uL/Mq7LEP+bs6KMpYqdyU5GipqWdDm45ebsrxJbmnnO963fQY7nNlXzHSPlvXM3USNOtzDz3VG1cYHLMW/vMtUKz0Wpe24a810eSS2l5zp6Rn2J9Ka/mh82EI9xaHjn/oLY5gTa9yG1yF7QxHdrTzPy8HmnY=###2800:XlxV32DM 3fff ad8eNrVW8uy3CgM/SWDBLZvvmM+4LbtXmY3q678+2CwsQDxsMmkKpVF+nZLAvQ4HGGDm3qjhHkY1GT+7Z9hGBBwQaUmXNRbTSAA1QwAGP5iPr1xxNl8N6OzY7UPSwhyGH79+inUgl/DF35+Gt2vdfnxL+DrS/74B/D7a5Ef0PBtDeAx2OQHU0qCQAXCfE4Ho9NZD93R65pvUCgRyhArb6UU7kszEnT0ywIv6+Yk7ZyezNo6O3Hw1Ohg9O4VoDrsuFks1o44w6RImF5BmNb3B8YoTFBzlHGBNEMNkaPU5SgroawElY6DCt1Brc2VcTSM2cSg8041IQhMmpj8zENtt86p6IuyHTf//TfYa9IFWJsAKxfgIYivgNfHGB/YSlR2yYvN6dySpxtVNHp7aXKQKmoYsVz9siFRxpvz3jLVP3pPbaT6m1dpvofMSmWw0vt1Pl2ArPKWVNWS8/jirHbMKLLjEnMkyPMdZuZgoGe+AT0jARNRhR5BEF1G0jpBdEliKjqKE3xx8nbG5iIHn+tTAa6W0i5qbfDe3arZCUkF1WKzkZooA31j/boMmi5oW+cwg+SQZlC+zuWxHS21Xb7oVZl4NeUHwGtWcQ2qfkkRp7reowaezloF8byNUoTVQBfaRfTzsaVj37Hbpz5zbCYoNfWglAwoj6yilCxkpGYzkmLacwohPUrpDpRS3g6UUIpgbM4G610FTtPIbZnsxLw2H5vDZtgM8SjVWI0ug74JSo1RBuEHpmonlOMIWK1bXlNV0QYb1gc30AZIdg5PZ213kucogQQlevBGEdzSXWgzHmiDu7TLlRdBG93RjR0uP8AGqmATS5fT/0l61ObKFbCudmO8pmaJRit0Oe01Ic/3oVT7bsyTXtOEfa1HgFUQYFjGj7Ers+3YRuhrOlrpaKBO9NFZTeDhrh1BygOYjUge3pN171k78ZHHXSv2oOM44+qzMx52gDmCardzwsdR9Imd2doZGpqJswng/dNqx8V9zfqn3c7kc71nXco3SRhD6E241wTuVXXLkZktto5ApWZSZTFPRQ1rjDFe0+VuFW/5FdZRAzOHGvEKN7a5pnmvyuNEeuLUU2B00B+d8C38HMzpkD40Sw1/zuvYsRLRoTk+1JRRfGk9lTUh2oflEd8h9GXG8+cMByZOnA/ZqGbi1L4G7NCcHmqq65BhJZQMowPUcT9AFSwrG21DAdYLp0e4xs89ZdFeotz4qVOaNn52HFk4nrpQ/skxwmUh1zaBjS/fbiV+OObKSysvcUrzRxRJI1g8omDRwY+Tq1Yo4XKVL4DH7h4OqTwXJUcSm8nI7chICDLSxHfnkPmHaxvZ77bicZe6jgKz2IJdR8voH0bprp1ekp1e9MyINHY9K8vP6D7rnDzrVF2sU3vW2cfyZp+NqovlTZ7l9awLfI+AXV4efI/Qx8ml5+TY5eXBc3Js5jZTdLhYZpT1fWCq8kJJeKGs8k+eYcNDvXhEjku1jMhxFlk4pk2ZqCQMR96OVqrVvhIR7W13NKeHmnFHxDGqjN+TdaZMNO95jonKgg/ZqGbi1L4GTDzerjk/1FRJJfK7eb1GTk2IuOaW6V7Ziqc81rGRN+HHIn0Il75gkDI9IHaB5cdI5gyEH8sq4316VpljvEAYL1QZLxDGC1XG6/yw1BjvwcogU2dz4bR3KeaL6GC80p+0QRfjBc8xpH+HZR1Mjr1djgkZPunV8v3Zg2WSbLKmX/sUzP9yH9gaOpyBGvcBKZQ7N196o/sEMtXKynG/X+MvmfGNw/7I+Gt2fPj7x1d7UQ5dUcDf7gX7nSmCC3K1tf8O5m0SXp2bmNe4fscVxT62hVwDDTgaHW2+P0Y361K4/y2N3RDevUUrz1okv6/mO/TW/Io6R81aLc/MtstGhx/djodHxEbOFk6RtSgqsaySuZW2jaWOTfOct/vOjD6aTxhGuWmUJks2k37PeE2WyNp5WecFI6wGOhaJMK05sOSsVHOnpQ35ustnV98c8nbL83yKPfp/QsC4YXFHekkVJmR235GE3X5TWcHI3rHrcqQuCwW7gpWVN2TxhqzutjvcsBvL4g3/6htr05X5hodeVJ4eenn581Hv/vdN7fOBc0738sCdkdfE15RuUu2aLnbo8uP6Q/gH47bpyg7d4ZbuktT2k/yQj2K8JHjVnl1rgovVGLsWRFxvcRntsM992T5XBX0uhXd6OST3JHX0wSdPbNXI9uaksA6JpnMHsyFJQ47OsKtzfmYbG8+7DcbemH2256SdxPnkyUkP7LZzSajgBTuR26T80xzReG51AQx7x+NYWTC/Fi9kLvxkY1qUxuiCAHfGg0XwXJIbMEv2BkwbBOfmsGSeorTbQX/JiL8Twxde9dmHK0J5nTUJiA+b9HnYlB3SmascB+ksg+IkS4e4Mjnc3FJpNh0v2eyjulwaBw/t+LsoQRqTGzcb+4Yml8alS1BPNHVHwl0v+gjmrku7HTf75bTjEg4o6sevf7/il3fpYNoExxouINnTqdZeeb9TrdpXa48dQa4cldLg3rufZUTEKiKmT3ta41PS5Ech9lzqIMWqIU2dOZc6wSY4OsMVSHZMZzXTmaqbxHxjC50JYRlYwkIf1Q2EsPBboSKERWQJQdilXOvPvapb92Lt9Y776X4VoOxCHe3vnOCFOoqmTnhl4D2XQKd++yqDztU7XyJ5ha86aoZIou+QNkIkc0TX91MVosvdsI4rRDZQqLErK5CAoGjuDnOrWYOb2ut+kRfOhyDvICu+4WPbj+zMz1ntI/8H+G3JSg==###2892:XlxV32DM 3fff b34eNq1G1uS4yjsSoDA2DPn2AP0JM7n/O1X19x9wdhYGEmAPVtd1d1JJCz0fsW+rHOzfbmPfdmP9XaxYD/OOQuTUuHV6qz7uBkMTG4Jv214l4I834s4H2vAAXScUEJ7O1lt1/Avh4kh6lPsdgrYfKsLNvqExY6fGTcr9efPb+3e/of6Yb9/B8wfGqaf/4L99cP8/AfsV3j9+gYdfr4KYmF73EQwSkciHDgPJjzuekmz4bkM4TYI5wzoAK0v0HBA7xBug1hF6ClDJOiaBQox6V3hhnesdrqEoW85whHr7Guj+qowNuMliKQkxx1paI/uGCCc36EVR9MO4cL7wKgVgBb5QnMD8dTNkXOPTkk0bBKIZCblnINywq6cZi2U80t9B6P6akmzKUszIEsTdTfw3Zb8DuZkgtEeFLjDHHfYpOdr+EtZxWm8CUKSk4H5gflv2EFSUVb2dAALdgCu4PFr/oZpwPo97bSaNmc6bM4PyGmzkd3mFO8pks0J/HYNfyFrtM124R6ckmiIn0GETjL7wnbxLu3inWTGPi/R1OC36ua22vWc0m17evyk28kSGI9lKx+ukH/TLf/GePwyZA7LcMN+lyHzF7YYW3B/DRbjOYsJcW/3xCHAA0nt1MF3DFu/m7T//n1d1rYn3nyjYtM04KNlBz8SPX2amCIRoOgpex1oep3txCTzF7a4V2lxticSQdPDzQMebmb8lR7QnwTNpaQnppyS6kf2tWFveoLs643tCwpevz+CfRHyi7Rt1McnsDfEEBSNM3tDO+q/H3BqzhblmrptO3QbSH6kDB42bw1CVByQwH6eOfO6FVvTr9KaTMOaEg8at5u6Kewt7mp70H8Zc3qUbUxZz1Bu9wl8ng5LMmVx530s7szFmGKRpmG5FGnUNT1R3lWY2R1rEno+gwDDFM24NKpON7uqWTbtUxnioI4vVXu4YAVTzOlf2xRHbjhOxc2Q/7pKqlFebJLaywtTUPS6crVxUtKt+Jm9ljVD56SbvY6bbSaxKux65sIkZvgOOF8CJ49Avv0Nv52TQwMLR4T0pVsLEiydEN7VglwYZOex6sApfXgPay6scrHMWMhQbIRGiCOt02c8h0tmplBI0FAWCuF/3yqwRVvWVdA4vYA/SsU9UV2Zho45vMxRXDIhVHc/ibKOSfRt2fMKBfDu23YaVX4ufaOCMjEpuOs7IFu8EXxQj+eYsucA9hzfPid7Ml1Y1ei9FuQROXrMlXO0vmR6DHuO6WgBwdkCKuDfV11qprX+SDeEBk9P9MkFkkBPT/vQ5vbhkzTb5abN9KDVtvuYKukfP2fJ+vzkHL3791Q+wKMmokcaFGky4bNYvsVzgo2GcxR+1342uRavA2zyMnWrIp3Qo4HXFsN9n0HLarzQc9kizKMWjM8W8ay0zsXSdk6SwBIlECNyHKtcZPZxOn56nhVbowHDpiYpd0aQqCbjoGk257gilM0ginYgzRnzeJBziaRd1U+L7qMEVmyWJ2cMXElbZUFMHG9lZqs4RmrT54RGHaaP89z06G8NWVCrbczxYRX43abKCgMHGfMuH7j8c27mXkDSelTXZ7Xr7+kGW1P30rewGbnryCkbQ7ZtbHZUDO6u9jN1ST+ld+9oLrJD8S93RpTQ6K8x9eYlPdhztJW7MGrY23pB8r7dJerSS9yFaUepQFsjSt2MY8VTjs+LO21cd100HPhX+bRji75wbZdr1Vej44kKsNDZ5YqwvoKlbV1tktND0MeqRwua1KYd8xzBrAZ1bqwu2hHLLDWNc2O02RLXXD7AwB7Rlu7gaRQ1DYLWrBUe0Jrx807MeloVksuZUe7xQODpknhaDloCs2IzTBENntOA9xlBFiyQ5m6R0rSh1QD0NABrStjcigKquYQaUTwsBCfQD+tq2Dw3px0GbEFEo+k5CNs7Bp8QA9ru0vIprEtL+IJL6zpdxhdcMhk4ZxQ4DUr+jGA6J49i8sfqwb77sWaJrbXEyGRjRskGoGTDdN2Am5xiTM26mwVtENFNR13xgIamOSbPSNWut9jeDWvBc3OCOFUuUL65E+9yoa64y9VZ5uekBkYjICwjVG7JUk0lTuj8Ht4krrQtTbYlEj+U6IqjiqNkSxoVJ2ERiw9wSDYCpCIgFWtl3FYBdX7CWlAxhimhm2KXFlKG3v9n8eZuPLH5etw+aqyIZwi8fadSwKu3G1p4TIuOoBO3BpP+XluD1WvcGkwpig0pynqkfapIUtyXj0mKF2bYyQ1Jq2EkJr893dmZKascjfJZyvXpPZXxCBoEaFOdzUPPA7C2i+ayIsmwRXZLVz8aTZ20GBRZfBZnNDE6T/w/EqPz9L+VGPFaZdiJIq6pNLucK/ctuFXku5jc/NIIq7zuqoXNbpBGCZq6Sakd6vJ6wbZo2XmGvrqvxnVOZ2FvRfJ8rpJeTiKxvuRETw/zgddK6il0cm+qThidSJthfVqFW1nUd9ZC91+ePtxfaee56kU+4WkLwyc0r5M81v0E8/5U0aKp4rPvOPk8zXuyAWDRxN11TTnFVObBBJjeaBifTtLz+vENgglJyj3YaTCIw/Bgx2JGOxbm0RzYZk7rR1tnU9ZA82gnZs47Maa5PUlbfFd8wP43pdwOdVrhU67nQtlprfTn0A32fnRpbVjftwitFkB7Y1KrxXVFsBJ67Ksk5tZXSdYJFTdQfsEtXD0WN/ZS3ODkxYnFzcyGU99YauXX2vrLIhBUVl7DMz2YeDxAjB6mztGDqsqpFvQ8AGtF2GuJk3CUOLTlh0qtEbF+NPYaK4VujO5u9IjbNlAPIHsx6wUPy5QYTkh0zSWVJAoZ/mw23TvXy+V0zzHufx5a0ffNFX3o8jNc0k1zqkeWlh/OHTf8D1Ben30=###2488:XlxV32DM 3fff 9a0eNq9W0uy4yoM3RICYZv0Ot4CcpN42LMepXrvj4+N+RphXF23qtOJpQMcJCGDQC4YY6jwI1GuchFcCKkECMWYFHIWHKWR2P6fS3MrvcTS+MIVZy0nrOyq9VDwgqbFk3PUDheg5aHYjvIS0kqU2tF90d9fKOWCr00bfVuL/lsRJMRSAdIqpcx76xFKktsI3HOun62oNKZ9rlvgFkP3XmMYiVWCeXog6ed6BEa2po+r1UzHNdleYXUsMSvmmUilg7ngTRwupOcQq0h2nhpI0vcIxTHqlCn/qx6/SL9rWTdH8wAz7RFRkaSY/YhC6XfgVzx9UmXm7ZkpzxVr9kcc1n4yU0sTB6yFOyTNRhVpvqlH6hZrpozMefnLj+tKvLGz9ffvb5Cf+cEe4vtbt/kA8fr1R+DPg//6T+DzMa9f3dqzPpc7L42oxGoxtCipxYox+4hlTqIWs6ezSNrgdgpirWdoCRl6Rwwtr6/m8pl5DQQMaY/Qv0u5VH3IjR2yEUOVJ4iYgsJaGDNlJOS2RtXXCLnZDN/sh1GZ3KUdd+bbzp3S3OHGHftE3H3gK2bNXdgX5n2p4Ic2rpRi4ZTFLReL4YhJ0cpZYt/6edCXEKEsu/OZzhrzejufRuJzKq28RM2qRTGqMmLsCS0bh5C2WYg95Bl4CPDYQ6AUQzQ/PgO7ltsECEVJiS/Ld31WnYS0EoVIENl4blXnq6HTdpbnWfoJfWGNfYHRfGH3fjQeWomTcOS2QZwM7a8+9y/STLh1sKOvRYvEYr8pnjAV8hTI7Pddsd9pmxlANeRRGHiU2Of4dXgCx2iKVWWpOIL1e1tKXecKS0ZJnri0iOoSUZb9bMZVXizAS0iXjBQSDKguHkBISmFPlczLhaP2HVArY2pVTG3e3FW7DhCKsp9ilNn1uJdwUWbS02UHWJUOJUqZn6iSygl5o9jzxiMmfR7wEJ+vZRMcm8Bw+Zr8Wf89o9hpWrLxX04a17zJ6BYkR1nxU0xib59+HvH79GUSGfv1VVF/Ghz/NDj+6eL4uV0x3X7Flf736ue7EX36o/1P52/Xh8Hxw+D4YdB+kajP7bvtgP0PacOg90LmfUfGeM37+vTL+Sa/bH297csh7Xzul32VGNAXZNuFIns9+mpIv9Z/PsD+iOctQ56n+vqecae6LBeK+mLAdoy+zT4uj56unVter74a0k9HH76Z/Jj9GMn0L60ZhGEMnq1+HuPi6tffB1Hn4uIK2t8HTOyptw+y8n7dN5842AdV2xm8aJO8by0ravOh1pE8+lxf9K2kGXtiaCUPzkT+TfvVd1K6H6YY7nToOoNOX/0j/dwCOt8EhrRh8D0m202KMZrnWMrvM4ni2QYdqXUiRkWSwYnYVD17pOyhzcEe2giS9LuXZzjLMA51AyvZJT/ZxGucqm4nSFDc86SfzSp/NjuN9IaAQ9kdr+G80vVh2H7oFQI0pOu+kZ0MNjjae1Tjmrrf3ZozOg56HBjC2beux/bxXV7ncGAIh284fPBcYfY4MISz8wxD/eF+3mFwvvYjCbsVXzwRi/elr9gzHWdfD8v204PDNxw+hHMWoYM35xvYoUQNCjuU/pxH6GA/YyhTCPZVBuNzsL9zS4/gth7BcIbXg3Se4QW7gLeMjlKtdB8SZeZIK/RpjkfvT1qHdRXH2f+rOi4k+lrbjuhILTvCm/wfb/L/4GylOfvMV+GN4JzPPh3nfPY73skaby50HAo/7CZ+2E3eMQ2Oi47T8noqzl1e34pmdBwKP/ImfmQvP65aYQ1KQOYLJSCcUAIyd5SAzEFhFdRLQIJS3NmVeFSKW3kiQS0DpJaAlIr3VhaQOsWkTo2Spaz6902o/hXn1b+ndIZVqtAkHxLy+ypq4FJFzQpHld8PRHQCvE1dDUvq/ISvCtAfpJsroUStSo5Xq/kn/+YD7arYwtxNScnXcZ/E9B+xfDdHbrdtjMTe/zNpTKW3SquytPASBzavSidcN2rI36luq/bTs7tU9pEo6165vnDlh7P+qMi6tNV+zU6neErMbqXAlkH5J/qT62mb4vsopef+V2V//ZjCP5liTzUpj2N4Q/s9uD+k/0XNE5paTDtug4CmMlf/qkwlObX1a9i51n6jaaztGMUGdC754S23tNqJGmL6+1mpF8/k1oloXu7sWV6f7doo9a4cNQ49TooyuzzkUUl/YrWq2uYim8x5FNvlORFfbPKsgM+r8sz3nxOiqpHHjihs5FmHvHLskKV5h/TStX4sXeNcukY5d41y7hrl1DXKqThKXpXml9e9ibBnGK17brUSQS7EklzoQ8uFIMiFoJkLndx2a+RCvJkLSXIuJIN5g2YuBE1pTKW3XAiauRAENgHNXAgq59diIBuC7f7kliNfzoeSm7fOvjDIhpY4G1LCZEMqyYaEPQmuZ0OskQ2xaH2Mb0qXsNP70AFOb8ZCbbkft56/XG8zuBlOzlPIrf0PTv6yuw==###2648:XlxV32DM 3fff a40eNq1m926qygMhm/JEH50zXXMBXTZ9nCfzVGffe8DgjQoEaLtyew1+gEmRPI2oNWglVF60qifxhhtnv7vWT+1C9fM06CejNZmGPz/+3vL/Ue4YpT/OytjaxyGwd9blcu1qDQjIlozIaBC199b1h3dW/qojFF7Omccaq3Y9iq1t1lrgheWtuj/DW1xabtvo7JmadDQA45CvRbqh53eVfXDoh/S87iGXuGY9LZTb5Ned+p10qudHln91OnNVa1F6kGgHpNfetVKoHYiK53ISiey0oqstDsrnZ7Rrz3heqHGrI4Ksyjeb3LQPn07sxsnt2TV++uwXEd/x5hR33c9kTtcazOGv42fl79//4Dv4Wf40a8/vuXP7fnPf6h/f9Q//6K+/QA8Xktc33bPbRCSf1S0eIl7VfGPWtRDVvD+mY4sW54aDbA2xhVz7PBxVuYIqM2pKSJXNdV6qz6IlxR/73hJnuTUG19XvKcQGO8ZhGZcLK2Th0einrdzSO+wcxju6fC2xfiyPr4wxtevK+ILb7dXWM3xlnJwJe++7/h/lZ84iyFmo5eY+705va6i/egdX/j/ag1eC8nq0IOXeQ2YKWTebqI41bdmiefa2GUv2vZylmhUYa9dzOU+SnDugODcCYJzhBqG97u9eAHSe4qJH/z7Q/hhqLcs+A13ejzQQ3g78xrVozc7fVzjt3ooeC+u8kf9Q4X3KOvCZhV0RJ8Yd3nLOT0y+vrzrPqhIIShQ68E+pL32motUg8C9SiycxRZ6URWOpGVTmSlrViplowMVbXJijVW1AHvaaJu5W9LFPL83cN1m/wd864jXPcouU5BH9cheeexyXXIWOaaXKebXAfMrNXIDop3HZtsh0317ldJYjtssh2S2MAm23EeHC+x3Zi9fIXtIjGNsac33Y2E7mxJd9a8wuie7lRBd2E1D35RO3IbCrKr3M9Xp2pfU2KmTZuTFFcd6UvU1jnWRUqrj/ItKquP9i0KW/uv6R8MR5kQ+/m+qdTbSmYxhCcGtl+FU8hWZb+sNjz31NYWxKiWJ49rYtFOP7ramayVtZtOtYsr35l27lQ7jH450c6cbLfzCzPXYc3W1VlTrBqzokdtKmr+STrms8xrArUTqG11xlYrz1NRmfnq9JC8tdbMuX5itpsIU92LbPd0r5DqdogUnbxHFM2U9wyTonUurUABS3MVlnQF1g6exC/w5iCoxqxYwzui8UFQJTSOC2odu/MzJUWEmb1PcAsnG4uOsSX+iI3YgkXQSHtK4RFmIPQTA+JG8MeU+DMs+KN9TFD8iQt+6GmPN4riT+1+vrovdWz7/XhRq2Pkr6DRmXGvYVLHiF9Cpo6Rv4NP7/478amWrjuBZ1kl2uDyLkAIEgnkJb1PbQVqRRQ9ai1SS6xEkZUoslKLrNR7K6slwnWVNVlxDDNR7bYww+QdtWYpmncK9fk13+SsO7I5lY7K9BGzxS/Bh7EsyQy/L5y4gszurVRkQ7JemAGyIYmknDUclHGOrFDVjUfInj9GsejHe/bj+SIEkiLEttgGhFbm1ozwBZWld2iWpOqjT9uSfJqlgSv+VOeWFP5j5MwkcuYicubp5Um2HzwdeTWAC4Yc0sAEQxtTVQemOgGmuuqTaIRL4WRIOOkLC0V8jjnugq6TdidwqEs4BAhwaDZwCEsQ1eFwaMBhiX5TWDgzPsR+gVNcqZV1jSrv8+hc14nxSGsrOEHWHsl+/jxax6jfOYv27r+m96KDc2gQK0RZZ7raTJU2j6JNubxivn+sxbWuV2h5jJkOqg+VfUVBjaWr1kbUkwgaUaR2ImgEkdqI1JMIMVGk3ljZKD+4TflhnXngYS/NPDD5CC9lEczZM9ecHiT12w003iTQaBq7miUGUsRkOSEjJjBnuvSl00Q6nyaCC/AZvXpfvdpAxp55rSOjaiKjaSIjEGSEbmQ0BBlhjZsniZvfEhlHCTKuv3vnFjI2QsE1kRGbyMj99uOfuzaV06WgdDkorwFjtnoFRv8znQAjlsCo5gCMVgCM0ABG+AAwfqKa+CFoFFcTxfB4uZp4GSJPVxOvgKS8msiDpGOhDSIadAEevDduWdgsIdMIINMJIHMSQCaIQAZEuKb2uMZUX+ENjkX91Rz0LUFpJYI7FPkERT7RIoTVFYTlD/noVFPN9bUMjsjtoGVwRFIlxYOa4tGhKnNpJysdQqPHxewABBfKYsUT9lube3IJXZpEl+xZsaTwC5l3BmeavZSebU7PVwqW0Z57PhF/zIyqY5LqzCj/oqHq+cbXBsB+/+DWLxpiECgSBLciCB7uhY5lxpDBFqMZR0AHtZXq2k6uvRTzYw4Mc2k/2ZL9ZP79bXlkFHAsbvo7pmjdQdG4TjgS4lSb/etpJc6ZEOewHjd+X2VKlHO1RDmTQ2Hbvj50fI8d5bNlyM4xTpYe671/o9xYH+kTJca5woZ0zltFxrVN/qTxoLi4asdebbGDDcs71DsGLJ989KoVsZmolxM1mtmRG/OZm9ZR96juPUYf1YNA7bo/FohqJVDb7o8FFDl036uWWGlEVpqqlaqxu4rks5jWiSjyIYJ/R5a1/yCHUsU+19hLO+A2n3rSb1bUBBPUpiT5kJQkoSh4IV+UTKD1P4rEie0=###2820:XlxV32DM 3fff aeceNq9W0mW5CgMvRIg8JB1jj5AZqS9rF2v4tXdGzNZYMmAyepXm4oMSSAhxNcQIISZ9QukVqCE0KvejDa7WcB+NisYEInCOIqX3vVs6cDR7gcfTPbvYL8xZtGvkht/w3Gbxf7btQaD6L+DJGklaVjybwhJk1vt+E6bpdAlyTAQdAFSlynbcdwBOF2k2+chXbJ72Y0xGuRBS6y/HuubGbRfP+xFub1g6rQeLTnIcHx//vyWkzAf4kO/f1t5H5/i17+gvz7Ur39Af368vt5Wqc/LwbrNEOJps8jS/F0HA85xju8kaMZV/H7uXcXtIrgKZK5ylXRIkHZNYxZWLtaZcRZraMU6PpBX5sayQZ67av7gpvPg1i07uE29Ye44uAmJrysEjEJr1aiq0ahTh2kO2q0WhQIFH4XUUBRSKArJIWdfg7Oj+zmjY37lxyz7jnlFpoKqqehjNkNhVsMcFAQn/6nJ/S5ezuCq6nbQ6HZr1fUFaROvVccppMsm4iEv6JDX7JB3G4SX5kP2vghGsfchKqTifUhvuGTVj2+4ZFxiGQrMGgXmkdvj9/GdsABtseDe9u/AHKd/aDrsnS6VqLqibnJFFORX6xiTdwwppswz5La/jwCYOYd95+yC/s2lTHQYeNaTfd82t92SUxVGqbtVXHEt3ApQUM6PVMLsVoKGI5UxXujrm411rcULmWIBJ0c1xR0V5ZhlYD9urej02pD2XIqTYqRUT/B0ay6iK279BHjVjTdhznSuZj49oYmz4nusPvxJdl43YjfgrvbmIr9MOnHUh0Zb0FomTtWt6RZWkTEEfNoQsIQQIE0WAizP276kVAgIV/Y4gvCYO1c6TEduSBUUHEoij5tQBcLq+gI2bKiIBgsUJlFTCFREg2FtbKgBQranjogWTtm31KqDeumg1TmtNqQ9LIDwtOF7Su6uV3sGJY8o5QfXQWFBK6NcMuP/9xW4jecOHAb9PzrsdcWp4PFObpCTX3kODznpOAQh3XutsISDw6hCSvw+k5D4Lbiy36Fvjzfe0mv/2jetUJexmxpF6emAwoEJQeVFBhJPrRrzFYYznA4wUHXqu8Pu5Pg7bBKFSeGSp14ThUHBlaYmrBb8Ex7qDkwoLuMkcYuQDqq4NdQ65hbyfDfVga56tkTbaM26p9f9mJSh94sVT7twtuBAR2mjU1INFsaikIdhfqdYQ4H/Gvacfba0XouZ2Qc07CNm/nTe3y7H30qfFqsBOZDg8h04Uv0VDQ9EviwQgQhEdAZEFvG2WnzyK0ZpFSi2stiEotzImhW+KdttzYqq2LYnJ0XN2NvodSbycoXMRjb+HfnaWoC1lcWDUKSWNFdrQktfNlFVMyboMT3Hlw1cubm8bFB+zi7bGVaclik0nbJuQhPHb1cRdzq6/atKyIWm3d1AhGd7z6RzEAdq8IQEYEluyszvn0aaX5aZPfkQe1oMpSVbM/C004XWQ15J0MoM7NapdRf1gsA3T62cP8XMOFEnWF9Sz+mGZbIZaqCoGdm1qIG4fFj6PkP3/rqN3HkUFI/7VkgCQ2vIfA+rZhAquzrtMhDUlhgSzkrbZk0k4/Mm5sxI00u/rU+0lNqihjODv4Et9nDUxPvMvFqypccQNKcfhTmW8qqPgkoWnIbkzOlxGdmPSo+ULl/uwhcryDJZZxqQIkNfmm5ztJcJdSpbKjBD5UZAeE4NFEDPWr0EM4QwDdrRCDyZkx+W4ER2Q5On3qeT15ghr5FJlxE5KnmfHvIaSGVUyfpMk/chn7mDWHIY/o3FZiD6N5kcV0OT1TbiPLwTOqPxwOO+sA59a7Ml7dPzYwZFV+50p64xY5MP15OPd3o9l1ZOWsuYfG0/aR2mZTCXyR6T6JkmDbmUsnUVydQQRdU71YWTtGSl0aKqdr9agj4xbO9aVPobaZ/8K0lfkJq69n0pn4rc58hDmhCgexFlJ+LkLn1Mp57InChjqpVTTkV6KNDk2pVSXtbnpeapYY12CbqUiWF5dwRJPYcdl/dZd1HXYzjN13orZe+KLFLlsri7aDI33VRzxiyfre2oKbrueZ1tNu+jvcjV2dwhRteGm/pamGk4t4/ndriO+e2kEPeUKNLUohEc1GSY2xqiyo8oWOem4ojt1/REV/aXVmQ75WlFOtyLu0QkJhmNM2BiqFJKJ8X9ydFPpWsCQW85lEBqtCMYSirSMCibqLeUMWRKuRQLleE+7HFgKd1hWZl5uvhmig98QDWVOuzapI05K7AuHEphw+EewuHXVsyIiGNGRDfXribU11dcWEwdfTyyovgmReUFEtVXQCG8VseFrfjzinlbc4BWTjrvaOOs5zp4+lA+XKc9S5mqZyCqZwBNOrVg+lZOr8szTtlnm3NE/9F60LVa269pMDgJA4eVR3Aa3IXpqnHzoXAZeopT04/42UjPc5UqPzeDrOJ/rHObVNsbkUN3AfqBCvf7q16gAgio6CGgcv+LsJ4q6s90FFo6JS1y6jXmtn7LkvxwTE5Wq/YgRFoQ8hkbaN8FCJlbQcg5XsGj/dZkdcp/8JbxTWhQFP2sjqHWqHRwS30OXDo+hQZM66sIVMyoUS9pGHWuDKMu11HUynjpkrr+jsN+t4WpblyCoQpBEhU1BCrlScZCkHjSUGmRZXMFqvtMuxwpzQtvqlJ46x8opeX/9DhpxdfZgcorOOMbyz13a2ZGJa/tiraC9ZN40CYFW4mTPSYDYK63jx79APLZbmSDf/YMgebtNjkEzuhGZz84k6lBOVJLyJv+2TAp0UJW5WeyhdwLgMom6XMAxDXWeyXVakf/AYt4p2Y=###2936:XlxV32DM 3fff b60eNq1W0ma7CYMvhIg4aFzjhyguobl22XVX+4ezGSBJcB2Z/XqVQshhNDwS7XYFTQsSiHgE61d8Gk/7tMHZ1zddyu+3f8NAMyO5uk/a/dp+x7txy5u9ep4GFDuW4tP0GjBbLQHHvqwcskr3/gG41ZC5mI2Lv/++0dP2nypL/z54yT80kb99Q/g95f562/Ax5dW3z+wwqNgO3u2pRAfay1GEewm4nYo9iAmU3hxLLh/ZGqVKYLwx2OvRLmvWkK7OBq0uqQR5D5xRieT8UpU7LqdwsYTBGp+F0WoNXtGA1Y8pRLPVqwOmgBk+KyDfNbIxd9VMB1wpqMh2g58F7YzT/gDk+NMrcfA5HdDb5S2ca/a3yxdCXllsh+vuWhtqqJGTw2ZwpInVFgbGmtQR204XaV1+blBlrW20iTTxJ4A/K0xJ/sFHnCQRBM3Qc7LWp6ziZ26aXkoykp34W7PXlwJjZXj+kHvdI/6wegMMe4fHOPRenTeM7lORTybGrFMRirrOfZvLUgoSVWf4a5U6IPPiFT8Pib5vPyiPTXrIRO1yRSSVEfbMzmY0pfJ2Z4SQ2jtzefoHyRt+/0ihehBTkkHB78mvNzmrarfsjXRf4bzrJX/7L/XjraLc4mRyMcZcN+7v3Zi93xqd8lTGff/D67uG0+7eUWSRG3cPlZvf905uL87LhuttB4/slZP+LKQ8F2JoWElST2r1e2kNCaa203Ut1D5l3beECzx5fMPYOTZdXJNnufhBfaS7TUn23AjH9I5rwIvWbCB2m7yt84aoP6/ow03O9+4Jx0zsyDJJN7UdPpEl/lELvoWlxDDX14avMEn5EovL4+9YcfBgwR5QOSjfuU9mPrlShEy3nuLk+py2vmUGjr7snT03UvOHXlOc/9sRCIY8s+uMmv45wveu+Ce/l5I6m1Ld/dOa+vSfNPV3MkVtLB+jeu32jhmJpEXX0ljRRs+GzZTWk7Q+hd+gno6Qd3I2NhVxLqc9lt6NSO5W+RBql101e4jFrsvKIpdgPePYzRXxe7uWupjBCc529kfhAc/MFPsUAkexK+hEgwIUQYdWsCKT8CdSt5iKj2JRQV/Ih7OSetMCecIMEqiHoNRiOPtwCj2UBR2TsNBWSxcgCWolctuJSZutln86ENJBoeC9Bxs0l9pLq7DszaSi264uGMrOcEUWjtlg2RFstRHOaYhHiW1lOZcT0pGkqSRpGTJSYm9lRRPOYWEW0ntTJJavJXUrlmiO8mxyUkt3Epqp3xf5lZSa3JSiylAWYLkf3+KAPVUGxj7EMJeG4qxrUQupWnijYY3JIZqlrIFHo1IDI3ks5/GWpJ8TrcKTYyFpucT7mgid4Sv8o5m6Y5W1ispEm+NnArFeGtEMFouyEOx3btbMwRzUFruXaw3ygVNbszcgBhwP/VmBeHGZndjU7wxvZT9sef3z1Y1iw8rJQWS65dRRIn6XDbb2p2vYvVwVwlzVwluPRLIj8TeMAFFTEDfkKeuPKlmFavZlCRy7df6LlMPUVXrSmnJ2lTfH7DQJ9vHVA3M93kKbVekeRzQb03Qb3XyrO+Isetuxcbbqhqx8Vyx6fR0F/d0U3tyteXTfUN6urKpPAcim248QJ7WCg2HqTgUEoCeo172grpoT3DUEGWa+ryL+gZ8G1UH+ICuOxbg7DrVL/eZddOlVQcg4miqnIzE9MJeM2mH1MAL+Pxsp2u3PyVYKXMRYaWwvgErbZ+GdujzaEBjw7tc5IEf/9wpcL7zpEC5qf9PgfPw1FeSVz118dQfr59GiK7fKIiN8Ksh5bfgVQjWlrOcO+eBGhYuuSQQt+P7MjT2IDnSs5ohes+bo52GL0CLvX59S3k6K+9OviLlGecL9zUXgvZWQcnz4YOZ6QYzeyKY2aFYTecQWgNseICuTDHvwAywSZMFcToCGmBTz/7SDAb0dTqYm01Dt1NylCZoruhxqjRzXo9I0fBv9+RtfPIWyye/mO3JQ/XksTFUNxPU1HTQVkPwU0MGU/g2OZA2uSHYQqOpTniPoMhkVGJfmfMP0VPnvEO6Rn6kTdSfz0mwNewVKWwxwmhGTsPqgavYiYz+9vrZ83wnsuaIyEfo8VGH9ASx4URHRhTWzCcjPk/3UJb4UB5lZmLmdWsbaWlGsmMiVpiVU7UpxqS2ddVzAySyt9IWzJHX3FSuzcqVoVM9AAjrPMlqbxkNL89ZPhRzwEZOMQLi2wziNzUUTt+dix6yrhN2qRnXZRuuqLdqZnCXwsFG6FNC39qOMqMKEWLVZ6QbGNBPHCyJtDKe1NsvxWcthbWOL5ECoi2DLRfW2CBta5Rsv+PgFl/OLc4JVn2U+cNrOcKq9PcMPKqcsA8jDztHDMN0kfPlAnJOJbzjOiicdtV1nJVoDEFfLvOhP1rQsHRdmcrdNvlXLaO9BS58FXwudTmuSCJCxB1bO858dPYWrJvoP48ejQCugqR55CgDru+9KPhUrZLVwwA4DAPwmphONEwEGEHSyIYmbSfbEKsCd+RX0JEq6PwkSBMKW9wPT62JnmXqjvbydJF8l2m6SOXTSxKtu35Od4l3PEn3Xxmz+1pqQ7jpy8AQ8VgoeKy166/S1INmRqWpDjsJXPZ6uXr4kDCp1nLobNJb9bAwYVJ6EgEjmnFy8frd6FhRCv8pohM8NaUYgU7HA1y7OzjOR5OmPjOtfRZyvhzWMF/wndPUgLI4v/or8Pw52+r/Vq3dLcQGb1lfzyHnoqsu5xVJ9OH3LiSknvgtXXfvyM2QFol8w/9nm0f/UrOKmWM+0Uw7rjbd9h2lNAT+EtqDjhLZWWkujOLwpDSemJPG3NSdC6iOo11Y2vkIAu71mf/0He3PjK731BOZ3961KFH3bJvo1Ic5o2iYK39IDMqDZHYgzKUtgGxhugcx/CT2sNpAmuT+D98MnQc=###2752:XlxV32DM 3fff aa8eNqtW0ma3CoMvpJBkofOOd4BqlxVy+yyqi93f9hgZjGYfFmkuy0JIf0aLDCstIGAeZpooQUQCUD9DOfPEuQ04YZvQvrQCvNJi/Y5Hc/Vz8DSTvZ5jXZuppQR5WJ0hYBSGspwVxKEpfzgRp+IQ1gqw4F7hWOyVCcH7opqUTRw0n0O3kMqSsv/ISKlEUlfhn0a8FtuBHFwuqeKV1Ecchpkl7k/VHrqditAY2UNdnmuqP4Kp619+zq+5eIzFJylZN96GQmaekzG8VflUWXFFfdUiqIR+FIS1pCOkT+mi4Stwb9lD2a58XNy8vvM78yzEa3qn7LFkQ/MGqFW9m9qLYh/V5TaNsuAFhpTWg8lckCStvPp2zPeLupXjGD/SR7Bxipqx3///hazFD/TD35/K76f9+PXH8Dnj/z1H+DjR+D+VVIFPJJo2bJomE/d0r9TNuIOGQvOCq3vIh9rM2NZrOB8a0b55uX1fGygl9uhSj0l1AtIJv9s9jmXfbR171iR42v3oAyi8RXJqWDutMMZA0i3pehdvC4pGrtSYXfR2F3eIXafrwO7GGBXWZ71vfbKacdjvbBWe3w+RU7LJdnhxd2yx+na49FvZOUknshWdGnk6Ox3V06QLZhdrQ27Wow2yGrTZp3NypmL+pw0JFiJvsdTLx+rvIt9AJmOqB1X72zn0bPi1ruiygeSWVH7XlO09TrtfCf2dHSCis7ZROceRucDjuiETHTqNZL+I+mOMzYMO2P1n2SpV0tBSus3a/V5CPezxSsMRTPYaKYBOcJGsxyKwiu3AK28J8wbB5clZWkfWsukh83FsGBRmqPM2qQHgeZtSzZwhT0M59UR3cn1cOjq4DqFkbZjbx2UZ4zrnU58vjIezu8agTryFYcSHIo+tNEnBvCud6JrshiKm7o+bdkAbTYY6RHQZgOq19KmWMzHRRFlJqOLalUUBYSUq5Rgog97dTX1VNxcEa9YJVcVBYXBKvf5e4iMglVac8SqnWXsSLNYML6h4JMxFTj3y/y2oOadNbuCaqmRpfZHZDXqtYMWY1qTxnK0UNxfMkrTmoe7zL7yQ5mf5akP5o6B29sNV6zEfzOa46T/m+GcH9TkrF5MASasiikACiWKfO96SAgHCl58XaMaEpWRQtz4FCPU6CEbvdk6LPP4zbAsGHKd8uIxV/J7dszVX5ImW5LkUKldbakdK/1kS61sQiGji07Ys0rYZBK2jCZk2851V2fGZ2sJZVMpnnxkKbRyxFDPlpocdRbor0SvrlkLI2e+PfnZgx1gw/RzcsGZJBYrxU/n7Awr9dNcrd0cJ3rpSTbN3i7OI+GTx3mlQZlJLNKbHRpEMNQV3Nn5Yxkbox1fGfm2i9LBtbhuaItia38esUWZZkhPahdnkezOLpStF4een5fOSHL0t85SAinMWVTuBFPnALc//wwxlwOy1sgimDL6kelbS6eDa5NFy7aRHbbx3z7hps6xlcS53hpFERetufYAg/LFZSlyZxLZAmb1uJl/98QOZY3cGYkMCnOvHOGdptnp3urOjcQjDN19/cIcxa1bq2eyYpFSmSjJ2D/hmpf2bbHMoq5tLgOsrdtQlD/p6/WZ1mK/zgC0zzbnsw3DbDspn63NPpOez6aqz/IzorkhK/i0XON519Kae0/a1l5LGxzoyG3ATnlPPfiTrNxqJFRfcWycPzzMiIEwR2+EX4CMaYqmwtimtjnZFObYbGZkHDUPgQ8t+OYh8M1Gjnfw8nQuW0UU5tsXtshns9X5eJEwh9X2JSUuwotXhMkeBHHUeh8iouYOuNjSe5VVqjcbbIvE0Oo9p5rnrUKFfTpqWblslfe2qHqbbHEYRZ9tg90hwu6hJjxMP8aS7YFOXqDLaqDLzhoaBHoVDtQc5NRwBtFv5qAG3w5ysskC3ZvTy3PXM3DX6/OFpdldS7XhFtWGu81d0JSXl2aXLR7QRBVo3JxnpIVA20LIgoPFvWbt7Tk4btaeLVlcFEZNaRYvUadZvDA1q2fxxlfqqSOTT14mF9VMXhqrpZlcFBq1+8gJm8a7yEF76RMccj4ectYwNbx6UsNamEx5kChmcj7AgtTQPXIvas3eFUnTApfQlqG8v1jniiHnBunldC5MzrkY3aqZIH6H0zcRIfKNthMUj0U8zqvaVjyUuwPJrszcMPC5TMk5jj+4N6jkZqPmFt2z4Ly2fbciE7t1T7XzkkS/JI2U42bvRyNlDhs6nBVSIMoEArZzeiurRTM+d9eckHBe91InjjqgqN8i4dbhpihlZDD3dQb8QN6cbB6Qs3hzOzEgRx/LX/fPYQhh6M02YQD16NmIBuQIPzNlbsJ4aB66X9cup3x82S6nfFPIj57a6dtm98XLocEbRz36kDkNRNY+0GTn8EZWmh8o2yJiw0gptc0rmZZl7yEyGRG8CyMT+7pS1dteTplu50Pi6l1l5IZZvvMEy70SMoM9zgpL9nWT0YmZM7dn9OUmn4gm1O2cMouGlsoKiU027wS4DUfSTGD0Naipgh7pffVC3hcrrb4sUbfsGLNfxLUg051FwfEdiBDmqnn4rkwov3AcP/OtDlSPBLOcLDV3FfzO+sgAQhaouSkxA+XikWj6weLW0aDnXqN62hfhlXgaktTyIV5T2xEehd6Ww7V4vc1CS5Fva15mW1TlQHEu3wXrkXN9NCSHmqDyJ1U9ckofMfU0U//GPtcnrtcdt7uR0daOi+HLDz3tr/fZzP/RocDp###2832:XlxV32DM 3fff af8eNqtW0uW3CoM3RIgYezOOt4CqqvKw8wy6pO9P2wwFh/xKXIy6ZQlAdLVB1kWAjd8a9S7XkHCpjcAUELgE3c09hngrrVG+8xEvx5cOypLLezvYJ9oveIrk/M6qLSMaRjp5Z288QnScu7arZXvQZ+/j5zDyVTDfKW1zbQMdRysIEMfO9XqOD3IivZzTjzP+AblOZ0Udf49pqdDRs63Xnza+P2p4v4G1/PS1EmRr2eladAmnCpfDwfXc9K487XXkx9zqtO66V7Pk1tOqHJuRU70nOg4vZSyDRSsBWr8wGIc31rgu32mfDLzIcpOeX///pYLwJf4kuLntw02X0b9+gP4/aV+/Qf4+MLn8mPFrfDoPOAZHuwBHSSBU4ynsAHKOgswG1yaxuaOtnUbRLHhETpkxNSlULOSIP5M4U6flAOBXu2/HeW57qdy1iBHTcmRh/t5STAl6USGl4QVSaotiegIJuTIE7eXlpBJz7H+XkVJdwqXU3LwRPHr1LWekKODHDw9ii87WufCcK45OetV4qTUQ3J69ANd+lmCfmBCjjrkeETrZnkHzfJupNDiohj+g0iosjicp5hy9FNja4dCBj5cT2YaywuL2ZLrym+uBFIfrrd+mNmgqNO4jFGkjFHNMkaRckQNa4Hn6zlNHzrbORY5KwxIkVlp2WtLzeD1WH9B6ag6rzDlNYkUV7ChLdhWV69J+YwKNniIo2CThYJN+Zuhu+FAsr0ydf0AulLe9KRcSVLuXIoTIRUsU3LWkAr0VIprlwB9qUmH/RzUyj45OgOHFBuWrRRBf8X9tGr0f0vrbGvCk+14crixXTmVtWt5PL33cnQQLIel5fjtKoLFD0Vbbw/CJaK3dwAgN+rYXSydpZZnEMnvWTLIUIXCkPBeZajmy1Yqk+u31M4JTGgVnhOr57y0shSokaVOd1Wjhi5bafa26rtNXHLl7/uJlZ/FPgajK2LbNq6t9Sq4/gD1kfTreXT20+6yufbFS3Ht5VqqZ6XcAa/XMv/xzP5w6cvLuuyf8yjHY+kCj+cv+x2QIgICX5nWpLS+cCj7sxyi1kPUbKygfC7Japtk0SfZb4iS7HP9gSXJsBi6j5l8ov0U23h1HoOta4VfmmnDmtcV2OYK+7wVx4p7YHY+uBdsZn1f3mW5MTvTmBxns+W22TOui/b3T9bF4g+uSI2fpii4TeaD10GhmWbxrRZdbUq7BuWnSnXcThlyQqne5KEga2nr4luY+r4faoqV2wR9M3GHutkQeGwTHo2kxSl4j/YGF5VrS+twqsujsVvNyBhqmfJoDOBbpsC3eDlwm2y9Tfb9iE22cSZDviBkCizHt3QUQVUvnSglWzvn0n95L0tT2TpEjFnjy2D8kDo34mdx5tyXkTBsiJ/Jpp8dFMbdWHmvjChab2ZHldqX23qUKoKcnrwPXVHCVEBfrzNVd3yh74kDHB4EDkvsw8tI2NUEDqoJB66Q2nrCbtODdbdKNBNJ5gCyhTwNEyFXh9CN9+vAbxJyX7G5vsdCrqi8Dc9DLvN2uthjykJuX+VbiQtlWq6o+dRwaYH1aaRxWnG5MlS/T+JnIjLc6/UDptvPVjL8oHizVf0MK4GUBK6mn63dfrZW3jvn0YELdWbKK00wrpwyrghygnFf5DoqE+s+Uuva9a/LcXe1zjfJBmvt8iW9SFm+NdHd62Zyp9T15J63hilvvRV7vduTUZAZlQKXlNuub2rXdrG0niut3Zd1yTToJayT8wfUtnU5C8HPWmnitCZCltpZJlog0S7uNgwTTS7qhTTLVKXFU7VYaJuFC89O8SAjPEj5/DnyEufq4fWoZPPuRW3SWTdCzYK7EAJeHSFA1kLAqYC8zeL7kb4zpkOb5V28dV/UdPaPvlBmw0uksRxw5UCzddQsyOpx6xhsuAYtFG4TwUaEYHOVdihucO3fMbaEvU5vSbAxLHRFXOcXuLbkXkG7++n7MEOc2O63gS9RXI/fpS628Vayy4AvBjHkTA3EqOLuFNEXVzCp4kzwzd0aPrmsDahZDW+jchxq5I2ax9YbkTAaShBsQ9WFU/S9+9BQZduv20mtkvZr4WrDvHfFnveuwXMWVgqMJfvCGSDpXZRLspwPTxRSTfFRLreCYazgqItpisgooZTyvroyxF3+oCLYMklEWvKIlGtOsaNH9V2Oz9fXdcTP9ZYsIYklZNPKstL4KGukNtmB2exH6/o2inwVkA8TUjBMddzXIASCF53gBTm8YDyKVB2Pwo7BJTkRW2TQjZrQzealcDECmlfdjUVdrCl+kBtdCWwxWh87q/nNPU6HXV7bOTbpsHKMSWmPlfhmJdf9yFvYRAuQU9U0fVJXri6GnQLS/2RgtisfBX+aw54J2JNN7ImBL3BKmlfsF0cx+ng71dEHBH3QRB92oI/9Kqmpk7XIuWTzDTWdiK5piBrS6QwEkhmIR3IXVaqv8qtdpGUpVoW8yPubIVNDpXkjbNcoWZugXAHAQAUA7EgsrxdTjJd5RXwOP/sbFO91xt8wZEfnetTrpe+2Hx1nOZXVZYhm4YZB5ja2Pe6BmZ/i10cRECqBV7JdP1IKdoJhGQDDUhlFysHQDl8qcdVuJ6noBqfSgAw9UZgs88Inr4dEBwhzp+4tfgclH+sReHQREzQliMrLY0et4wtY9eO/KNF3zfCMpvlED58X3+G7GDnlqCo4PHakD0E6oO10LYi2Ry6iG0nX7YsodPr1xtvbB1Tuyxjkk32VE5kh1yVtmVQ1KrIGy31F77DWTe18jozabGlzcO25WrV9qP2hbjt1Y5dVxy4hiuBKttD7P29Trsw=###2920:XlxV32DM 3fff b50eNq1W0uW3CoM3ZJBYOzOOt4Cuj4eZpZRn+z98TMWWOJjV04GXVUWAl1L4koQENOkQQNIJcF+Vqt6a6U3vYCAVa+gQCUJDV5aPUGw0pAkvLR6qk0ZKwdedrPjJGj7u5VRWi/qlY2W+RNitFvNYj+JihZoavFr8Hq8fX///hazWr+mL/j5bUd+vaZff0A9vuSv/0B9f83PHwD4TkqfcTplpwO/kKdbkp3MPkWTP7PJN/tU2VFQAIe0kLLn5UM+R6GFnh2NtYYHCJPp34fpz3dm+rL9WERbpstO0+cB02fS9Pnkd5SOXPr8+3QDwAkBKHYAHwjAxwXfgU4A1wEAV9J0c8N0k0yXh+lPZLrKTJfixyqvmB4niksuv9tP732SF5pkyfF99+CruvCVPgH14Rtkzxh5p7iMsB+dMNa7+W9kvs7jU9fic/5Iapq51GT3Ben3AjalRQnNJDKfgm6ApRJYcDjkhsCSF8C6l8xmLpklsKYmWBMDlrkFlkFg7ZlfTwdYj+0CWPcS18wlrsRJaLAwJ5kYlsF7lmqCJZFneT4RwBIIrOcFsO5loZnLQiyBO4PVQ8nGwdIIrORZ8gBrXTq2RAmLnTC+z8s5K9NymU5hLeN0SgMyfe6gU6Xp1zJQ3fQ+OkXrGKdT/QBSdEorBCBc8J1rWakOYC+d6jedolNaH6Yvzw46habrplN6RvhOHXSqxPdaIqvhO0Kn+hGm6ZQ2CONXRx7fJxQfSU1ikE7hNzxOp0bAouiUXhBY3xfAupfMxCCdosDqp1MjYJF0CvUQljzzPyxYcxOse4lLsHTKaAOKAEslsIKEtr9DBM94TlH6IvgWy5okvLg2sSlUBrxM0iY2hSTDQCTxMtLoJgORiIEkz0VdjSXfRR7Q8zLuZTlRoWuGoGt2P0Cea1K/bX91kngR2aur6pan18ZRQbj1IgC9CLm/CNQdEY+8fhUyxIWWVolVYSd0k6x+YvCQzF5pem7/SovlDJOXdVMb+rmHYPO6pHa+Lfd2oPVG+83+ruznyc+1+Nc2e4iwdK9WB8wjrMe/FAuxBWeJGgrpNJ/JZVmNqiJFyjh/8JbJiKRASBYy8fU1NCUWkcmFVSqINcOyz3L87uStu8hc2ur2nzt1YOnVvfn9F5evLLoq5KHgbq4jZaK7ibyoBSV/XKTZ2MeFkpsyeP47RodEO0xZjgVpiXYYOqnpU18kjWSluUq27LSXWvb8MjG69ZgOC6oms47w4w6JiBQj7XKUtTqXto5FS5tdOkroVNzy0ipJ9EhPA9LzgKw8yWIi58P/vJomnfMkTEmswf7TMaSTlvQ805DG2w3RBe/x9AiZLu318ZuuPR3x2nfcuehoO8fmsc9Rp0BBj0+QWrDnQXj+NhJ1W8nxajt1sAzKHvWdeCJsS6ObJ1xTPOECtDps0YR/jevMvuPttYJxfR0h87x2PnBZj0p6gGywLyc9nZ092kf3yHRFMxOdajynHlkhbFTuVEPFjWoV2Ual4OEKcU1uVHQB7UPEhQfRkA9LE0lCR+m3T2m0tE4ShzSv2ySJtm6IK8l189J6SHodkFZIokfaDEhr0krJSkOJIHO4EqRVktAoOUqScoQgfB/1Ghuorv5UPvCftl6TvnzfCl1uY/TPI0eVfoMoN59Mn5qVtcRzdNiZbQzWrvnG9Ngny/U52jrwM/tZf2KOoCfD9eH/Cg3eVse3JZv4UmNOi2a5SpNSPqfsdA2IkjKM2+kaICoIRKchp4I13cuJCvK67VcvPbd1e98Rfhtxnx5xvNrHd802H8QTS0d6SEtj4tmSngdk5UkWN8VK4hlX09Eaq1HDpIUlnmF8hTi6T10ztHVUSFmUaFaXKeqeKcLyqlN2rbW9Eo4iioKgBZ0lIRPl9xNB66uhZaWGTi0bdONgW/OOjV7cOcSE2meYnK77Ba027SaI8UploRhpkvXrYO+S5DSKt/MRspPFZeNUOW5eUIxJUpZey9Q8oC5jzNuavCpp+WCMcTN8Isbas1zUQUTHoRNHgyy/4+gIPo0uhmwm92kzO58WDZ+WTZ/WnT6tkU+LTp8WyKdFw6drFzWdbHFNs7hBQK9FNO8RCKbhkcazY0abH4fGf9H8OLTfaX60tV9vKLTjoVrO+3iY3d2fR4gHMxVt0m/XJp2L6jPUV5J5X5qpKxRZpY1pgWqpXsuzcMrpvSO1r/aujFTkSCBbA7iFKZm1LsRuxUv37m2tNZnIJcn84VEwkUXyt0IG5utufY/pALJNM6ZDAdcCg9RmbPOd/HT+rKXVADOpAQa3Gmmf0RPiylvONvagq1Gp0lV8uKEn5JnXfgJ8WU9A5VX9LwZ9jU+T1qOYuh06GpbF/ShGjxjWc45oMZSRJ05HamtPn4nH1Oqf9n0LXcPcitNkd32pzePaRwJLJ49bUH6l6hmD9gr+ECnIQnmIRN6pEMeB03GjonHgJMgDJ13tFRwsRd/oFbR52t1eQRdXG6xjaryqXoXf4nztLkHwf3SzdsvvtQh3arA2vF917FSi0/9FVpUAMUpXu1k1T0VjYiTUxkwoIvoqirJSNY2Ke6yi4LR/pqLgtF8YT1YU1AEhlN/PFQWgmxcqvywo38aVFJCVFNkNgWppqYuUzIxkCuRd+lQiV6WnAel5QFaeCnVdypKNaotCcnS9j05HfoK5a7C3J99HG2E4jct/3vKVH235nhDn7xxnrY88beKxL/I+4KvrPmBjBSyZbWN1r+XMWztGtfO7Bdda1+d1iOY6zN6WY60R2Z1FriCaU0EkWT1LBypLQkWT+WRt3hhTp1vQbe+V5MVbQAf+zwp9M4O++o5bcSLjCqV8nbMRua0u5Ssi5ct0Ni67r8/hkf3X5wRzKW0duD6nSjcadLA1OZi+oad+laY/bES8LW0//w+pONvH###2968:XlxV32DM 3fff b80eNq1W0mW5CgMvRIg8JB1jj5ApiO8rF2v4vXdGzMKLAG2qxb5XmRYkkFo+JIImITQSq9618rsZgEFk1lB4G/1fv7f0gr7/9vM9gnoTRuz6C1I0FaCAlU+sZ92PVsecHxWEhiQluZ4ZlmEl6dPMt7agDr+DlpGhl/bar+x3x8cBu/moNiNPFaeJdjnVorR7s0kf9h33MMrSIRDIqz2yetYuZElDVrjbozRlkNUe8sSaFpql+aiDLsLqzWvwZpPOY14CoN07Kn7utTQ0uUNTRfS4/NCC3ZtMPBuJDvtOMi1KpzdfoHUMIR3Z7750JTjs/ryfEGGcjJqWv8cQHudBj6adj7RHp/PpzW7U5aXqM0l6sOC7Fdd6p69eRmO77//fstpMl/iy3x+W8/40r/+Bf3zpX79A/r7S276Y0VN8F28QDrD1MEwdTgo//msRE+91NT2eM7UdtnH8Xi3cBRR9uYOSJHUMlEEFwnHSVNnCj5QLeQeqh2bObynDhrCUWcKcxj+QcUYpV+ZCofaN/0yzCFuJriV3Mcz6eRTcmBAjtfP8Uy7YMeH3Z6cOcnRrBGbcFZcuJ0rThU5rZWbpEvDnJU/WUE4S3DmEG6B2GfiNcuxh256kafA1Xk79invqpN1VfCuusvSVzV8YLWeWp/qETxiCpQDa9SVbUZ+kjIFIUFw4fAmTrR1+Pc8suYJnt/iyXSclbhQixKa20FKaEkKm9A8fyOhHZ+G3tCX0UjKw2+5KcPCKFmBzCwTg0pV/49BprfUOVvqey8t1byPrCI6tqoGbHUettUZ2Z/s2Gq0QcXQQnpO0bbtOvCQNgptfpaHi/QcgMsSnwC4vvS/AT6z9PtlQt++m0WUt+8F2fersu9pxL6vlyO8fasivqqOffOQ19PqE5QGErVk2A0xzya5/RivLsTrq/Z7PV7fsOEb8fqGLbdkDMdrWf9/tucV2fNPac8w95GFHrBmGLbmWMBRFYJJRVmqD5LlU7S42Dtb89lCTRWt70VY81cjrPmrEdb84Qhr7kVYa3k2ln6cKYpf7qufbKTyVeLfxcJffTJSD7HlAwCMJdAQOJaBkigDfSESykAmiauiiNpq7k5nznHbAmSJZZRX3oY1pQpNrdadTVdT1+FXW1MzC6oi39yEVTW16QIqzZRssi5aaV6nUUfrNfqyGtVBo7rsk7zFB+aqSeLL0IULb669UReW25n3FFq3gdA68na645WK59QiASZBr+zZv5stDMOW0mMtA4jwSa+s5vpe4/3Sew3AFM/4jb3G3Igvd3rMstev656V6ZyVfqQpjTQlo6Z27A1ThRfMgX9l5RA6dUtiX+Zc35fUsYuTKnszB2rgukWBIvbnZrZ3k5rr3s37x8Y25wnK1DUS5Kik0kFyRppaImcUjXSTd9RON8AbYNAYZ0gT0X0cd90pdR+1Xlsn0u1iitTFjC3sWWDHLc1xXUfS3XX82nZcQKMaynHj6Cd3KDlqPAYyTUSqHmlVJa1GEDFLpNXtu9TqQmkV95CdVrs6lWyPnqaNwzJ6bqDRsIxPc5HadNMc32+HARBR9du9TpXV6eR1qqphy+s8bLE5PG2MaxHTo5ElbxGNRij8eM6jmLuHPteAUiRIVo6+jmLHhhO+jeCVfHwePSyCjzaPSUu/wtiyYM2VomS1EXfaRXaSeaOpwgF6+0XrMQ13Uij9tt7iqaEcuaTUDtfWVIxcenxlcuFqqysaYWR754U8KTVV0+9np0alKr0tTm75dkWkFmXDIs1ra+opjUqRbPeZSiNLQZ3GYs3oQWlpbayI3C07eoNMjeANBwgB2VgGhIDAUNfbOr62XtIBl1qWS6nlvEN8j4Gz6Vo3KzrbrTnYpgBc5u7VXjLVXtzYd2R8nEempZyruQfSnSSUXjWGLKWLrlsJWVg7seu2z7uRWVyILLiOUyx0MflaQup+KD4yh+4HfdaauBE1PuLXCWSrDAePeyJb1G0JXmCy4U+5LnG9WI1ucPAghNrmCKes7mpc4ZTkAVLYU6BUKbjklxKyQJN7mnpGN0l61BrdBIjUG4tqdbgklpN26+7MiJ5EN8AJ5kw16yCYk65+x98jj/bNwHuogHaXU58mz+Ocig15KoWgHiwU1yy3qWG4dB79HQIL33XdieEiQSgD5AM5Li6EppV5JCf2iNQjOSI1lOWjcgulKaJ1PC7JeU1q68GD0s170dZZUV+O96nt8Xq8h20euj+QE1K5O7PYIJ6nXACsJf5f1gP/A5sAT5gAXQek0LcurgOqxnjfb2gZukuK0U5NrVjqPtoANrkQ+6bMseVa3nFOqIycST1ch2nsZPb17x/n9HDgdoBKgUU9kALpKmarlur/TgByCsu4EV0F0+VVsG3zg7NuPhyD5MNZUXYcRHXc6XxrYIk3hIfdStVulaYb1J0zhSj4G2SUG82Dt4OrTOePbsHl1NIcI58y0CMsY2gsw0xWUBFVTpeC/kW3iBpBa9eLKJWcKmWQFQ3OtrnQ6Guux8hUG7ff7qsal+wM5X7hLVJmVE/QDAoW403CugLqlfP37Q9rnFy9P9FvfKLl7Ol79z4yZt+y+hZXYLyOt3DK7WaFGfYybhXwCG8KdNbyke1Bsr0UpX4yKlPVUEXaDLMMnECvkQyNActoI1kxVaO52ox+vJvmCVwcTtw/SZVOUj+qiWZUE01PaiJko8m7N+TdZbh+b61wTUIO1Irpps0HkMc8wLuoPhjoJY8aIhtEHyUiHFZavWR99fet/uhfGPyUd2LXqTP+Pk0cXgMTB374vXaH2VBNHNqDclMNyseuE1wZfRPXCfDtqu1d6HN6fVzt3NHnWA3Iwz2GloJu8hHwkwn4JWvCN6bWrYQJbxom0D8NY/yRsf4i9fZvEpKFyoVVsAH45On0HlIAfiSnbEk5/S8C6V+Ud/v214ccXSjGZvTFxqfK3nDjB3hewv9ZQc5y###2960:XlxV32DM 3fff b78eNqtW1mS5CgMvZJBksE155gDVOfy2X/zVdF3H2wwCIxY0h0dXVGVKQRofRKglwUf+EaDGwK+iQhBAS4LAWlQ6P47ig1fhPQm677baIPj00BB/nd8NKiXSBGoyYCuUFtH7cZECmLzaNBVastWos/fHaWbD4ksPkrq7JuTOvzOvn1mOyi+YTLbV/R2q4Ndasd3CtZl+fPnt1qt+lq+zM9vN/JLkf7nP8BfX/qffwG/v0C/fxzjFb7ZphybU7ySWoKgl0wY5zgu6CXjkZZJ0kiR+vr5chEU59MW1L5Ge4jpqiYnj4PLln9T4UK7kI/vEBxL1O4b9zlby8I/xfcxW/a3o/WSMOI67PQ6Pt2PPrRrD8nwHW3ub0fj/hHx3e27eZPad5K47UbsRqCjfZPII8iirj91GjEpUZPMHjNLSjJ77c4o2qCXWRjptKFRxVXQwcMEHhh4eH6S1dNB8cqoUaQWfSvwuI5LOnyFQDOwr4ZEXiGgfTrPYSsD9oHQs48PLSib5fw+W+ce3A+99NfA+Gea8qEfGnakqrEMwrhgDYFH3RpMhVayHBVXNEZNU9RbvtsmdTM/pN36FKRdCsKQgtBkKej1/AFT5B8d092Vf10LPlr1eOTUNZvWleipL8lXip6aRU85uvXT+HpmJ7JVye8cqJlh19Y+zjW62Ynk7MIlPqMdSujAax+49m2u/YekfSm6QRcLPC582npb/Vy7REppTPFZomRVASo5D4OryzSvwnvytXwykgQPWGp6anAQd3/ubcxqTt2j0z153Zs1U70LFT+wFbpP2afkKPmyuuy7xiOnrvnuegsHYsRf6hb+WlkEoVuIkOKK9IB82jL2+5N39RiOJlpYTVFAiTua2Acv2bwtErPFPAwprVq2+AqxVjeyRh1xXVcGkZ9uaKY9I4Ft2oaPZaqrC5hc9xF/9hWI4zjF3LpHvCzureEb2408Pe9l2Yq8la3Myr5zK1tctrOylaVWRnXVNKEtzRC+6iJ8KR+YvpXd9fq/FoN6Oiemc7xlhSbqHG/ZTpYzvO2YhJT0VtjOeo1QezsJDu2ddepedxgyB2ovvRtP6kBBl1hU7sWP0AN7Ce0r9xlVcO8W19nGvRQrf8+Hrz7xoE5sVNV964Go2szdp/V0bH0rZq/qKGLk8dy8sZ4CnPZiU6xRlNvLr+Vnr8Yyi/GNxLL6Ydi92UJFn1VTC3WgDmMjZ+owoQWKA7WTjp09EBqwAOp2Lccl2VnP4ZO2gsS62pC4yWsR6rrnQF3HZVOvJ/vIh/Eg061PS0lA1ttIPPRlpZ6aCuqzW6Gq1NsEddND0jjvg5vzwTX4IOQ++FS7D9KAD6b6Twk9cN2UgQ6x/1wddOULTL59LerhqmnGx6Rq51nusXvsYULe0Ld81UvZH5/gLZ9fo89T318HutwjVtqzobrXSbauGry7dijq6DrSVCxYixa8FRbcom7sjPuJ9+Jv58XgvZh+5S0q5UG7aOa32mn1sCsEnMs4nTWPVZcaBgOsidQsjIunsSY2FtlpbNauqlJ3Glo5iH5eRvdc0Eb3sqeSfzEl5/D6YX0fsqvkblWtqqKXFHzgwnAQDRVBBdwaDqJ5hNdVsVqmYN2lxgq1Fqk181QpH6hbKlNBZZBU9mAIV+XZlWDPrmoY4RrxRKMWXZYuNU1Rl+c2p+tBN/eC0MnEW5nOxoypb+RwxU6M4VbuVaFC3/mM42Qj5BrbzbowhJLNzZWo1Bd6Jkt+F6XaY65Usw3Hvhqy7lLTFLUqqI1QMl4NWQ0V7O1CROKihlQ1xuVzZzDMGe655xbdE245lYlOhRPyQRHEbX9ByjgB1+xAq0Zw8C6sjknmxXBBfjr9fI+BPxgCf2YYGRh2QW2p4oKFXVBrZR+ffdcyVzWBH+U3uDrAD8treAFFqC6KUI0zuk9RhIoGoBOKeDMF532yxzoG/KAL/Oywclvx+4rqdZcaLtSmC+PMCeOicqGH6t2eX1LJeUNh2WWHQ13bkloqzzxVvl57qjRFqvSiXtnGDpGE+1ogJ71wH+pOsPMqxSoH26x4Uw1bx//CroQOjz2rhZx3F2VCE2VOSaBTjatGr6odyvUQVruTcM9isdV7Hknb8eaiuKuxflY9/c8CknRq0eiQkDnd+1DLIu6Ln1Msx2hkdwoTp3oFJPvNK/mpd3+VkHLeilFbFSnbdDiRbmzvlwSrzc10kEDNCwfjGIWGLqa0sZISP19uIdKFmQDeOFaBeKyCt/DoEh0N+27fRXAkh7WmbqUuXAFOmrf+IWuftICPp7YTnbqLNX9wXEH5GwfvWpoBIfioA6aHkC4OgyHs5DRdyZctapjIgDo70WydiCQwNHMiMt8By84NvMqAqUx9hF11F7vSsLqoY+c6u0Tc70hfD/FMlXplyjWJOqSORqkR0tNIvT9famTVtVcXsuPA5yNPXyvVOpYYUcGrE7RKPIlnGLqoaWX3f3R11Mh8y9x8QiOIzde+O1BJdHHGswzrGPI6teLRE0284DYp3VrWAKJbnKTEPcsJ2a1kakl49rTWmztxcy+uLNn3bu5QubTEH9RQ82phom5fLSydQ5qnb+b+yjNWL+Gsx9UdqtTi/uqOH0Xhoo9mKLS8jGUSdXBCyKHwR3uRni8gKwXmXKgnjdGr1GkH91yIr+fuZerxNbWdcZyTZs4Yy501JXilXrVbXMCS/HmnTsX3PfVb+c/6rfxMtZFHjfJInTVD92+FIFIEQxeozUnN3UJoaHnqscMLT9s+uri+6TLsTVe9XXYds/p3nLxp1nh/IY6feM3idZJevR06Ya/eTo53X731Z/i7r/ekWT7kUb6nzXjyV7a6/Ju/uvVOaJITvvK3Afrb7m+kF+eDfCaozLS5n4Rrzr/2fUMqJd9yzyeP423l8TeTmvuJqBytCra0c8D9tqn7dOvoI838Gd/LqEE7+B/eJ655###2696:XlxV32DM 3fff a70eNq9W02a4ygMvZJBYOyac8wB0qlk2btZ1dd3H/4tDALhJL3orqrwJAOWn56EA7DqHZZlUUo/1a7u6qmM/Qn6qUHt2n7sfrPjqxJKaunG1FNrPcI7pEVYlEfbz6Ud2QDyFWc9Jn+7eiR/Bzp4AMO6MtdTwvXGvI+T/xb+oQ0oJeP1vY1fvVDf0VpZa5mR2iMbVh4rLVYxsYvFriyshM1iNybWrVYgRB+tPFoy0dKjTyvUpokWftYeHRE93yLOu9oR9SDREiHSTCTY6AVxQuuEjgjtEH5WsuEbENoh9Cl6HNZGib2H2n4OdkTrLcYLssYjpLUbE9re2z9/fot1376WL/j5bS2/Huaf/0D9+pL//Avq9iXV8uP2FG7Wl4vy8PS4KAI/u/iZ/SltcK925KnDukx7PH+6NzyFZ6i2qNjA/q/sCuy/uDJnZWEWI/ROXGPeC8lC3CsgPJvhCN8z9hxOo+4E15biw+V0N1OEH3e6xltI43lT0SKM6g5yayAfTaTw89B5vOdV+Bnoyu+DxO4lM3Sxws+YjzZM1oGExqzjLSWJ3jMioju+I/8h3zXLKL+2qxwVrL99TswctR8ctRYUdZM/oC0/na+2u6yYPQnyqiEKQzbCaz3s29h63ivpwfin90Ew+lW7ai9P1v1dDrlms7+D44ywyzeUCcpttrfFZQLTyAT6bZlA/4VMoD+eCfQHM4H+S5lAfzgTaCITtFnbKUBz4uwHmTN2FrtvEcnNGSLyaBddqHgRlStUdg+W3YnxXTR6VgaK8SNChytGDm+jN8ThgPID0Iwf8wM0uUh7TrzK+MHajcHB+L8QF+mTKv2mVGmbi8SAi8Q0F4l5FomV6xv4KHoa1chTvHSxsn+JnyZr+ascNareZzjKdNWqZqtVPcE8ZkKtmgm1KrIy5KH1FLrSwpGPWuhSU47UbVVTZ51E61WMaCiwppLislewdmPqYK87Yi9Vstf6/HF+G+y1R2X5Di2FfX1OTYWrfFZPEdd4k6IK3v+GptpjjfE5VbWfKpNsYWdP6aodjff4ZU1YzC+EX985dBoD+9U2zTc6XwG75vEDS/mVeXyENWEOTKyawC5s7JrXNt6HNc8h70PUfC0s5PHkt9VZNB4r8zivr3gvbfHnpO297Cp+WwbUgQHLpqK4gZNvrmg/N25VNVFNJII9oSOi37g4iuJB44LdBJDkhhMrIUIkoIEZqAmtWCGV0LJ6uNq7FNAiI6hdgsldGtzBwdW6TQ7fwBB61N6RLzRKVLpKs/F+xGHfy5K9iOoxQzs/etC8l+BHpQftgaQGnKSGdk/aPiE1rpRKI6nxvmLpkty4WC4NZMebCqZJ+fFiycSXIFeLprYE6ZdNwYZXOFXYrlTgp/9tIv1vE+nfNNM/hZUTsmKbwNZra3EykhXowDJlOTGQFZyjgDlZEXNKeRDwtGynAtvZGRZ0d1c/1u+tODwORZwgG++txvhe8XzyI6cyTj0PSeXIpsxDs8dCj1hJe8ZiXL7mNW0veAm79p0ynL9Xt+XITPpRasD1l8tMojq4kT6jQi6pxzstTqoNe2hj2+wCfq1wLnGI1gz4430ILzGQ6Pq1EJP0W9USlkOrFbVh65YKZWXK1krj3nlloyXKFdi2zgLWLlkp5RSDetK5ivQ7tLT37KrvCcusVp7+OZNIJyGPx+dnnPsba6YQ+QIdVy6nyNe8yJeMyDcTkY9zsBhGvkCxLIaRX6M5kR+s7owY1hl58Xlxd50sfAURSWsn+oNa78Rwx2fXqhe7HZ9MKxS1CxHt6ym6l/PfdbRLG+23mJPvp7Oa3Xc7RaPYT2VsTz5of1J1xVK9YNkqVaF5HhCosy2R+FeEqqTe0hVzn1sSYmWdnGvqrMuLVxTVvo53B5q7E+wANScEkqayicbtAkns5U6U6ce7b3JIrHpujeQ9pecxek8vv7lCth2A0XaALMtkQ4ijuz6Q4kkmOqGoGp1CvicfP9ETdDypoafADffBjBSjzEh+KvSkH5HKlZfmA7ns8fc+UCwgQSGvSWkYFy1VAUILClnIXXmSCKKSCBLJD0kKCo3QpW+OoJBIFMuxoEA8kmSIYAiKe6dZSUvp9UNSen2rlO5Lga7wvSJN+mI8RL5CkV+epAp5//HNzX7cK0bcw0TcA4pkGArpHtq00LkZAJ1Y9OV2bgrAlLANpfp7hW3w+V5hG3y+S9iGHZsUthrF3npiXUGxLmSlcr1VBFSriGheyBhLvEYq5mcOWrfQxNkviury9JdR6JVRPdes6Ef1dYYdRvYLzYphhE83K+ooZzQrVhTlWxHlcLfaAvxbv/0oHzcrNDvKNfq+jjhZiSPnx+/rCBKdVPJaovM3h1rf1wk5zzB8Qzq2Zc1E+GPChYU+jhTHWOOxarzC8vtlyYqzUo9dz7OJ737VWF18P2qEVRPYjY1do6bjYVc21kyszUyszUysbZtY2zaxtn1ibfvE2vaJtQlYJlbn0OsEWkysUKRvHLLRM6uUg1Wes2OyqlZbHONRVmb42osgtCb2QFlRulMR37zFPl/RoBz/r+hRjv8LHqLuVChzI4/H52dcW58alLlvZd9VfqdXP/qZe9wV2NiZeyNr/JY+lUhDSqr+yhqy1z+oq64e2rTQ+fi8hZbFIf4YLbvotvYVxYE+30pNzEwULy6c0P8DlsSi/Q==###2792:XlxV32DM 3fff ad0eNqtW92SrCgMfiUgIDj7HPsA3Wpfnru9mtp3X9QWgiYEdOvU1JnpTiIk+fIH2tEuzrqPCwDg3QiDUg4cgLUOzPq7nUBbs/5uR/uxo4s/Jx6X6L48kd8IPJDoNh47RTofqWCj/ERut9LU+Fme6+d6W6M5pBVSjicUXAePtaDjd+jbyB0pXNTP+hsrVeSzH3dPcgff9r9ZqUGnz83JCoajWv+OtGrTolfq33//6OEVftSP/f0T7f2jw1//gH3/mL/+Bvv6me0vDPBCptIQ1oeAJY0Cm4Kpz1eHiA+IGwp2ukhC37Dc63f6TN0lZ1VFiP9WOfX1bM9ympX4cc5Fd9hon+pGN8jAz2Mk76YcoylhN+UwFabU8+s3Sliteexp3p4Y+bcnmk07n+hzeN8zue9yzUgCQxsJY/gxX3BmPp/4dgqXgghHbSCgcCZT2y5q1UGti8AqU5sO6p49Ujs03A5RiL7SnsPyzqNKHtL/VhvnELVZPnqPKaWwYXnnr4TXJul1/kqIbZJ+gz8GW5W+O8vDIRnOf19D9AuF6FeB68nVQvSy5/B1sdtjKeP5jgDkk0zzNemZz+WnMk+0DcHXNARfz0pxYiqwKaWYFcYPUpNPcvRhrDcyVhmEZ2jLp/sWDaNAd8J2Pe9wqFUPtm1h/G77ouwuOQpl5PY8aFjHGkXHAtGxNum7ISdkyKVEne8z5GqCwep9oexGMQXhaw8U7ZLB7DN/RwazHQbjanvZYLbBYHAYbM4GM6oReY5YcGCWq9mQx1FTjUs1cH3VK/tpaFhLbTe2EgHkALrt4lhrpSpvCcUqhVB7GHLJdaw2vrDkGKHnLlWs/lZwRxWr4+fxW6mSPekwyaAoT03wmUuV7e+pzS6p9er4uMFm+gJqj7oAzVzpdL59zq7RT4bGZyg7AzX8wnjCRn7SBW7kaj23S4o/1bOK5HKoolUitT5TM+XJTq2Q3nfZZqOuanvXpdgXUZYe0zP4eADMsxvs/A3Ia8EUHviLP6SkIuatMAKHGwg0TQi0zQi0bG9DIRCQJ4CIQDo9jQ80OiaNHsnprRECbYlAM629uWrGoEOo0CKGtEitL9SmErsU8ulzpKtjyIgYcs1xxFXQJEkoqanPLYflaszm44jsMTlqwyMsb2v/5uWEZoPR7Eo0jy1ohiY0+2Y0e4RmJaJZjutjGddJvQyPtDokrSZEA0K0OeXU0JNTA0KoEfFsRGpdHfnXcqJB6AcRzyDiOTTjOTCIkrIqMHzhARJDmoU+QWJGj81ItBiJZRoY3y1ItG2VLYMqekarEBq1iEY5Q4xlhiB1MzzS7JA0e8y+3w6hUZ3yq+7Lr7rImSAiEkRqfaau1iaqrE2StpWIyP7pvaiHSGnYte5rWupYFBCsKuclNBaU7CGpA7pfXe8rmLfaPxxeNmD8Qolf19SZ3uojaOSaUwdz5dJl/1HFrTlXdh1daYtNrl3p22fMLktbV3qe/vV2pSy/0GcOXV2puVDzVtKElXIsZrX9uCtN0ZycytzHzc47V7vSFn8hutKA0WfudKW3OhAafU7Ek650Sgz66jMhNgM04S95TZ60vUeEwNOJsTFc1qQx5CqHQyhXiEdS5Sl//y6L/uemD+8WmFM3VkMQd9nFiOi92w9f/KoymSxjkVy7DR2TA9YPMNfuZy+MXH0Dufd6DRq5e7/lSZ0NCLkeTXOdNPvdKHjkhkc+HZJPp3oXHTMuY1v3SdtL7j6Hru7TXKhNpdbVZS9XzPjq6LnrEep/6T5rNyIGNk7LkWfnnavdZ1MFTHWfU0ahncsTTfsLHoGwPMZBV6fk8zjyYEp3Fl1h26ZvLLp2amg8CggpsOCjAF9pyXZqXx0X8+He9LUru6nQWaa2ZaMxDb/FRa7pe7nEZPduPzktLvwYvkCuXi4yqO3fgBGftrDD1YHkDp2wms7cwkHjgDQTWDljw9HngI4+k73QkaUpr+iEWEdZ4t7dmIAxN1Xy56k0lkDSMl3HwafEsynqDARxixFoPPaWI9AnqwlKNb2WX/J6Yl7snYYHL5eMP9/EXsaISL8hYUSJXaFRCEUNxShkiyii+n1V/UCkkXb1Q0okueGe0LGemW54qWnwUt/hpZ6tRykvZS7GPPJSSF6az+omjbz03aGmu4V9zUv5tgpztd70u68mn9R0gHlCx0pmueFNcgXHbVlz98KYapPyJu5S0hPQuQQ6WNPEriZA3jTd8KbeQrfmTaFHRZUsbonxbLuabBqt5kPKCR2NQDnAD7bFm2yDN0GHN9UKHqwqqeBxxFlHj0cNx/5yfHJIVWUdH5YWj7pzyZ/3Kc3kr6FJRklNKcA9Up9L6ktZEA3xoZwiBlWq7ygObX7D4da7IYUEslaj2w/8dkZv+4Hfy+htPyaPVLQ01Wn5YXfLWRBURNdqh2p1U62GDdFSqyH1V2s19UD9qbbNsRANusFWUwbtoa0X6Fs91CMPVaKHcnPdJz6q8ww/Z1b0vhN8mjJr6aV3ylmoq4mt1TKfXKuNDxR1vXo2oeErDDe8qfHWfKM3mQJwIAKOGyOMj7wp3WHJ3vRGago31HRn4lJTEyA1KVFNimnh7ZPEkA5TUPGBXotYTteezEAdGcGN1yItOTCHNJ+6l2OwBJp2iWUcNWGE43XCL8U3x1Spw5naeZJao+mBF2Vr9HZXlu3I3Ih171BubL1uAZf3QpquStyWs1t9Pl4q2P0NTUKX8uQoBtzV3zTpbwZpSFeOJndqOL23RlcPeCeLcH1F9t/+7FP335X2P6f23HU=###3288:XlxV32DM 3fff cc0eNq9W0euJLkRvYwOQBN09S+gvaQDpF02MAtp89F3F9MxX7DINJW/Bw0MfmUYhnlhmFUz0KCJlJZCUKDBkBmN11JrE7TSFJ8OM4eZOYZDbn+DW2tV4FZVbkocC3dHI7nIp2feMcqR1vG5jhRjPPVv0kCpSk80ZfwDPXqOwqxn8vD371/SdsNLvOj7V5R8DeLrv5ral/r6j6bmJZX4jtqFbmo+mxiR6LOq+CwqtqqZMtmhjaxaPRpjaOV9z6dgZyLvlll1ihp1yu1vcHPUqBSfGrfOInjMfR7v5fmn2Fikl5z4R1gVCWO0YWzcMdaPHGOkJ4zJOsbWupqiZUkup1QjhBwlH+v1W+MueWhOcU0XcK1v4FoD9vQprs+5/Q1ujmsN3VCfdkNdjKCtdoYrCLMQ5WdINRvip0zPSO0FIHXgSO1oQqrLkCrjaTRHKD6aIxStMxE8czzz3iVn23ziuMJNnDt6tPQJwHKcCyoif4uAShEwa8eQIFevHnPSzwPEtJulXZS1C3/kkQz1XQH1cj5nPx3kS5yVyExS5mIUF166wSsu85K2N3hVnscZL+WsFxA15YVzF7JOU6ZX3u2Ubs56qVZpwcXMUavV+lRZpP+uqRJSrZqtViXUas9rtZmnii1MFVqQvkZWQs5kMUKIhjNuzfCwcR/ujStHfdbIk5pTF2rOXa45V/XwvebkCS/d4BWXeek9xmsdcd6w5Xqlrz2wyHuEDFXlVjx78e96fyXgqPXX+lS8Umk/NxVl2t9SpalYaXqpNGkMK7VWfs91xjEa9cx7xueTgWko8pr3jjjL2SRnoA9u23WZG3fx5Q5R6pobNyWOWtdUE0rfYrJLlyPBpI2P/2I29yxoyELvWBZ8zAIVsqBSda3aTrIQMn+TfIkzIV4UpJAj17D5uXSmks1vu0ZNevVLp7tGTxglz6OkTqI0n3QWo7wfHEVJrR2qjCaI0yGaZGHzuhOnAHGyW5wMxqk5jNN7D5kn8ckNR863jLPbFvJuu0reb2nfUNc4yct4QumP8GQxTu0HcVKncTI34mQONnm6uMmX8HQnTkU8uX0bi1clvo6J8K1DtoyFtObmTh5diUL1AqWq3BYGtYC2JYvcBtqWvPFiK/kzB+bs+l+ytBqNyvDapPLhVXrxR1WL9YXXhhuUJRtrfR63D14N9R5hoxlsRvOtfRE1uloaJev1I5vZOvQghjrF8FjPZy0DsXt+oXiXdBcvLgGWWVx9y5eik2zhKQsaAjTbLlxYceLgSJnssrorr5l50wT5Iq856xbsJUtpmQsP8KfSxVfuUWpwJPF39rb5jnqbg+beZfjqLuGLTkbSWd3dHTKLdLfVy+J3i+jouN8995vHeXsJQfG/Jr8eFZY2Vcy1Ki54tZdlvpp1daHr+PS6I3XKDrPOB2xnypewdOH4cP3fLyzF9f/wkqRP11qVLYh4Gatxs+dVDaUX+kNJw7rQmAeXtaWTbevQ9rVa3yNWxws1quZOtOTgkxpl8g9qFPXcrVHfvuRLfs/Oyq/4ecKsXKKwByE+H3c+sQQlGD9h2L/VsJpfiMr9q8ubsxHly7zbZV9ULlkqXQ3vThcmX+KNE9DB5jpSiFpz+eWFhElTHe09lpmrLz7V1b1w0qeSltmyaZ5lmjY605Dkoy+T7E6dToz8UdMl7cfyozmi5nkW9V1jfV205VDtUYt/z3atiItb9IQY8BvpqKdAXzPVM/pZRms96fPMLPIHkZ3+epqdVcdBhlaOUhzEot+4dUaIC8gWP4Zs8UeRLX4A2aUuKB71wHptuGtxZ7m6j1nxxzErfhSz+QSZJqJbfmJQjcCnknRBUlZ/AsG5B5qeRv2xI5ns5E9s05WJenzatfo7z0NRB43P9R/oFpc645+yXT22/bMs1yVrSK/13atadHUvVT+iRX8cC3/jfKrGIlS1HP9QiQ5ycSYpL/WRkqStSa5bqqn2LvcD2aJbMa9rCR/6bw663HA490w9cqc/SHMfS/rKjiDz901V6X77evGBHpf00CM9NunRj/SYpEc90JP93OSBHvYe54Eel/ToR3ps0vMsPkdvxe/oYd8IfKxHp3ypR/HJfiD9QM/R2/47elTS8yw+Mul5Fh+R9Ki0g+R7S3oatxGdf468S8dzl+RV/vlAXjw8X9w9//fvX0Him6z4WcEbr7C/8QoEzy08N/Pz/bPN9AWQ63a5buB880+sNz6x8/VgT9vDc8Pl56+5N3kNfD7jA3vaZueTsuGv/qRsd87gkDMzXSqRP5AgKkFU6Z3gByQQD6NUJtfpQSeBqOkzTjPAIR44LZjlUYWlTIU1wNkip8s5wSwPrioBrrYAJCXBitYjASDQQsCV6oEA2FMaUtQaIBBmGTxVxgEBYKLQ41btBG1A1QDmaguqBjBXO1A1gLnaQ0gGMFcHCMlASICQDGCuHiEkEl03GF7ZtEhRSIFaNLZBbRIpA1IEUkbUBu/GjbNIGZDCzlFI6VAG6tw69FSAjPV4jtBIQdsE+GMx0nGkAKUH20Yw2g6QtXFEAtg8oskDBG2EHuMQrwSqHIFZ1CMB0GfARWcEEMBDhw1XCkIKRl9A/l3DouKRgpgR6EsHA0EGoHiGsxYJUDGyRwKiDHqFV3gIlJLHcSQlVJ9nvjAZ5gs7pkNKQJMHj5QB5x5gzEDIgsXMNEiA+BtCAsDC4Gx1AD0jkADuG4UEwCSBI6GFYiHwo9HoIWCyIQiKAoQ1HisyeKSwbgG+NwFPacGwphGoDbLSCuijTiIBDHBQFK0ECQu+tAQSFpDXNtgpNFjcWexICgnoPqSxczgQ8Dn6DlnsPLiOR3uAMK5MHpsBPgdgQTq6tkXAt7hUYdD7ASnYVHtcuHAKywFXNM1kRly+IIhYPT2umQ3qwiaFaOixrgNEpW+xrWFbGRQml0Bm0Oh/yyjYPnHhHDxEs4F0DQHT2CIByhdn2oDVgIN4GFkxgMgosLRwdozaIAXOHw2jQPhHRIxsFFIQMw0U19hjOaJpuHo7sCzOV9ZXHSPhLMD9MJJYF8EFVmgsSmJSzFmciFJqwIHDbVYaFgfBNnVosTYwCoTItowCllvH1nvUBrUbr6Fsk7NIYt7iRjz9n0HgEqfASQ7t1ph0hzZQYEnnJLaYESOxDRAtp4atgI6RmBQaSC2iv8HEG4SLlYyCMddIwU3YjIwC2sxef7//92/pZqH4T3z/K66OL63CK166X1Oi+r596T4OyX9Kp77+kjGIremm65d4RfR9x8f09Q8ZN+PeRYr7Px7foN0=###712:XlxV32DM 47b 2b0eNqlU7ty20AM/Bl/AHDvWzaepEnhIv6Ee5aZUc3xv2fB8TiKoi6SiNNxwQV2cXRQiH3PH5rD8aLZoxeuaWPm46PrmM9S6l2Ky/VZSr5nye1ZSvqLxT1L2X9S7PP6+v3UsiP8UA27dN75dvbTh8QnFR6aIzsuwUKcx82HcnwQdxd+QdsgsRAsVAvdQrJgaDI0GZoMTYYmonnWL8a5yehYsUAqpB0vfinaJqZpXdWoqKyNfVCQ3N1X/soWhBAQUkasDXEq4m5IO2CGiBVYVKhUtReoC3TQJfbv+oIGIUVUbmNIj/TBG72tvHpCGBVhTVh+LB5xeCTHy7NczchRkVtDHgPFVZg5pXUUPlfWQC0RlVUr22s0urWMTq5O/3pRdGJ9cs/WR40YTXh1zOYwO4c3M+UIVl1YndJYZ+2JrQ7bF+y4sGnB7hQlZo6wiooNRexYSKNQVepW06Y2HrWhaGae0nZ1lfccG1O3GDzLqU+DoZLAL/oYHC0Mwdzr4dGzaJY5NFqxhC1xuup2fEy7nKWDlvWI2bTNgfGF+GFnJOB6gOLF2SERbJ5uPxeGHm+exrnzbSb48zbj8cvPAeFCGeR4Dqi9DTyC8km/TPz8l9/9Dz9frZ/ne4PI8d4hetxUbHPjhK5dWQvFVp7Sfa3pc60UfP3plH39WWbYTatcnR7k/g3N/y0O |
/syn/spi_master_atlys_top.vhd
51,6 → 51,8
--- output LEDs ---- |
led_o : out std_logic_vector (7 downto 0); -- output leds |
--- debug outputs --- |
s_do_o : out std_logic_vector (7 downto 0); |
m_do_o : out std_logic_vector (7 downto 0); |
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state |
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state |
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins |
69,8 → 71,8
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz |
-- spi port generics |
constant N : integer := 8; -- 8 bits |
constant CPOL : std_logic := '1'; |
constant CPHA : std_logic := '1'; |
constant CPOL : std_logic := '0'; |
constant CPHA : std_logic := '0'; |
|
-- button definitions |
constant btRESET : integer := 0; -- these are constants to use as btn_i(x) |
89,7 → 91,7
st_wait_spi_di_req_3, st_wait_spi_ack_3); |
|
type fsm_slave_write_state_type is |
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, |
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, st_wait_spi_do_valid_1, |
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end); |
|
type fsm_slave_read_state_type is |
154,6 → 156,9
signal spi_do_s : std_logic_vector (N-1 downto 0); |
signal spi_wr_ack_s : std_logic; |
signal spi_rx_bit_s : std_logic; |
-- spi debug data -- |
signal spi_state_m : std_logic_vector (3 downto 0); |
signal spi_state_s : std_logic_vector (3 downto 0); |
-- slave data output regs -- |
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0'); |
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0'); |
188,8 → 193,9
wren_i => spi_wren_reg_m, |
wr_ack_o => spi_wr_ack_m, |
do_valid_o => spi_do_valid_m, |
do_o => spi_do_m |
do_o => spi_do_m, |
------------ debug pins ------------ |
state_dbg_o => spi_state_m -- debug: internal state register |
); |
|
-- spi slave port: data and control signals driven by the slave fsm |
206,13 → 212,14
wren_i => spi_wren_reg_s, |
wr_ack_o => spi_wr_ack_s, |
do_valid_o => spi_do_valid_s, |
do_o => spi_do_s |
do_o => spi_do_s, |
------------ debug pins ------------ |
state_dbg_o => spi_state_s -- debug: internal state register |
); |
|
-- debounce for the input switches, with new data strobe output |
Inst_sw_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 8, CNT_VAL => 20000) -- debounce 8 inputs with 200 us settling time |
generic map (N => 8, CNT_VAL => 200) -- debounce 8 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => sw_i, -- noisy input data |
221,7 → 228,7
|
-- debounce for the input pushbuttons, with new data strobe output |
Inst_btn_debouncer: entity work.grp_debouncer(rtl) |
generic map (N => 6, CNT_VAL => 20000) -- debounce 6 inputs with 200 us settling time |
generic map (N => 6, CNT_VAL => 200) -- debounce 6 inputs with 200 us settling time |
port map( |
clk_i => gclk_i, -- system clock |
data_i => btn_i, -- noisy input data |
357,7 → 364,7
-- master port fsm state and combinatorial logic |
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m, |
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg, |
new_button) is |
new_button, clear) is |
begin |
spi_rst_next <= spi_rst_reg; |
spi_di_next_m <= spi_di_reg_m; |
385,7 → 392,7
m_wr_st_next <= st_send_spi_data_sw; |
elsif new_button = '1' then |
btn_next <= btn_data; -- load new button data (end the mismatch condition) |
if btn_data(btUP) = '0' then |
if clear = '0' then |
if btn_data(btDOWN) = '1' then |
m_wr_st_next <= st_send_spi_data_sw; |
elsif btn_data(btLEFT) = '1' then |
453,7 → 460,7
end process fsm_m_wr_combi_proc; |
|
-- slave port fsm state and combinatorial logic |
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, |
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s, |
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is |
begin |
spi_wren_next_s <= spi_wren_reg_s; |
473,9 → 480,9
|
when st_wait_spi_di_req_2 => |
if spi_di_req_s = '1' then |
spi_di_next_s <= X"D2"; |
spi_wren_next_s <= '1'; |
s_wr_st_next <= st_wait_spi_ack_2; |
-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss) |
-- spi_wren_next_s <= '1'; |
s_wr_st_next <= st_wait_spi_do_valid_1; |
end if; |
|
when st_wait_spi_ack_2 => -- the actual write happens on this state |
484,6 → 491,11
s_wr_st_next <= st_wait_spi_di_req_3; |
end if; |
|
when st_wait_spi_do_valid_1 => |
if spi_do_valid_s = '1' then |
s_wr_st_next <= st_wait_spi_di_req_3; |
end if; |
|
when st_wait_spi_di_req_3 => |
if spi_di_req_s = '1' then |
spi_di_next_s <= X"D3"; |
595,11 → 607,17
dbg(10) <= spi_wr_ack_m; |
dbg(9) <= spi_di_req_m; |
dbg(8) <= spi_do_valid_m; |
-- dbg(11 downto 8) <= spi_state_s; |
-- slave signals mapped on dbg |
dbg(7) <= spi_wren_reg_s; |
dbg(6) <= spi_wr_ack_s; |
dbg(5) <= spi_di_req_s; |
dbg(4) <= spi_do_valid_s; |
-- specific ports to test on testbench |
s_do_o <= spi_do_s; |
m_do_o <= spi_do_m; |
m_state_o <= spi_state_m; -- master spi fsm state |
s_state_o <= spi_state_s; -- slave spi fsm state |
|
end behavioral; |
|
/syn/fuseRelaunch.cmd
0,0 → 1,17
-intstyle "ise" -incremental -lib "secureip" -o "D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.exe" -prj "D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_translate.prj" "work.testbench" |
/syn/spi_master_atlys_top_bit.zip
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/syn/spi_master_atlys_top_map.psr
0,0 → 1,530
Release 13.1 Physical Synthesis Report O.40d (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
|
TABLE OF CONTENTS |
1) Physical Synthesis Options Summary |
2) Optimizations statistics and details |
|
|
========================================================================= |
* Physical Synthesis Options Summary * |
========================================================================= |
---- Options |
Global Optimization : ON |
Retiming : OFF |
Equivalent Register Removal : ON |
Timing-Driven Packing and Placement : ON |
Logic Optimization : OFF |
Register Duplication : OFF |
|
---- Intelligent clock gating : OFF |
|
---- Target Parameters |
Target Device : 6slx45csg324-2 |
|
========================================================================= |
|
|
========================================================================= |
* Optimizations * |
========================================================================= |
---- Statistics |
Number of SRLs added by SRL Inferencing | 4 |
Number of LUTs removed by SmartOpt Trimming | 463 |
Number of registers removed by SRL Inferencing | 8 |
Number of registers removed by Equivalence Removal | 4 |
|
Overall change in number of design objects | -471 |
|
|
---- Details |
|
New or modified components | Optimization | Objective |
-------------------------------------------------------|--------------------------|---------------------- |
Inst_spi_master_port/Mshreg_di_req_o_C | SRL Inferencing | Area |
Inst_spi_master_port/Mshreg_do_valid_C | SRL Inferencing | Area |
Inst_spi_slave_port/Mshreg_di_req_o_C | SRL Inferencing | Area |
Inst_spi_slave_port/Mshreg_do_valid_C | SRL Inferencing | Area |
|
|
Removed components | Optimization |
-------------------------------------------------------|-------------------------- |
Inst_spi_master_port/di_req_o_C | SRL Inferencing |
Inst_spi_master_port/di_req_o_D | SRL Inferencing |
Inst_spi_master_port/do_valid_C | SRL Inferencing |
Inst_spi_master_port/do_valid_D | SRL Inferencing |
Inst_spi_slave_port/di_req_o_C | SRL Inferencing |
Inst_spi_slave_port/di_req_o_D | SRL Inferencing |
Inst_spi_slave_port/do_valid_C | SRL Inferencing |
Inst_spi_slave_port/do_valid_D | SRL Inferencing |
Inst_spi_slave_port/state_reg_0_1 | Equivalence Removal |
Inst_spi_slave_port/state_reg_1_1 | Equivalence Removal |
Inst_spi_slave_port/state_reg_2_1 | Equivalence Removal |
Inst_spi_slave_port/state_reg_2_2 | Equivalence Removal |
][100_9 | SmartOpt Trimming |
][104_10 | SmartOpt Trimming |
][111_11 | SmartOpt Trimming |
][118_12 | SmartOpt Trimming |
][125_13 | SmartOpt Trimming |
][132_14 | SmartOpt Trimming |
][139_15 | SmartOpt Trimming |
][148_16 | SmartOpt Trimming |
][152_17 | SmartOpt Trimming |
][156_18 | SmartOpt Trimming |
][163_19 | SmartOpt Trimming |
][170_20 | SmartOpt Trimming |
][177_21 | SmartOpt Trimming |
][184_22 | SmartOpt Trimming |
][191_23 | SmartOpt Trimming |
][205_26 | SmartOpt Trimming |
][214_42 | SmartOpt Trimming |
][218_47 | SmartOpt Trimming |
][222_52 | SmartOpt Trimming |
][226_57 | SmartOpt Trimming |
][230_62 | SmartOpt Trimming |
][234_67 | SmartOpt Trimming |
][238_72 | SmartOpt Trimming |
][246_85 | SmartOpt Trimming |
][250_90 | SmartOpt Trimming |
][254_95 | SmartOpt Trimming |
][258_100 | SmartOpt Trimming |
][262_105 | SmartOpt Trimming |
][406_203 | SmartOpt Trimming |
][410_208 | SmartOpt Trimming |
][414_213 | SmartOpt Trimming |
][418_218 | SmartOpt Trimming |
][422_223 | SmartOpt Trimming |
][426_228 | SmartOpt Trimming |
][430_233 | SmartOpt Trimming |
][450_251 | SmartOpt Trimming |
][454_255 | SmartOpt Trimming |
][458_258 | SmartOpt Trimming |
][462_262 | SmartOpt Trimming |
][466_266 | SmartOpt Trimming |
][470_270 | SmartOpt Trimming |
][696_424 | SmartOpt Trimming |
][701_427 | SmartOpt Trimming |
][706_430 | SmartOpt Trimming |
][722_442 | SmartOpt Trimming |
][726_446 | SmartOpt Trimming |
][730_451 | SmartOpt Trimming |
][734_455 | SmartOpt Trimming |
][737_456 | SmartOpt Trimming |
][814_514 | SmartOpt Trimming |
][820_519 | SmartOpt Trimming |
][823_522 | SmartOpt Trimming |
][826_525 | SmartOpt Trimming |
][832_530 | SmartOpt Trimming |
][96_8 | SmartOpt Trimming |
][const_100_156 | SmartOpt Trimming |
][const_101_157 | SmartOpt Trimming |
][const_102_158 | SmartOpt Trimming |
][const_103_159 | SmartOpt Trimming |
][const_104_160 | SmartOpt Trimming |
][const_105_161 | SmartOpt Trimming |
][const_106_162 | SmartOpt Trimming |
][const_107_163 | SmartOpt Trimming |
][const_108_166 | SmartOpt Trimming |
][const_109_167 | SmartOpt Trimming |
][const_110_171 | SmartOpt Trimming |
][const_111_172 | SmartOpt Trimming |
][const_112_174 | SmartOpt Trimming |
][const_113_175 | SmartOpt Trimming |
][const_114_177 | SmartOpt Trimming |
][const_115_178 | SmartOpt Trimming |
][const_116_180 | SmartOpt Trimming |
][const_117_181 | SmartOpt Trimming |
][const_118_184 | SmartOpt Trimming |
][const_119_185 | SmartOpt Trimming |
][const_120_187 | SmartOpt Trimming |
][const_121_188 | SmartOpt Trimming |
][const_122_191 | SmartOpt Trimming |
][const_123_192 | SmartOpt Trimming |
][const_124_195 | SmartOpt Trimming |
][const_125_196 | SmartOpt Trimming |
][const_126_201 | SmartOpt Trimming |
][const_127_202 | SmartOpt Trimming |
][const_128_206 | SmartOpt Trimming |
][const_129_207 | SmartOpt Trimming |
][const_130_211 | SmartOpt Trimming |
][const_131_212 | SmartOpt Trimming |
][const_132_216 | SmartOpt Trimming |
][const_133_217 | SmartOpt Trimming |
][const_134_221 | SmartOpt Trimming |
][const_135_222 | SmartOpt Trimming |
][const_136_226 | SmartOpt Trimming |
][const_137_227 | SmartOpt Trimming |
][const_138_231 | SmartOpt Trimming |
][const_139_232 | SmartOpt Trimming |
][const_140_238 | SmartOpt Trimming |
][const_142_240 | SmartOpt Trimming |
][const_144_244 | SmartOpt Trimming |
][const_146_249 | SmartOpt Trimming |
][const_148_252 | SmartOpt Trimming |
][const_150_256 | SmartOpt Trimming |
][const_152_259 | SmartOpt Trimming |
][const_154_263 | SmartOpt Trimming |
][const_156_267 | SmartOpt Trimming |
][const_158_271 | SmartOpt Trimming |
][const_160_272 | SmartOpt Trimming |
][const_161_273 | SmartOpt Trimming |
][const_162_276 | SmartOpt Trimming |
][const_163_277 | SmartOpt Trimming |
][const_164_278 | SmartOpt Trimming |
][const_165_279 | SmartOpt Trimming |
][const_166_280 | SmartOpt Trimming |
][const_167_281 | SmartOpt Trimming |
][const_168_282 | SmartOpt Trimming |
][const_169_283 | SmartOpt Trimming |
][const_170_284 | SmartOpt Trimming |
][const_171_285 | SmartOpt Trimming |
][const_172_286 | SmartOpt Trimming |
][const_173_287 | SmartOpt Trimming |
][const_174_288 | SmartOpt Trimming |
][const_175_289 | SmartOpt Trimming |
][const_176_290 | SmartOpt Trimming |
][const_177_291 | SmartOpt Trimming |
][const_179_292 | SmartOpt Trimming |
][const_180_293 | SmartOpt Trimming |
][const_182_294 | SmartOpt Trimming |
][const_183_295 | SmartOpt Trimming |
][const_185_296 | SmartOpt Trimming |
][const_186_297 | SmartOpt Trimming |
][const_188_298 | SmartOpt Trimming |
][const_189_299 | SmartOpt Trimming |
][const_191_300 | SmartOpt Trimming |
][const_192_301 | SmartOpt Trimming |
][const_194_302 | SmartOpt Trimming |
][const_195_303 | SmartOpt Trimming |
][const_197_304 | SmartOpt Trimming |
][const_198_305 | SmartOpt Trimming |
][const_200_306 | SmartOpt Trimming |
][const_201_307 | SmartOpt Trimming |
][const_203_308 | SmartOpt Trimming |
][const_204_309 | SmartOpt Trimming |
][const_206_310 | SmartOpt Trimming |
][const_207_311 | SmartOpt Trimming |
][const_209_312 | SmartOpt Trimming |
][const_210_313 | SmartOpt Trimming |
][const_212_314 | SmartOpt Trimming |
][const_213_315 | SmartOpt Trimming |
][const_215_316 | SmartOpt Trimming |
][const_216_317 | SmartOpt Trimming |
][const_218_318 | SmartOpt Trimming |
][const_219_319 | SmartOpt Trimming |
][const_221_320 | SmartOpt Trimming |
][const_222_321 | SmartOpt Trimming |
][const_224_322 | SmartOpt Trimming |
][const_225_323 | SmartOpt Trimming |
][const_226_326 | SmartOpt Trimming |
][const_227_327 | SmartOpt Trimming |
][const_228_328 | SmartOpt Trimming |
][const_229_329 | SmartOpt Trimming |
][const_230_330 | SmartOpt Trimming |
][const_231_331 | SmartOpt Trimming |
][const_232_332 | SmartOpt Trimming |
][const_233_333 | SmartOpt Trimming |
][const_234_334 | SmartOpt Trimming |
][const_235_335 | SmartOpt Trimming |
][const_236_336 | SmartOpt Trimming |
][const_237_337 | SmartOpt Trimming |
][const_239_338 | SmartOpt Trimming |
][const_240_339 | SmartOpt Trimming |
][const_242_340 | SmartOpt Trimming |
][const_243_341 | SmartOpt Trimming |
][const_245_342 | SmartOpt Trimming |
][const_246_343 | SmartOpt Trimming |
][const_248_344 | SmartOpt Trimming |
][const_249_345 | SmartOpt Trimming |
][const_24_24 | SmartOpt Trimming |
][const_251_346 | SmartOpt Trimming |
][const_252_347 | SmartOpt Trimming |
][const_254_348 | SmartOpt Trimming |
][const_255_349 | SmartOpt Trimming |
][const_257_350 | SmartOpt Trimming |
][const_258_351 | SmartOpt Trimming |
][const_25_25 | SmartOpt Trimming |
][const_260_352 | SmartOpt Trimming |
][const_261_353 | SmartOpt Trimming |
][const_263_354 | SmartOpt Trimming |
][const_264_355 | SmartOpt Trimming |
][const_266_356 | SmartOpt Trimming |
][const_267_357 | SmartOpt Trimming |
][const_269_358 | SmartOpt Trimming |
][const_26_27 | SmartOpt Trimming |
][const_270_359 | SmartOpt Trimming |
][const_272_360 | SmartOpt Trimming |
][const_273_361 | SmartOpt Trimming |
][const_274_363 | SmartOpt Trimming |
][const_275_364 | SmartOpt Trimming |
][const_276_365 | SmartOpt Trimming |
][const_277_366 | SmartOpt Trimming |
][const_278_367 | SmartOpt Trimming |
][const_279_368 | SmartOpt Trimming |
][const_27_28 | SmartOpt Trimming |
][const_280_369 | SmartOpt Trimming |
][const_281_370 | SmartOpt Trimming |
][const_282_371 | SmartOpt Trimming |
][const_283_372 | SmartOpt Trimming |
][const_284_373 | SmartOpt Trimming |
][const_285_374 | SmartOpt Trimming |
][const_286_375 | SmartOpt Trimming |
][const_287_376 | SmartOpt Trimming |
][const_288_379 | SmartOpt Trimming |
][const_289_380 | SmartOpt Trimming |
][const_28_32 | SmartOpt Trimming |
][const_290_384 | SmartOpt Trimming |
][const_291_385 | SmartOpt Trimming |
][const_292_388 | SmartOpt Trimming |
][const_293_389 | SmartOpt Trimming |
][const_294_392 | SmartOpt Trimming |
][const_295_393 | SmartOpt Trimming |
][const_296_396 | SmartOpt Trimming |
][const_297_397 | SmartOpt Trimming |
][const_298_400 | SmartOpt Trimming |
][const_299_401 | SmartOpt Trimming |
][const_29_33 | SmartOpt Trimming |
][const_300_404 | SmartOpt Trimming |
][const_301_405 | SmartOpt Trimming |
][const_302_408 | SmartOpt Trimming |
][const_303_409 | SmartOpt Trimming |
][const_304_410 | SmartOpt Trimming |
][const_305_411 | SmartOpt Trimming |
][const_307_412 | SmartOpt Trimming |
][const_308_413 | SmartOpt Trimming |
][const_30_40 | SmartOpt Trimming |
][const_310_414 | SmartOpt Trimming |
][const_311_415 | SmartOpt Trimming |
][const_313_416 | SmartOpt Trimming |
][const_314_417 | SmartOpt Trimming |
][const_316_419 | SmartOpt Trimming |
][const_317_423 | SmartOpt Trimming |
][const_318_426 | SmartOpt Trimming |
][const_319_429 | SmartOpt Trimming |
][const_31_41 | SmartOpt Trimming |
][const_320_431 | SmartOpt Trimming |
][const_321_432 | SmartOpt Trimming |
][const_323_433 | SmartOpt Trimming |
][const_324_434 | SmartOpt Trimming |
][const_326_435 | SmartOpt Trimming |
][const_327_436 | SmartOpt Trimming |
][const_329_437 | SmartOpt Trimming |
][const_32_45 | SmartOpt Trimming |
][const_330_438 | SmartOpt Trimming |
][const_332_440 | SmartOpt Trimming |
][const_333_441 | SmartOpt Trimming |
][const_334_444 | SmartOpt Trimming |
][const_335_445 | SmartOpt Trimming |
][const_336_449 | SmartOpt Trimming |
][const_337_450 | SmartOpt Trimming |
][const_338_453 | SmartOpt Trimming |
][const_339_454 | SmartOpt Trimming |
][const_33_46 | SmartOpt Trimming |
][const_340_457 | SmartOpt Trimming |
][const_341_458 | SmartOpt Trimming |
][const_342_460 | SmartOpt Trimming |
][const_343_461 | SmartOpt Trimming |
][const_345_463 | SmartOpt Trimming |
][const_346_464 | SmartOpt Trimming |
][const_348_465 | SmartOpt Trimming |
][const_349_466 | SmartOpt Trimming |
][const_34_50 | SmartOpt Trimming |
][const_350_467 | SmartOpt Trimming |
][const_351_468 | SmartOpt Trimming |
][const_352_469 | SmartOpt Trimming |
][const_353_470 | SmartOpt Trimming |
][const_354_471 | SmartOpt Trimming |
][const_355_472 | SmartOpt Trimming |
][const_356_473 | SmartOpt Trimming |
][const_357_474 | SmartOpt Trimming |
][const_358_475 | SmartOpt Trimming |
][const_359_476 | SmartOpt Trimming |
][const_35_51 | SmartOpt Trimming |
][const_360_477 | SmartOpt Trimming |
][const_361_478 | SmartOpt Trimming |
][const_362_479 | SmartOpt Trimming |
][const_363_480 | SmartOpt Trimming |
][const_364_483 | SmartOpt Trimming |
][const_365_484 | SmartOpt Trimming |
][const_366_488 | SmartOpt Trimming |
][const_367_489 | SmartOpt Trimming |
][const_368_491 | SmartOpt Trimming |
][const_369_492 | SmartOpt Trimming |
][const_36_55 | SmartOpt Trimming |
][const_370_495 | SmartOpt Trimming |
][const_371_496 | SmartOpt Trimming |
][const_372_499 | SmartOpt Trimming |
][const_373_500 | SmartOpt Trimming |
][const_374_504 | SmartOpt Trimming |
][const_375_505 | SmartOpt Trimming |
][const_376_506 | SmartOpt Trimming |
][const_377_507 | SmartOpt Trimming |
][const_378_510 | SmartOpt Trimming |
][const_379_511 | SmartOpt Trimming |
][const_37_56 | SmartOpt Trimming |
][const_380_512 | SmartOpt Trimming |
][const_381_513 | SmartOpt Trimming |
][const_383_515 | SmartOpt Trimming |
][const_384_516 | SmartOpt Trimming |
][const_386_517 | SmartOpt Trimming |
][const_387_518 | SmartOpt Trimming |
][const_389_520 | SmartOpt Trimming |
][const_38_60 | SmartOpt Trimming |
][const_390_521 | SmartOpt Trimming |
][const_392_523 | SmartOpt Trimming |
][const_393_524 | SmartOpt Trimming |
][const_395_526 | SmartOpt Trimming |
][const_396_527 | SmartOpt Trimming |
][const_398_528 | SmartOpt Trimming |
][const_399_529 | SmartOpt Trimming |
][const_39_61 | SmartOpt Trimming |
][const_401_531 | SmartOpt Trimming |
][const_402_532 | SmartOpt Trimming |
][const_405_534 | SmartOpt Trimming |
][const_407_537 | SmartOpt Trimming |
][const_409_540 | SmartOpt Trimming |
][const_40_65 | SmartOpt Trimming |
][const_411_542 | SmartOpt Trimming |
][const_412_543 | SmartOpt Trimming |
][const_413_544 | SmartOpt Trimming |
][const_415_545 | SmartOpt Trimming |
][const_416_546 | SmartOpt Trimming |
][const_418_547 | SmartOpt Trimming |
][const_419_548 | SmartOpt Trimming |
][const_41_66 | SmartOpt Trimming |
][const_421_549 | SmartOpt Trimming |
][const_422_550 | SmartOpt Trimming |
][const_424_551 | SmartOpt Trimming |
][const_425_552 | SmartOpt Trimming |
][const_427_553 | SmartOpt Trimming |
][const_428_554 | SmartOpt Trimming |
][const_42_70 | SmartOpt Trimming |
][const_430_555 | SmartOpt Trimming |
][const_431_556 | SmartOpt Trimming |
][const_433_557 | SmartOpt Trimming |
][const_434_558 | SmartOpt Trimming |
][const_436_560 | SmartOpt Trimming |
][const_437_561 | SmartOpt Trimming |
][const_439_564 | SmartOpt Trimming |
][const_43_71 | SmartOpt Trimming |
][const_440_565 | SmartOpt Trimming |
][const_442_566 | SmartOpt Trimming |
][const_443_567 | SmartOpt Trimming |
][const_445_570 | SmartOpt Trimming |
][const_446_571 | SmartOpt Trimming |
][const_448_573 | SmartOpt Trimming |
][const_449_574 | SmartOpt Trimming |
][const_44_75 | SmartOpt Trimming |
][const_451_576 | SmartOpt Trimming |
][const_452_577 | SmartOpt Trimming |
][const_454_578 | SmartOpt Trimming |
][const_455_579 | SmartOpt Trimming |
][const_456_580 | SmartOpt Trimming |
][const_457_581 | SmartOpt Trimming |
][const_458_582 | SmartOpt Trimming |
][const_459_583 | SmartOpt Trimming |
][const_45_76 | SmartOpt Trimming |
][const_461_584 | SmartOpt Trimming |
][const_462_585 | SmartOpt Trimming |
][const_464_587 | SmartOpt Trimming |
][const_465_588 | SmartOpt Trimming |
][const_467_590 | SmartOpt Trimming |
][const_468_591 | SmartOpt Trimming |
][const_46_83 | SmartOpt Trimming |
][const_470_593 | SmartOpt Trimming |
][const_471_594 | SmartOpt Trimming |
][const_473_596 | SmartOpt Trimming |
][const_474_597 | SmartOpt Trimming |
][const_476_600 | SmartOpt Trimming |
][const_477_601 | SmartOpt Trimming |
][const_479_604 | SmartOpt Trimming |
][const_47_84 | SmartOpt Trimming |
][const_480_605 | SmartOpt Trimming |
][const_482_610 | SmartOpt Trimming |
][const_483_611 | SmartOpt Trimming |
][const_485_613 | SmartOpt Trimming |
][const_486_614 | SmartOpt Trimming |
][const_488_616 | SmartOpt Trimming |
][const_489_617 | SmartOpt Trimming |
][const_48_88 | SmartOpt Trimming |
][const_491_619 | SmartOpt Trimming |
][const_492_620 | SmartOpt Trimming |
][const_494_622 | SmartOpt Trimming |
][const_495_623 | SmartOpt Trimming |
][const_497_625 | SmartOpt Trimming |
][const_498_626 | SmartOpt Trimming |
][const_49_89 | SmartOpt Trimming |
][const_500_628 | SmartOpt Trimming |
][const_501_629 | SmartOpt Trimming |
][const_503_631 | SmartOpt Trimming |
][const_504_632 | SmartOpt Trimming |
][const_506_637 | SmartOpt Trimming |
][const_507_638 | SmartOpt Trimming |
][const_509_640 | SmartOpt Trimming |
][const_50_93 | SmartOpt Trimming |
][const_510_641 | SmartOpt Trimming |
][const_512_643 | SmartOpt Trimming |
][const_513_644 | SmartOpt Trimming |
][const_515_646 | SmartOpt Trimming |
][const_516_647 | SmartOpt Trimming |
][const_518_649 | SmartOpt Trimming |
][const_519_650 | SmartOpt Trimming |
][const_51_94 | SmartOpt Trimming |
][const_521_652 | SmartOpt Trimming |
][const_522_653 | SmartOpt Trimming |
][const_524_655 | SmartOpt Trimming |
][const_525_656 | SmartOpt Trimming |
][const_527_658 | SmartOpt Trimming |
][const_528_659 | SmartOpt Trimming |
][const_52_98 | SmartOpt Trimming |
][const_53_99 | SmartOpt Trimming |
][const_54_103 | SmartOpt Trimming |
][const_55_104 | SmartOpt Trimming |
][const_56_106 | SmartOpt Trimming |
][const_57_107 | SmartOpt Trimming |
][const_58_111 | SmartOpt Trimming |
][const_59_112 | SmartOpt Trimming |
][const_60_113 | SmartOpt Trimming |
][const_61_114 | SmartOpt Trimming |
][const_62_116 | SmartOpt Trimming |
][const_63_117 | SmartOpt Trimming |
][const_64_118 | SmartOpt Trimming |
][const_65_119 | SmartOpt Trimming |
][const_66_120 | SmartOpt Trimming |
][const_67_121 | SmartOpt Trimming |
][const_68_122 | SmartOpt Trimming |
][const_69_123 | SmartOpt Trimming |
][const_70_124 | SmartOpt Trimming |
][const_71_125 | SmartOpt Trimming |
][const_72_126 | SmartOpt Trimming |
][const_73_127 | SmartOpt Trimming |
][const_74_128 | SmartOpt Trimming |
][const_75_129 | SmartOpt Trimming |
][const_76_130 | SmartOpt Trimming |
][const_77_131 | SmartOpt Trimming |
][const_78_133 | SmartOpt Trimming |
][const_79_134 | SmartOpt Trimming |
][const_80_135 | SmartOpt Trimming |
][const_81_136 | SmartOpt Trimming |
][const_82_137 | SmartOpt Trimming |
][const_83_138 | SmartOpt Trimming |
][const_84_139 | SmartOpt Trimming |
][const_85_140 | SmartOpt Trimming |
][const_86_141 | SmartOpt Trimming |
][const_87_142 | SmartOpt Trimming |
][const_88_143 | SmartOpt Trimming |
][const_89_144 | SmartOpt Trimming |
][const_90_145 | SmartOpt Trimming |
][const_91_146 | SmartOpt Trimming |
][const_92_147 | SmartOpt Trimming |
][const_93_148 | SmartOpt Trimming |
][const_94_150 | SmartOpt Trimming |
][const_95_151 | SmartOpt Trimming |
][const_96_152 | SmartOpt Trimming |
][const_97_153 | SmartOpt Trimming |
][const_98_154 | SmartOpt Trimming |
][const_99_155 | SmartOpt Trimming |
|
|
Flops added for Enable Generation |
------------------------- |
/syn/spi_test_ct.wcfg
3,7 → 3,7
<wave_state> |
</wave_state> |
<db_ref_list> |
<db_ref path="C:/dropbox/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto"> |
<db_ref path="D:/Dropbox/VHDL_training/ISE_projects/spi_ms_atlys_ct/testbench_isim_translate.wdb" id="1" type="auto"> |
<top_modules> |
<top_module name="numeric_std" /> |
<top_module name="std_logic_1164" /> |
16,7 → 16,7
</top_modules> |
</db_ref> |
</db_ref_list> |
<WVObjectSize size="22" /> |
<WVObjectSize size="21" /> |
<wvobject fp_name="/testbench/dbg" type="array" db_ref_id="1"> |
<obj_property name="ElementShortName">dbg[11:0]</obj_property> |
<obj_property name="ObjectShortName">dbg[11:0]</obj_property> |
48,10 → 48,6
<obj_property name="ElementShortName">spi_mosi</obj_property> |
<obj_property name="ObjectShortName">spi_mosi</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/dbg[3]" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">[3]</obj_property> |
<obj_property name="ObjectShortName">dbg[3]</obj_property> |
</wvobject> |
<wvobject fp_name="/testbench/spi_miso" type="logic" db_ref_id="1"> |
<obj_property name="ElementShortName">spi_miso</obj_property> |
<obj_property name="ObjectShortName">spi_miso</obj_property> |
/syn/spi_master_atlys_top.pcf
0,0 → 1,50
//! ************************************************************************** |
// Written by: Map O.40d on Wed Aug 10 22:56:48 2011 |
//! ************************************************************************** |
|
SCHEMATIC START; |
COMP "dbg_o<10>" LOCATE = SITE "V13" LEVEL 1; |
COMP "dbg_o<11>" LOCATE = SITE "U13" LEVEL 1; |
COMP "spi_miso_o" LOCATE = SITE "V15" LEVEL 1; |
COMP "spi_mosi_o" LOCATE = SITE "U15" LEVEL 1; |
COMP "sw_i<0>" LOCATE = SITE "A10" LEVEL 1; |
COMP "sw_i<1>" LOCATE = SITE "D14" LEVEL 1; |
COMP "sw_i<2>" LOCATE = SITE "C14" LEVEL 1; |
COMP "sw_i<3>" LOCATE = SITE "P15" LEVEL 1; |
COMP "sw_i<4>" LOCATE = SITE "P12" LEVEL 1; |
COMP "sw_i<5>" LOCATE = SITE "R5" LEVEL 1; |
COMP "sw_i<6>" LOCATE = SITE "T5" LEVEL 1; |
COMP "sw_i<7>" LOCATE = SITE "E4" LEVEL 1; |
COMP "spi_ssel_o" LOCATE = SITE "U16" LEVEL 1; |
COMP "m_state_o<0>" LOCATE = SITE "T3" LEVEL 1; |
COMP "m_state_o<1>" LOCATE = SITE "R3" LEVEL 1; |
COMP "m_state_o<2>" LOCATE = SITE "P6" LEVEL 1; |
COMP "m_state_o<3>" LOCATE = SITE "N5" LEVEL 1; |
COMP "dbg_o<0>" LOCATE = SITE "N9" LEVEL 1; |
COMP "dbg_o<1>" LOCATE = SITE "M10" LEVEL 1; |
COMP "dbg_o<2>" LOCATE = SITE "P11" LEVEL 1; |
COMP "dbg_o<3>" LOCATE = SITE "N10" LEVEL 1; |
COMP "dbg_o<4>" LOCATE = SITE "V12" LEVEL 1; |
COMP "dbg_o<5>" LOCATE = SITE "T12" LEVEL 1; |
COMP "dbg_o<6>" LOCATE = SITE "T11" LEVEL 1; |
COMP "dbg_o<7>" LOCATE = SITE "R11" LEVEL 1; |
COMP "dbg_o<8>" LOCATE = SITE "N11" LEVEL 1; |
COMP "dbg_o<9>" LOCATE = SITE "M11" LEVEL 1; |
COMP "btn_i<0>" LOCATE = SITE "T15" LEVEL 1; |
COMP "btn_i<1>" LOCATE = SITE "N4" LEVEL 1; |
COMP "btn_i<2>" LOCATE = SITE "P4" LEVEL 1; |
COMP "btn_i<3>" LOCATE = SITE "P3" LEVEL 1; |
COMP "btn_i<4>" LOCATE = SITE "F6" LEVEL 1; |
COMP "btn_i<5>" LOCATE = SITE "F5" LEVEL 1; |
COMP "led_o<0>" LOCATE = SITE "U18" LEVEL 1; |
COMP "led_o<1>" LOCATE = SITE "M14" LEVEL 1; |
COMP "led_o<2>" LOCATE = SITE "N14" LEVEL 1; |
COMP "led_o<3>" LOCATE = SITE "L14" LEVEL 1; |
COMP "led_o<4>" LOCATE = SITE "M13" LEVEL 1; |
COMP "led_o<5>" LOCATE = SITE "D4" LEVEL 1; |
COMP "led_o<6>" LOCATE = SITE "P16" LEVEL 1; |
COMP "led_o<7>" LOCATE = SITE "N12" LEVEL 1; |
COMP "gclk_i" LOCATE = SITE "L15" LEVEL 1; |
COMP "spi_sck_o" LOCATE = SITE "V16" LEVEL 1; |
SCHEMATIC END; |
|
/syn/spi_ms_atlys.xise
0,0 → 1,379
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="spi_master_atlys_top.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="spi_master.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="grp_debouncer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="spi_master_atlys.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="spi_master_atlys_test.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> |
</file> |
</files> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
<properties> |
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Gray" xil_pn:valueState="non-default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map" xil_pn:value="Area" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_master_atlys_top|behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="spi_master_atlys_top.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Area" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spi_master_atlys_top_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="spi_master_atlys_top_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spi_master_atlys_top_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spi_master_atlys_top_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="Testbed for the spi master/slave cores for continuous transmission mode" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spi_master_atlys_top" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="inst_spi_master_atlys_top" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="30000 ns" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="12000 ns" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="12 us" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/13.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="spi_master_atlys" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-07T09:55:20" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C5BE631B69F48AB8C2F24035AF7A13B" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings> |
<binding xil_pn:location="/spi_master_atlys_top" xil_pn:name="spi_master_atlys.ucf"/> |
</bindings> |
|
<libraries/> |
|
</project> |
/syn/par_usage_statistics.html
0,0 → 1,32
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> |
<xtag-section name="ParStatistics"> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>302</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>829</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>829</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>710</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.2 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.6 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.9 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>9.3 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.7 sec</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>7.8</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.6</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.7</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>26.3</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> |
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0172</xtag-par-property-value></TD></TR> |
</xtag-section> |
</TABLE> |
/syn/spi_master_atlys_top_summary.html
0,0 → 1,442
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status (08/10/2011 - 22:59:24)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>spi_ms_atlys.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
<TD> No Errors </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>spi_master_atlys_top</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Programming File Generated</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6slx45-2csg324</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/*.xmsgs?&DataKey=Warning'>30 Warnings (30 new)</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.unroutes'>All Signals Completely Routed</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_envsettings.html'> |
System Settings</A> |
</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD>0 <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=CENTER BGCOLOR='#FFFF99'> |
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> |
<TD ALIGN=RIGHT>209</TD> |
<TD ALIGN=RIGHT>54,576</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD> |
<TD ALIGN=RIGHT>209</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latch-thrus</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as AND/OR logics</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> |
<TD ALIGN=RIGHT>145</TD> |
<TD ALIGN=RIGHT>27,288</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD> |
<TD ALIGN=RIGHT>127</TD> |
<TD ALIGN=RIGHT>27,288</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>75</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>13</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>39</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as ROM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Memory</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>6,408</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Dual Port RAM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Single Port RAM</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Shift Register</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O6 output only</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 output only</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number using O5 and O6</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used exclusively as route-thrus</TD> |
<TD ALIGN=RIGHT>14</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice register load</TD> |
<TD ALIGN=RIGHT>12</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with same-slice carry load</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with other load</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> |
<TD ALIGN=RIGHT>91</TD> |
<TD ALIGN=RIGHT>6,822</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused Flip Flop</TD> |
<TD ALIGN=RIGHT>49</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>21%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number with an unused LUT</TD> |
<TD ALIGN=RIGHT>80</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>35%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of fully used LUT-FF pairs</TD> |
<TD ALIGN=RIGHT>96</TD> |
<TD ALIGN=RIGHT>225</TD> |
<TD ALIGN=RIGHT>42%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of unique control sets</TD> |
<TD ALIGN=RIGHT>25</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of slice register sites lost<BR> to control set restrictions</TD> |
<TD ALIGN=RIGHT>59</TD> |
<TD ALIGN=RIGHT>54,576</TD> |
<TD ALIGN=RIGHT>1%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD> |
<TD ALIGN=RIGHT>63</TD> |
<TD ALIGN=RIGHT>218</TD> |
<TD ALIGN=RIGHT>28%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of LOCed IOBs</TD> |
<TD ALIGN=RIGHT>43</TD> |
<TD ALIGN=RIGHT>63</TD> |
<TD ALIGN=RIGHT>68%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>116</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>232</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>32</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>16</TD> |
<TD ALIGN=RIGHT>12%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGs</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as BUFGMUX</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>376</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>256</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>8</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>58</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>2</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>4</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD> |
<TD ALIGN=RIGHT>0</TD> |
<TD ALIGN=RIGHT>1</TD> |
<TD ALIGN=RIGHT>0%</TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> |
<TD ALIGN=RIGHT>2.81</TD> |
<TD> </TD> |
<TD> </TD> |
<TD COLSPAN='2'> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD> |
<TD>0 (Setup: 0, Hold: 0)</TD> |
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.unroutes'>All Signals Completely Routed</A></TD> |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD> |
<TD BGCOLOR='#FFFF99'><B> </B></TD> |
<TD COLSPAN='2'> </TD> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:21 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Warning'>29 Warnings (29 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/xst.xmsgs?&DataKey=Info'>22 Infos (22 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:26 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:56:49 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/map.xmsgs?&DataKey=Info'>13 Infos (13 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:57:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:57:08 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Aug 10 22:59:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\spi_master_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:56:49 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:59:16 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/spi_master_slave/spi_master_slave/trunk/syn\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Aug 10 22:59:24 2011</TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 08/10/2011 - 22:59:24</center> |
</BODY></HTML> |
/syn/spi_master_atlys_top.par
0,0 → 1,187
Release 13.1 par O.40d (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
|
DEVELOP-W7:: Wed Aug 10 22:56:51 2011 |
|
par -w -intstyle ise -ol high -xe n -mt 4 spi_master_atlys_top_map.ncd |
spi_master_atlys_top.ncd spi_master_atlys_top.pcf |
|
|
Constraints file: spi_master_atlys_top.pcf. |
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\. |
"spi_master_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2 |
|
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) |
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) |
|
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par |
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all |
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be |
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. |
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". |
|
Device speed data version: "PRODUCTION 1.18 2011-04-07". |
|
|
|
Device Utilization Summary: |
|
Slice Logic Utilization: |
Number of Slice Registers: 209 out of 54,576 1% |
Number used as Flip Flops: 209 |
Number used as Latches: 0 |
Number used as Latch-thrus: 0 |
Number used as AND/OR logics: 0 |
Number of Slice LUTs: 145 out of 27,288 1% |
Number used as logic: 127 out of 27,288 1% |
Number using O6 output only: 75 |
Number using O5 output only: 13 |
Number using O5 and O6: 39 |
Number used as ROM: 0 |
Number used as Memory: 4 out of 6,408 1% |
Number used as Dual Port RAM: 0 |
Number used as Single Port RAM: 0 |
Number used as Shift Register: 4 |
Number using O6 output only: 4 |
Number using O5 output only: 0 |
Number using O5 and O6: 0 |
Number used exclusively as route-thrus: 14 |
Number with same-slice register load: 12 |
Number with same-slice carry load: 2 |
Number with other load: 0 |
|
Slice Logic Distribution: |
Number of occupied Slices: 91 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 225 |
Number with an unused Flip Flop: 49 out of 225 21% |
Number with an unused LUT: 80 out of 225 35% |
Number of fully used LUT-FF pairs: 96 out of 225 42% |
Number of slice register sites lost |
to control set restrictions: 0 out of 54,576 0% |
|
A LUT Flip Flop pair for this architecture represents one LUT paired with |
one Flip Flop within a slice. A control set is a unique combination of |
clock, reset, set, and enable signals for a registered element. |
The Slice Logic Distribution report is not meaningful if the design is |
over-mapped for a non-slice resource or if Placement fails. |
|
IO Utilization: |
Number of bonded IOBs: 63 out of 218 28% |
Number of LOCed IOBs: 43 out of 63 68% |
|
Specific Feature Utilization: |
Number of RAMB16BWERs: 0 out of 116 0% |
Number of RAMB8BWERs: 0 out of 232 0% |
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
Number of BUFG/BUFGMUXs: 2 out of 16 12% |
Number used as BUFGs: 2 |
Number used as BUFGMUX: 0 |
Number of DCM/DCM_CLKGENs: 0 out of 8 0% |
Number of ILOGIC2/ISERDES2s: 0 out of 376 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% |
Number of OLOGIC2/OSERDES2s: 0 out of 376 0% |
Number of BSCANs: 0 out of 4 0% |
Number of BUFHs: 0 out of 256 0% |
Number of BUFPLLs: 0 out of 8 0% |
Number of BUFPLL_MCBs: 0 out of 4 0% |
Number of DSP48A1s: 0 out of 58 0% |
Number of ICAPs: 0 out of 1 0% |
Number of MCBs: 0 out of 2 0% |
Number of PCILOGICSEs: 0 out of 2 0% |
Number of PLL_ADVs: 0 out of 4 0% |
Number of PMVs: 0 out of 1 0% |
Number of STARTUPs: 0 out of 1 0% |
Number of SUSPEND_SYNCs: 0 out of 1 0% |
|
|
Overall effort level (-ol): High |
Router effort level (-rl): High |
|
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor. |
|
Starting initial Timing Analysis. REAL time: 4 secs |
Finished initial Timing Analysis. REAL time: 4 secs |
|
Starting Router |
|
|
Phase 1 : 910 unrouted; REAL time: 5 secs |
|
Phase 2 : 760 unrouted; REAL time: 6 secs |
|
Phase 3 : 207 unrouted; REAL time: 7 secs |
|
Phase 4 : 207 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Updating file: spi_master_atlys_top.ncd with current fully routed design. |
|
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
|
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs |
Total REAL time to Router completion: 9 secs |
Total CPU time to Router completion: 9 secs |
|
Partition Implementation Status |
------------------------------- |
|
No Partitions were found in this design. |
|
------------------------------- |
|
Generating "PAR" statistics. |
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. |
Timing Score: 0 (Setup: 0, Hold: 0) |
|
Asterisk (*) preceding a constraint indicates it was not met. |
This may be due to a setup or hold violation. |
|
---------------------------------------------------------------------------------------------------------- |
Constraint | Check | Worst Case | Best Case | Timing | Timing |
| | Slack | Achievable | Errors | Score |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net gcl | SETUP | N/A| 5.299ns| N/A| 0 |
k_i_BUFGP | HOLD | 0.388ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
Autotimespec constraint for clock net Ins | SETUP | N/A| 5.052ns| N/A| 0 |
t_spi_master_port/spi_clk_reg_BUFG | HOLD | 0.497ns| | 0| 0 |
---------------------------------------------------------------------------------------------------------- |
|
|
All constraints were met. |
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the |
constraint is not analyzed due to the following: No paths covered by this |
constraint; Other constraints intersect with this constraint; or This |
constraint was disabled by a Path Tracing Control. Please run the Timespec |
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. |
|
|
Generating Pad Report. |
|
All signals are completely routed. |
|
Total REAL time to PAR completion: 10 secs |
Total CPU time to PAR completion: 10 secs |
|
Peak Memory Usage: 269 MB |
|
Placer: Placement generated during map. |
Routing: Completed - No errors found. |
|
Number of error messages: 0 |
Number of warning messages: 1 |
Number of info messages: 2 |
|
Writing design to file spi_master_atlys_top.ncd |
|
|
|
PAR done! |
/syn/spi_master_summary.html
0,0 → 1,94
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>spi_master_atlys_top Project Status</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>spi_ms_atlys_ct.xise</TD> |
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>spi_master_atlys_top</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>New</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6slx45-2csg324</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> </TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD> </TD> |
</TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Errors</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentErrors"><B>[-]</B></a></TD></TR> |
<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='3'><B>No Errors Found</B></TD></TR> |
</TABLE> |
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='2'><B>Current Warnings</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=CurrentWarnings"><B>[-]</B></a></TD></TR> |
<TR ALIGN=LEFT BGCOLOR='#FFFF99'><TD COLSPAN='3'><B>No Warnings Found</B></TD></TR> |
</TABLE> |
|
|
|
|
|
|
|
|
|
|
|
|
|
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 08/10/2011 - 22:47:40</center> |
</BODY></HTML> |
/syn/usage_statistics_webtalk.html
17,7 → 17,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">31</xtag-property></TD> |
<TD><xtag-property name="RandomID">d557c6c4bb5b4e4fa669c510e7b04848</xtag-property>.<xtag-property name="ProjectID">2C5BE631B69F48AB8C2F24035AF7A13B</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD> |
<TD><xtag-property name="TargetPackage">csg324</xtag-property></TD> |
</TR> |
29,7 → 29,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD> |
<TD><xtag-property name="Date Generated">2011-07-18T02:50:20</xtag-property></TD> |
<TD><xtag-property name="Date Generated">2011-08-10T22:59:16</xtag-property></TD> |
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD> |
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD> |
</TR> |
84,22 → 84,21
<xtag-group><xtag-group-name name="Counters=5">Counters=5</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit up counter=3</xtag-item1></LI> |
<LI><xtag-item1>14-bit up counter=1</xtag-item1></LI> |
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI> |
<LI><xtag-item1>8-bit up counter=2</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FSMs=1">FSMs=1</xtag-group-name> |
<xtag-group><xtag-group-name name="FSMs=3">FSMs=3</xtag-group-name> |
</xtag-group> |
<xtag-group><xtag-group-name name="Multiplexers=42">Multiplexers=42</xtag-group-name> |
<xtag-group><xtag-group-name name="Multiplexers=46">Multiplexers=46</xtag-group-name> |
<UL> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=21</xtag-item1></LI> |
<LI><xtag-item1>4-bit 2-to-1 multiplexer=13</xtag-item1></LI> |
<LI><xtag-item1>8-bit 2-to-1 multiplexer=8</xtag-item1></LI> |
<LI><xtag-item1>1-bit 2-to-1 multiplexer=20</xtag-item1></LI> |
<LI><xtag-item1>4-bit 2-to-1 multiplexer=12</xtag-item1></LI> |
<LI><xtag-item1>8-bit 2-to-1 multiplexer=14</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="Registers=171">Registers=171</xtag-group-name> |
<xtag-group><xtag-group-name name="Registers=205">Registers=205</xtag-group-name> |
<UL> |
<LI><xtag-item1>Flip-Flops=171</xtag-item1></LI> |
<LI><xtag-item1>Flip-Flops=205</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
108,37 → 107,36
<TD> |
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>AGG_BONDED_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=39</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=70</xtag-item1></LI> |
<LI><xtag-item1>NUM_BONDED_IOB=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=76</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=41</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=78</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=195</xtag-item1></LI> |
<LI><xtag-item1>AGG_BONDED_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_IO=63</xtag-item1></LI> |
<LI><xtag-item1>AGG_LOCED_IO=43</xtag-item1></LI> |
<LI><xtag-item1>AGG_SLICE=91</xtag-item1></LI> |
<LI><xtag-item1>NUM_BONDED_IOB=63</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSFULL=96</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSLUTONLY=49</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSREGONLY=80</xtag-item1></LI> |
<LI><xtag-item1>NUM_BSUSED=225</xtag-item1></LI> |
<LI><xtag-item1>NUM_BUFG=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_IOB_FF=9</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=32</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=27</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=48</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOCED_IOB=43</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=39</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O5ONLY=13</xtag-item1></LI> |
<LI><xtag-item1>NUM_LOGIC_O6ONLY=75</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=6</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=6</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO5=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_EXO6=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=26</xtag-item1></LI> |
<LI><xtag-item1>NUM_OLOGIC2=9</xtag-item1></LI> |
<LI><xtag-item1>NUM_LUT_RT_O6=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEL=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEM=1</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=61</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=8</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=20</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=177</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=171</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=12</xtag-item1></LI> |
<LI><xtag-item1>NUM_SRL_O6ONLY=2</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=51</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICEX=82</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CARRY4=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CONTROLSET=25</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_CYINIT=198</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_F7MUX=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_FF=209</xtag-item1></LI> |
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=15</xtag-item1></LI> |
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI> |
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=59</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
145,39 → 143,38
<TD> |
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>NumNets_Active=311</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Active=365</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI> |
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=4</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=23</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=11</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=67</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=15</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=35</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=253</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=53</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=78</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=10</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=38</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=417</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=268</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=257</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=24</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=76</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=13</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=39</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=326</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=73</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=75</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_INPUT=8</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=58</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=561</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=313</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=298</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=44</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=15</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=178</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=530</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED2=9</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=423</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=90</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=350</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=210</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=694</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_QUAD=616</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=101</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=431</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=22</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=25</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=62</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=59</xtag-item1></LI> |
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
184,11 → 181,11
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name> |
<UL> |
<LI><xtag-item1>BUFG-BUFGMUX=2</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBM=20</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBS=19</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=4</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=17</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=8</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBM=33</xtag-item1></LI> |
<LI><xtag-item1>IOB-IOBS=30</xtag-item1></LI> |
<LI><xtag-item1>SLICEL-SLICEM=2</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEL=18</xtag-item1></LI> |
<LI><xtag-item1>SLICEX-SLICEM=20</xtag-item1></LI> |
</UL> |
</xtag-group> |
</TD> |
199,23 → 196,22
<UL> |
<LI><xtag-item2>BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>BUFG_BUFG=2</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=8</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=30</xtag-item2></LI> |
<LI><xtag-item2>CARRY4=4</xtag-item2></LI> |
<LI><xtag-item2>FF_SR=42</xtag-item2></LI> |
<LI><xtag-item2>HARD0=2</xtag-item2></LI> |
<LI><xtag-item2>IOB=39</xtag-item2></LI> |
<LI><xtag-item2>IOB=63</xtag-item2></LI> |
<LI><xtag-item2>IOB_IMUX=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_INBUF=15</xtag-item2></LI> |
<LI><xtag-item2>IOB_OUTBUF=24</xtag-item2></LI> |
<LI><xtag-item2>LUT5=65</xtag-item2></LI> |
<LI><xtag-item2>LUT6=108</xtag-item2></LI> |
<LI><xtag-item2>LUT_OR_MEM6=2</xtag-item2></LI> |
<LI><xtag-item2>OLOGIC2=9</xtag-item2></LI> |
<LI><xtag-item2>OLOGIC2_OUTFF=9</xtag-item2></LI> |
<LI><xtag-item2>PAD=39</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=141</xtag-item2></LI> |
<LI><xtag-item2>IOB_OUTBUF=48</xtag-item2></LI> |
<LI><xtag-item2>LUT5=64</xtag-item2></LI> |
<LI><xtag-item2>LUT6=128</xtag-item2></LI> |
<LI><xtag-item2>LUT_OR_MEM6=4</xtag-item2></LI> |
<LI><xtag-item2>PAD=63</xtag-item2></LI> |
<LI><xtag-item2>REG_SR=167</xtag-item2></LI> |
<LI><xtag-item2>SELMUX2_1=4</xtag-item2></LI> |
<LI><xtag-item2>SLICEL=8</xtag-item2></LI> |
<LI><xtag-item2>SLICEM=1</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=61</xtag-item2></LI> |
<LI><xtag-item2>SLICEX=82</xtag-item2></LI> |
</UL> |
</xtag-group> |
</TD> |
227,52 → 223,33
<TD> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:26] [CK_INV:4]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:30]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:28] [SYNC:2]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:42] [CK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:42]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:36] [SYNC:6]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name> |
<UL> |
<LI><xtag-item3>DRIVEATTRBOX=[12:24]</xtag-item3></LI> |
<LI><xtag-item3>SLEW=[SLOW:24]</xtag-item3></LI> |
<LI><xtag-item3>SUSPEND=[3STATE:24]</xtag-item3></LI> |
<LI><xtag-item3>DRIVEATTRBOX=[12:48]</xtag-item3></LI> |
<LI><xtag-item3>SLEW=[SLOW:48]</xtag-item3></LI> |
<LI><xtag-item3>SUSPEND=[3STATE:48]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> |
<UL> |
<LI><xtag-item3>LUT_OR_MEM=[LUT:1]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:2] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>LUT_OR_MEM=[RAM:2]</xtag-item3></LI> |
<LI><xtag-item3>RAMMODE=[SRL16:2]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:4] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>LUT_OR_MEM=[RAM:4]</xtag-item3></LI> |
<LI><xtag-item3>RAMMODE=[SRL16:4]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK0=[CLK0_INV:0] [CLK0:9]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK0=[CK0_INV:0] [CK0:9]</xtag-item3></LI> |
<LI><xtag-item3>OUTFFTYPE=[FF:9]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT_OQ=[0:9]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item3>CK=[CK:125] [CK_INV:16]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:141]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:139] [SRINIT1:2]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:121] [SYNC:20]</xtag-item3></LI> |
<LI><xtag-item3>CK=[CK:166] [CK_INV:1]</xtag-item3></LI> |
<LI><xtag-item3>LATCH_OR_FF=[FF:167]</xtag-item3></LI> |
<LI><xtag-item3>SRINIT=[SRINIT0:164] [SRINIT1:3]</xtag-item3></LI> |
<LI><xtag-item3>SYNC_ATTR=[ASYNC:159] [SYNC:8]</xtag-item3></LI> |
</UL> |
</TD> |
<TD> |
279,7 → 256,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:5] [CLK_INV:0]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:3] [CLK_INV:1]</xtag-item3></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> |
289,7 → 266,7
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item3>CLK=[CLK:46] [CLK_INV:6]</xtag-item3></LI> |
<LI><xtag-item3>CLK=[CLK:71] [CLK_INV:0]</xtag-item3></LI> |
</UL> |
</xtag-group> |
</TD> |
313,30 → 290,30
</xtag-group> |
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name> |
<UL> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CO3=6</xtag-item1></LI> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CO3=2</xtag-item1></LI> |
<LI><xtag-item1>CYINIT=2</xtag-item1></LI> |
<LI><xtag-item1>DI0=8</xtag-item1></LI> |
<LI><xtag-item1>DI1=7</xtag-item1></LI> |
<LI><xtag-item1>DI2=7</xtag-item1></LI> |
<LI><xtag-item1>DI3=6</xtag-item1></LI> |
<LI><xtag-item1>O0=8</xtag-item1></LI> |
<LI><xtag-item1>O1=8</xtag-item1></LI> |
<LI><xtag-item1>O2=7</xtag-item1></LI> |
<LI><xtag-item1>O3=7</xtag-item1></LI> |
<LI><xtag-item1>S0=8</xtag-item1></LI> |
<LI><xtag-item1>S1=8</xtag-item1></LI> |
<LI><xtag-item1>S2=7</xtag-item1></LI> |
<LI><xtag-item1>S3=7</xtag-item1></LI> |
<LI><xtag-item1>DI0=4</xtag-item1></LI> |
<LI><xtag-item1>DI1=4</xtag-item1></LI> |
<LI><xtag-item1>DI2=4</xtag-item1></LI> |
<LI><xtag-item1>DI3=2</xtag-item1></LI> |
<LI><xtag-item1>O0=4</xtag-item1></LI> |
<LI><xtag-item1>O1=4</xtag-item1></LI> |
<LI><xtag-item1>O2=4</xtag-item1></LI> |
<LI><xtag-item1>O3=4</xtag-item1></LI> |
<LI><xtag-item1>S0=4</xtag-item1></LI> |
<LI><xtag-item1>S1=4</xtag-item1></LI> |
<LI><xtag-item1>S2=4</xtag-item1></LI> |
<LI><xtag-item1>S3=4</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=14</xtag-item1></LI> |
<LI><xtag-item1>CK=30</xtag-item1></LI> |
<LI><xtag-item1>D=30</xtag-item1></LI> |
<LI><xtag-item1>Q=30</xtag-item1></LI> |
<LI><xtag-item1>SR=4</xtag-item1></LI> |
<LI><xtag-item1>CE=20</xtag-item1></LI> |
<LI><xtag-item1>CK=42</xtag-item1></LI> |
<LI><xtag-item1>D=42</xtag-item1></LI> |
<LI><xtag-item1>Q=42</xtag-item1></LI> |
<LI><xtag-item1>SR=7</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name> |
347,8 → 324,8
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name> |
<UL> |
<LI><xtag-item1>I=15</xtag-item1></LI> |
<LI><xtag-item1>O=24</xtag-item1></LI> |
<LI><xtag-item1>PAD=39</xtag-item1></LI> |
<LI><xtag-item1>O=48</xtag-item1></LI> |
<LI><xtag-item1>PAD=63</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_IMUX">IOB_IMUX</xtag-group-name> |
365,125 → 342,106
</xtag-group> |
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name> |
<UL> |
<LI><xtag-item1>IN=24</xtag-item1></LI> |
<LI><xtag-item1>OUT=24</xtag-item1></LI> |
<LI><xtag-item1>IN=48</xtag-item1></LI> |
<LI><xtag-item1>OUT=48</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=15</xtag-item1></LI> |
<LI><xtag-item1>A2=23</xtag-item1></LI> |
<LI><xtag-item1>A3=14</xtag-item1></LI> |
<LI><xtag-item1>A4=16</xtag-item1></LI> |
<LI><xtag-item1>A5=19</xtag-item1></LI> |
<LI><xtag-item1>O5=65</xtag-item1></LI> |
<LI><xtag-item1>A1=17</xtag-item1></LI> |
<LI><xtag-item1>A2=29</xtag-item1></LI> |
<LI><xtag-item1>A3=31</xtag-item1></LI> |
<LI><xtag-item1>A4=30</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>O5=64</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=39</xtag-item1></LI> |
<LI><xtag-item1>A2=58</xtag-item1></LI> |
<LI><xtag-item1>A3=69</xtag-item1></LI> |
<LI><xtag-item1>A4=90</xtag-item1></LI> |
<LI><xtag-item1>A5=91</xtag-item1></LI> |
<LI><xtag-item1>A6=107</xtag-item1></LI> |
<LI><xtag-item1>O6=108</xtag-item1></LI> |
<LI><xtag-item1>A1=34</xtag-item1></LI> |
<LI><xtag-item1>A2=66</xtag-item1></LI> |
<LI><xtag-item1>A3=97</xtag-item1></LI> |
<LI><xtag-item1>A4=108</xtag-item1></LI> |
<LI><xtag-item1>A5=126</xtag-item1></LI> |
<LI><xtag-item1>A6=128</xtag-item1></LI> |
<LI><xtag-item1>O6=128</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name> |
<UL> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=1</xtag-item1></LI> |
<LI><xtag-item1>O5=1</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=2</xtag-item1></LI> |
<LI><xtag-item1>A2=2</xtag-item1></LI> |
<LI><xtag-item1>A3=2</xtag-item1></LI> |
<LI><xtag-item1>A4=2</xtag-item1></LI> |
<LI><xtag-item1>A5=2</xtag-item1></LI> |
<LI><xtag-item1>A6=2</xtag-item1></LI> |
<LI><xtag-item1>CLK=2</xtag-item1></LI> |
<LI><xtag-item1>DI2=2</xtag-item1></LI> |
<LI><xtag-item1>O6=2</xtag-item1></LI> |
<LI><xtag-item1>WE=2</xtag-item1></LI> |
<LI><xtag-item1>A1=4</xtag-item1></LI> |
<LI><xtag-item1>A2=4</xtag-item1></LI> |
<LI><xtag-item1>A3=4</xtag-item1></LI> |
<LI><xtag-item1>A4=4</xtag-item1></LI> |
<LI><xtag-item1>A5=4</xtag-item1></LI> |
<LI><xtag-item1>A6=4</xtag-item1></LI> |
<LI><xtag-item1>CLK=4</xtag-item1></LI> |
<LI><xtag-item1>DI2=4</xtag-item1></LI> |
<LI><xtag-item1>O6=4</xtag-item1></LI> |
<LI><xtag-item1>WE=4</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2">OLOGIC2</xtag-group-name> |
<UL> |
<LI><xtag-item1>CLK0=9</xtag-item1></LI> |
<LI><xtag-item1>D1=9</xtag-item1></LI> |
<LI><xtag-item1>OQ=9</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="OLOGIC2_OUTFF">OLOGIC2_OUTFF</xtag-group-name> |
<UL> |
<LI><xtag-item1>CK0=9</xtag-item1></LI> |
<LI><xtag-item1>D1=9</xtag-item1></LI> |
<LI><xtag-item1>Q=9</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name> |
<UL> |
<LI><xtag-item1>PAD=39</xtag-item1></LI> |
<LI><xtag-item1>PAD=63</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> |
<UL> |
<LI><xtag-item1>CE=69</xtag-item1></LI> |
<LI><xtag-item1>CK=141</xtag-item1></LI> |
<LI><xtag-item1>D=141</xtag-item1></LI> |
<LI><xtag-item1>Q=141</xtag-item1></LI> |
<LI><xtag-item1>SR=23</xtag-item1></LI> |
<LI><xtag-item1>CE=92</xtag-item1></LI> |
<LI><xtag-item1>CK=167</xtag-item1></LI> |
<LI><xtag-item1>D=167</xtag-item1></LI> |
<LI><xtag-item1>Q=167</xtag-item1></LI> |
<LI><xtag-item1>SR=11</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name> |
<UL> |
<LI><xtag-item1>0=2</xtag-item1></LI> |
<LI><xtag-item1>1=2</xtag-item1></LI> |
<LI><xtag-item1>OUT=2</xtag-item1></LI> |
<LI><xtag-item1>S0=2</xtag-item1></LI> |
<LI><xtag-item1>0=4</xtag-item1></LI> |
<LI><xtag-item1>1=4</xtag-item1></LI> |
<LI><xtag-item1>OUT=4</xtag-item1></LI> |
<LI><xtag-item1>S0=4</xtag-item1></LI> |
</UL> |
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> |
<UL> |
<LI><xtag-item1>A4=3</xtag-item1></LI> |
<LI><xtag-item1>A1=1</xtag-item1></LI> |
<LI><xtag-item1>A2=1</xtag-item1></LI> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=5</xtag-item1></LI> |
<LI><xtag-item1>A6=8</xtag-item1></LI> |
<LI><xtag-item1>AMUX=5</xtag-item1></LI> |
<LI><xtag-item1>AQ=4</xtag-item1></LI> |
<LI><xtag-item1>A6=5</xtag-item1></LI> |
<LI><xtag-item1>AMUX=4</xtag-item1></LI> |
<LI><xtag-item1>AQ=2</xtag-item1></LI> |
<LI><xtag-item1>AX=1</xtag-item1></LI> |
<LI><xtag-item1>B4=4</xtag-item1></LI> |
<LI><xtag-item1>B5=3</xtag-item1></LI> |
<LI><xtag-item1>B6=8</xtag-item1></LI> |
<LI><xtag-item1>B5=4</xtag-item1></LI> |
<LI><xtag-item1>B6=4</xtag-item1></LI> |
<LI><xtag-item1>BMUX=4</xtag-item1></LI> |
<LI><xtag-item1>BQ=5</xtag-item1></LI> |
<LI><xtag-item1>BQ=1</xtag-item1></LI> |
<LI><xtag-item1>BX=1</xtag-item1></LI> |
<LI><xtag-item1>C1=1</xtag-item1></LI> |
<LI><xtag-item1>C2=4</xtag-item1></LI> |
<LI><xtag-item1>C3=4</xtag-item1></LI> |
<LI><xtag-item1>C4=4</xtag-item1></LI> |
<LI><xtag-item1>C5=3</xtag-item1></LI> |
<LI><xtag-item1>C6=7</xtag-item1></LI> |
<LI><xtag-item1>CIN=6</xtag-item1></LI> |
<LI><xtag-item1>CLK=5</xtag-item1></LI> |
<LI><xtag-item1>CMUX=3</xtag-item1></LI> |
<LI><xtag-item1>COUT=6</xtag-item1></LI> |
<LI><xtag-item1>CQ=5</xtag-item1></LI> |
<LI><xtag-item1>CX=1</xtag-item1></LI> |
<LI><xtag-item1>D=1</xtag-item1></LI> |
<LI><xtag-item1>D1=1</xtag-item1></LI> |
<LI><xtag-item1>D2=1</xtag-item1></LI> |
<LI><xtag-item1>D3=1</xtag-item1></LI> |
<LI><xtag-item1>D4=5</xtag-item1></LI> |
<LI><xtag-item1>D5=4</xtag-item1></LI> |
<LI><xtag-item1>D6=7</xtag-item1></LI> |
<LI><xtag-item1>DMUX=3</xtag-item1></LI> |
<LI><xtag-item1>DQ=5</xtag-item1></LI> |
<LI><xtag-item1>C5=8</xtag-item1></LI> |
<LI><xtag-item1>C6=8</xtag-item1></LI> |
<LI><xtag-item1>CIN=2</xtag-item1></LI> |
<LI><xtag-item1>CLK=4</xtag-item1></LI> |
<LI><xtag-item1>CMUX=5</xtag-item1></LI> |
<LI><xtag-item1>COUT=2</xtag-item1></LI> |
<LI><xtag-item1>CQ=3</xtag-item1></LI> |
<LI><xtag-item1>CX=4</xtag-item1></LI> |
<LI><xtag-item1>D1=3</xtag-item1></LI> |
<LI><xtag-item1>D2=3</xtag-item1></LI> |
<LI><xtag-item1>D3=4</xtag-item1></LI> |
<LI><xtag-item1>D4=4</xtag-item1></LI> |
<LI><xtag-item1>D5=6</xtag-item1></LI> |
<LI><xtag-item1>D6=8</xtag-item1></LI> |
<LI><xtag-item1>DMUX=4</xtag-item1></LI> |
<LI><xtag-item1>DQ=1</xtag-item1></LI> |
<LI><xtag-item1>DX=1</xtag-item1></LI> |
<LI><xtag-item1>SR=4</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
490,6 → 448,22
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> |
<UL> |
<LI><xtag-item1>A1=1</xtag-item1></LI> |
<LI><xtag-item1>A2=1</xtag-item1></LI> |
<LI><xtag-item1>A3=1</xtag-item1></LI> |
<LI><xtag-item1>A4=1</xtag-item1></LI> |
<LI><xtag-item1>A5=1</xtag-item1></LI> |
<LI><xtag-item1>A6=1</xtag-item1></LI> |
<LI><xtag-item1>AI=1</xtag-item1></LI> |
<LI><xtag-item1>AQ=1</xtag-item1></LI> |
<LI><xtag-item1>B1=1</xtag-item1></LI> |
<LI><xtag-item1>B2=1</xtag-item1></LI> |
<LI><xtag-item1>B3=1</xtag-item1></LI> |
<LI><xtag-item1>B4=1</xtag-item1></LI> |
<LI><xtag-item1>B5=1</xtag-item1></LI> |
<LI><xtag-item1>B6=1</xtag-item1></LI> |
<LI><xtag-item1>BI=1</xtag-item1></LI> |
<LI><xtag-item1>BQ=1</xtag-item1></LI> |
<LI><xtag-item1>C1=1</xtag-item1></LI> |
<LI><xtag-item1>C2=1</xtag-item1></LI> |
<LI><xtag-item1>C3=1</xtag-item1></LI> |
512,49 → 486,49
</xtag-group> |
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> |
<UL> |
<LI><xtag-item1>A=20</xtag-item1></LI> |
<LI><xtag-item1>A=16</xtag-item1></LI> |
<LI><xtag-item1>A1=16</xtag-item1></LI> |
<LI><xtag-item1>A2=19</xtag-item1></LI> |
<LI><xtag-item1>A3=24</xtag-item1></LI> |
<LI><xtag-item1>A4=26</xtag-item1></LI> |
<LI><xtag-item1>A5=27</xtag-item1></LI> |
<LI><xtag-item1>A6=27</xtag-item1></LI> |
<LI><xtag-item1>AMUX=11</xtag-item1></LI> |
<LI><xtag-item1>AQ=32</xtag-item1></LI> |
<LI><xtag-item1>AX=24</xtag-item1></LI> |
<LI><xtag-item1>B=7</xtag-item1></LI> |
<LI><xtag-item1>B1=10</xtag-item1></LI> |
<LI><xtag-item1>B2=17</xtag-item1></LI> |
<LI><xtag-item1>B3=17</xtag-item1></LI> |
<LI><xtag-item1>B4=18</xtag-item1></LI> |
<LI><xtag-item1>B5=17</xtag-item1></LI> |
<LI><xtag-item1>B6=17</xtag-item1></LI> |
<LI><xtag-item1>BMUX=7</xtag-item1></LI> |
<LI><xtag-item1>BQ=32</xtag-item1></LI> |
<LI><xtag-item1>BX=22</xtag-item1></LI> |
<LI><xtag-item1>C=8</xtag-item1></LI> |
<LI><xtag-item1>C1=6</xtag-item1></LI> |
<LI><xtag-item1>A2=26</xtag-item1></LI> |
<LI><xtag-item1>A3=32</xtag-item1></LI> |
<LI><xtag-item1>A4=34</xtag-item1></LI> |
<LI><xtag-item1>A5=35</xtag-item1></LI> |
<LI><xtag-item1>A6=32</xtag-item1></LI> |
<LI><xtag-item1>AMUX=13</xtag-item1></LI> |
<LI><xtag-item1>AQ=46</xtag-item1></LI> |
<LI><xtag-item1>AX=28</xtag-item1></LI> |
<LI><xtag-item1>B=10</xtag-item1></LI> |
<LI><xtag-item1>B1=8</xtag-item1></LI> |
<LI><xtag-item1>B2=14</xtag-item1></LI> |
<LI><xtag-item1>B3=19</xtag-item1></LI> |
<LI><xtag-item1>B4=23</xtag-item1></LI> |
<LI><xtag-item1>B5=24</xtag-item1></LI> |
<LI><xtag-item1>B6=22</xtag-item1></LI> |
<LI><xtag-item1>BMUX=8</xtag-item1></LI> |
<LI><xtag-item1>BQ=36</xtag-item1></LI> |
<LI><xtag-item1>BX=24</xtag-item1></LI> |
<LI><xtag-item1>C=9</xtag-item1></LI> |
<LI><xtag-item1>C1=9</xtag-item1></LI> |
<LI><xtag-item1>C2=12</xtag-item1></LI> |
<LI><xtag-item1>C3=14</xtag-item1></LI> |
<LI><xtag-item1>C4=15</xtag-item1></LI> |
<LI><xtag-item1>C5=16</xtag-item1></LI> |
<LI><xtag-item1>C6=15</xtag-item1></LI> |
<LI><xtag-item1>CE=25</xtag-item1></LI> |
<LI><xtag-item1>CLK=52</xtag-item1></LI> |
<LI><xtag-item1>CMUX=9</xtag-item1></LI> |
<LI><xtag-item1>CQ=27</xtag-item1></LI> |
<LI><xtag-item1>C3=18</xtag-item1></LI> |
<LI><xtag-item1>C4=20</xtag-item1></LI> |
<LI><xtag-item1>C5=23</xtag-item1></LI> |
<LI><xtag-item1>C6=21</xtag-item1></LI> |
<LI><xtag-item1>CE=29</xtag-item1></LI> |
<LI><xtag-item1>CLK=71</xtag-item1></LI> |
<LI><xtag-item1>CMUX=8</xtag-item1></LI> |
<LI><xtag-item1>CQ=35</xtag-item1></LI> |
<LI><xtag-item1>CX=19</xtag-item1></LI> |
<LI><xtag-item1>D=11</xtag-item1></LI> |
<LI><xtag-item1>D1=11</xtag-item1></LI> |
<LI><xtag-item1>D2=15</xtag-item1></LI> |
<LI><xtag-item1>D3=16</xtag-item1></LI> |
<LI><xtag-item1>D4=19</xtag-item1></LI> |
<LI><xtag-item1>D5=19</xtag-item1></LI> |
<LI><xtag-item1>D6=18</xtag-item1></LI> |
<LI><xtag-item1>DMUX=10</xtag-item1></LI> |
<LI><xtag-item1>DQ=29</xtag-item1></LI> |
<LI><xtag-item1>DX=22</xtag-item1></LI> |
<LI><xtag-item1>SR=6</xtag-item1></LI> |
<LI><xtag-item1>D=14</xtag-item1></LI> |
<LI><xtag-item1>D1=13</xtag-item1></LI> |
<LI><xtag-item1>D2=21</xtag-item1></LI> |
<LI><xtag-item1>D3=25</xtag-item1></LI> |
<LI><xtag-item1>D4=28</xtag-item1></LI> |
<LI><xtag-item1>D5=30</xtag-item1></LI> |
<LI><xtag-item1>D6=28</xtag-item1></LI> |
<LI><xtag-item1>DMUX=21</xtag-item1></LI> |
<LI><xtag-item1>DQ=39</xtag-item1></LI> |
<LI><xtag-item1>DX=24</xtag-item1></LI> |
<LI><xtag-item1>SR=10</xtag-item1></LI> |
</UL> |
</TD> |
<TD> |
567,185 → 541,10
<TR VALIGN=TOP><TD ALIGN=LEFT>Command Line History<xtag-section name="CommandLineLog"><UL> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/translate -ofmt vhdl -sim <fname>.ngd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>netgen -intstyle ise -s 2 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -insert_pp_buffers true -w -dir netgen/par -ofmt vhdl -sim <fname>.ncd <fname>.vhd</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
<LI><xtag-cmdline>xst -intstyle ise -ifn <ise_file></xtag-cmdline></LI> |
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-2 <fname>.ngc <fname>.ngd</xtag-cmdline></LI> |
<LI><xtag-cmdline>map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area -equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power off -o <fname>.ncd <fname>.ngd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>par -w -intstyle ise -ol high -xe n -mt 4 <fname>.ncd <fname>.ncd <fname>.pcf</xtag-cmdline></LI> |
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf</xtag-cmdline></LI> |
<LI><xtag-cmdline>bitgen -intstyle ise -f <fname>.ut <fname>.ncd</xtag-cmdline></LI> |
</xtag-section></UL></TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR> |
771,8 → 570,8
</tr> |
<tr> |
<td><xtag-program-name>bitgen</xtag-program-name></td> |
<td><xtag-total-run-started>137</xtag-total-run-started></td> |
<td><xtag-total-run-finished>137</xtag-total-run-finished></td> |
<td><xtag-total-run-started>178</xtag-total-run-started></td> |
<td><xtag-total-run-finished>178</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
831,8 → 630,8
</tr> |
<tr> |
<td><xtag-program-name>map</xtag-program-name></td> |
<td><xtag-total-run-started>444</xtag-total-run-started></td> |
<td><xtag-total-run-finished>429</xtag-total-run-finished></td> |
<td><xtag-total-run-started>506</xtag-total-run-started></td> |
<td><xtag-total-run-finished>490</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
841,8 → 640,8
</tr> |
<tr> |
<td><xtag-program-name>netgen</xtag-program-name></td> |
<td><xtag-total-run-started>459</xtag-total-run-started></td> |
<td><xtag-total-run-finished>451</xtag-total-run-finished></td> |
<td><xtag-total-run-started>489</xtag-total-run-started></td> |
<td><xtag-total-run-finished>481</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
861,8 → 660,8
</tr> |
<tr> |
<td><xtag-program-name>ngdbuild</xtag-program-name></td> |
<td><xtag-total-run-started>476</xtag-total-run-started></td> |
<td><xtag-total-run-finished>476</xtag-total-run-finished></td> |
<td><xtag-total-run-started>550</xtag-total-run-started></td> |
<td><xtag-total-run-finished>550</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
871,8 → 670,8
</tr> |
<tr> |
<td><xtag-program-name>par</xtag-program-name></td> |
<td><xtag-total-run-started>462</xtag-total-run-started></td> |
<td><xtag-total-run-finished>407</xtag-total-run-finished></td> |
<td><xtag-total-run-started>522</xtag-total-run-started></td> |
<td><xtag-total-run-finished>464</xtag-total-run-finished></td> |
<td><xtag-total-error>14</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
891,8 → 690,8
</tr> |
<tr> |
<td><xtag-program-name>trce</xtag-program-name></td> |
<td><xtag-total-run-started>433</xtag-total-run-started></td> |
<td><xtag-total-run-finished>433</xtag-total-run-finished></td> |
<td><xtag-total-run-started>491</xtag-total-run-started></td> |
<td><xtag-total-run-finished>491</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
921,8 → 720,8
</tr> |
<tr> |
<td><xtag-program-name>xst</xtag-program-name></td> |
<td><xtag-total-run-started>754</xtag-total-run-started></td> |
<td><xtag-total-run-finished>749</xtag-total-run-finished></td> |
<td><xtag-total-run-started>848</xtag-total-run-started></td> |
<td><xtag-total-run-finished>843</xtag-total-run-finished></td> |
<td><xtag-total-error>0</xtag-total-error></td> |
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> |
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> |
970,8 → 769,11
<TD><xtag-design-property-name>PROP_ManualCompileOrderImp</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_MapLUTCombining_spartan6</xtag-process-property-name>=<xtag-process-property-value>Area</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_ProjectDescription</xtag-process-property-name>=<xtag-process-property-value>Testbed for the spi master/slave cores for continuous transmission mode</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_PropSpecInProjFile</xtag-design-property-name>=<xtag-design-property-value>Store all values</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_SelectedInstanceHierarchicalPath</xtag-process-property-name>=<xtag-process-property-value>/testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_Simulator</xtag-design-property-name>=<xtag-design-property-value>ISim (VHDL/Verilog)</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_SynthExtractRAM</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
|
993,10 → 795,16
</TR><TR><TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2011-07-07T09:55:20</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>2C5BE631B69F48AB8C2F24035AF7A13B</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>31</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>1</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_behav</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_par</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_selectedSimRootSourceNode_translate</xtag-process-property-name>=<xtag-process-property-value>work.testbench</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_selectedSimSourceNode</xtag-process-property-name>=<xtag-process-property-value>inst_spi_master_atlys_top</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_xilxBitgStart_Clk_DriveDone</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_xilxMapReportDetail</xtag-process-property-name>=<xtag-process-property-value>true</xtag-process-property-value></TD> |
1005,6 → 813,9
</TR><TR><TD><xtag-design-property-name>PROP_AutoTop</xtag-design-property-name>=<xtag-design-property-value>false</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevFamily</xtag-design-property-name>=<xtag-design-property-value>Spartan6</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_ISimSimulationRun_behav_tb</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRun_translate_tb</xtag-process-property-name>=<xtag-process-property-value>false</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-process-property-name>PROP_MapExtraEffort_spartan6</xtag-process-property-name>=<xtag-process-property-value>Normal</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_xilxMapEnableMultiThreading</xtag-process-property-name>=<xtag-process-property-value>2</xtag-process-property-value></TD> |
|
1012,16 → 823,21
<TD><xtag-design-property-name>PROP_DevDevice</xtag-design-property-name>=<xtag-design-property-value>xc6slx45</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_DevFamilyPMName</xtag-design-property-name>=<xtag-design-property-value>spartan6</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRunTime_behav_tb</xtag-process-property-name>=<xtag-process-property-value>30000 ns</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD> |
<TD><xtag-process-property-name>PROP_parEnableMultiThreading_spartan6</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_ISimSimulationRunTime_par_tb</xtag-process-property-name>=<xtag-process-property-value>12000 ns</xtag-process-property-value></TD> |
<TD><xtag-process-property-name>PROP_ISimSimulationRunTime_translate_tb</xtag-process-property-name>=<xtag-process-property-value>12 us</xtag-process-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD> |
</TR><TR><TD><xtag-design-property-name>PROP_DevPackage</xtag-design-property-name>=<xtag-design-property-value>csg324</xtag-design-property-value></TD> |
<TD><xtag-design-property-name>PROP_Synthesis_Tool</xtag-design-property-name>=<xtag-design-property-value>XST (VHDL/Verilog)</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD> |
<TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>4</xtag-source-property-value></TD> |
</TR><TR><TD><xtag-process-property-name>PROP_parEnableMultiThreading_spartan6</xtag-process-property-name>=<xtag-process-property-value>4</xtag-process-property-value></TD> |
<TD><xtag-design-property-name>PROP_DevSpeed</xtag-design-property-name>=<xtag-design-property-value>-2</xtag-design-property-value></TD> |
|
</TR><TR><TD><xtag-design-property-name>PROP_PreferredLanguage</xtag-design-property-name>=<xtag-design-property-value>VHDL</xtag-design-property-value></TD> |
<TD><xtag-source-property-name>FILE_UCF</xtag-source-property-name>=<xtag-source-property-value>1</xtag-source-property-value></TD> |
|
</TR><TR><TD><xtag-source-property-name>FILE_VHDL</xtag-source-property-name>=<xtag-source-property-value>5</xtag-source-property-value></TD> |
</TR></xtag-section></TABLE> |
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'> |
<xtag-section name="UnisimStatistics"> |
1029,68 → 845,68
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>65</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>83</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>74</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>18</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>111</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>10</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>6</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>25</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>12</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>17</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>55</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>19</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>46</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>24</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>47</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>14</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>48</xtag-preunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>30</xtag-preunisim-param-value></TD> |
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>16</xtag-preunisim-param-value></TD> |
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>83</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>111</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>74</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>10</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>25</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>12</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>17</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>55</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>19</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>46</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>24</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>47</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>14</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>48</xtag-postunisim-param-value></TD> |
</TR> |
<TR> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>30</xtag-postunisim-param-value></TD> |
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>16</xtag-postunisim-param-value></TD> |
</xtag-section></TABLE> |
<BR></BODY></HTML> |
/syn/sim_master_slave_ct.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
syn/sim_master_slave_ct.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: syn/spi_ms_atlys.gise
===================================================================
--- syn/spi_ms_atlys.gise (nonexistent)
+++ syn/spi_ms_atlys.gise (revision 20)
@@ -0,0 +1,189 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 11.1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Index: syn/spi_master_atlys_top_map.mrp
===================================================================
--- syn/spi_master_atlys_top_map.mrp (nonexistent)
+++ syn/spi_master_atlys_top_map.mrp (revision 20)
@@ -0,0 +1,402 @@
+Release 13.1 Map O.40d (nt)
+Xilinx Mapping Report File for Design 'spi_master_atlys_top'
+
+Design Information
+------------------
+Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
+high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
+-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
+off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
+spi_master_atlys_top.pcf
+Target Device : xc6slx45
+Target Package : csg324
+Target Speed : -2
+Mapper Version : spartan6 -- $Revision: 1.55 $
+Mapped Date : Wed Aug 10 22:56:29 2011
+
+Design Summary
+--------------
+Number of errors: 0
+Number of warnings: 0
+Slice Logic Utilization:
+ Number of Slice Registers: 209 out of 54,576 1%
+ Number used as Flip Flops: 209
+ Number used as Latches: 0
+ Number used as Latch-thrus: 0
+ Number used as AND/OR logics: 0
+ Number of Slice LUTs: 145 out of 27,288 1%
+ Number used as logic: 127 out of 27,288 1%
+ Number using O6 output only: 75
+ Number using O5 output only: 13
+ Number using O5 and O6: 39
+ Number used as ROM: 0
+ Number used as Memory: 4 out of 6,408 1%
+ Number used as Dual Port RAM: 0
+ Number used as Single Port RAM: 0
+ Number used as Shift Register: 4
+ Number using O6 output only: 4
+ Number using O5 output only: 0
+ Number using O5 and O6: 0
+ Number used exclusively as route-thrus: 14
+ Number with same-slice register load: 12
+ Number with same-slice carry load: 2
+ Number with other load: 0
+
+Slice Logic Distribution:
+ Number of occupied Slices: 91 out of 6,822 1%
+ Number of LUT Flip Flop pairs used: 225
+ Number with an unused Flip Flop: 49 out of 225 21%
+ Number with an unused LUT: 80 out of 225 35%
+ Number of fully used LUT-FF pairs: 96 out of 225 42%
+ Number of unique control sets: 25
+ Number of slice register sites lost
+ to control set restrictions: 59 out of 54,576 1%
+
+ A LUT Flip Flop pair for this architecture represents one LUT paired with
+ one Flip Flop within a slice. A control set is a unique combination of
+ clock, reset, set, and enable signals for a registered element.
+ The Slice Logic Distribution report is not meaningful if the design is
+ over-mapped for a non-slice resource or if Placement fails.
+
+IO Utilization:
+ Number of bonded IOBs: 63 out of 218 28%
+ Number of LOCed IOBs: 43 out of 63 68%
+
+Specific Feature Utilization:
+ Number of RAMB16BWERs: 0 out of 116 0%
+ Number of RAMB8BWERs: 0 out of 232 0%
+ Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
+ Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
+ Number of BUFG/BUFGMUXs: 2 out of 16 12%
+ Number used as BUFGs: 2
+ Number used as BUFGMUX: 0
+ Number of DCM/DCM_CLKGENs: 0 out of 8 0%
+ Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
+ Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
+ Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
+ Number of BSCANs: 0 out of 4 0%
+ Number of BUFHs: 0 out of 256 0%
+ Number of BUFPLLs: 0 out of 8 0%
+ Number of BUFPLL_MCBs: 0 out of 4 0%
+ Number of DSP48A1s: 0 out of 58 0%
+ Number of ICAPs: 0 out of 1 0%
+ Number of MCBs: 0 out of 2 0%
+ Number of PCILOGICSEs: 0 out of 2 0%
+ Number of PLL_ADVs: 0 out of 4 0%
+ Number of PMVs: 0 out of 1 0%
+ Number of STARTUPs: 0 out of 1 0%
+ Number of SUSPEND_SYNCs: 0 out of 1 0%
+
+Average Fanout of Non-Clock Nets: 2.81
+
+Peak Memory Usage: 303 MB
+Total REAL time to MAP completion: 19 secs
+Total CPU time to MAP completion (all processors): 17 secs
+
+Table of Contents
+-----------------
+Section 1 - Errors
+Section 2 - Warnings
+Section 3 - Informational
+Section 4 - Removed Logic Summary
+Section 5 - Removed Logic
+Section 6 - IOB Properties
+Section 7 - RPMs
+Section 8 - Guide Report
+Section 9 - Area Group and Partition Summary
+Section 10 - Timing Report
+Section 11 - Configuration String Information
+Section 12 - Control Set Information
+Section 13 - Utilization by Hierarchy
+
+Section 1 - Errors
+------------------
+
+Section 2 - Warnings
+--------------------
+
+Section 3 - Informational
+-------------------------
+INFO:Map:284 - Map is running with the multi-threading option on. Map currently
+ supports the use of up to 2 processors. Based on the the user options and
+ machine load, Map will use 2 processors during this run.
+INFO:Xst:2261 - The FF/Latch in Unit
+ is equivalent to the following FF/Latch, which will be
+ removed :
+INFO:Xst:2261 - The FF/Latch in Unit
+ is equivalent to the following FF/Latch, which will be
+ removed :
+INFO:Xst:2261 - The FF/Latch in Unit
+ is equivalent to the following 2 FFs/Latches, which
+ will be removed :
+
+INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
+INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
+INFO:MapLib:562 - No environment variables are currently set.
+INFO:LIT:244 - All of the single ended outputs in this design are using slew
+ rate limited output drivers. The delay on speed critical single ended outputs
+ can be dramatically reduced by designating them as fast outputs.
+INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
+ 0.000 to 85.000 Celsius)
+INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
+ 1.260 Volts)
+INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+ (.mrp).
+INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked
+ and 20 are not locked. If you would like to print the names of these IOs,
+ please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
+INFO:Pack:1650 - Map created a placed design.
+
+Section 4 - Removed Logic Summary
+---------------------------------
+ 2 block(s) removed
+ 2 block(s) optimized away
+ 2 signal(s) removed
+ 55 Block(s) redundant
+
+Section 5 - Removed Logic
+-------------------------
+
+The trimmed logic report below shows the logic removed from your design due to
+sourceless or loadless signals, and VCC or ground connections. If the removal
+of a signal or symbol results in the subsequent removal of an additional signal
+or symbol, the message explaining that second removal will be indented. This
+indentation will be repeated as a chain of related logic is removed.
+
+To quickly locate the original cause for the removal of a chain of logic, look
+above the place where that logic is listed in the trimming report, then locate
+the lines that are least indented (begin at the leftmost edge).
+
+The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
+The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
+Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
+Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
+
+Optimized Block(s):
+TYPE BLOCK
+GND XST_GND
+VCC XST_VCC
+
+Redundant Block(s):
+TYPE BLOCK
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
+LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
+LUT1 Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
+INV ][1034_3_INV_0
+INV ][269_110_INV_0
+INV ][369_165_INV_0
+INV ][373_170_INV_0
+INV ][389_183_INV_0
+INV ][397_190_INV_0
+INV ][401_194_INV_0
+INV ][402_198_INV_0
+INV ][405_200_INV_0
+INV ][409_205_INV_0
+INV ][413_210_INV_0
+INV ][417_215_INV_0
+INV ][421_220_INV_0
+INV ][425_225_INV_0
+INV ][429_230_INV_0
+INV ][441_243_INV_0
+INV ][453_254_INV_0
+INV ][461_261_INV_0
+INV ][465_265_INV_0
+INV ][469_269_INV_0
+INV ][645_378_INV_0
+INV ][649_383_INV_0
+INV ][653_387_INV_0
+INV ][657_391_INV_0
+INV ][661_395_INV_0
+INV ][665_399_INV_0
+INV ][669_403_INV_0
+INV ][673_407_INV_0
+INV ][694_422_INV_0
+INV ][729_448_INV_0
+INV ][783_487_INV_0
+INV ][791_494_INV_0
+INV ][795_498_INV_0
+INV ][799_503_INV_0
+INV ][807_509_INV_0
+INV ][840_536_INV_0
+INV ][845_539_INV_0
+INV ][882_563_INV_0
+INV ][888_569_INV_0
+INV ][923_599_INV_0
+INV ][926_603_INV_0
+
+Section 6 - IOB Properties
+--------------------------
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
+| | | | | Term | Strength | Rate | | | Delay |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+| btn_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
+| btn_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
+| btn_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
+| btn_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
+| btn_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
+| btn_i<5> | IOB | INPUT | LVCMOS25 | | | | | | |
+| dbg_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| gclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
+| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| led_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| m_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_do_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_state_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_state_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_state_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| s_state_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| spi_miso_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| spi_mosi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| spi_sck_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| spi_ssel_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+| sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<5> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<6> | IOB | INPUT | LVCMOS25 | | | | | | |
+| sw_i<7> | IOB | INPUT | LVCMOS25 | | | | | | |
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+Section 7 - RPMs
+----------------
+
+Section 8 - Guide Report
+------------------------
+Guide not run on this design.
+
+Section 9 - Area Group and Partition Summary
+--------------------------------------------
+
+Partition Implementation Status
+-------------------------------
+
+ No Partitions were found in this design.
+
+-------------------------------
+
+Area Group Information
+----------------------
+
+ No area groups were found in this design.
+
+----------------------
+
+Section 10 - Timing Report
+--------------------------
+A logic-level (pre-route) timing report can be generated by using Xilinx static
+timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
+mapped NCD and PCF files. Please note that this timing report will be generated
+using estimated delay information. For accurate numbers, please generate a
+timing report with the post Place and Route NCD file.
+
+For more information about the Timing Analyzer, consult the Xilinx Timing
+Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
+Command Line Tools User Guide "TRACE" chapter.
+
+Section 11 - Configuration String Details
+-----------------------------------------
+
+Section 12 - Control Set Information
+------------------------------------
++-----------------------------------------------------------------------------------------------------------------------------------+
+| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
++-----------------------------------------------------------------------------------------------------------------------------------+
+| Inst_spi_master_port/spi_clk_reg_BUFG | | | | 6 | 11 |
+| Inst_spi_master_port/spi_clk_reg_BUFG | | | lut1153_485 | 3 | 8 |
+| Inst_spi_master_port/spi_clk_reg_BUFG | ][1032_0 | | | 2 | 3 |
+| Inst_spi_master_port/spi_clk_reg_BUFG | ][IN_virtPIBox_530_660 | | | 1 | 1 |
++-----------------------------------------------------------------------------------------------------------------------------------+
+| gclk_i_BUFGP | | | | 31 | 71 |
+| gclk_i_BUFGP | | | GLOBAL_LOGIC1 | 1 | 4 |
+| gclk_i_BUFGP | | | ][210_37 | 1 | 8 |
+| gclk_i_BUFGP | | | ][242_80 | 2 | 6 |
+| gclk_i_BUFGP | | | ][402_198 | 2 | 8 |
+| gclk_i_BUFGP | | | ][691_420 | 2 | 4 |
+| gclk_i_BUFGP | | | lut403_108 | 1 | 2 |
+| gclk_i_BUFGP | | | lut415_115 | 2 | 8 |
+| gclk_i_BUFGP | | | lut456_132 | 2 | 8 |
+| gclk_i_BUFGP | | | lut497_149 | 2 | 8 |
+| gclk_i_BUFGP | | | lut539_168 | 2 | 8 |
+| gclk_i_BUFGP | | | lut703_275 | 1 | 8 |
+| gclk_i_BUFGP | | | lut825_325 | 2 | 6 |
+| gclk_i_BUFGP | | | lut916_362 | 2 | 8 |
+| gclk_i_BUFGP | | | lut958_381 | 2 | 8 |
+| gclk_i_BUFGP | | | spi_wren_reg_m | 1 | 8 |
+| gclk_i_BUFGP | | | spi_wren_reg_s | 1 | 2 |
+| gclk_i_BUFGP | ][1032_0 | | | 4 | 6 |
+| gclk_i_BUFGP | clear | | | 2 | 4 |
+| gclk_i_BUFGP | spi_rst_reg | | ][691_420 | 1 | 4 |
++-----------------------------------------------------------------------------------------------------------------------------------+
+| ~Inst_spi_master_port/spi_clk_reg_BUFG | | | | 1 | 1 |
++-----------------------------------------------------------------------------------------------------------------------------------+
+
+Section 13 - Utilization by Hierarchy
+-------------------------------------
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| spi_master_atlys_top/ | | 64/121 | 71/209 | 109/119 | 0/4 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top |
+| +Inst_btn_debouncer | | 10/10 | 26/26 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_btn_debouncer |
+| +Inst_spi_master_port | | 18/18 | 45/45 | 2/2 | 2/2 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_master_port |
+| +Inst_spi_slave_port | | 21/21 | 35/35 | 6/6 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_spi_slave_port |
+| +Inst_sw_debouncer | | 8/8 | 32/32 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | spi_master_atlys_top/Inst_sw_debouncer |
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+* Slices can be packed with basic elements from multiple hierarchies.
+ Therefore, a slice will be counted in every hierarchical module
+ that each of its packed basic elements belong to.
+** For each column, there are two numbers reported /.
+ is the number of elements that belong to that specific hierarchical module.
+ is the total number of elements from that hierarchical module and any lower level
+ hierarchical modules below.
+*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
Index: syn/spi_master_atlys.ucf
===================================================================
--- syn/spi_master_atlys.ucf (revision 19)
+++ syn/spi_master_atlys.ucf (revision 20)
@@ -206,14 +206,14 @@
# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET
# PMOD Connector
-# NET "spi_ssel_o" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N
-# NET "spi_sck_o" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P
-# NET "spi_mosi_o" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N
-# NET "dbg_o<0>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P
-# NET "dbg_o<1>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N
-# NET "dbg_o<2>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P
-# NET "dbg_o<3>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N
-# NET "dbg_o<4>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P
+ NET "m_state_o<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N
+ NET "m_state_o<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P
+ NET "m_state_o<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N
+ NET "m_state_o<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P
+# NET "s_state_o<0>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, PMOD JB<7>, Sch name = JA-CLK_N
+# NET "s_state_o<1>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, PMOD JB<8>, Sch name = JA-CLK_P
+# NET "s_state_o<2>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, PMOD JB<9>, Sch name = JA-D1_N
+# NET "s_state_o<3>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, PMOD JB<10>, Sch name = JA-D1_P
# onboard VHDCI
# Channnel 1 connects to P signals, Channel 2 to N signals
/syn/spi_master_atlys_top_envsettings.html
0,0 → 1,568
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> |
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<center><big><big><b>System Settings</b></big></big></center><br> |
<A NAME="Environment Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Environment Variable</b></td> |
<td><b>xst</b></td> |
<td><b>ngdbuild</b></td> |
<td><b>map</b></td> |
<td><b>par</b></td> |
</tr> |
<tr> |
<td>PATHEXT</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
</tr> |
<tr> |
<td>Path</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
</tr> |
<tr> |
<td>XILINX</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-ifn</td> |
<td> </td> |
<td>spi_master_atlys_top.prj</td> |
<td> </td> |
</tr> |
<tr> |
<td>-ifmt</td> |
<td> </td> |
<td>mixed</td> |
<td>Mixed</td> |
</tr> |
<tr> |
<td>-ofn</td> |
<td> </td> |
<td>spi_master_atlys_top</td> |
<td> </td> |
</tr> |
<tr> |
<td>-ofmt</td> |
<td> </td> |
<td>NGC</td> |
<td>NGC</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-2-csg324</td> |
<td> </td> |
</tr> |
<tr> |
<td>-top</td> |
<td> </td> |
<td>spi_master_atlys_top</td> |
<td> </td> |
</tr> |
<tr> |
<td>-opt_mode</td> |
<td>Optimization Goal</td> |
<td>Speed</td> |
<td>Speed</td> |
</tr> |
<tr> |
<td>-opt_level</td> |
<td>Optimization Effort</td> |
<td>2</td> |
<td>1</td> |
</tr> |
<tr> |
<td>-power</td> |
<td>Power Reduction</td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-iuc</td> |
<td>Use synthesis Constraints File</td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-keep_hierarchy</td> |
<td>Keep Hierarchy</td> |
<td>No</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-netlist_hierarchy</td> |
<td>Netlist Hierarchy</td> |
<td>As_Optimized</td> |
<td>As_Optimized</td> |
</tr> |
<tr> |
<td>-rtlview</td> |
<td>Generate RTL Schematic</td> |
<td>Yes</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-glob_opt</td> |
<td>Global Optimization Goal</td> |
<td>AllClockNets</td> |
<td>AllClockNets</td> |
</tr> |
<tr> |
<td>-read_cores</td> |
<td>Read Cores</td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-write_timing_constraints</td> |
<td>Write Timing Constraints</td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-cross_clock_analysis</td> |
<td>Cross Clock Analysis</td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-bus_delimiter</td> |
<td>Bus Delimiter</td> |
<td><></td> |
<td><></td> |
</tr> |
<tr> |
<td>-slice_utilization_ratio</td> |
<td>Slice Utilization Ratio</td> |
<td>100</td> |
<td>100</td> |
</tr> |
<tr> |
<td>-bram_utilization_ratio</td> |
<td>BRAM Utilization Ratio</td> |
<td>100</td> |
<td>100</td> |
</tr> |
<tr> |
<td>-dsp_utilization_ratio</td> |
<td>DSP Utilization Ratio</td> |
<td>100</td> |
<td>100</td> |
</tr> |
<tr> |
<td>-reduce_control_sets</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-fsm_extract</td> |
<td> </td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-fsm_encoding</td> |
<td> </td> |
<td>Gray</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-safe_implementation</td> |
<td> </td> |
<td>No</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-fsm_style</td> |
<td> </td> |
<td>LUT</td> |
<td>LUT</td> |
</tr> |
<tr> |
<td>-ram_extract</td> |
<td> </td> |
<td>No</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-rom_extract</td> |
<td> </td> |
<td>No</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-shreg_extract</td> |
<td> </td> |
<td>NO</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-auto_bram_packing</td> |
<td> </td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-resource_sharing</td> |
<td> </td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-async_to_sync</td> |
<td> </td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-use_dsp48</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-iobuf</td> |
<td> </td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-max_fanout</td> |
<td> </td> |
<td>100000</td> |
<td>100000</td> |
</tr> |
<tr> |
<td>-bufg</td> |
<td> </td> |
<td>16</td> |
<td>16</td> |
</tr> |
<tr> |
<td>-register_duplication</td> |
<td> </td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-register_balancing</td> |
<td> </td> |
<td>No</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-optimize_primitives</td> |
<td> </td> |
<td>NO</td> |
<td>No</td> |
</tr> |
<tr> |
<td>-use_clock_enable</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-use_sync_set</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-use_sync_reset</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-iob</td> |
<td> </td> |
<td>Auto</td> |
<td>Auto</td> |
</tr> |
<tr> |
<td>-equivalent_register_removal</td> |
<td> </td> |
<td>YES</td> |
<td>Yes</td> |
</tr> |
<tr> |
<td>-slice_utilization_ratio_maxmargin</td> |
<td> </td> |
<td>5</td> |
<td>0</td> |
</tr> |
</TABLE> |
<A NAME="Translation Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-dd</td> |
<td> </td> |
<td>_ngo</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-uc</td> |
<td> </td> |
<td>spi_master_atlys.ucf</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Map Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-detail</td> |
<td>Generate Detailed MAP Report</td> |
<td>TRUE</td> |
<td>TRUE</td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>high</td> |
</tr> |
<tr> |
<td>-xe</td> |
<td>Placer Extra Effort Map</td> |
<td>NORMAL</td> |
<td> </td> |
</tr> |
<tr> |
<td>-xt</td> |
<td>Extra Cost Tables</td> |
<td>0</td> |
<td>0</td> |
</tr> |
<tr> |
<td>-global_opt</td> |
<td>Global Optimization map</td> |
<td>TRUE</td> |
<td>FALSE</td> |
</tr> |
<tr> |
<td>-ir</td> |
<td>Use RLOC Constraints</td> |
<td>OFF</td> |
<td>OFF</td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>2</td> |
<td>0</td> |
</tr> |
<tr> |
<td>-t</td> |
<td>Starting Placer Cost Table (1-100) Map</td> |
<td>1</td> |
<td>0</td> |
</tr> |
<tr> |
<td>-r</td> |
<td>Register Ordering</td> |
<td>4</td> |
<td>4</td> |
</tr> |
<tr> |
<td>-equivalent_register_removal</td> |
<td>Equivalent Register Removal</td> |
<td>TRUE</td> |
<td>TRUE</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-lc</td> |
<td>LUT Combining</td> |
<td>area</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-o</td> |
<td> </td> |
<td>spi_master_atlys_top_map.ncd</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
<tr> |
<td>-pr</td> |
<td>Pack I/O Registers/Latches into IOBs</td> |
<td>off</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td> </td> |
<td>n</td> |
<td>None</td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td> </td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>4</td> |
<td>off</td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>std</td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Operating System Information</b></td> |
<td><b>xst</b></td> |
<td><b>ngdbuild</b></td> |
<td><b>map</b></td> |
<td><b>par</b></td> |
</tr> |
<tr> |
<td>CPU Architecture/Speed</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
</tr> |
<tr> |
<td>Host</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
</tr> |
<tr> |
<td>OS Name</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
</tr> |
<tr> |
<td>OS Release</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
</tr> |
</TABLE> |
</BODY> </HTML> |
/syn/spi_master_atlys_test.vhd
101,6 → 101,8
sw_i => sw_data, |
btn_i => btn_data, |
led_o => leds, |
m_do_o => m_do_reg, |
s_do_o => s_do_reg, |
m_state_o => master_state, |
s_state_o => slave_state, |
dbg_o => dbg |
111,6 → 113,7
wr_ack_m <= dbg(10); |
di_req_m <= dbg(9); |
do_valid_m <= dbg(8); |
|
-- slave signals mapped on dbg |
wren_s <= dbg(7); |
wr_ack_s <= dbg(6); |
136,14 → 139,18
begin |
wait for 100 ns; -- wait until global set/reset completes |
|
btn_data(btRESET) <= '1'; |
btn_data(btUP) <= '1'; |
wait for 1 us; |
btn_data(btRESET) <= '0'; |
wait for 900 ns; |
|
sw_data <= X"5A"; |
|
wait; -- will wait forever |
btn_data(btUP) <= '0'; |
sw_data <= X"81"; |
wait for 5 us; |
sw_data <= X"C1"; |
wait for 5 us; |
sw_data <= X"C9"; |
wait for 5 us; |
sw_data <= X"55"; |
wait for 5 us; |
assert false report "End Simulation" severity failure; -- stop simulation |
end process tb; |
-- End Test Bench |
END; |
/syn/spi_master_envsettings.html
16,44 → 16,51
<tr> |
<td>PATHEXT</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td> |
</tr> |
<tr> |
<td>Path</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td> |
<td><font color=gray>< data not available ></font></td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Flash Magic</td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Flash Magic</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</font></td> |
</tr> |
<tr> |
<td>XILINX</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE\</font></td> |
</tr> |
<tr> |
<td>XILINX_DSP</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td>C:\Xilinx\13.1\ISE_DS\ISE</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\ISE</font></td> |
</tr> |
<tr> |
<td>XILINX_EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td>C:\Xilinx\13.1\ISE_DS\EDK</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\EDK</font></td> |
</tr> |
<tr> |
<td>XILINX_FOR_ALTIUM_OVERRIDE</td> |
<td> </td> |
<td><font color=gray> </font></td> |
<td><font color=gray>< not set ></font></td> |
<td><font color=gray>< not set ></font></td> |
</tr> |
<tr> |
<td>XILINX_PLANAHEAD</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
<td><font color=gray>C:\Xilinx\13.1\ISE_DS\PlanAhead</font></td> |
</tr> |
</TABLE> |
<A NAME="Synthesis Property Settings"></A> |
350,28 → 357,28
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-dd</td> |
<td> </td> |
<td>_ngo</td> |
<td>None</td> |
<td><font color=gray>-dd</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>_ngo</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-uc</td> |
<td> </td> |
<td>spi_master_atlys.ucf</td> |
<td>None</td> |
<td><font color=gray>-uc</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys.ucf</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
</TABLE> |
<A NAME="Map Property Settings"></A> |
386,102 → 393,144
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td>-detail</td> |
<td>Generate Detailed MAP Report</td> |
<td>TRUE</td> |
<td>TRUE</td> |
<td><font color=gray>-detail</font></td> |
<td><font color=gray>Generate Detailed MAP Report</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
</tr> |
<tr> |
<td>-ol</td> |
<td>Place & Route Effort Level (Overall)</td> |
<td>high</td> |
<td>high</td> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>high</font></td> |
</tr> |
<tr> |
<td>-xe</td> |
<td>Placer Extra Effort Map</td> |
<td>NORMAL</td> |
<td> </td> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray>Placer Extra Effort Map</font></td> |
<td><font color=gray>NORMAL</font></td> |
<td><font color=gray> </font></td> |
</tr> |
<tr> |
<td>-xt</td> |
<td>Extra Cost Tables</td> |
<td>0</td> |
<td>0</td> |
<td><font color=gray>-xt</font></td> |
<td><font color=gray>Extra Cost Tables</font></td> |
<td><font color=gray>0</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-global_opt</td> |
<td>Global Optimization map</td> |
<td>TRUE</td> |
<td>FALSE</td> |
<td><font color=gray>-global_opt</font></td> |
<td><font color=gray>Global Optimization map</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>FALSE</font></td> |
</tr> |
<tr> |
<td>-ir</td> |
<td>Use RLOC Constraints</td> |
<td>OFF</td> |
<td>OFF</td> |
<td><font color=gray>-ir</font></td> |
<td><font color=gray>Use RLOC Constraints</font></td> |
<td><font color=gray>OFF</font></td> |
<td><font color=gray>OFF</font></td> |
</tr> |
<tr> |
<td>-mt</td> |
<td>Enable Multi-Threading</td> |
<td>2</td> |
<td>0</td> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>2</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-t</td> |
<td>Starting Placer Cost Table (1-100) Map</td> |
<td>1</td> |
<td>0</td> |
<td><font color=gray>-t</font></td> |
<td><font color=gray>Starting Placer Cost Table (1-100) Map</font></td> |
<td><font color=gray>1</font></td> |
<td><font color=gray>0</font></td> |
</tr> |
<tr> |
<td>-r</td> |
<td>Register Ordering</td> |
<td>4</td> |
<td>4</td> |
<td><font color=gray>-r</font></td> |
<td><font color=gray>Register Ordering</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>4</font></td> |
</tr> |
<tr> |
<td>-equivalent_register_removal</td> |
<td>Equivalent Register Removal</td> |
<td>TRUE</td> |
<td>TRUE</td> |
<td><font color=gray>-equivalent_register_removal</font></td> |
<td><font color=gray>Equivalent Register Removal</font></td> |
<td><font color=gray>TRUE</font></td> |
<td><font color=gray>TRUE</font></td> |
</tr> |
<tr> |
<td>-intstyle</td> |
<td> </td> |
<td>ise</td> |
<td>None</td> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-lc</td> |
<td>LUT Combining</td> |
<td>area</td> |
<td>off</td> |
<td><font color=gray>-lc</font></td> |
<td><font color=gray>LUT Combining</font></td> |
<td><font color=gray>area</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td>-o</td> |
<td> </td> |
<td>spi_master_atlys_top_map.ncd</td> |
<td>None</td> |
<td><font color=gray>-o</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>spi_master_atlys_top_map.ncd</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td>-w</td> |
<td> </td> |
<td>true</td> |
<td>false</td> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
</tr> |
<tr> |
<td>-pr</td> |
<td>Pack I/O Registers/Latches into IOBs</td> |
<td>off</td> |
<td>off</td> |
<td><font color=gray>-pr</font></td> |
<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td> |
<td><font color=gray>off</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td>-p</td> |
<td> </td> |
<td>xc6slx45-csg324-2</td> |
<td>None</td> |
<td><font color=gray>-p</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>xc6slx45-csg324-2</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
</TABLE> |
<A NAME="Place and Route Property Settings"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD> |
</tr> |
<tr bgcolor='#ffff99'> |
<td><b>Switch Name</b></td> |
<td><b>Property Name</b></td> |
<td><b>Value</b></td> |
<td><b>Default Value</b></td> |
</tr> |
<tr> |
<td><font color=gray>-xe</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>n</font></td> |
<td><font color=gray>None</font></td> |
</tr> |
<tr> |
<td><font color=gray>-intstyle</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>ise</font></td> |
<td><font color=gray> </font></td> |
</tr> |
<tr> |
<td><font color=gray>-mt</font></td> |
<td><font color=gray>Enable Multi-Threading</font></td> |
<td><font color=gray>4</font></td> |
<td><font color=gray>off</font></td> |
</tr> |
<tr> |
<td><font color=gray>-ol</font></td> |
<td><font color=gray>Place & Route Effort Level (Overall)</font></td> |
<td><font color=gray>high</font></td> |
<td><font color=gray>std</font></td> |
</tr> |
<tr> |
<td><font color=gray>-w</font></td> |
<td><font color=gray> </font></td> |
<td><font color=gray>true</font></td> |
<td><font color=gray>false</font></td> |
</tr> |
</TABLE> |
<A NAME="Operating System Information"></A> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
496,31 → 545,31
</tr> |
<tr> |
<td>CPU Architecture/Speed</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Intel(R) Xeon(R) CPU E5620 @ 2.40GHz/2394 MHz</td> |
<td><font color=gray>Intel(R) Xeon(R) CPU E5620 @ 2.40GHz/2394 MHz</font></td> |
<td><font color=gray>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</font></td> |
<td><font color=gray>Intel(R) Core(TM) i7 CPU 950 @ 3.07GHz/3066 MHz</font></td> |
</tr> |
<tr> |
<td>Host</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td>Develop-W7</td> |
<td><font color=gray>< data not available ></font></td> |
<td>EELE313</td> |
<td><font color=gray>EELE313</font></td> |
<td><font color=gray>Develop-W7</font></td> |
<td><font color=gray>Develop-W7</font></td> |
</tr> |
<tr> |
<td>OS Name</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td>Microsoft Windows 7 , 32-bit</td> |
<td><font color=gray>< data not available ></font></td> |
<td>Microsoft Windows 7 , 64-bit</td> |
<td><font color=gray>Microsoft Windows 7 , 64-bit</font></td> |
<td><font color=gray>Microsoft Windows 7 , 32-bit</font></td> |
<td><font color=gray>Microsoft Windows 7 , 32-bit</font></td> |
</tr> |
<tr> |
<td>OS Release</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td>Service Pack 1 (build 7601)</td> |
<td><font color=gray>< data not available ></font></td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
<td><font color=gray>Service Pack 1 (build 7601)</font></td> |
</tr> |
</TABLE> |
</BODY> </HTML> |
/syn/fuse.xmsgs
0,0 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
</messages> |
|
/syn/spi_master_atlys_top.drc
0,0 → 1,8
Release 13.1 Drc O.40d (nt) |
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. |
|
Wed Aug 10 22:59:10 2011 |
|
drc -z spi_master_atlys_top.ncd spi_master_atlys_top.pcf |
|
DRC detected 0 errors and 0 warnings. |
/syn/readme.txt
11,28 → 11,27
The files are: |
------------- |
|
spi_master.vhd vhdl model for the spi_master interface |
spi_slave.vhd vhdl model for the spi_slave interface |
grp_debouncer.vhd vhdl model for the switch debouncer |
spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board |
spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd' |
spi_master_atlys.xise ISE 13.1 project file |
spi_master_atlys.ucf pin lock constraints for the Atlys board |
spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests |
spi_master_envsettings.html synthesis env settings, with the tools setup used |
ATLYS_01.SET Tek MSO2014 settings files with the debug pin names |
ATLYS_02.SET |
ATLYS_03.SET |
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board |
spi_master.vhd vhdl model for the spi_master interface |
spi_slave.vhd vhdl model for the spi_slave interface |
grp_debouncer.vhd vhdl model for the switch debouncer |
spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys board |
spi_master_atlys_test.vhd testbench for the synthesizable toplevel 'spi_master_atlys_top.vhd' |
spi_master_atlys.xise ISE 13.1 project file |
spi_master_atlys.ucf pin lock constraints for the Atlys board |
spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests |
spi_master_envsettings.html synthesis env settings, with the tools setup used |
ATLYS_0x.SET Tek MSO2014 settings files with the debug pin names |
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board |
|
|
|
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer. |
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer, or send me e-mail: jdoin@opencores.org |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
|
http://opencores.org/project,spi_master_slave,bugtracker |
|
If you find this core useful, please let me know: jdoin@opencores.org |
|
In any case, thank you very much for testing this core. |
|
40,4 → 39,3
Jonny Doin |
jdoin@opencores.org |
|
|
/syn/spi_master_atlys_top_map.map
0,0 → 1,162
Release 13.1 Map O.40d (nt) |
Xilinx Map Application Log File for Design 'spi_master_atlys_top' |
|
Design Information |
------------------ |
Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol |
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area |
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power |
off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd |
spi_master_atlys_top.pcf |
Target Device : xc6slx45 |
Target Package : csg324 |
Target Speed : -2 |
Mapper Version : spartan6 -- $Revision: 1.55 $ |
Mapped Date : Wed Aug 10 22:56:29 2011 |
|
Running global optimization... |
Mapping design into LUTs... |
Running directed packing... |
Running delay-based LUT packing... |
Updating timing models... |
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report |
(.mrp). |
Running timing-driven placement... |
Total REAL time at the beginning of Placer: 10 secs |
Total CPU time at the beginning of Placer: 9 secs |
|
Phase 1.1 Initial Placement Analysis |
Phase 1.1 Initial Placement Analysis (Checksum:542d7d4b) REAL time: 11 secs |
|
Phase 2.7 Design Feasibility Check |
INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked |
and 20 are not locked. If you would like to print the names of these IOs, |
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. |
Phase 2.7 Design Feasibility Check (Checksum:542d7d4b) REAL time: 11 secs |
|
Phase 3.31 Local Placement Optimization |
Phase 3.31 Local Placement Optimization (Checksum:542d7d4b) REAL time: 11 secs |
|
Phase 4.2 Initial Placement for Architecture Specific Features |
... |
Phase 4.2 Initial Placement for Architecture Specific Features |
(Checksum:23369eb) REAL time: 16 secs |
|
Phase 5.36 Local Placement Optimization |
Phase 5.36 Local Placement Optimization (Checksum:23369eb) REAL time: 16 secs |
|
Phase 6.30 Global Clock Region Assignment |
Phase 6.30 Global Clock Region Assignment (Checksum:23369eb) REAL time: 16 secs |
|
Phase 7.3 Local Placement Optimization |
... |
Phase 7.3 Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs |
|
Phase 8.5 Local Placement Optimization |
Phase 8.5 Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs |
|
Phase 9.8 Global Placement |
........... |
..... |
Phase 9.8 Global Placement (Checksum:55e2a6f9) REAL time: 17 secs |
|
Phase 10.5 Local Placement Optimization |
Phase 10.5 Local Placement Optimization (Checksum:55e2a6f9) REAL time: 17 secs |
|
Phase 11.18 Placement Optimization |
Phase 11.18 Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs |
|
Phase 12.5 Local Placement Optimization |
Phase 12.5 Local Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs |
|
Phase 13.34 Placement Validation |
Phase 13.34 Placement Validation (Checksum:55d3da5) REAL time: 18 secs |
|
Total REAL time to Placer completion: 18 secs |
Total CPU time to Placer completion: 16 secs |
Running post-placement packing... |
Writing output files... |
|
Design Summary |
-------------- |
|
Design Summary: |
Number of errors: 0 |
Number of warnings: 0 |
Slice Logic Utilization: |
Number of Slice Registers: 209 out of 54,576 1% |
Number used as Flip Flops: 209 |
Number used as Latches: 0 |
Number used as Latch-thrus: 0 |
Number used as AND/OR logics: 0 |
Number of Slice LUTs: 145 out of 27,288 1% |
Number used as logic: 127 out of 27,288 1% |
Number using O6 output only: 75 |
Number using O5 output only: 13 |
Number using O5 and O6: 39 |
Number used as ROM: 0 |
Number used as Memory: 4 out of 6,408 1% |
Number used as Dual Port RAM: 0 |
Number used as Single Port RAM: 0 |
Number used as Shift Register: 4 |
Number using O6 output only: 4 |
Number using O5 output only: 0 |
Number using O5 and O6: 0 |
Number used exclusively as route-thrus: 14 |
Number with same-slice register load: 12 |
Number with same-slice carry load: 2 |
Number with other load: 0 |
|
Slice Logic Distribution: |
Number of occupied Slices: 91 out of 6,822 1% |
Number of LUT Flip Flop pairs used: 225 |
Number with an unused Flip Flop: 49 out of 225 21% |
Number with an unused LUT: 80 out of 225 35% |
Number of fully used LUT-FF pairs: 96 out of 225 42% |
Number of unique control sets: 25 |
Number of slice register sites lost |
to control set restrictions: 59 out of 54,576 1% |
|
A LUT Flip Flop pair for this architecture represents one LUT paired with |
one Flip Flop within a slice. A control set is a unique combination of |
clock, reset, set, and enable signals for a registered element. |
The Slice Logic Distribution report is not meaningful if the design is |
over-mapped for a non-slice resource or if Placement fails. |
|
IO Utilization: |
Number of bonded IOBs: 63 out of 218 28% |
Number of LOCed IOBs: 43 out of 63 68% |
|
Specific Feature Utilization: |
Number of RAMB16BWERs: 0 out of 116 0% |
Number of RAMB8BWERs: 0 out of 232 0% |
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% |
Number of BUFG/BUFGMUXs: 2 out of 16 12% |
Number used as BUFGs: 2 |
Number used as BUFGMUX: 0 |
Number of DCM/DCM_CLKGENs: 0 out of 8 0% |
Number of ILOGIC2/ISERDES2s: 0 out of 376 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0% |
Number of OLOGIC2/OSERDES2s: 0 out of 376 0% |
Number of BSCANs: 0 out of 4 0% |
Number of BUFHs: 0 out of 256 0% |
Number of BUFPLLs: 0 out of 8 0% |
Number of BUFPLL_MCBs: 0 out of 4 0% |
Number of DSP48A1s: 0 out of 58 0% |
Number of ICAPs: 0 out of 1 0% |
Number of MCBs: 0 out of 2 0% |
Number of PCILOGICSEs: 0 out of 2 0% |
Number of PLL_ADVs: 0 out of 4 0% |
Number of PMVs: 0 out of 1 0% |
Number of STARTUPs: 0 out of 1 0% |
Number of SUSPEND_SYNCs: 0 out of 1 0% |
|
Average Fanout of Non-Clock Nets: 2.81 |
|
Peak Memory Usage: 303 MB |
Total REAL time to MAP completion: 19 secs |
Total CPU time to MAP completion (all processors): 17 secs |
|
Mapping completed. |
See MAP report file "spi_master_atlys_top_map.mrp" for details. |