URL
https://opencores.org/ocsvn/spi_slave/spi_slave/trunk
Subversion Repositories spi_slave
Compare Revisions
- This comparison shows the changes necessary to convert path
/spi_slave/trunk/sim/rtl_sim
- from Rev 26 to Rev 35
- ↔ Reverse comparison
Rev 26 → Rev 35
/modelsim_sim/run/crc_core/crc_core_tb_c.do
0,0 → 1,12
vlib work |
# packages |
vcom -93 ../../../../../bench/vhdl/images-body.vhd |
vcom -93 ../../../../../bench/vhdl/txt_util.vhd |
# DUT |
vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd |
vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd |
vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd |
vcom -93 ../../../../../rtl/vhdl/crc_core.vhd |
|
# Testbench |
vcom -93 ../../../../../bench/vhdl/crc_core_tb.vhd |
/modelsim_sim/run/crc_core/crc_core_tb_s.do
0,0 → 1,4
vsim -t ps crc_core_tb |
view wave |
do crc_core_tb_w.do |
run -all |
/modelsim_sim/run/crc_core/crc_core_tb_w.do
0,0 → 1,35
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Logic /crc_core_tb/rst |
add wave -noupdate -format Logic /crc_core_tb/opb_clk |
add wave -noupdate -format Logic /crc_core_tb/crc_clr |
add wave -noupdate -format Logic /crc_core_tb/opb_m_last_block |
add wave -noupdate -divider RX |
add wave -noupdate -format Logic /crc_core_tb/fifo_rx_en |
add wave -noupdate -format Literal /crc_core_tb/fifo_rx_data |
add wave -noupdate -format Literal /crc_core_tb/opb_rx_crc_value |
add wave -noupdate -divider TX |
add wave -noupdate -format Logic /crc_core_tb/fifo_tx_en |
add wave -noupdate -format Literal /crc_core_tb/fifo_tx_data |
add wave -noupdate -format Logic /crc_core_tb/tx_crc_insert |
add wave -noupdate -format Literal /crc_core_tb/opb_tx_crc_value |
add wave -noupdate -divider Internal |
add wave -noupdate -format Literal /crc_core_tb/dut/state |
add wave -noupdate -format Logic /crc_core_tb/dut/rx_crc_en |
add wave -noupdate -format Logic /crc_core_tb/dut/tx_crc_en |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {493567 ps} 0} |
configure wave -namecolwidth 211 |
configure wave -valuecolwidth 169 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
update |
WaveRestoreZoom {0 ps} {582750 ps} |
/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_c.do
0,0 → 1,24
vlib work |
# packages |
vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd |
|
# DUT |
vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd |
vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd |
vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd |
vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd |
vcom -93 ../../../../../rtl/vhdl/ram.vhd |
vcom -93 ../../../../../rtl/vhdl/fifo.vhd |
vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd |
vcom -93 ../../../../../rtl/vhdl/opb_if.vhd |
vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd |
vcom -93 ../../../../../rtl/vhdl/shift_register.vhd |
vcom -93 ../../../../../rtl/vhdl/irq_ctl.vhd |
vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd |
vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd |
vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd |
vcom -93 ../../../../../rtl/vhdl/crc_core.vhd |
vcom -93 ../../../../../rtl/vhdl/opb_spi_slave.vhd |
|
# Testbench |
vcom -93 ../../../../../bench/vhdl/opb_spi_slave_tb.vhd |
/modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_w.do
0,0 → 1,64
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider OPB-Bus |
add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rst |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_abus |
add wave -noupdate -format Literal /opb_spi_slave_tb/opb_be |
add wave -noupdate -format Logic /opb_spi_slave_tb/opb_clk |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/opb_dbus |
add wave -noupdate -format Logic /opb_spi_slave_tb/opb_rnw |
add wave -noupdate -format Logic /opb_spi_slave_tb/opb_select |
add wave -noupdate -format Logic /opb_spi_slave_tb/opb_seqaddr |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/sln_dbus |
add wave -noupdate -format Logic /opb_spi_slave_tb/sln_xferack |
add wave -noupdate -divider SPI |
add wave -noupdate -format Logic /opb_spi_slave_tb/sclk |
add wave -noupdate -format Logic /opb_spi_slave_tb/ss_n |
add wave -noupdate -format Logic /opb_spi_slave_tb/mosi |
add wave -noupdate -format Logic /opb_spi_slave_tb/miso |
add wave -noupdate -divider Internal |
add wave -noupdate -format Literal /opb_spi_slave_tb/opb_read_data |
add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/dout |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_thresh |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/rx_thresh |
add wave -noupdate -format Literal /opb_spi_slave_tb/spi_value_in |
add wave -noupdate -divider TX_FIFO |
add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_full_thresh |
add wave -noupdate -format Literal /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty_thresh |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_clk |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/wr_en |
add wave -noupdate -format Literal -radix hexadecimal /opb_spi_slave_tb/dut/tx_fifo_1/din |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_empty |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/empty |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/underflow |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/prog_full |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/full |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/tx_fifo_1/overflow |
add wave -noupdate -divider RX_FIFO |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_clk |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/wr_en |
add wave -noupdate -format Literal /opb_spi_slave_tb/dut/rx_fifo_1/din |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/empty |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_empty |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/underflow |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/prog_full |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/full |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/rx_fifo_1/overflow |
add wave -noupdate -divider Internal |
add wave -noupdate -format Logic /opb_spi_slave_tb/dut/opb_abort_flg |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {525982512 ps} 0} |
configure wave -namecolwidth 302 |
configure wave -valuecolwidth 53 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
update |
WaveRestoreZoom {0 ps} {568438500 ps} |
/modelsim_sim/run/opb_spi_slave/work/.keepdir
--- modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (nonexistent)
+++ modelsim_sim/run/opb_spi_slave/opb_spi_slave_tb_s.do (revision 35)
@@ -0,0 +1,4 @@
+vsim -t ps opb_spi_slave_tb
+view wave
+do opb_spi_slave_tb_w.do
+run -all
\ No newline at end of file
/modelsim_sim/run/shift_register/work/.keepdir
--- modelsim_sim/run/shift_register/shift_register_tb_c.do (nonexistent)
+++ modelsim_sim/run/shift_register/shift_register_tb_c.do (revision 35)
@@ -0,0 +1,9 @@
+vlib work
+# packages
+vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd
+# DUT
+vcom -93 ../../../../../rtl/vhdl/shift_register.vhd
+# Testbench
+vcom -93 ../../../../../bench/vhdl/tx_fifo_emu.vhd
+vcom -93 ../../../../../bench/vhdl/rx_fifo_emu.vhd
+vcom -93 ../../../../../bench/vhdl/shift_register_tb.vhd
\ No newline at end of file
/modelsim_sim/run/shift_register/shift_register_tb_s.do
0,0 → 1,4
vsim -t ps shift_register_tb |
view wave |
do shift_register_tb_w.do |
run -all |
/modelsim_sim/run/shift_register/shift_register_tb_w.do
0,0 → 1,36
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Literal /shift_register_tb/test_num |
add wave -noupdate -format Logic /shift_register_tb/s_rst |
add wave -noupdate -divider External |
add wave -noupdate -format Logic /shift_register_tb/s_sclk |
add wave -noupdate -format Logic /shift_register_tb/s_cs_n |
add wave -noupdate -format Logic /shift_register_tb/s_mosi |
add wave -noupdate -format Logic /shift_register_tb/s_miso_o |
add wave -noupdate -format Logic /shift_register_tb/s_miso_i |
add wave -noupdate -format Logic /shift_register_tb/s_miso_t |
add wave -noupdate -divider TX-FIFO |
add wave -noupdate -format Logic /shift_register_tb/s_tx_clk |
add wave -noupdate -format Logic /shift_register_tb/s_tx_en |
add wave -noupdate -format Literal -radix unsigned /shift_register_tb/s_tx_data |
add wave -noupdate -divider RX-FIFO |
add wave -noupdate -format Logic /shift_register_tb/s_rx_clk |
add wave -noupdate -format Logic /shift_register_tb/s_rx_en |
add wave -noupdate -format Literal /shift_register_tb/s_rx_data |
add wave -noupdate -divider Internal |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {62874 ps} 0} |
configure wave -namecolwidth 281 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
update |
WaveRestoreZoom {0 ps} {3570 ns} |
/modelsim_sim/run/fifo/fifo_tb_w.do
0,0 → 1,35
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_empty_thresh |
add wave -noupdate -format Literal -radix hexadecimal /fifo_tb/prog_full_thresh |
add wave -noupdate -divider {write port} |
add wave -noupdate -format Logic /fifo_tb/wr_clk |
add wave -noupdate -format Logic /fifo_tb/wr_en |
add wave -noupdate -format Literal /fifo_tb/din |
add wave -noupdate -divider read_port |
add wave -noupdate -format Logic /fifo_tb/rd_clk |
add wave -noupdate -format Logic /fifo_tb/rd_en |
add wave -noupdate -format Literal /fifo_tb/dout |
add wave -noupdate -divider flags |
add wave -noupdate -format Logic /fifo_tb/prog_empty |
add wave -noupdate -format Logic /fifo_tb/empty |
add wave -noupdate -format Logic /fifo_tb/underflow |
add wave -noupdate -format Logic /fifo_tb/prog_full |
add wave -noupdate -format Logic /fifo_tb/full |
add wave -noupdate -format Logic /fifo_tb/overflow |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {387500 ps} 0} |
configure wave -namecolwidth 192 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
update |
WaveRestoreZoom {0 ps} {1160250 ps} |
/modelsim_sim/run/fifo/work/.keepdir
--- modelsim_sim/run/fifo/fifo_tb_c.do (nonexistent)
+++ modelsim_sim/run/fifo/fifo_tb_c.do (revision 35)
@@ -0,0 +1,13 @@
+vlib work
+# packages
+vcom -93 ../../../../../bench/vhdl/images-body.vhd
+vcom -93 ../../../../../bench/vhdl/txt_util.vhd
+# DUT
+vcom -93 ../../../../../rtl/vhdl/gray_adder.vhd
+vcom -93 ../../../../../rtl/vhdl/gray2bin.vhd
+vcom -93 ../../../../../rtl/vhdl/bin2gray.vhd
+vcom -93 ../../../../../rtl/vhdl/fifo_prog_flags.vhd
+vcom -93 ../../../../../rtl/vhdl/ram.vhd
+vcom -93 ../../../../../rtl/vhdl/fifo.vhd
+# Testbench
+vcom -93 ../../../../../bench/vhdl/fifo_tb.vhd
\ No newline at end of file
/modelsim_sim/run/fifo/fifo_tb_s.do
0,0 → 1,4
vsim -t ps fifo_tb |
view wave |
do fifo_tb_w.do |
run -all |
/modelsim_sim/run/grey_adder/work/.keepdir
--- modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (nonexistent)
+++ modelsim_sim/run/opb_m_if/opb_m_if_tb_c.do (revision 35)
@@ -0,0 +1,7 @@
+vlib work
+# packages
+vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd
+# DUT
+vcom -93 ../../../../../rtl/vhdl/opb_m_if.vhd
+# Testbench
+vcom -93 ../../../../../bench/vhdl/opb_m_if_tb.vhd
\ No newline at end of file
/modelsim_sim/run/opb_m_if/opb_m_if_tb_s.do
0,0 → 1,4
vsim -t ps opb_m_if_tb |
view wave |
do opb_m_if_tb_w.do |
run -all |
/modelsim_sim/run/opb_m_if/work/.keepdir
--- modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (nonexistent)
+++ modelsim_sim/run/opb_m_if/opb_m_if_tb_w.do (revision 35)
@@ -0,0 +1,53 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider Internal
+add wave -noupdate -format Logic /opb_m_if_tb/opb_clk
+add wave -noupdate -format Logic /opb_m_if_tb/opb_rst
+add wave -noupdate -format Logic /opb_m_if_tb/m_request
+add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant
+add wave -noupdate -format Logic /opb_m_if_tb/m_buslock
+add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr
+add wave -noupdate -format Logic /opb_m_if_tb/m_select
+add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack
+add wave -noupdate -format Literal /opb_m_if_tb/m_be
+add wave -noupdate -format Logic /opb_m_if_tb/m_rnw
+add wave -noupdate -format Literal /opb_m_if_tb/m_abus
+add wave -noupdate -format Literal /opb_m_if_tb/m_dbus
+add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus
+add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry
+add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout
+add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack
+add wave -noupdate -divider T-FIFIO
+add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req
+add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en
+add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data
+add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl
+add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr
+add wave -noupdate -divider R-FIFO
+add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req
+add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en
+add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data
+add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl
+add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr
+add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data
+add wave -noupdate -divider Internal
+add wave -noupdate -format Logic /opb_m_if_tb/opb_m_if_2/read_transfer
+add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/state
+add wave -noupdate -format Literal -radix hexadecimal /opb_m_if_tb/opb_m_if_2/opb_tx_dma_addr_int
+add wave -noupdate -format Literal /opb_m_if_tb/opb_m_if_2/opb_rx_dma_addr_int
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1332415 ps} 0}
+configure wave -namecolwidth 276
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {1055780 ps}
/modelsim_sim/run/opb_if/opb_if_tb_c.do
0,0 → 1,8
vlib work |
# packages |
vcom -93 ../../../../../rtl/vhdl/opb_spi_slave_pack.vhd |
# DUT |
vcom -93 ../../../../../rtl/vhdl/opb_if.vhd |
# Testbench |
vcom -93 ../../../../../bench/vhdl/opb_if_tb.vhd |
|
/modelsim_sim/run/opb_if/opb_if_tb_s.do
0,0 → 1,4
vsim -t ps opb_if_tb |
view wave |
do opb_if_tb_w.do |
run -all |
/modelsim_sim/run/opb_if/opb_if_tb_w.do
0,0 → 1,49
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider Internal |
add wave -noupdate -format Logic /opb_m_if_tb/opb_clk |
add wave -noupdate -format Logic /opb_m_if_tb/opb_rst |
add wave -noupdate -format Logic /opb_m_if_tb/m_request |
add wave -noupdate -format Logic /opb_m_if_tb/mopb_mgrant |
add wave -noupdate -format Logic /opb_m_if_tb/m_buslock |
add wave -noupdate -format Logic /opb_m_if_tb/m_seqaddr |
add wave -noupdate -format Logic /opb_m_if_tb/m_select |
add wave -noupdate -format Logic /opb_m_if_tb/mopb_errack |
add wave -noupdate -format Literal /opb_m_if_tb/m_be |
add wave -noupdate -format Logic /opb_m_if_tb/m_rnw |
add wave -noupdate -format Literal /opb_m_if_tb/m_abus |
add wave -noupdate -format Literal /opb_m_if_tb/m_dbus |
add wave -noupdate -format Literal /opb_m_if_tb/opb_dbus |
add wave -noupdate -format Logic /opb_m_if_tb/mopb_retry |
add wave -noupdate -format Logic /opb_m_if_tb/mopb_timeout |
add wave -noupdate -format Logic /opb_m_if_tb/mopb_xferack |
add wave -noupdate -divider T-FIFIO |
add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_req |
add wave -noupdate -format Logic /opb_m_if_tb/opb_m_tx_en |
add wave -noupdate -format Literal /opb_m_if_tb/opb_m_tx_data |
add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_ctl |
add wave -noupdate -format Literal /opb_m_if_tb/opb_tx_dma_addr |
add wave -noupdate -divider R-FIFO |
add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_req |
add wave -noupdate -format Logic /opb_m_if_tb/opb_m_rx_en |
add wave -noupdate -format Literal /opb_m_if_tb/opb_m_rx_data |
add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_ctl |
add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_dma_addr |
add wave -noupdate -format Literal /opb_m_if_tb/opb_rx_data |
add wave -noupdate -divider Internal |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {1710000 ps} 0} |
configure wave -namecolwidth 276 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
update |
WaveRestoreZoom {0 ps} {3370500 ps} |