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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib/trunk/env/verilog
    from Rev 14 to Rev 18
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Rev 14 → Rev 18

/scoreboard/sb_monitor.v
0,0 → 1,52
// combination refmodel/monitor for scoreboard
 
module sb_monitor
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
 
input c_srdy,
input c_drdy,
input c_req_type, // 0=read, 1=write
input [txid_sz-1:0] c_txid,
input [width-1:0] c_mask,
input [width-1:0] c_data,
input [asz-1:0] c_itemid,
 
input p_srdy,
output reg p_drdy,
input [txid_sz-1:0] p_txid,
input [width-1:0] p_data
);
 
reg [width-1:0] sbmem [0:items-1];
 
always @(posedge clk)
begin
if (c_srdy & c_drdy & (c_req_type == 1))
begin
sbmem[c_itemid] <= #20 (sbmem[c_itemid] & ~c_mask) | (c_data & c_mask);
end
 
if (p_srdy & p_drdy)
begin
if (p_data != sbmem[p_txid])
begin
$display ("%t: ERROR: sb returned %x, expected %x",
$time, p_data, sbmem[p_txid]);
end
end
end
initial
begin
p_drdy = 1;
end
 
endmodule // sb_monitor
/scoreboard/sb_driver.v
0,0 → 1,147
//----------------------------------------------------------------------
// Srdy/Drdy sequence generator
//
// Simplistic traffic generator for srdy/drdy blocks. Generates an
// incrementing data sequence.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
`define SDLIB_DELAY #1
`endif
 
module sb_driver
#(parameter width=8,
parameter items=64,
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
(input clk,
input reset,
output reg p_srdy,
input p_drdy,
output reg p_req_type, // 0=read, 1=write
output reg [txid_sz-1:0] p_txid,
output reg [width-1:0] p_mask,
output reg [asz-1:0] p_itemid,
output reg [width-1:0] p_data);
 
/* -----\/----- EXCLUDED -----\/-----
parameter pat_dep = 8;
 
reg [pat_dep-1:0] srdy_pat;
integer spp, startup;
integer rep_count;
 
initial
begin
srdy_pat = {pat_dep{1'b1}};
spp = 0;
startup = 0;
rep_count = 0;
end
 
always @*
begin
nxt_p_data = p_data;
nxt_p_srdy = p_srdy;
nxt_p_req_type = p_req_type;
if (p_srdy & p_drdy)
begin
 
if (srdy_pat[spp] && (rep_count > 1))
begin
nxt_p_data = p_data + 1;
nxt_p_srdy = 1;
end
else
nxt_p_srdy = 0;
end // if (p_srdy & p_drdy)
else if (!p_srdy && (rep_count != 0))
begin
if (srdy_pat[spp])
begin
nxt_p_data = p_data + 1;
nxt_p_srdy = 1;
end
else
nxt_p_srdy = 0;
end
end // always @ *
 
always @(posedge clk)
begin
if ((p_srdy & p_drdy) | !p_srdy)
spp = (spp + 1) % pat_dep;
 
if (p_srdy & p_drdy)
begin
if (rep_count != -1)
rep_count = rep_count - 1;
end
end
 
always @(posedge clk)
begin
if (reset)
begin
p_srdy <= `SDLIB_DELAY 0;
p_data <= `SDLIB_DELAY 0;
end
else
begin
p_srdy <= `SDLIB_DELAY nxt_p_srdy;
p_data <= `SDLIB_DELAY nxt_p_data;
end
end // always @ (posedge clk)
-----/\----- EXCLUDED -----/\----- */
 
initial
begin
p_srdy <= #1 0;
p_req_type <= #1 0;
p_txid <= #1 0;
p_mask <= #1 0;
p_itemid <= #1 0;
p_data <= #1 0;
end
 
task send;
input req_type;
//input [txid_sz-1:0] txid;
input [width-1:0] mask;
input [width-1:0] data;
input [asz-1:0] itemid;
begin
p_srdy <= #1 1;
//input p_drdy,
p_req_type <= #1 req_type;
p_txid <= #1 itemid;
p_mask <= #1 mask;
p_itemid <= #1 itemid;
p_data <= #1 data;
@(negedge clk);
if (p_drdy)
begin
@(posedge clk);
p_srdy <= #1 0;
end
else
begin
while (!p_drdy)
@(posedge clk);
p_srdy <= #1 0;
end
end
endtask
 
endmodule // sb_driver
/scoreboard/run
0,0 → 1,11
#!/bin/bash
 
which iverilog &> /dev/null
if [ "$?" == "0" ]; then
rm -f a.out
iverilog -f scoreboard.vf $*
./a.out -lxt
else
vcs -full64 +v2k -R -I -f scoreboard.vf $*
fi
 
/scoreboard/sb_bench.v
0,0 → 1,179
`timescale 1ns/1ns
 
module sb_bench;
 
localparam width = 32;
localparam items = 32;
localparam use_txid = 1;
localparam use_mask = 1;
localparam asz=$clog2(items);
localparam txid_sz = asz;
 
reg clk, reset;
wire p_drdy = 1'b1;
 
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] c_data; // From driver of sb_driver.v
wire c_drdy; // From sboard of sd_scoreboard.v
wire [asz-1:0] c_itemid; // From driver of sb_driver.v
wire [width-1:0] c_mask; // From driver of sb_driver.v
wire c_req_type; // From driver of sb_driver.v
wire c_srdy; // From driver of sb_driver.v
wire [txid_sz-1:0] c_txid; // From driver of sb_driver.v
wire [width-1:0] p_data; // From sboard of sd_scoreboard.v
wire p_srdy; // From sboard of sd_scoreboard.v
wire [txid_sz-1:0] p_txid; // From sboard of sd_scoreboard.v
// End of automatics
 
/* sb_driver AUTO_TEMPLATE
(
.p_\(.*\) (c_\1[]),
);
*/
sb_driver #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) driver
(/*AUTOINST*/
// Outputs
.p_srdy (c_srdy), // Templated
.p_req_type (c_req_type), // Templated
.p_txid (c_txid[txid_sz-1:0]), // Templated
.p_mask (c_mask[width-1:0]), // Templated
.p_itemid (c_itemid[asz-1:0]), // Templated
.p_data (c_data[width-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.p_drdy (c_drdy)); // Templated
/* sd_scoreboard AUTO_TEMPLATE
(
);
*/
sd_scoreboard #(
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz)) sboard
(/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_drdy (p_drdy));
 
sb_monitor #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) monitor
(/*AUTOINST*/
// Outputs
.p_drdy (p_drdy),
// Inputs
.clk (clk),
.reset (reset),
.c_srdy (c_srdy),
.c_drdy (c_drdy),
.c_req_type (c_req_type),
.c_txid (c_txid[txid_sz-1:0]),
.c_mask (c_mask[width-1:0]),
.c_data (c_data[width-1:0]),
.c_itemid (c_itemid[asz-1:0]),
.p_srdy (p_srdy),
.p_txid (p_txid[txid_sz-1:0]),
.p_data (p_data[width-1:0]));
 
/* -----\/----- EXCLUDED -----\/-----
task send;
input req_type;
input [txid_sz-1:0] txid;
input [width-1:0] mask;
input [width-1:0] data;
input [asz-1:0] itemid;
-----/\----- EXCLUDED -----/\----- */
integer i, entry;
integer op;
initial
begin
`ifdef VCS
$vcdpluson;
`else
$dumpfile ("sb.lxt");
$dumpvars;
`endif
reset = 1;
#200;
reset = 0;
 
repeat (5) @(posedge clk);
 
// fill up scoreboard with random data
for (i=0; i<items; i=i+1)
begin
driver.send (1, {width{1'b1}}, $random, i);
end
 
// request random entries from scoreboard
for (i=0; i<64; i=i+1)
begin
entry = {$random} % items;
driver.send (0, 0, 0, entry);
end
 
// mix updates with requests
for (i=0; i<1024; i=i+1)
begin
entry = {$random} % items;
 
op = {$random} % 8;
 
if (op == 0)
driver.send (1, {width{1'b1}}, $random, entry);
else if (op == 1)
driver.send (1, $random, $random, entry);
else
driver.send (0, 0, 0, entry);
end
#500;
$finish;
end
endmodule // sb_bench
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/utility")
// End:
 
/scoreboard/scoreboard.vf
0,0 → 1,9
sb_bench.v
sb_driver.v
sb_monitor.v
../../../rtl/verilog/utility/sd_scoreboard.v
../../../rtl/verilog/utility/sd_scoreboard_fsm.v
+libext+.v
-y ../../../rtl/verilog/closure/
-y ../../../rtl/verilog/memory
 

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