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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib/trunk/env/verilog
    from Rev 6 to Rev 14
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  •

Rev 6 → Rev 14

/bench_fifo_b.v
4,11 → 4,13
 
reg clk, reset;
 
localparam width = 8, depth=256, asz=$clog2(depth);
localparam width = 16, depth=32, asz=$clog2(depth);
 
initial clk = 0;
always #10 clk = ~clk;
 
reg gen_commit, gen_abort;
reg chk_commit, chk_abort;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] chk_data; // From fifo_s of sd_fifo_b.v
25,7 → 27,7
.p_\(.*\) (gen_\1[]),
);
*/
sd_seq_gen gen
sd_seq_gen #(width) gen
(/*AUTOINST*/
// Outputs
.p_srdy (gen_srdy), // Templated
40,7 → 42,7
.c_\(.*\) (chk_\1[]),
);
*/
sd_seq_check chk
sd_seq_check #(width) chk
(/*AUTOINST*/
// Outputs
.c_drdy (chk_drdy), // Templated
56,7 → 58,7
.c_\(.*\) (gen_\1[]),
);
*/
sd_fifo_b #(width, depth) fifo_s
sd_fifo_b #(width, depth, 1, 1) fifo_s
(/*AUTOINST*/
// Outputs
.c_drdy (gen_drdy), // Templated
79,9 → 81,26
$dumpfile("fifo_b.vcd");
$dumpvars;
reset = 1;
gen.rep_count = 0;
gen_commit = 0;
gen_abort = 0;
chk_commit = 1;
chk_abort = 0;
#100;
reset = 0;
repeat (5) @(posedge clk);
 
//test1();
//test2();
test3();
end // initial begin
 
// test basic overflow/underflow
task test1;
begin
gen_commit = 1;
gen.rep_count = 2000;
 
// burst normal data for 50 cycles
repeat (50) @(posedge clk);
 
102,7 → 121,108
#5000;
$finish;
end
endtask // test1
 
// test of write commit/abort behavior
task test2;
begin
// first fill up entire FIFO
gen.send (depth-1);
#50;
 
wait (gen_drdy == 0);
@(posedge clk);
gen_abort <= #1 1;
 
@(posedge clk);
gen_abort <= #1 0;
#5;
if (gen_drdy !== 1)
begin
$display ("ERROR -- drdy should be asserted on empty FIFO");
#100 $finish;
end
 
gen.send (depth-2);
@(posedge clk);
gen_commit <= 1;
gen.send (1);
gen_commit <= 0;
 
repeat (depth+10)
@(posedge clk);
 
if (chk.last_seq != (depth*2-2))
begin
$display ("ERROR -- last sequence number incorrect (%x)", chk.last_seq);
$finish;
end
 
#5000;
$finish;
end
endtask // test2
 
// test read/commit behavior
task test3;
begin
// fill up FIFO
gen_commit <= 1;
chk_commit <= 0;
chk_abort <= 0;
 
@(negedge clk);
chk.drdy_pat = 0;
chk.c_drdy = 0;
chk.nxt_c_drdy = 0;
 
repeat (10) @(posedge clk);
gen.send (depth-1);
 
// read out contents of FIFO
chk.drdy_pat = 8'h5A;
 
repeat (depth*2+2)
@(posedge clk);
chk.drdy_pat = 0;
 
// FIFO should be full at this point to write side, and empty to
// read side
if (gen_drdy || chk_srdy)
begin
$display ("ERROR -- c_drdy or p_srdy asserted");
#100 $finish;
end
// reset the read pointer and the expected value
chk.last_seq = 0;
chk_abort <= #1 1;
@(posedge clk);
chk_abort <= #1 0;
 
// read out contents of FIFO again
chk.drdy_pat = 8'hFF;
 
@(posedge clk);
repeat (depth-3) @(posedge clk);
chk_commit <= #1 1;
repeat (4) @(posedge clk);
chk_commit <= #1 0;
 
// All data has been committed, so drdy should be asserted
if (gen_drdy)
begin
$display ("ERROR -- c_drdy not asserted");
#100 $finish;
end
#500;
$finish;
end
endtask
 
endmodule // bench_fifo_s
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/buffers")
/bench_fifo_s.v
82,6 → 82,8
#100;
reset = 0;
 
gen.rep_count = 1000;
 
// burst normal data for 20 cycles
repeat (20) @(posedge clk);
 
/sd_seq_gen.v
31,6 → 31,7
 
reg [pat_dep-1:0] srdy_pat;
integer spp, startup;
integer rep_count;
 
initial
begin
37,6 → 38,7
srdy_pat = {pat_dep{1'b1}};
spp = 0;
startup = 0;
rep_count = 0;
end
 
always @*
44,12 → 46,10
nxt_p_data = p_data;
nxt_p_srdy = p_srdy;
 
if (startup < 10)
if (p_srdy & p_drdy)
begin
end
else if (p_srdy & p_drdy)
begin
if (srdy_pat[spp])
 
if (srdy_pat[spp] && (rep_count > 1))
begin
nxt_p_data = p_data + 1;
nxt_p_srdy = 1;
56,8 → 56,8
end
else
nxt_p_srdy = 0;
end
else if (!p_srdy)
end // if (p_srdy & p_drdy)
else if (!p_srdy && (rep_count != 0))
begin
if (srdy_pat[spp])
begin
73,6 → 73,12
begin
if ((p_srdy & p_drdy) | !p_srdy)
spp = (spp + 1) % pat_dep;
 
if (p_srdy & p_drdy)
begin
if (rep_count != -1)
rep_count = rep_count - 1;
end
end
 
always @(posedge clk)
86,9 → 92,18
begin
p_srdy <= `SDLIB_DELAY nxt_p_srdy;
p_data <= `SDLIB_DELAY nxt_p_data;
if (startup < 10)
startup = startup + 1;
end
end // always @ (posedge clk)
 
// simple blocking task to send N words and then wait until complete
task send;
input [31:0] amount;
begin
rep_count = amount;
@(posedge clk);
while (rep_count != 0)
@(posedge clk);
end
endtask
 
endmodule // sd_seq_gen
/bench_fifo_s.vf
4,3 → 4,5
../../rtl/verilog/buffers/sd_fifo_s.v
../../rtl/verilog/buffers/sd_fifo_head_s.v
../../rtl/verilog/buffers/sd_fifo_tail_s.v
../../rtl/verilog/memory/behave2p_mem.v
 

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