URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
Compare Revisions
- This comparison shows the changes necessary to convert path
/srdydrdy_lib/trunk/env/verilog
- from Rev 22 to Rev 25
- ↔ Reverse comparison
Rev 22 → Rev 25
/sync/sync_bench.v
0,0 → 1,105
module sync_bench; |
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parameter width = 16; |
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reg a_clk, a_reset; |
reg b_clk, b_reset; |
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wire [width-1:0] a_data; |
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wire a_srdy, a_drdy; |
wire b_srdy, b_drdy; |
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initial |
begin |
`ifdef VCS |
$vcdpluson; |
`else |
$dumpfile ("sync.vcd"); |
$dumpvars; |
`endif |
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a_clk = 0; |
b_clk = 0; |
a_reset = 1; |
b_reset = 1; |
#200; |
a_reset = 0; |
b_reset = 0; |
#200; |
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seq_gen.send (25); |
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seq_gen.srdy_pat = 8'h01; |
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seq_gen.send (25); |
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seq_gen.srdy_pat = 8'hFF; |
seq_chk.drdy_pat = 8'h01; |
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seq_gen.send (25); |
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seq_gen.srdy_pat = 8'h01; |
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seq_gen.send (25); |
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#2000; |
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if (seq_chk.last_seq == 100) |
$display ("TEST PASSED"); |
else |
$display ("TEST FAILED"); |
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$finish; |
end // initial begin |
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initial |
begin |
#50000; // timeout value |
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$display ("TEST FAILED"); |
$finish; |
end |
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always a_clk = #5 ~a_clk; |
always b_clk = #17 ~b_clk; |
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sd_seq_gen #(.width(width)) seq_gen |
( |
.clk (a_clk), |
.reset (a_reset), |
.p_srdy (a_srdy), |
.p_data (a_data), |
// Inputs |
.p_drdy (a_drdy)); |
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sd_sync sync0 |
( |
// Outputs |
.c_drdy (a_drdy), |
.p_srdy (b_srdy), |
// Inputs |
.c_clk (a_clk), |
.c_reset (a_reset), |
.c_srdy (a_srdy), |
.p_clk (b_clk), |
.p_reset (b_reset), |
.p_drdy (b_drdy)); |
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sd_seq_check #(.width(width)) seq_chk |
( |
// Outputs |
.c_drdy (b_drdy), |
// Inputs |
.clk (b_clk), |
.reset (b_reset), |
.c_srdy (b_srdy), |
.c_data (a_data)); |
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endmodule // sync_bench |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/utility" "../common") |
// End: |
|
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/sync/sync.vf
0,0 → 1,4
../common/sd_seq_check.v |
../common/sd_seq_gen.v |
../../../rtl/verilog/utility/sd_sync.v |
sync_bench.v |