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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib/trunk/examples/bridge/env
    from Rev 4 to Rev 8
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  •

Rev 4 → Rev 8

/run
0,0 → 1,5
#!/bin/bash
 
iverilog -f bridge.vf
./a.out
 
/gmii_driver.v
0,0 → 1,114
// Send an ethernet packet over GMII
 
module gmii_driver
(output reg [7:0] rxd,
output reg rx_dv,
output reg rx_clk);
 
integer startup_skew;
 
reg [7:0] rxbuf [0:2048];
reg [31:0] crc32_result;
 
// begin start clock with random skew amount
initial
begin
startup_skew = {$random} % 200;
rx_clk = 0;
rx_dv = 0;
rxd = 0;
repeat (startup_skew) #0.1;
forever rx_clk = #4 ~rx_clk;
end
 
// Copied from: http://www.mindspring.com/~tcoonan/gencrc.v
//
// Generate a (DOCSIS) CRC32.
//
// Uses the GLOBAL variables:
//
// Globals referenced:
// parameter CRC32_POLY = 32'h04C11DB7;
// reg [ 7:0] crc32_packet[0:255];
// integer crc32_length;
//
// Globals modified:
// reg [31:0] crc32_result;
//
localparam CRC32_POLY = 32'h04C11DB7;
task gencrc32;
input [31:09] crc32_length;
integer cbyte, cbit;
reg msb;
reg [7:0] current_cbyte;
reg [31:0] temp;
begin
crc32_result = 32'hffffffff;
for (cbyte = 0; cbyte < crc32_length; cbyte = cbyte + 1) begin
current_cbyte = rxbuf[cbyte];
for (cbit = 0; cbit < 8; cbit = cbit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_cbyte[cbit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (cbit = 0; cbit < 32; cbit = cbit + 1)
temp[31-cbit] = crc32_result[cbit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
 
task send_packet;
input [47:0] da, sa;
input [15:0] length;
integer p;
begin
{ rxbuf[0],rxbuf[1],rxbuf[2],rxbuf[3],rxbuf[4],rxbuf[5] } = da;
{ rxbuf[6],rxbuf[7],rxbuf[8],rxbuf[9],rxbuf[10],rxbuf[11] } = sa;
for (p=12; p<length; p=p+1)
rxbuf[p] = $random;
 
gencrc32 (length);
{ rxbuf[length-4], rxbuf[length-3],
rxbuf[length-2], rxbuf[length-1] } = crc32_result;
 
$display ("%m : Sending packet DA=%x SA=%x of length %0d", da, sa, length);
repeat (7)
begin
@(posedge rx_clk);
rx_dv <= #1 1;
rxd <= #1 `GMII_PRE;
end
 
@(posedge rx_clk);
rxd <= #1 `GMII_SFD;
 
p = 0;
while (p < length)
begin
@(posedge rx_clk);
rxd <= #1 rxbuf[p];
p = p + 1;
end
 
// complete 12B inter frame gap
repeat (12)
begin
@(posedge rx_clk);
rx_dv <= #1 0;
rxd <= #1 0;
end
end
endtask // send_packet
 
endmodule // gmii_driver
/bridge.vf
0,0 → 1,25
../rtl/bridge.vh
 
env_top.v
gmii_driver.v
 
../rtl/basic_hashfunc.v
../rtl/bridge_ex1.v
../rtl/concentrator.v
../rtl/distributor.v
../rtl/egr_oflow.v
../rtl/fib_lookup_fsm.v
../rtl/fib_lookup.v
../rtl/pkt_parse.v
../rtl/port_clocking.v
../rtl/port_macro.v
../rtl/port_ring_tap_fsm.v
../rtl/port_ring_tap.v
../rtl/sd_rx_gigmac.v
../rtl/sd_tx_gigmac.v
+libext+.v
-y ../../../rtl/verilog/buffers
-y ../../../rtl/verilog/closure
-y ../../../rtl/verilog/forks
-y ../../../rtl/verilog/memory
 
/env_top.v
0,0 → 1,120
`timescale 1ns/1ps
 
module env_top;
 
reg clk, reset;
 
initial
begin
clk = 0;
forever clk = #4 ~clk;
end
 
initial
begin
$dumpfile ("env_top.vcd");
$dumpvars;
reset = 1;
#200;
reset = 0;
#200;
 
fork
driver0.send_packet (1, 2, 20);
driver1.send_packet (2, 3, 64);
driver2.send_packet (3, 4, 64);
driver3.send_packet (4, 1, 64);
join
 
#500;
$finish;
end
 
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire gmii_rx_clk_0; // From driver0 of gmii_driver.v
wire gmii_rx_clk_1; // From driver1 of gmii_driver.v
wire gmii_rx_clk_2; // From driver2 of gmii_driver.v
wire gmii_rx_clk_3; // From driver3 of gmii_driver.v
wire gmii_rx_dv_0; // From driver0 of gmii_driver.v
wire gmii_rx_dv_1; // From driver1 of gmii_driver.v
wire gmii_rx_dv_2; // From driver2 of gmii_driver.v
wire gmii_rx_dv_3; // From driver3 of gmii_driver.v
wire [7:0] gmii_rxd_0; // From driver0 of gmii_driver.v
wire [7:0] gmii_rxd_1; // From driver1 of gmii_driver.v
wire [7:0] gmii_rxd_2; // From driver2 of gmii_driver.v
wire [7:0] gmii_rxd_3; // From driver3 of gmii_driver.v
wire gmii_tx_dv_0; // From bridge of bridge_ex1.v
wire gmii_tx_dv_1; // From bridge of bridge_ex1.v
wire gmii_tx_dv_2; // From bridge of bridge_ex1.v
wire gmii_tx_dv_3; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_0; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_1; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_2; // From bridge of bridge_ex1.v
wire [7:0] gmii_txd_3; // From bridge of bridge_ex1.v
// End of automatics
 
/* gmii_driver AUTO_TEMPLATE
(
.\(.*\) (gmii_\1_@[]),
);
*/
gmii_driver driver0
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_0[7:0]), // Templated
.rx_dv (gmii_rx_dv_0), // Templated
.rx_clk (gmii_rx_clk_0)); // Templated
 
gmii_driver driver1
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_1[7:0]), // Templated
.rx_dv (gmii_rx_dv_1), // Templated
.rx_clk (gmii_rx_clk_1)); // Templated
 
gmii_driver driver2
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_2[7:0]), // Templated
.rx_dv (gmii_rx_dv_2), // Templated
.rx_clk (gmii_rx_clk_2)); // Templated
 
gmii_driver driver3
(/*AUTOINST*/
// Outputs
.rxd (gmii_rxd_3[7:0]), // Templated
.rx_dv (gmii_rx_dv_3), // Templated
.rx_clk (gmii_rx_clk_3)); // Templated
 
bridge_ex1 bridge
(/*AUTOINST*/
// Outputs
.gmii_tx_dv_0 (gmii_tx_dv_0),
.gmii_tx_dv_1 (gmii_tx_dv_1),
.gmii_tx_dv_2 (gmii_tx_dv_2),
.gmii_tx_dv_3 (gmii_tx_dv_3),
.gmii_txd_0 (gmii_txd_0[7:0]),
.gmii_txd_1 (gmii_txd_1[7:0]),
.gmii_txd_2 (gmii_txd_2[7:0]),
.gmii_txd_3 (gmii_txd_3[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.gmii_rx_clk_0 (gmii_rx_clk_0),
.gmii_rx_clk_1 (gmii_rx_clk_1),
.gmii_rx_clk_2 (gmii_rx_clk_2),
.gmii_rx_clk_3 (gmii_rx_clk_3),
.gmii_rx_dv_0 (gmii_rx_dv_0),
.gmii_rx_dv_1 (gmii_rx_dv_1),
.gmii_rx_dv_2 (gmii_rx_dv_2),
.gmii_rx_dv_3 (gmii_rx_dv_3),
.gmii_rxd_0 (gmii_rxd_0[7:0]),
.gmii_rxd_1 (gmii_rxd_1[7:0]),
.gmii_rxd_2 (gmii_rxd_2[7:0]),
.gmii_rxd_3 (gmii_rxd_3[7:0]));
 
endmodule // env_top
// Local Variables:
// verilog-library-directories:("." "../rtl")
// End:

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