URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
Compare Revisions
- This comparison shows the changes necessary to convert path
/srdydrdy_lib/trunk/examples/bridge
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/rtl/port_ring_tap_fsm.v
39,12 → 39,14
s_rfwd = 1, |
s_rcopy = 2, |
s_rsink = 3, |
s_tdata = 4; |
s_tdata = 4, |
s_tdrop = 5; |
localparam ns_idle = 1, |
ns_rfwd = 2, |
ns_rcopy = 4, |
ns_rsink = 8, |
ns_tdata = 16; |
ns_tdata = 16, |
ns_tdrop = 32; |
|
assign rarb_req = lfli_srdy & lprx_srdy | state[s_tdata]; |
|
77,7 → 79,10
end |
end |
else |
lfli_drdy = 1; |
begin |
lfli_drdy = 1; |
nxt_state = ns_tdrop; |
end |
end |
else if (lri_srdy) |
begin |
131,6 → 136,19
end |
end // case: state[s_tdata] |
|
// received lookup from FIB with zero port index; drop |
// the packet by reading out |
state[s_tdrop] : |
begin |
lprx_drdy = 1; |
if (lprx_srdy) |
begin |
if ((lprx_data[`PRW_PCC] == `PCC_EOP) | |
(lprx_data[`PRW_PCC] == `PCC_BADEOP)) |
nxt_state = ns_idle; |
end |
end |
|
// data on ring is for our port as well as further ports |
// copy ring data to our TX buffer as well as on the ring |
state[s_rcopy] : |
/rtl/egr_oflow.v
1,5 → 1,5
module egr_oflow |
#(parameter drop_thr=`TX_FIFO_DEPTH-10) |
#(parameter drop_thr=`TX_FIFO_DEPTH-128) |
( |
input clk, |
input reset, |
60,7 → 60,7
p_commit = 1; |
nxt_state = s_idle; |
end |
else if (tx_usage >= drop_thr) |
else if (!p_drdy | (tx_usage >= drop_thr)) |
begin |
c_drdy = 1; |
nxt_state = s_idle; |
/rtl/fib_lookup_fsm.v
102,7 → 102,7
end |
else |
begin |
lout_data = 1 << ft_rdata[`FIB_PORT]; |
lout_data = (1 << ft_rdata[`FIB_PORT]) & ~source_port_mask; |
end |
|
lout_srdy = 1; |
/rtl/bridge.vh
38,8 → 38,8
`define PFW_SZ 69 |
|
// Port FIFO sizes |
`define RX_FIFO_DEPTH 64 |
`define TX_FIFO_DEPTH 256 |
`define RX_FIFO_DEPTH 256 |
`define TX_FIFO_DEPTH 1024 |
|
`define RX_USG_SZ $clog2(`RX_FIFO_DEPTH)+1 |
`define TX_USG_SZ $clog2(`TX_FIFO_DEPTH)+1 |
/env/tests/sample_test.v
0,0 → 1,29
module sample_test; |
|
integer pcount; |
`include "test_tasks.v" |
|
initial |
begin |
wait (env_top.reset === 1'b0); |
#200; |
|
repeat (`FIB_ENTRIES) |
@(posedge env_top.clk); |
|
fork |
env_top.driver0.send_packet (1, 2, 20); |
env_top.driver1.send_packet (2, 3, 64); |
env_top.driver2.send_packet (3, 4, 64); |
env_top.driver3.send_packet (4, 1, 64); |
join |
|
#2000; |
|
get_packet_count (pcount); |
check_expected (9, pcount); |
$display ("TEST: Received %d packets", pcount); |
$finish; |
end |
|
endmodule // sample_test |
/env/tests/overflow1.v
0,0 → 1,43
module sample_test; |
|
integer pcount; |
`include "test_tasks.v" |
|
initial |
begin |
wait (env_top.reset === 1'b0); |
#200; |
|
repeat (`FIB_ENTRIES) |
@(posedge env_top.clk); |
|
fork |
begin : drv0 |
repeat (600) |
env_top.driver0.send_packet ($random, $random, 64); |
end |
|
begin : drv1 |
repeat (300) |
env_top.driver1.send_packet ($random, $random, 128); |
end |
|
begin : drv2 |
repeat (450) |
env_top.driver2.send_packet ($random, $random, 96); |
end |
begin : drv3 |
repeat (150) |
env_top.driver3.send_packet ($random, $random, 256); |
end |
join |
|
#10000; |
|
get_packet_count (pcount); |
check_expected (9, pcount); |
$display ("TEST: Received %d packets", pcount); |
$finish; |
end |
|
endmodule // sample_test |
/env/run
1,11 → 1,14
#!/bin/bash |
|
TESTNAME=$1 |
shift |
|
which vcs &> /dev/null |
if [ "$?" == "-1" ]; then |
iverilog -f bridge.vf |
iverilog -f bridge.vf tests/$TESTNAME.v $* |
./a.out |
else |
vcs -full64 +v2k -R -I -f bridge.vf |
vcs -full64 +v2k -R -I -f bridge.vf tests/$TESTNAME.v $* |
#vcd2vpd env_top.vcd env_top.vpd |
fi |
|
/env/test_tasks.v
0,0 → 1,21
|
task get_packet_count; |
output [31:0] pcount; |
integer p; |
begin |
p = 0; |
p = p + env_top.mon0.rxpkt_num; |
p = p + env_top.mon1.rxpkt_num; |
p = p + env_top.mon2.rxpkt_num; |
p = p + env_top.mon3.rxpkt_num; |
pcount = p; |
end |
endtask // get_packet_count |
|
task check_expected; |
input [31:0] exp_val, act_val; |
begin |
if (exp_val !== act_val) |
$display ("%t: ERROR: Expected %x, Actual value %x", $time, exp_val, act_val); |
end |
endtask // check_expected |
/env/env_top.v
21,22 → 21,9
reset = 1; |
#200; |
reset = 0; |
#200; |
end // initial begin |
|
|
repeat (`FIB_ENTRIES) |
@(posedge clk); |
|
fork |
driver0.send_packet (1, 2, 20); |
driver1.send_packet (2, 3, 64); |
driver2.send_packet (3, 4, 64); |
driver3.send_packet (4, 1, 64); |
join |
|
#2000; |
$finish; |
end |
|
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire gmii_rx_clk_0; // From driver0 of gmii_driver.v |