URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
Compare Revisions
- This comparison shows the changes necessary to convert path
/srdydrdy_lib/trunk/examples/bridge
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/rtl/port_ring_tap_fsm.v
27,10 → 27,9
input rarb_ack |
); |
|
reg [4:0] state, nxt_state; |
reg [5:0] state, nxt_state; |
|
wire [`NUM_PORTS-1:0] port_mask; |
//reg [`NUM_PORTS-1:0] pe_vec, nxt_pe_vec; |
wire [`NUM_PORTS-1:0] nxt_pe_vec = lri_data[`PRW_DATA] & ~port_mask; |
|
assign port_mask = 1 << portnum; |
/rtl/port_macro.v
8,14 → 8,14
input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input fli_srdy, // To ring_tap of port_ring_tap.v |
input gmii_rx_clk, // To port_clocking of port_clocking.v, ... |
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v |
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v |
input p2f_drdy, // To pkt_parse of pkt_parse.v |
input rarb_ack, // To ring_tap of port_ring_tap.v |
input ri_srdy, // To ring_tap of port_ring_tap.v |
input ro_drdy, // To ring_tap of port_ring_tap.v |
input fli_srdy, // To ring_tap of port_ring_tap.v |
input gmii_rx_clk, // To port_clocking of port_clocking.v, ... |
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v |
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v |
input p2f_drdy, // To pkt_parse of pkt_parse.v |
input rarb_ack, // To ring_tap of port_ring_tap.v |
input ri_srdy, // To ring_tap of port_ring_tap.v |
input ro_drdy, // To ring_tap of port_ring_tap.v |
// End of automatics |
|
output rarb_req, |
38,37 → 38,36
wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire crx_abort; // From con of concentrator.v |
wire crx_commit; // From con of concentrator.v |
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v |
wire crx_drdy; // From fifo_rx of sd_fifo_b.v |
wire crx_srdy; // From con of concentrator.v |
wire ctx_abort; // From oflow of egr_oflow.v |
wire ctx_commit; // From oflow of egr_oflow.v |
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v |
wire ctx_srdy; // From oflow of egr_oflow.v |
wire gmii_rx_reset; // From port_clocking of port_clocking.v |
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v |
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v |
wire pdo_drdy; // From con of concentrator.v |
wire pdo_srdy; // From pkt_parse of pkt_parse.v |
wire prx_drdy; // From ring_tap of port_ring_tap.v |
wire prx_srdy; // From fifo_rx of sd_fifo_b.v |
wire ptx_drdy; // From dst of distributor.v |
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v |
wire rarb_req; // From ring_tap of port_ring_tap.v |
wire rttx_drdy; // From oflow of egr_oflow.v |
wire rttx_srdy; // From ring_tap of port_ring_tap.v |
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v |
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v |
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v |
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v |
wire rxg_drdy; // From pkt_parse of pkt_parse.v |
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v |
wire [1:0] txg_code; // From dst of distributor.v |
wire [7:0] txg_data; // From dst of distributor.v |
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v |
wire txg_srdy; // From dst of distributor.v |
wire crx_abort; // From con of concentrator.v |
wire crx_commit; // From con of concentrator.v |
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v |
wire crx_drdy; // From fifo_rx of sd_fifo_b.v |
wire crx_srdy; // From con of concentrator.v |
wire ctx_abort; // From oflow of egr_oflow.v |
wire ctx_commit; // From oflow of egr_oflow.v |
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v |
wire ctx_srdy; // From oflow of egr_oflow.v |
wire gmii_rx_reset; // From port_clocking of port_clocking.v |
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v |
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v |
wire pdo_drdy; // From con of concentrator.v |
wire pdo_srdy; // From pkt_parse of pkt_parse.v |
wire prx_drdy; // From ring_tap of port_ring_tap.v |
wire prx_srdy; // From fifo_rx of sd_fifo_b.v |
wire ptx_drdy; // From dst of distributor.v |
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v |
wire rttx_drdy; // From oflow of egr_oflow.v |
wire rttx_srdy; // From ring_tap of port_ring_tap.v |
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v |
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v |
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v |
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v |
wire rxg_drdy; // From pkt_parse of pkt_parse.v |
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v |
wire [1:0] txg_code; // From dst of distributor.v |
wire [7:0] txg_data; // From dst of distributor.v |
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v |
wire txg_srdy; // From dst of distributor.v |
// End of automatics |
|
|
75,11 → 74,11
port_clocking port_clocking |
(/*AUTOINST*/ |
// Outputs |
.gmii_rx_reset (gmii_rx_reset), |
.gmii_rx_reset (gmii_rx_reset), |
// Inputs |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk (gmii_rx_clk)); |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk (gmii_rx_clk)); |
|
/* sd_rx_gigmac AUTO_TEMPLATE |
( |
91,15 → 90,15
sd_rx_gigmac rx_gigmac |
(/*AUTOINST*/ |
// Outputs |
.rxg_srdy (rxc_rxg_srdy), // Templated |
.rxg_code (rxc_rxg_code[1:0]), // Templated |
.rxg_data (rxc_rxg_data[7:0]), // Templated |
.rxg_srdy (rxc_rxg_srdy), // Templated |
.rxg_code (rxc_rxg_code[1:0]), // Templated |
.rxg_data (rxc_rxg_data[7:0]), // Templated |
// Inputs |
.clk (gmii_rx_clk), // Templated |
.reset (gmii_rx_reset), // Templated |
.gmii_rx_dv (gmii_rx_dv), |
.gmii_rxd (gmii_rxd[7:0]), |
.rxg_drdy (rxc_rxg_drdy)); // Templated |
.clk (gmii_rx_clk), // Templated |
.reset (gmii_rx_reset), // Templated |
.gmii_rx_dv (gmii_rx_dv), |
.gmii_rxd (gmii_rxd[7:0]), |
.rxg_drdy (rxc_rxg_drdy)); // Templated |
|
/* sd_fifo_s AUTO_TEMPLATE |
( |
116,35 → 115,35
sd_fifo_s #(8+2,16,1) rx_sync_fifo |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rxc_rxg_drdy), // Templated |
.p_srdy (rxg_srdy), // Templated |
.p_data ({rxg_code,rxg_data}), // Templated |
.c_drdy (rxc_rxg_drdy), // Templated |
.p_srdy (rxg_srdy), // Templated |
.p_data ({rxg_code,rxg_data}), // Templated |
// Inputs |
.c_clk (gmii_rx_clk), // Templated |
.c_reset (gmii_rx_reset), // Templated |
.c_srdy (rxc_rxg_srdy), // Templated |
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (rxg_drdy)); // Templated |
.c_clk (gmii_rx_clk), // Templated |
.c_reset (gmii_rx_reset), // Templated |
.c_srdy (rxc_rxg_srdy), // Templated |
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (rxg_drdy)); // Templated |
|
pkt_parse #(port_num) pkt_parse |
(/*AUTOINST*/ |
// Outputs |
.rxg_drdy (rxg_drdy), |
.p2f_srdy (p2f_srdy), |
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]), |
.pdo_srdy (pdo_srdy), |
.pdo_code (pdo_code[1:0]), |
.pdo_data (pdo_data[7:0]), |
.rxg_drdy (rxg_drdy), |
.p2f_srdy (p2f_srdy), |
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]), |
.pdo_srdy (pdo_srdy), |
.pdo_code (pdo_code[1:0]), |
.pdo_data (pdo_data[7:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.rxg_srdy (rxg_srdy), |
.rxg_code (rxg_code[1:0]), |
.rxg_data (rxg_data[7:0]), |
.p2f_drdy (p2f_drdy), |
.pdo_drdy (pdo_drdy)); |
.clk (clk), |
.reset (reset), |
.rxg_srdy (rxg_srdy), |
.rxg_code (rxg_code[1:0]), |
.rxg_data (rxg_data[7:0]), |
.p2f_drdy (p2f_drdy), |
.pdo_drdy (pdo_drdy)); |
|
/* concentrator AUTO_TEMPLATE |
( |
155,24 → 154,25
concentrator con |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (pdo_drdy), // Templated |
.p_data (crx_data[`PFW_SZ-1:0]), // Templated |
.p_srdy (crx_srdy), // Templated |
.p_commit (crx_commit), // Templated |
.p_abort (crx_abort), // Templated |
.c_drdy (pdo_drdy), // Templated |
.p_data (crx_data[`PFW_SZ-1:0]), // Templated |
.p_srdy (crx_srdy), // Templated |
.p_commit (crx_commit), // Templated |
.p_abort (crx_abort), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_data (pdo_data[7:0]), // Templated |
.c_code (pdo_code[1:0]), // Templated |
.c_srdy (pdo_srdy), // Templated |
.p_drdy (crx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_data (pdo_data[7:0]), // Templated |
.c_code (pdo_code[1:0]), // Templated |
.c_srdy (pdo_srdy), // Templated |
.p_drdy (crx_drdy)); // Templated |
|
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)" |
( |
.p_abort (1'b0), |
.p_commit (1'b0), |
.usage (@_usage), |
.c_usage (@_usage), |
.p_usage (), |
.c_\(.*\) (c@_\1), |
.p_\(.*\) (p@_\1), |
); |
180,38 → 180,40
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (crx_drdy), // Templated |
.p_srdy (prx_srdy), // Templated |
.p_data (prx_data), // Templated |
.usage (rx_usage), // Templated |
.c_drdy (crx_drdy), // Templated |
.p_srdy (prx_srdy), // Templated |
.p_data (prx_data), // Templated |
.p_usage (), // Templated |
.c_usage (rx_usage), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (crx_srdy), // Templated |
.c_commit (crx_commit), // Templated |
.c_abort (crx_abort), // Templated |
.c_data (crx_data), // Templated |
.p_drdy (prx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (crx_srdy), // Templated |
.c_commit (crx_commit), // Templated |
.c_abort (crx_abort), // Templated |
.c_data (crx_data), // Templated |
.p_drdy (prx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
|
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ctx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data), // Templated |
.usage (tx_usage), // Templated |
.c_drdy (ctx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data), // Templated |
.p_usage (), // Templated |
.c_usage (tx_usage), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (ctx_srdy), // Templated |
.c_commit (ctx_commit), // Templated |
.c_abort (ctx_abort), // Templated |
.c_data (ctx_data), // Templated |
.p_drdy (ptx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (ctx_srdy), // Templated |
.c_commit (ctx_commit), // Templated |
.c_abort (ctx_abort), // Templated |
.c_data (ctx_data), // Templated |
.p_drdy (ptx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
|
/* port_ring_tap AUTO_TEMPLATE |
( |
224,26 → 226,26
port_ring_tap #(port_num) ring_tap |
(/*AUTOINST*/ |
// Outputs |
.ri_drdy (ri_drdy), |
.prx_drdy (prx_drdy), // Templated |
.ro_srdy (ro_srdy), |
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated |
.ptx_srdy (rttx_srdy), // Templated |
.ptx_data (rttx_data), // Templated |
.fli_drdy (fli_drdy), |
.rarb_req (rarb_req), |
.ri_drdy (ri_drdy), |
.prx_drdy (prx_drdy), // Templated |
.ro_srdy (ro_srdy), |
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated |
.ptx_srdy (rttx_srdy), // Templated |
.ptx_data (rttx_data), // Templated |
.fli_drdy (fli_drdy), |
.rarb_req (rarb_req), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ri_srdy (ri_srdy), |
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated |
.prx_srdy (prx_srdy), // Templated |
.prx_data (prx_data), // Templated |
.ro_drdy (ro_drdy), |
.ptx_drdy (rttx_drdy), // Templated |
.fli_srdy (fli_srdy), |
.fli_data (fli_data[`NUM_PORTS-1:0]), |
.rarb_ack (rarb_ack)); |
.clk (clk), |
.reset (reset), |
.ri_srdy (ri_srdy), |
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated |
.prx_srdy (prx_srdy), // Templated |
.prx_data (prx_data), // Templated |
.ro_drdy (ro_drdy), |
.ptx_drdy (rttx_drdy), // Templated |
.fli_srdy (fli_srdy), |
.fli_data (fli_data[`NUM_PORTS-1:0]), |
.rarb_ack (rarb_ack)); |
|
/* egr_oflow AUTO_TEMPLATE |
( |
254,18 → 256,18
egr_oflow oflow |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rttx_drdy), // Templated |
.p_srdy (ctx_srdy), // Templated |
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated |
.p_commit (ctx_commit), // Templated |
.p_abort (ctx_abort), // Templated |
.c_drdy (rttx_drdy), // Templated |
.p_srdy (ctx_srdy), // Templated |
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated |
.p_commit (ctx_commit), // Templated |
.p_abort (ctx_abort), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (rttx_srdy), // Templated |
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated |
.tx_usage (tx_usage[`TX_USG_SZ-1:0]), |
.p_drdy (ctx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_srdy (rttx_srdy), // Templated |
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated |
.tx_usage (tx_usage[`TX_USG_SZ-1:0]), |
.p_drdy (ctx_drdy)); // Templated |
|
/* distributor AUTO_TEMPLATE |
( |
275,29 → 277,29
distributor dst |
(/*AUTOINST*/ |
// Outputs |
.ptx_drdy (ptx_drdy), |
.p_srdy (txg_srdy), // Templated |
.p_code (txg_code[1:0]), // Templated |
.p_data (txg_data[7:0]), // Templated |
.ptx_drdy (ptx_drdy), |
.p_srdy (txg_srdy), // Templated |
.p_code (txg_code[1:0]), // Templated |
.p_data (txg_data[7:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
.p_drdy (txg_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
.p_drdy (txg_drdy)); // Templated |
|
sd_tx_gigmac tx_gmii |
(/*AUTOINST*/ |
// Outputs |
.gmii_tx_en (gmii_tx_en), |
.gmii_txd (gmii_txd[7:0]), |
.txg_drdy (txg_drdy), |
.gmii_tx_en (gmii_tx_en), |
.gmii_txd (gmii_txd[7:0]), |
.txg_drdy (txg_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.txg_srdy (txg_srdy), |
.txg_code (txg_code[1:0]), |
.txg_data (txg_data[7:0])); |
.clk (clk), |
.reset (reset), |
.txg_srdy (txg_srdy), |
.txg_code (txg_code[1:0]), |
.txg_data (txg_data[7:0])); |
|
endmodule // port_macro |
// Local Variables: |
/env/run
5,8 → 5,9
|
which iverilog &> /dev/null |
if [ "$?" == "0" ]; then |
rm -f a.out |
iverilog -f bridge.vf tests/$TESTNAME.v $* |
./a.out |
./a.out -lxt |
else |
vcs -full64 +v2k -R -I -f bridge.vf tests/$TESTNAME.v $* |
fi |
/env/env_top.v
15,7 → 15,7
`ifdef VCS |
$vcdpluson; |
`else |
$dumpfile ("env_top.vcd"); |
$dumpfile ("env_top.lxt"); |
$dumpvars; |
`endif |
reset = 1; |