URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
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- This comparison shows the changes necessary to convert path
/srdydrdy_lib/trunk/rtl/verilog/memory
- from Rev 6 to Rev 19
- ↔ Reverse comparison
Rev 6 → Rev 19
/behave1p_mem.v
38,4 → 38,15
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assign d_out = array[r_addr]; |
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genvar g; |
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generate |
for (g=0; g<depth; g=g+1) |
begin : breakout |
wire [width-1:0] brk; |
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assign brk=array[g]; |
end |
endgenerate |
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endmodule |