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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib/trunk/rtl/verilog
    from Rev 18 to Rev 19
    ↔ Reverse comparison
  •

Rev 18 → Rev 19

/utility/sd_scoreboard_fsm.v
81,7 → 81,11
if (state[s_idle])
begin
if (ip_srdy & (ip_req_type==1))
if (state[s_read] & !ic_drdy)
begin
// output is busy, stall
end
else if (ip_srdy & (ip_req_type==1))
begin
if ((use_mask==0) | (ip_mask=={width{1'b1}}))
begin
96,7 → 100,7
nxt_state[s_idle] = 0;
end
end
else if (ip_srdy & (ip_req_type==0) & (!state[s_read] | ic_drdy))
else if (ip_srdy & (ip_req_type==0))
begin
rd_en = 1;
nxt_state[s_read] = 1;
/memory/behave1p_mem.v
38,4 → 38,15
 
assign d_out = array[r_addr];
 
genvar g;
 
generate
for (g=0; g<depth; g=g+1)
begin : breakout
wire [width-1:0] brk;
 
assign brk=array[g];
end
endgenerate
 
endmodule
/buffers/sd_fifo_tail_b.v
57,7 → 57,7
output reg mem_re,
input mem_we,
 
output reg [usz:0] p_usage,
output reg [usz-1:0] p_usage,
output p_srdy,
input p_drdy,
105,8 → 105,6
nxt_cur_rdptr = com_rdptr;
mem_re = 0;
end
// else if (enable & !empty & (!valid_a | (!prev_re & !valid_b) |
// (valid_a & valid_b & p_drdy)))
else if (enable & !empty & ip_drdy)
begin
nxt_cur_rdptr = cur_rdptr_p1;
126,42 → 124,9
p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
end // always @ *
 
/* -----\/----- EXCLUDED -----\/-----
// alternate usage calc
reg [asz-1:0] prev_wr;
reg [asz:0] usage2, nxt_usage2;
wire lcl_wr_en;
//assign lcl_wr_en = (prev_wr0 != wrptr[0]);
always @(posedge clk)
begin
if (reset)
begin
/-*AUTORESET*-/
// Beginning of autoreset for uninitialized flops
usage2 <= {(1+(asz)){1'b0}};
// End of automatics
end
else
begin
usage2 <= #1 nxt_usage2;
end
end
always @*
begin
if (mem_re & !mem_we)
nxt_usage2 = usage2 - 1;
else if (!mem_re & mem_we)
nxt_usage2 = usage2 + 1;
else
nxt_usage2 = usage2;
end
-----/\----- EXCLUDED -----/\----- */
 
always @(posedge clk)
begin
if (reset)
cur_rdptr <= `SDLIB_DELAY bound_low;
else
cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
/buffers/sd_fifo_b.v
25,7 → 25,8
parameter depth=256,
parameter rd_commit=0,
parameter wr_commit=0,
parameter asz=$clog2(depth)
parameter asz=$clog2(depth),
parameter usz=$clog2(depth+1)
)
(
input clk,
43,8 → 44,8
input p_abort,
output [width-1:0] p_data,
 
output [asz:0] p_usage,
output [asz:0] c_usage
output [usz-1:0] p_usage,
output [usz-1:0] c_usage
);
 
wire [asz-1:0] com_rdptr; // From tail of sd_fifo_tail_b.v
54,7 → 55,6
wire [width-1:0] mem_rd_data;
wire mem_re; // From tail of sd_fifo_tail_b.v
wire mem_we; // From head of sd_fifo_head_b.v
wire [asz:0] usage; // From tail of sd_fifo_tail_b.v
wire [asz-1:0] bound_high;
 
assign bound_high = depth-1;

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