URL
https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk
Subversion Repositories srdydrdy_lib
Compare Revisions
- This comparison shows the changes necessary to convert path
/srdydrdy_lib/trunk/rtl
- from Rev 14 to Rev 16
- ↔ Reverse comparison
Rev 14 → Rev 16
/verilog/buffers/sd_fifo_head_b.v
29,7 → 29,8
module sd_fifo_head_b |
#(parameter depth=16, |
parameter commit=0, |
parameter asz=$clog2(depth) |
parameter asz=$clog2(depth), |
parameter usz=$clog2(depth+1) |
) |
( |
input clk, |
46,6 → 47,7
input [asz-1:0] rdptr, |
output reg [asz-1:0] cur_wrptr, |
output reg [asz-1:0] com_wrptr, |
output reg [usz-1:0] c_usage, |
output reg mem_we |
); |
|
54,7 → 56,11
reg empty; |
reg full, nxt_full; |
reg [asz-1:0] nxt_com_wrptr; |
reg [usz:0] tmp_usage; |
wire [usz-1:0] fifo_size; |
|
assign fifo_size = bound_high - bound_low + 1; |
|
assign c_drdy = !nxt_full & enable; |
|
always @* |
93,6 → 99,12
nxt_wrptr = cur_wrptr; |
mem_we = 0; |
end |
|
tmp_usage = cur_wrptr[asz-1:0] - rdptr[asz-1:0]; |
if (~tmp_usage[usz]) |
c_usage = tmp_usage[usz-1:0]; |
else |
c_usage = fifo_size - (rdptr[asz-1:0] - cur_wrptr[asz-1:0]); |
end |
|
always @(posedge clk) |
/verilog/buffers/sd_fifo_tail_b.v
40,7 → 40,9
#(parameter width=8, |
parameter depth=16, |
parameter commit=0, |
parameter asz=$clog2(depth)) |
parameter asz=$clog2(depth), |
parameter usz=$clog2(depth+1) |
) |
( |
input clk, |
input reset, |
55,7 → 57,7
output reg mem_re, |
input mem_we, |
|
output reg [asz:0] usage, |
output reg [usz:0] p_usage, |
|
output p_srdy, |
input p_drdy, |
74,8 → 76,8
reg [width-1:0] hold_a, hold_b; |
reg valid_a, valid_b; |
reg prev_re; |
reg [asz:0] tmp_usage; |
reg [asz:0] fifo_size; |
reg [usz:0] tmp_usage; |
reg [usz:0] fifo_size; |
wire rbuf1_drdy; |
wire ip_srdy, ip_drdy; |
wire [width-1:0] ip_data; |
118,10 → 120,10
|
fifo_size = (bound_high - bound_low + 1); |
tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0]; |
if (~tmp_usage[asz]) |
usage = tmp_usage[asz-1:0]; |
if (~tmp_usage[usz]) |
p_usage = tmp_usage[usz-1:0]; |
else |
usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]); |
p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]); |
end // always @ * |
|
/* -----\/----- EXCLUDED -----\/----- |
/verilog/buffers/sd_fifo_b.v
43,7 → 43,8
input p_abort, |
output [width-1:0] p_data, |
|
output [asz:0] usage |
output [asz:0] p_usage, |
output [asz:0] c_usage |
); |
|
wire [asz-1:0] com_rdptr; // From tail of sd_fifo_tail_b.v |
65,6 → 66,7
.cur_wrptr (cur_wrptr[asz-1:0]), |
.com_wrptr (com_wrptr[asz-1:0]), |
.mem_we (mem_we), |
.c_usage (c_usage), |
// Inputs |
.clk (clk), |
.reset (reset), |
95,7 → 97,7
.cur_rdptr (cur_rdptr[asz-1:0]), |
.com_rdptr (com_rdptr[asz-1:0]), |
.mem_re (mem_re), |
.usage (usage[asz:0]), |
.p_usage (p_usage[asz:0]), |
.p_srdy (p_srdy), |
.p_data (p_data[width-1:0]), |
// Inputs |