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URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

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  • This comparison shows the changes necessary to convert path 
    /srdydrdy_lib/trunk/rtl
    from Rev 22 to Rev 24
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Rev 22 → Rev 24

/verilog/utility/sd_scoreboard_fsm.v
32,7 → 32,7
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
parameter asz=6) //log2(items))
(input clk,
input reset,
 
/verilog/utility/sd_scoreboard.v
19,7 → 19,7
parameter use_txid=0,
parameter use_mask=0,
parameter txid_sz=2,
parameter asz=$clog2(items))
parameter asz=6) //log2(items))
(input clk,
input reset,
 
37,7 → 37,8
output [width-1:0] p_data
);
 
localparam tot_in_sz = width*2+txid_sz+asz+1;
localparam tot_in_sz = ((use_mask)?width*2:width)+
((use_txid)?txid_sz:0)+asz+1;
wire ip_req_type; // 0=read, 1=write
wire [txid_sz-1:0] ip_txid;
49,9 → 50,9
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [asz-1:0] addr; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_in; // From fsm of sd_scoreboard_fsm.v
wire [width-1:0] d_out; // From sb_mem of behave1p_mem.v
wire [(asz)-1:0] addr; // From fsm of sd_scoreboard_fsm.v
wire [(width)-1:0] d_in; // From fsm of sd_scoreboard_fsm.v
wire [(width)-1:0] d_out; // From sb_mem of behave1p_mem.v
wire ic_drdy; // From outhold of sd_output.v
wire ic_srdy; // From fsm of sd_scoreboard_fsm.v
wire ip_drdy; // From fsm of sd_scoreboard_fsm.v
60,10 → 61,38
wire wr_en; // From fsm of sd_scoreboard_fsm.v
// End of automatics
 
wire [tot_in_sz-1:0] c_hold_data, p_hold_data;
generate if ((use_txid == 1) && (use_mask == 1))
begin : txid_and_mask
assign c_hold_data = {c_txid,c_req_type,c_itemid,c_mask,c_data};
assign {ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data} = p_hold_data;
end
else if ((use_txid == 0) && (use_mask == 1))
begin : no_txid_and_mask
assign c_hold_data = {c_req_type,c_itemid,c_mask,c_data};
assign {ip_req_type,ip_itemid,ip_mask,ip_data} = p_hold_data;
assign ip_mask = 0;
end
else if ((use_txid == 1) && (use_mask == 0))
begin : txid_and_no_mask
assign c_hold_data = {c_txid,c_req_type,c_itemid,c_data};
assign {ip_txid,ip_req_type,ip_itemid,ip_data} = p_hold_data;
assign ip_txid = 0;
end
else if ((use_txid == 0) && (use_mask == 0))
begin : no_txid_no_mask
assign c_hold_data = {c_req_type,c_itemid,c_data};
assign {ip_req_type,ip_itemid,ip_data} = p_hold_data;
assign ip_mask = 0;
assign ip_txid = 0;
end
endgenerate
sd_input #(.width(tot_in_sz)) inhold
(
.c_data ({c_txid,c_req_type,c_itemid,c_mask,c_data}),
.ip_data ({ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data}),
.c_data (c_hold_data),
.ip_data (p_hold_data),
/*AUTOINST*/
// Outputs
.c_drdy (c_drdy),
74,40 → 103,50
.c_srdy (c_srdy),
.ip_drdy (ip_drdy));
 
behave1p_mem #(.depth(items), .width(width)) sb_mem
behave1p_mem #(.depth(items),
.addr_sz (asz), /*AUTOINSTPARAM*/
// Parameters
.width (width)) sb_mem
(
.addr (addr[asz-1:0]),
/*AUTOINST*/
// Outputs
.d_out (d_out[width-1:0]),
.d_out (d_out[(width)-1:0]),
// Inputs
.wr_en (wr_en),
.rd_en (rd_en),
.clk (clk),
.d_in (d_in[width-1:0]));
.d_in (d_in[(width)-1:0]));
 
sd_scoreboard_fsm #(width,items,use_txid,use_mask,txid_sz) fsm
sd_scoreboard_fsm #(/*AUTOINSTPARAM*/
// Parameters
.width (width),
.items (items),
.use_txid (use_txid),
.use_mask (use_mask),
.txid_sz (txid_sz),
.asz (asz)) fsm
(/*AUTOINST*/
// Outputs
.ip_drdy (ip_drdy),
.ic_srdy (ic_srdy),
.ic_txid (ic_txid[txid_sz-1:0]),
.ic_data (ic_data[width-1:0]),
.ic_txid (ic_txid[(txid_sz)-1:0]),
.ic_data (ic_data[(width)-1:0]),
.wr_en (wr_en),
.rd_en (rd_en),
.d_in (d_in[width-1:0]),
.addr (addr[asz-1:0]),
.d_in (d_in[(width)-1:0]),
.addr (addr[(asz)-1:0]),
// Inputs
.clk (clk),
.reset (reset),
.ip_srdy (ip_srdy),
.ip_req_type (ip_req_type),
.ip_txid (ip_txid[txid_sz-1:0]),
.ip_mask (ip_mask[width-1:0]),
.ip_data (ip_data[width-1:0]),
.ip_itemid (ip_itemid[asz-1:0]),
.ip_txid (ip_txid[(txid_sz)-1:0]),
.ip_mask (ip_mask[(width)-1:0]),
.ip_data (ip_data[(width)-1:0]),
.ip_itemid (ip_itemid[(asz)-1:0]),
.ic_drdy (ic_drdy),
.d_out (d_out[width-1:0]));
.d_out (d_out[(width)-1:0]));
 
sd_output #(.width(width+txid_sz)) outhold
(
128,4 → 167,4
// verilog-library-directories:("." "../closure" "../memory")
// End:
 
/verilog/forks/sd_rrmux.v
14,9 → 14,9
// When input deasserts, device will begin to hunt for a
// new input with data.
// Mode 2 : Continue to accept input until the incoming data
// matches a particular "end pattern". The trigger pattern
// is when (c_data & eod_mask) == eod_pattern. Once
// trigger pattern is seen, begin hunting for new input.
// matches a particular "end pattern". The end pattern
// is provided on the c_rearb (re-arbitrate) input. When
// c_rearb is high, will hunt for new inputs on next clock.
//
// This component also supports two arbitration modes: slow and fast.
// slow rotates the grant from requestor to requestor cycle by cycle,
51,8 → 51,6
#(parameter width=8,
parameter inputs=2,
parameter mode=0,
parameter eod_pattern=0,
parameter eod_mask=0,
parameter fast_arb=0)
(
input clk,
61,6 → 59,7
input [(width*inputs)-1:0] c_data,
input [inputs-1:0] c_srdy,
output [inputs-1:0] c_drdy,
input c_rearb, // for use with mode 2 only
 
output reg [width-1:0] p_data,
output [inputs-1:0] p_grant,
77,7 → 76,6
reg rr_locked;
genvar i;
integer j;
wire trig_pattern;
 
assign c_drdy = rr_state & {inputs{p_drdy}};
assign p_grant = rr_state;
108,7 → 106,6
begin : tp_gen
reg nxt_rr_locked;
assign trig_pattern = (rr_mux_grid[data_ind] & eod_mask) == eod_pattern;
always @*
begin
data_ind = 0;
120,7 → 117,7
 
if ((c_srdy & rr_state) & (!rr_locked))
nxt_rr_locked = 1;
else if ((c_srdy & rr_state) & p_drdy & trig_pattern )
else if ((c_srdy & rr_state & c_rearb) & p_drdy )
nxt_rr_locked = 0;
end
 
132,10 → 129,6
rr_locked <= `SDLIB_DELAY nxt_rr_locked;
end
end // block: tp_gen
else
begin : ntp_gen
assign trig_pattern = 1'b0;
end
endgenerate
 
always @*

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