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Rev 30 → Rev 31
/trunk/examples/bridge/rtl/allocator.v
0,0 → 1,272
`timescale 1ns/100ps |
|
module allocator |
( |
input clk, //% System clock |
input reset, //% Active high reset |
|
input crx_abort, //% asserted at end of packet, indicates packet drop |
input crx_commit, //% asserted at end of packet, indicates packet accept |
input [`PFW_SZ-1:0] crx_data, //% Incoming data from accumulator |
output crx_drdy, //% destination flow control |
input crx_srdy, //% source data available |
|
// page request i/f |
output par_srdy, |
input par_drdy, |
|
input parr_srdy, |
output parr_drdy, |
input [`LL_PG_ASZ-1:0] parr_page, |
|
// link to next page i/f |
output reg lnp_srdy, |
input lnp_drdy, |
output reg [`LL_LNP_SZ-1:0] lnp_pnp, |
|
// interface to packet buffer |
output [`PBR_SZ-1:0] pbra_data, |
output pbra_srdy, |
input pbra_drdy, |
|
output [`LL_PG_ASZ-1:0] a2f_start, |
output [`LL_PG_ASZ-1:0] a2f_end, |
output reg a2f_srdy, |
input a2f_drdy |
); |
|
wire icrx_srdy; |
|
reg icrx_drdy; |
wire icrx_commit, icrx_abort; |
wire [`PFW_SZ-1:0] icrx_data; |
|
reg [2:0] pcount; |
reg [1:0] word_count; |
reg [`LL_PG_ASZ-1:0] start_pg; |
reg [`LL_PG_ASZ-1:0] cur_pg; |
reg [`LL_PG_ASZ-1:0] nxt_start_pg; |
reg [`LL_PG_ASZ-1:0] nxt_cur_pg; |
|
reg obuf_srdy; |
wire [`PB_ASZ-1:0] obuf_addr; |
reg [1:0] cur_line, nxt_cur_line; |
wire obuf_drdy; |
|
wire [`PBR_SZ-1:0] obuf_pbr_word; |
|
wire pp_srdy; |
reg pp_drdy; |
wire [`LL_PG_ASZ-1:0] pp_page; |
|
assign obuf_addr = { cur_pg, cur_line }; |
|
//------------------------------------------------------------ |
// icarus debug |
|
/* -----\/----- EXCLUDED -----\/----- |
tape_record #(9+`PFW_SZ+`LL_PG_ASZ) record0 |
(.clk (clk), |
.data ({ reset, |
crx_abort, |
crx_commit, |
crx_srdy, |
par_drdy, |
parr_srdy, |
lnp_drdy, |
pbra_drdy, |
a2f_drdy, crx_data, parr_page })); |
-----/\----- EXCLUDED -----/\----- */ |
|
//------------------------------------------------------------ |
// page prefetch FIFO and state machine logic |
//------------------------------------------------------------ |
|
wire pcount_inc = par_srdy & par_drdy; |
wire pcount_dec = pp_srdy & pp_drdy; |
assign par_srdy = (pcount < 4); |
|
always @(posedge clk) |
begin |
if (reset) |
pcount <= 0; |
else |
begin |
if (pcount_inc & !pcount_dec) |
pcount <= pcount + 1; |
else if (pcount_dec & !pcount_inc) |
pcount <= pcount - 1; |
end |
end |
|
sd_fifo_s #(.width(`LL_PG_ASZ), .depth(4)) page_prefetch |
( |
.c_clk (clk), |
.c_reset (reset), |
.p_clk (clk), |
.p_reset (reset), |
|
.c_srdy (parr_srdy), |
.c_drdy (parr_drdy), |
.c_data (parr_page), |
|
.p_srdy (pp_srdy), |
.p_drdy (pp_drdy), |
.p_data (pp_page)); |
|
always @(posedge clk) |
begin |
if (pp_srdy & pp_drdy) |
$display ("%t %m: Storing in page %0d", $time, pp_page); |
if (crx_srdy & crx_drdy & crx_commit) |
$display ("%t %m: Sent packet (%0d,%0d)", $time, start_pg, cur_pg); |
end |
|
sd_iohalf #(.width(`PFW_SZ+2)) crx_buf |
(.clk (clk), .reset (reset), |
|
.c_srdy (crx_srdy), |
.c_drdy (crx_drdy), |
.c_data ({crx_commit,crx_abort,crx_data}), |
|
.p_srdy (icrx_srdy), |
.p_drdy (icrx_drdy), |
.p_data ({icrx_commit,icrx_abort,icrx_data})); |
|
//------------------------------------------------------------ |
// |
//------------------------------------------------------------ |
|
assign a2f_start = start_pg; |
assign a2f_end = cur_pg; |
|
reg [2:0] state, nxt_state; |
localparam s_idle = 0, s_noalloc = 1, s_link = 2, s_commit = 3, |
s_abort = 4, s_commit2 = 5; |
|
always @* |
begin |
icrx_drdy = 0; |
obuf_srdy = 0; |
lnp_srdy = 0; |
nxt_start_pg = start_pg; |
nxt_cur_pg = cur_pg; |
nxt_cur_line = cur_line; |
lnp_pnp = { cur_pg, 1'b0, pp_page }; |
a2f_srdy = 0; |
pp_drdy = 0; |
|
case (state) |
s_idle : |
begin |
// if output buffer is ready and a page is allocated, |
// preload the address counters to get ready for a packet |
if (pp_srdy) |
begin |
nxt_start_pg = pp_page; |
nxt_cur_pg = pp_page; |
nxt_cur_line = 0; |
nxt_state = s_noalloc; |
pp_drdy = 1; |
end |
end // case: s_idle |
|
s_noalloc : |
begin |
if (icrx_srdy & obuf_drdy) |
begin |
icrx_drdy = 1; |
obuf_srdy = 1; |
nxt_cur_line = cur_line + 1; |
if (`ANY_EOP(icrx_data[`PRW_PCC])) |
begin |
if (icrx_commit) |
nxt_state = s_commit; |
else |
nxt_state = s_abort; |
end |
else if (cur_line == 3) |
begin |
nxt_state = s_link; |
end |
end // if (icrx_srdy & obuf_drdy) |
end // case: s_noalloc |
|
|
s_link : |
begin |
if (pp_srdy) |
begin |
lnp_srdy = 1; |
if (lnp_drdy) |
begin |
nxt_cur_pg = pp_page; |
pp_drdy = 1; |
nxt_state = s_noalloc; |
end |
end |
end // case: s_link |
|
s_commit : |
begin |
lnp_pnp = { cur_pg, `LL_ENDPAGE }; |
lnp_srdy = 1; |
if (lnp_drdy) |
nxt_state = s_commit2; |
end |
|
s_commit2 : |
begin |
a2f_srdy = 1; |
if (a2f_drdy) |
nxt_state = s_idle; |
end |
|
s_abort : |
begin |
// need to reclaim pages here |
end |
|
default : nxt_state = s_idle; |
endcase // case (state) |
end |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
state <= s_idle; |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
cur_line <= 2'h0; |
cur_pg <= {(1+(`LL_PG_ASZ-1)){1'b0}}; |
start_pg <= {(1+(`LL_PG_ASZ-1)){1'b0}}; |
// End of automatics |
end |
else |
begin |
start_pg <= nxt_start_pg; |
cur_pg <= nxt_cur_pg; |
cur_line <= nxt_cur_line; |
state <= nxt_state; |
end |
end |
|
assign obuf_pbr_word[`PBR_DATA] = icrx_data; |
assign obuf_pbr_word[`PBR_ADDR] = obuf_addr; |
assign obuf_pbr_word[`PBR_WRITE] = 1'b1; |
assign obuf_pbr_word[`PBR_PORT] = 0; |
|
sd_iohalf #(.width(`PBR_SZ)) obuf |
(.clk (clk), .reset (reset), |
|
.c_srdy (obuf_srdy), |
.c_drdy (obuf_drdy), |
.c_data (obuf_pbr_word), |
|
.p_srdy (pbra_srdy), |
.p_drdy (pbra_drdy), |
.p_data (pbra_data)); |
|
endmodule // allocator |
|
/trunk/examples/bridge/rtl/sd_rx_gigmac.v
20,7 → 20,9
output rxg_srdy, |
input rxg_drdy, |
output [1:0] rxg_code, |
output [7:0] rxg_data |
output [7:0] rxg_data, |
|
input cfg_check_crc |
); |
|
reg rxdv1, rxdv2; |
155,7 → 157,7
begin |
ic_srdy =1; |
ic_data = pkt_crc[31:24]; |
if (pkt_crc == crc) |
if ((pkt_crc == crc) | !cfg_check_crc) |
begin |
ic_code = `PCC_EOP; |
end |
/trunk/examples/bridge/rtl/deallocator.v
0,0 → 1,201
module deallocator |
( |
input clk, |
input reset, |
|
input [1:0] port_num, |
|
// packet input from FIB |
input f2d_srdy, |
output reg f2d_drdy, |
input [`LL_PG_ASZ-1:0] f2d_data, |
|
// read link page i/f |
output reg rlp_srdy, |
input rlp_drdy, |
output [`LL_PG_ASZ-1:0] rlp_rd_page, |
|
// read link page reply i/f |
input rlpr_srdy, |
output reg rlpr_drdy, |
input [`LL_PG_ASZ:0] rlpr_data, |
|
// page dereference interface |
output reg drf_srdy, |
input drf_drdy, |
output [`LL_PG_ASZ*2-1:0] drf_page_list, |
|
// interface to packet buffer |
output [`PBR_SZ-1:0] pbrd_data, |
output reg pbrd_srdy, |
input pbrd_drdy, |
|
// return interface from packet buffer |
input pbrr_srdy, |
output pbrr_drdy, |
input [`PFW_SZ-1:0] pbrr_data, |
|
// i/f to distributor |
output ptx_srdy, |
input ptx_drdy, |
output [`PFW_SZ-1:0] ptx_data |
|
); |
|
reg [2:0] state, nxt_state; |
reg [`LL_PG_ASZ-1:0] start, nxt_start; |
reg [`LL_PG_ASZ-1:0] cur, nxt_cur; |
reg [1:0] lcount, nxt_lcount; |
|
reg pb_req, eop_seen, nxt_eop_seen; |
|
assign rlp_rd_page = cur; |
assign drf_page_list = { start, cur }; |
|
assign pbrd_data[`PBR_DATA] = 0; |
assign pbrd_data[`PBR_ADDR] = { cur, lcount }; |
assign pbrd_data[`PBR_WRITE] = 1'b0; |
assign pbrd_data[`PBR_PORT] = port_num; |
|
sd_iohalf #(.width(`PFW_SZ)) pkt_rd_buf |
(.clk (clk), .reset (reset), |
|
.c_srdy (pbrr_srdy), |
.c_drdy (pbrr_drdy), |
.c_data (pbrr_data), |
|
.p_srdy (ptx_srdy), |
.p_drdy (ptx_drdy), |
.p_data (ptx_data)); |
|
always @(posedge clk) |
begin |
if (reset) |
pb_req <= 0; |
else |
begin |
if (ptx_srdy & ptx_drdy) |
pb_req <= 0; |
else if (pbrd_srdy & pbrd_drdy) |
pb_req <= 1; |
end |
end // always @ (posedge clk) |
|
localparam s_idle = 0, s_fetch = 1, s_link = 2, s_link_reply = 3, |
s_return = 4; |
|
always @(posedge clk) |
begin |
if (f2d_srdy & f2d_drdy) |
$display ("%t %m: Dealloc packet %0d", $time, f2d_data); |
if (drf_srdy & drf_drdy) |
$display ("%t %m: Returning packet (%0d,%0d)", $time, start, cur); |
end |
|
always @* |
begin |
f2d_drdy = 0; |
nxt_state = state; |
nxt_start = start; |
nxt_cur = cur; |
nxt_lcount = lcount; |
nxt_eop_seen = eop_seen; |
rlp_srdy = 0; |
rlpr_drdy = 0; |
drf_srdy = 0; |
pbrd_srdy = 0; |
|
case (state) |
s_idle : |
begin |
f2d_drdy = 1; |
if (f2d_srdy) |
begin |
nxt_start = f2d_data; |
nxt_cur = f2d_data; |
nxt_state = s_fetch; |
nxt_eop_seen = 0; |
nxt_lcount = 0; |
end |
end |
|
// if no requests to the packet buffer are outstanding, |
// then dispatch another request to the packet buffer. |
// If this was the last request of a page then go to |
// link page fetch state. |
s_fetch : |
begin |
if (ptx_srdy & (`ANY_EOP(ptx_data[`PRW_PCC]))) |
nxt_eop_seen = 1; |
|
if (!pb_req & !eop_seen) |
begin |
pbrd_srdy = 1; |
if (pbrd_drdy) |
begin |
nxt_lcount = lcount + 1; |
if (lcount == 3) |
nxt_state = s_link; |
end |
end |
else if (eop_seen) |
nxt_state = s_link; |
end // case: s_fetch |
|
s_link : |
begin |
rlp_srdy = 1; |
if (rlp_drdy) |
nxt_state = s_link_reply; |
end |
|
s_link_reply : |
begin |
rlpr_drdy = 1; |
if (rlpr_srdy) |
begin |
if (rlpr_data == `LL_ENDPAGE) |
nxt_state = s_return; |
else |
begin |
nxt_cur = rlpr_data; |
nxt_state = s_fetch; |
end |
end |
end // case: s_link_reply |
|
s_return : |
begin |
drf_srdy = 1; |
if (drf_drdy) |
nxt_state = s_idle; |
end |
|
default : nxt_state = s_idle; |
endcase // case (state) |
end // always @ * |
|
always @(posedge clk) |
begin |
if (reset) |
begin |
state <= s_idle; |
/*AUTORESET*/ |
// Beginning of autoreset for uninitialized flops |
cur <= {(1+(`LL_PG_ASZ-1)){1'b0}}; |
eop_seen <= 1'h0; |
lcount <= 2'h0; |
start <= {(1+(`LL_PG_ASZ-1)){1'b0}}; |
// End of automatics |
end |
else |
begin |
state <= nxt_state; |
start <= nxt_start; |
cur <= nxt_cur; |
lcount <= nxt_lcount; |
eop_seen <= nxt_eop_seen; |
end |
end |
|
endmodule // deallocator |
/trunk/examples/bridge/rtl/fib_lookup.v
4,29 → 4,33
module fib_lookup |
(/*AUTOARG*/ |
// Outputs |
ppi_drdy, flo_data, flo_srdy, |
refup_srdy, refup_page, refup_count, ppi_drdy, flo_data, flo_srdy, |
// Inputs |
ppi_srdy, clk, reset, ppi_data, flo_drdy |
refup_drdy, ppi_srdy, clk, reset, ppi_data, flo_drdy |
); |
|
input clk; |
input reset; |
|
input [`PAR_DATA_SZ-1:0] ppi_data; |
output [`NUM_PORTS-1:0] flo_data; |
input [`PM2F_SZ-1:0] ppi_data; |
output [`LL_PG_ASZ-1:0] flo_data; |
output [`NUM_PORTS-1:0] flo_srdy; |
input [`NUM_PORTS-1:0] flo_drdy; |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input ppi_srdy; // To port_parse_in of sd_input.v |
input refup_drdy; // To fsm0 of fib_lookup_fsm.v |
// End of automatics |
/*AUTOOUTPUT*/ |
// Beginning of automatic outputs (from unused autoinst outputs) |
output ppi_drdy; // From port_parse_in of sd_input.v |
output [`LL_REFSZ-1:0] refup_count; // From fsm0 of fib_lookup_fsm.v |
output [`LL_PG_ASZ-1:0] refup_page; // From fsm0 of fib_lookup_fsm.v |
output refup_srdy; // From fsm0 of fib_lookup_fsm.v |
// End of automatics |
|
wire [`FIB_ENTRY_SZ-1:0] ft_rdata; |
wire [`PAR_DATA_SZ-1:0] lpp_data; |
wire [`PM2F_SZ-1:0] lpp_data; |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [`FIB_ASZ-1:0] ft_addr; // From fsm0 of fib_lookup_fsm.v |
33,10 → 37,10
wire ft_rd_en; // From fsm0 of fib_lookup_fsm.v |
wire [`FIB_ENTRY_SZ-1:0] ft_wdata; // From fsm0 of fib_lookup_fsm.v |
wire ft_wr_en; // From fsm0 of fib_lookup_fsm.v |
wire [`NUM_PORTS-1:0] lout_data; // From fsm0 of fib_lookup_fsm.v |
wire lout_drdy; // From fib_res_out of sd_mirror.v |
wire [`NUM_PORTS-1:0] lout_dst_vld; // From fsm0 of fib_lookup_fsm.v |
wire lout_srdy; // From fsm0 of fib_lookup_fsm.v |
wire [`LL_PG_ASZ-1:0] lout_start; // From fsm0 of fib_lookup_fsm.v |
wire lpp_drdy; // From fsm0 of fib_lookup_fsm.v |
wire lpp_srdy; // From port_parse_in of sd_input.v |
// End of automatics |
47,7 → 51,7
.ip_\(.*\) (lpp_\1), |
); |
*/ |
sd_input #(`PAR_DATA_SZ) port_parse_in |
sd_input #(`PM2F_SZ) port_parse_in |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ppi_drdy), // Templated |
87,24 → 91,31
.ft_rd_en (ft_rd_en), |
.ft_wr_en (ft_wr_en), |
.ft_addr (ft_addr[`FIB_ASZ-1:0]), |
.lout_data (lout_data[`NUM_PORTS-1:0]), |
.lout_start (lout_start[`LL_PG_ASZ-1:0]), |
.lout_srdy (lout_srdy), |
.lout_dst_vld (lout_dst_vld[`NUM_PORTS-1:0]), |
.refup_srdy (refup_srdy), |
.refup_page (refup_page[`LL_PG_ASZ-1:0]), |
.refup_count (refup_count[`LL_REFSZ-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.lpp_data (lpp_data[`PAR_DATA_SZ-1:0]), |
.lpp_data (lpp_data[`PM2F_SZ-1:0]), |
.lpp_srdy (lpp_srdy), |
.ft_rdata (ft_rdata[`FIB_ENTRY_SZ-1:0]), |
.lout_drdy (lout_drdy)); |
.lout_drdy (lout_drdy), |
.refup_drdy (refup_drdy)); |
|
/* sd_mirror AUTO_TEMPLATE |
( |
.c_data (lout_start[`LL_PG_ASZ-1:0]), |
.c_\(.*\) (lout_\1), |
.p_\(.*\) (flo_\1), |
) |
*/ |
sd_mirror #(`NUM_PORTS, `NUM_PORTS) fib_res_out |
sd_mirror #(// Parameters |
.mirror (`NUM_PORTS), |
.width (`LL_PG_ASZ)) fib_res_out |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (lout_drdy), // Templated |
114,7 → 125,7
.clk (clk), |
.reset (reset), |
.c_srdy (lout_srdy), // Templated |
.c_data (lout_data), // Templated |
.c_data (lout_start[`LL_PG_ASZ-1:0]), // Templated |
.c_dst_vld (lout_dst_vld), // Templated |
.p_drdy (flo_drdy)); // Templated |
|
/trunk/examples/bridge/rtl/control_pipe.v
0,0 → 1,310
module control_pipe |
( |
input [`PM2F_SZ-1:0] pm2f_data_0, // To fib_arb of sd_rrmux.v |
input [`PM2F_SZ-1:0] pm2f_data_1, // To fib_arb of sd_rrmux.v |
input [`PM2F_SZ-1:0] pm2f_data_2, // To fib_arb of sd_rrmux.v |
input [`PM2F_SZ-1:0] pm2f_data_3, // To fib_arb of sd_rrmux.v |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input clk, // To fib_arb of sd_rrmux.v, ... |
input [`NUM_PORTS*`LL_PG_ASZ*2-1:0] drf_page_list,// To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] drf_srdy, // To lm of llmanager.v |
input [3:0] f2d_drdy, // To cq0 of sd_fifo_s.v, ... |
input [`LL_LNP_SZ*4-1:0] lnp_pnp, // To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] lnp_srdy, // To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] par_srdy, // To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] parr_drdy, // To lm of llmanager.v |
input [`NUM_PORTS-1:0] pm2f_srdy, // To fib_arb of sd_rrmux.v |
input reset, // To fib_arb of sd_rrmux.v, ... |
input [(`NUM_PORTS)*(`LL_PG_ASZ)-1:0] rlp_rd_page,// To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] rlp_srdy, // To lm of llmanager.v |
input [(`NUM_PORTS)-1:0] rlpr_drdy, // To lm of llmanager.v |
// End of automatics |
/*AUTOOUTPUT*/ |
// Beginning of automatic outputs (from unused autoinst outputs) |
output [(`NUM_PORTS)-1:0] drf_drdy, // From lm of llmanager.v |
output [`LL_PG_ASZ-1:0] f2d_data_0, // From cq0 of sd_fifo_s.v |
output [`LL_PG_ASZ-1:0] f2d_data_1, // From cq1 of sd_fifo_s.v |
output [`LL_PG_ASZ-1:0] f2d_data_2, // From cq2 of sd_fifo_s.v |
output [`LL_PG_ASZ-1:0] f2d_data_3, // From cq3 of sd_fifo_s.v |
output [3:0] f2d_srdy, // From cq0 of sd_fifo_s.v, ... |
output [(`NUM_PORTS)-1:0] lnp_drdy, // From lm of llmanager.v |
output [(`NUM_PORTS)-1:0] par_drdy, // From lm of llmanager.v |
output [(`LL_PG_ASZ)-1:0] parr_page, // From lm of llmanager.v |
output [(`NUM_PORTS)-1:0] parr_srdy, // From lm of llmanager.v |
output [`NUM_PORTS-1:0] pm2f_drdy, // From fib_arb of sd_rrmux.v |
output [(`NUM_PORTS)-1:0] rlp_drdy, // From lm of llmanager.v |
output [(`LL_PG_ASZ+1)-1:0] rlpr_data, // From lm of llmanager.v |
output [(`NUM_PORTS)-1:0] rlpr_srdy // From lm of llmanager.v |
// End of automatics |
); |
|
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [`LL_PG_ASZ-1:0] flo_data; // From fib_lookup of fib_lookup.v |
wire [3:0] flo_drdy; // From cq0 of sd_fifo_s.v, ... |
wire [`NUM_PORTS-1:0] flo_srdy; // From fib_lookup of fib_lookup.v |
wire [(`LL_PG_ASZ)-1:0] pgmem_rd_addr; // From lm of llmanager.v |
wire [(`LL_PG_ASZ+1)-1:0] pgmem_rd_data; // From pglist_mem of behave2p_mem.v |
wire pgmem_rd_en; // From lm of llmanager.v |
wire [(`LL_PG_ASZ)-1:0] pgmem_wr_addr; // From lm of llmanager.v |
wire [(`LL_PG_ASZ+1)-1:0] pgmem_wr_data; // From lm of llmanager.v |
wire pgmem_wr_en; // From lm of llmanager.v |
wire [`PM2F_SZ-1:0] ppi_data; // From fib_arb of sd_rrmux.v |
wire ppi_drdy; // From fib_lookup of fib_lookup.v |
wire ppi_srdy; // From fib_arb of sd_rrmux.v |
wire [(`LL_PG_ASZ)-1:0] ref_rd_addr; // From lm of llmanager.v |
wire [(`LL_REFSZ)-1:0] ref_rd_data; // From ref_mem of behave2p_mem.v |
wire ref_rd_en; // From lm of llmanager.v |
wire [(`LL_PG_ASZ)-1:0] ref_wr_addr; // From lm of llmanager.v |
wire [(`LL_REFSZ)-1:0] ref_wr_data; // From lm of llmanager.v |
wire ref_wr_en; // From lm of llmanager.v |
wire [`LL_REFSZ-1:0] refup_count; // From fib_lookup of fib_lookup.v |
wire refup_drdy; // From lm of llmanager.v |
wire [`LL_PG_ASZ-1:0] refup_page; // From fib_lookup of fib_lookup.v |
wire refup_srdy; // From fib_lookup of fib_lookup.v |
// End of automatics |
|
/* sd_rrmux AUTO_TEMPLATE |
( |
.p_grant (), |
.p_data (ppi_data[`PM2F_SZ-1:0]), |
.c_data ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}), |
.c_srdy (pm2f_srdy[`NUM_PORTS-1:0]), |
.c_drdy (pm2f_drdy[`NUM_PORTS-1:0]), |
.c_rearb (1'b1), |
.c_\(.*\) (pm2f_\1[]), |
.p_\(.*\) (ppi_\1[]), |
); |
*/ |
sd_rrmux #( |
// Parameters |
.width (`PM2F_SZ), |
.inputs (`NUM_PORTS), |
.mode (0), |
.fast_arb (1)) fib_arb |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (pm2f_drdy[`NUM_PORTS-1:0]), // Templated |
.p_data (ppi_data[`PM2F_SZ-1:0]), // Templated |
.p_grant (), // Templated |
.p_srdy (ppi_srdy), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_data ({pm2f_data_3,pm2f_data_2,pm2f_data_1,pm2f_data_0}), // Templated |
.c_srdy (pm2f_srdy[`NUM_PORTS-1:0]), // Templated |
.c_rearb (1'b1), // Templated |
.p_drdy (ppi_drdy)); // Templated |
|
fib_lookup fib_lookup |
(/*AUTOINST*/ |
// Outputs |
.flo_data (flo_data[`LL_PG_ASZ-1:0]), |
.flo_srdy (flo_srdy[`NUM_PORTS-1:0]), |
.ppi_drdy (ppi_drdy), |
.refup_count (refup_count[`LL_REFSZ-1:0]), |
.refup_page (refup_page[`LL_PG_ASZ-1:0]), |
.refup_srdy (refup_srdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.ppi_data (ppi_data[`PM2F_SZ-1:0]), |
.flo_drdy (flo_drdy[`NUM_PORTS-1:0]), |
.ppi_srdy (ppi_srdy), |
.refup_drdy (refup_drdy)); |
|
/* llmanager AUTO_TEMPLATE |
( |
.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]), |
.drf_page_list (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]), |
.free_count (), |
); |
*/ |
llmanager #( |
// Parameters |
.lpsz (`LL_PG_ASZ), |
.lpdsz (`LL_PG_ASZ+1), |
.pages (`LL_PAGES), |
.sources (`NUM_PORTS), |
.maxref (`LL_MAX_REF), |
.refsz (`LL_REFSZ), |
.sinks (`NUM_PORTS), |
.sksz (2)) lm |
(/*AUTOINST*/ |
// Outputs |
.par_drdy (par_drdy[(`NUM_PORTS)-1:0]), |
.parr_srdy (parr_srdy[(`NUM_PORTS)-1:0]), |
.parr_page (parr_page[(`LL_PG_ASZ)-1:0]), |
.lnp_drdy (lnp_drdy[(`NUM_PORTS)-1:0]), |
.rlp_drdy (rlp_drdy[(`NUM_PORTS)-1:0]), |
.rlpr_srdy (rlpr_srdy[(`NUM_PORTS)-1:0]), |
.rlpr_data (rlpr_data[(`LL_PG_ASZ+1)-1:0]), |
.drf_drdy (drf_drdy[(`NUM_PORTS)-1:0]), |
.refup_drdy (refup_drdy), |
.pgmem_wr_en (pgmem_wr_en), |
.pgmem_wr_addr (pgmem_wr_addr[(`LL_PG_ASZ)-1:0]), |
.pgmem_wr_data (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]), |
.pgmem_rd_addr (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]), |
.pgmem_rd_en (pgmem_rd_en), |
.ref_wr_en (ref_wr_en), |
.ref_wr_addr (ref_wr_addr[(`LL_PG_ASZ)-1:0]), |
.ref_wr_data (ref_wr_data[(`LL_REFSZ)-1:0]), |
.ref_rd_addr (ref_rd_addr[(`LL_PG_ASZ)-1:0]), |
.ref_rd_en (ref_rd_en), |
.free_count (), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.par_srdy (par_srdy[(`NUM_PORTS)-1:0]), |
.parr_drdy (parr_drdy[(`NUM_PORTS)-1:0]), |
.lnp_srdy (lnp_srdy[(`NUM_PORTS)-1:0]), |
.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]), // Templated |
.rlp_srdy (rlp_srdy[(`NUM_PORTS)-1:0]), |
.rlp_rd_page (rlp_rd_page[(`NUM_PORTS)*(`LL_PG_ASZ)-1:0]), |
.rlpr_drdy (rlpr_drdy[(`NUM_PORTS)-1:0]), |
.drf_srdy (drf_srdy[(`NUM_PORTS)-1:0]), |
.drf_page_list (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]), // Templated |
.refup_srdy (refup_srdy), |
.refup_page (refup_page[(`LL_PG_ASZ)-1:0]), |
.refup_count (refup_count[(`LL_REFSZ)-1:0]), |
.pgmem_rd_data (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]), |
.ref_rd_data (ref_rd_data[(`LL_REFSZ)-1:0])); |
|
/* behave2p_mem AUTO_TEMPLATE |
( |
|
.wr_clk (clk), |
.rd_clk (clk), |
|
.wr_en (pgmem_wr_en), |
.d_in (pgmem_wr_data[]), |
.wr_addr (pgmem_wr_addr[]), |
|
.rd_en (pgmem_rd_en), |
.rd_addr (pgmem_rd_addr[]), |
.d_out (pgmem_rd_data[]), |
); |
*/ |
behave2p_mem #(.depth (`LL_PAGES), |
.addr_sz (`LL_PG_ASZ), |
.width (`LL_PG_ASZ+1)) pglist_mem |
(/*AUTOINST*/ |
// Outputs |
.d_out (pgmem_rd_data[(`LL_PG_ASZ+1)-1:0]), // Templated |
// Inputs |
.wr_en (pgmem_wr_en), // Templated |
.rd_en (pgmem_rd_en), // Templated |
.wr_clk (clk), // Templated |
.rd_clk (clk), // Templated |
.d_in (pgmem_wr_data[(`LL_PG_ASZ+1)-1:0]), // Templated |
.rd_addr (pgmem_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated |
.wr_addr (pgmem_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated |
|
/* behave2p_mem AUTO_TEMPLATE |
( |
|
.wr_clk (clk), |
.rd_clk (clk), |
|
.wr_en (ref_wr_en), |
.d_in (ref_wr_data[]), |
.wr_addr (ref_wr_addr[]), |
|
.rd_en (ref_rd_en), |
.rd_addr (ref_rd_addr[]), |
.d_out (ref_rd_data[]), |
); |
*/ |
behave2p_mem #(.depth (`LL_PAGES), |
.addr_sz (`LL_PG_ASZ), |
.width (`LL_REFSZ)) ref_mem |
(/*AUTOINST*/ |
// Outputs |
.d_out (ref_rd_data[(`LL_REFSZ)-1:0]), // Templated |
// Inputs |
.wr_en (ref_wr_en), // Templated |
.rd_en (ref_rd_en), // Templated |
.wr_clk (clk), // Templated |
.rd_clk (clk), // Templated |
.d_in (ref_wr_data[(`LL_REFSZ)-1:0]), // Templated |
.rd_addr (ref_rd_addr[(`LL_PG_ASZ)-1:0]), // Templated |
.wr_addr (ref_wr_addr[(`LL_PG_ASZ)-1:0])); // Templated |
|
/* sd_fifo_s AUTO_TEMPLATE |
( |
.c_clk (clk), |
.c_reset (reset), |
.p_clk (clk), |
.p_reset (reset), |
.c_data (flo_data[`LL_PG_ASZ-1:0]), |
.c_\(.*\) (flo_\1[@]), |
.p_\(.*\) (f2d_\1[@]), |
.p_data (f2d_data_@[`LL_PG_ASZ-1:0]), |
); |
*/ |
sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq0 |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (flo_drdy[0]), // Templated |
.p_srdy (f2d_srdy[0]), // Templated |
.p_data (f2d_data_0[`LL_PG_ASZ-1:0]), // Templated |
// Inputs |
.c_clk (clk), // Templated |
.c_reset (reset), // Templated |
.c_srdy (flo_srdy[0]), // Templated |
.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (f2d_drdy[0])); // Templated |
|
sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq1 |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (flo_drdy[1]), // Templated |
.p_srdy (f2d_srdy[1]), // Templated |
.p_data (f2d_data_1[`LL_PG_ASZ-1:0]), // Templated |
// Inputs |
.c_clk (clk), // Templated |
.c_reset (reset), // Templated |
.c_srdy (flo_srdy[1]), // Templated |
.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (f2d_drdy[1])); // Templated |
|
sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq2 |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (flo_drdy[2]), // Templated |
.p_srdy (f2d_srdy[2]), // Templated |
.p_data (f2d_data_2[`LL_PG_ASZ-1:0]), // Templated |
// Inputs |
.c_clk (clk), // Templated |
.c_reset (reset), // Templated |
.c_srdy (flo_srdy[2]), // Templated |
.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (f2d_drdy[2])); // Templated |
|
sd_fifo_s #(.width(`LL_PG_ASZ), .depth(8)) cq3 |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (flo_drdy[3]), // Templated |
.p_srdy (f2d_srdy[3]), // Templated |
.p_data (f2d_data_3[`LL_PG_ASZ-1:0]), // Templated |
// Inputs |
.c_clk (clk), // Templated |
.c_reset (reset), // Templated |
.c_srdy (flo_srdy[3]), // Templated |
.c_data (flo_data[`LL_PG_ASZ-1:0]), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (f2d_drdy[3])); // Templated |
|
|
endmodule // control_pipe |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks" "../../../rtl/verilog/memory" "../../llmanager") |
// End: |
/trunk/examples/bridge/rtl/fib_lookup_fsm.v
1,15 → 1,15
module fib_lookup_fsm |
(/*AUTOARG*/ |
// Outputs |
lpp_drdy, ft_wdata, ft_rd_en, ft_wr_en, ft_addr, lout_data, |
lout_srdy, lout_dst_vld, |
lpp_drdy, ft_wdata, ft_rd_en, ft_wr_en, ft_addr, lout_start, |
lout_srdy, lout_dst_vld, refup_srdy, refup_page, refup_count, |
// Inputs |
clk, reset, lpp_data, lpp_srdy, ft_rdata, lout_drdy |
clk, reset, lpp_data, lpp_srdy, ft_rdata, lout_drdy, refup_drdy |
); |
|
input clk, reset; |
|
input [`PAR_DATA_SZ-1:0] lpp_data; |
input [`PM2F_SZ-1:0] lpp_data; |
input lpp_srdy; |
output reg lpp_drdy; |
|
18,11 → 18,16
output reg ft_rd_en, ft_wr_en; |
output reg [`FIB_ASZ-1:0] ft_addr; |
|
output reg [`NUM_PORTS-1:0] lout_data; |
output [`LL_PG_ASZ-1:0] lout_start; |
output reg lout_srdy; |
input lout_drdy; |
output [`NUM_PORTS-1:0] lout_dst_vld; |
output reg [`NUM_PORTS-1:0] lout_dst_vld; |
|
output refup_srdy; |
input refup_drdy; |
output [`LL_PG_ASZ-1:0] refup_page; |
output [`LL_REFSZ-1:0] refup_count; |
|
wire [`FIB_ASZ-1:0] hf_out; |
reg [47:0] hf_in; |
|
29,10 → 34,36
wire [`NUM_PORTS-1:0] source_port_mask; |
|
reg [`FIB_ASZ-1:0] init_ctr, nxt_init_ctr; |
reg [4:0] state, nxt_state; |
|
reg [5:0] state, nxt_state; |
reg lrefup_srdy; |
reg [`LL_REFSZ-1:0] lrefup_count; |
|
assign source_port_mask = 1 << lpp_data[`PAR_SRCPORT]; |
|
//assign lrefup_count = count_bits (lout_dst_vld); |
//assign refup_page = lpp_data[`A2F_STARTPG]; |
assign lout_start = lpp_data[`A2F_STARTPG]; |
|
function [`LL_REFSZ-1:0] count_bits; |
input [`NUM_PORTS-1:0] dest; |
integer i, count; |
begin |
count = 0; |
for (i=0; i<4; i=i+1) |
if (dest[i]) count = count + 1; |
count_bits = count; |
end |
endfunction // for |
|
sd_iohalf #(.width(`LL_PG_ASZ+`LL_REFSZ)) refup_buf |
(.clk (clk), .reset (reset), |
.c_srdy (lrefup_srdy), |
.c_drdy (lrefup_drdy), |
.c_data ({lrefup_count, lpp_data[`A2F_STARTPG]}), |
.p_srdy (refup_srdy), |
.p_drdy (refup_drdy), |
.p_data ({refup_count, refup_page})); |
|
basic_hashfunc #(48, `FIB_ENTRIES) hashfunc |
( |
// Outputs |
41,13 → 72,10
.hf_in (hf_in)); |
|
localparam s_idle = 0, s_da_lookup = 1, s_sa_lookup = 2, |
s_init0 = 3, s_init1 = 4; |
s_init0 = 3, s_init1 = 4, s_wait_refup = 5; |
localparam ns_idle = 1, ns_da_lookup = 2, ns_sa_lookup = 4, |
ns_init0 = 8, ns_init1 = 16; |
ns_init0 = 8, ns_init1 = 16, ns_wait_refup = 1 << s_wait_refup; |
|
// send all results back to their originating port |
assign lout_dst_vld = source_port_mask; |
|
reg amux; |
|
always @* |
65,10 → 93,11
ft_rd_en = 0; |
ft_wr_en = 0; |
amux = 0; |
lout_data = 0; |
lout_dst_vld = 0; |
lout_srdy = 0; |
lpp_drdy = 0; |
nxt_init_ctr = init_ctr; |
lrefup_srdy = 0; |
|
case (1'b1) |
state[s_idle] : |
79,7 → 108,7
if (lpp_data[`PAR_MACDA] & `MULTICAST) |
begin |
// flood the packet, don't bother to do DA lookup |
lout_data = ~source_port_mask; |
lout_dst_vld = ~source_port_mask; |
lout_srdy = 1; |
if (lout_drdy) |
nxt_state = ns_sa_lookup; |
101,11 → 130,11
// no match, flood packet |
if (ft_rdata[`FIB_AGE] == 0) |
begin |
lout_data = ~source_port_mask; |
lout_dst_vld = ~source_port_mask; |
end |
else |
begin |
lout_data = (1 << ft_rdata[`FIB_PORT]) & ~source_port_mask; |
lout_dst_vld = (1 << ft_rdata[`FIB_PORT]) & ~source_port_mask; |
end |
|
lout_srdy = 1; |
123,7 → 152,25
ft_wdata[`FIB_AGE] = `FIB_MAX_AGE; |
ft_wdata[`FIB_PORT] = lpp_data[`PAR_SRCPORT]; |
nxt_state = ns_idle; |
lpp_drdy = 1; |
|
lrefup_srdy = 1; |
if (lrefup_drdy) |
begin |
nxt_state = ns_idle; |
lpp_drdy = 1; |
end |
else |
nxt_state = ns_wait_refup; |
end // case: state[s_sa_lookup] |
|
state[s_wait_refup] : |
begin |
lrefup_srdy = 1; |
if (lrefup_drdy) |
begin |
nxt_state = ns_idle; |
lpp_drdy = 1; |
end |
end |
|
state[s_init0] : |
153,11 → 200,14
begin |
init_ctr <= #1 0; |
state <= #1 ns_init0; |
lrefup_count <= #1 0; |
end |
else |
begin |
init_ctr <= #1 nxt_init_ctr; |
state <= #1 nxt_state; |
if (lout_srdy) |
lrefup_count <= #1 count_bits (lout_dst_vld); |
end |
end |
|
/trunk/examples/bridge/rtl/packet_buffer.v
0,0 → 1,102
module packet_buffer |
( |
input clk, |
input reset, |
|
input [3:0] pbra_srdy, |
output [3:0] pbra_drdy, |
input [`PBR_SZ-1:0] pbra_data_0, // From p0 of port_macro.v |
input [`PBR_SZ-1:0] pbra_data_1, // From p1 of port_macro.v |
input [`PBR_SZ-1:0] pbra_data_2, // From p2 of port_macro.v |
input [`PBR_SZ-1:0] pbra_data_3, // From p3 of port_macro.v |
input [`PBR_SZ-1:0] pbrd_data_0, // From p0 of port_macro.v |
input [`PBR_SZ-1:0] pbrd_data_1, // From p1 of port_macro.v |
input [`PBR_SZ-1:0] pbrd_data_2, // From p2 of port_macro.v |
input [`PBR_SZ-1:0] pbrd_data_3, // From p3 of port_macro.v |
input [3:0] pbrd_srdy, |
output [3:0] pbrd_drdy, |
|
output [3:0] pbrr_srdy, |
input [3:0] pbrr_drdy, |
output [`PFW_SZ-1:0] pbrr_data |
); |
|
wire [`PBR_SZ-1:0] pbi_data; |
wire [`NUM_PORTS*2-1:0] pbi_grant; |
wire pbi_srdy; |
wire pbi_drdy; |
|
wire pbo_srdy; |
wire pbo_drdy; |
wire [`PORT_ASZ-1:0] pbo_portnum; |
wire [`PFW_SZ-1:0] pbo_data; |
wire [`NUM_PORTS-1:0] pbo_portsel; |
|
assign pbo_portsel = 1 << pbo_portnum; |
|
sd_rrmux #( |
// Parameters |
.width (`PBR_SZ), |
.inputs (`NUM_PORTS*2), |
.mode (0), |
.fast_arb (1)) fib_arb |
( |
// Outputs |
.p_data (pbi_data[`PBR_SZ-1:0]), |
.p_grant (pbi_grant[(`NUM_PORTS*2)-1:0]), |
.p_srdy (pbi_srdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
|
.c_data ({pbra_data_3,pbra_data_2,pbra_data_1,pbra_data_0, |
pbrd_data_3,pbrd_data_2,pbrd_data_1,pbrd_data_0}), |
.c_srdy ({pbra_srdy,pbrd_srdy}), |
.c_drdy ({pbra_drdy,pbrd_drdy}), |
|
.c_rearb (1'b1), |
.p_drdy (pbi_drdy)); |
|
sd_scoreboard #( |
// Parameters |
.width (`PFW_SZ), |
.items (`PB_DEPTH), |
.use_txid (1), |
.use_mask (0), |
.txid_sz (`PORT_ASZ), |
.asz (`PB_ASZ)) pbmem |
( |
// Outputs |
.c_drdy (pbi_drdy), |
.p_srdy (pbo_srdy), |
.p_txid (pbo_portnum), |
.p_data (pbo_data), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (pbi_srdy), |
.c_req_type (pbi_data[`PBR_WRITE]), |
.c_txid (pbi_data[`PBR_PORT]), |
.c_mask ({`PFW_SZ{1'b1}}), |
.c_data (pbi_data[`PBR_DATA]), |
.c_itemid (pbi_data[`PBR_ADDR]), |
.p_drdy (pbo_drdy)); |
|
sd_mirror #(.mirror (`NUM_PORTS), .width(`PFW_SZ)) pbo_mirror |
( |
// Outputs |
.c_drdy (pbo_drdy), |
.p_srdy (pbrr_srdy), |
.p_data (pbrr_data), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (pbo_srdy), |
.c_data (pbo_data), |
.c_dst_vld (pbo_portsel), |
.p_drdy (pbrr_drdy)); |
|
endmodule // packet_buffer |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/utility" "../../../rtl/verilog/forks") |
// End: |
/trunk/examples/bridge/rtl/bridge.vh
6,7 → 6,7
// We will have only 4 ports in our sample design |
`define NUM_PORTS 4 |
|
// Data structure from parser to FIB. Contains MAC DA, |
// Data structure from parser to Allocator/FIB. Contains MAC DA, |
// MAC SA, and source port |
`define PAR_DATA_SZ (48+48+4) |
`define PAR_MACDA 47:0 |
13,6 → 13,13
`define PAR_MACSA 95:48 |
`define PAR_SRCPORT 99:96 |
|
// additional information from allocator to FIB |
`define A2F_STARTPG 111:100 |
`define A2F_ENDPG 123:112 |
|
// total size of parser+allocator structure to FIB |
`define PM2F_SZ 124 |
|
// number of entries in FIB table |
`define FIB_ENTRIES 256 |
`define FIB_ASZ $clog2(`FIB_ENTRIES) |
33,9 → 40,13
`define PCC_EOP 2'b10 // End of packet |
`define PCC_BADEOP 2'b11 // End of packet w/ error |
|
`define ANY_EOP(x) (( (x) == `PCC_EOP) || ( (x) == `PCC_BADEOP)) |
|
// Packet FIFO Word |
// uses same field definitions as Packet Ring Word, but no PVEC bit |
`define PFW_SZ 69 |
`define PRW_DATA 63:0 // 64 bits of packet data |
`define PRW_PCC 65:64 // packet control code |
`define PRW_VALID 68:66 // # of valid bytes modulo 8 |
`define PFW_SZ 69 |
|
// Port FIFO sizes |
`define RX_FIFO_DEPTH 256 |
44,14 → 55,30
`define RX_USG_SZ $clog2(`RX_FIFO_DEPTH)+1 |
`define TX_USG_SZ $clog2(`TX_FIFO_DEPTH)+1 |
|
// Packet Ring Word |
// Linked List Definitions |
`define LL_PAGES 4096 |
`define LL_PG_ASZ $clog2(`LL_PAGES) |
|
`define PRW_SZ 70 |
`define PRW_DATA 63:0 // 64 bits of packet data |
`define PRW_PCC 65:64 // packet control code |
`define PRW_VALID 68:66 // # of valid bytes modulo 8 |
`define PRW_PVEC 69 // indicates this is port vector word |
`define LL_ENDPAGE { 1'b1, {`LL_PG_ASZ{1'b0}} } |
|
`define LL_MAX_REF 16 |
`define LL_REFSZ 4 |
|
`define LL_LNP_SZ (`LL_PG_ASZ*2+1) |
|
|
// Packet buffer size |
`define PB_LINES_PER_PAGE 4 |
`define PB_DEPTH (`LL_PAGES*`PB_LINES_PER_PAGE) |
`define PB_ASZ $clog2(`PB_DEPTH) |
|
// Packet buffer request structure |
`define PBR_DATA 68:0 // only valid for writes |
`define PBR_ADDR 82:69 |
`define PBR_WRITE 83 |
`define PBR_PORT 87:84 // only valid for reads |
`define PBR_SZ 88 |
|
// GMII definitions |
`define GMII_PRE 8'h55 |
`define GMII_SFD 8'hD5 |
/trunk/examples/bridge/rtl/port_macro.v
1,31 → 1,53
module port_macro |
#(parameter port_num = 0) |
#(parameter port_num = 0, |
parameter lpsz = 12, |
parameter lpdsz = 13) |
(input clk, |
input reset, |
|
input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v |
output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v |
input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input fli_srdy, // To ring_tap of port_ring_tap.v |
input gmii_rx_clk, // To port_clocking of port_clocking.v, ... |
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v |
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v |
input p2f_drdy, // To pkt_parse of pkt_parse.v |
input rarb_ack, // To ring_tap of port_ring_tap.v |
input ri_srdy, // To ring_tap of port_ring_tap.v |
input ro_drdy, // To ring_tap of port_ring_tap.v |
input drf_drdy, // To dealloc of deallocator.v |
input [`LL_PG_ASZ-1:0] f2d_data, // To dealloc of deallocator.v |
input f2d_srdy, // To dealloc of deallocator.v |
input gmii_rx_clk, // To port_clocking of port_clocking.v, ... |
input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v |
input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v |
input lnp_drdy, // To alloc of allocator.v |
input par_drdy, // To alloc of allocator.v |
input [`LL_PG_ASZ-1:0] parr_page, // To alloc of allocator.v |
input parr_srdy, // To alloc of allocator.v |
input pbra_drdy, // To alloc of allocator.v |
input pbrd_drdy, // To dealloc of deallocator.v |
input [`PFW_SZ-1:0] pbrr_data, // To dealloc of deallocator.v |
input pbrr_srdy, // To dealloc of deallocator.v |
input pm2f_drdy, // To pm2f_join of sd_ajoin2.v |
input rlp_drdy, // To dealloc of deallocator.v |
input [`LL_PG_ASZ:0] rlpr_data, // To dealloc of deallocator.v |
input rlpr_srdy, // To dealloc of deallocator.v |
// End of automatics |
|
output rarb_req, |
output fli_drdy, // From ring_tap of port_ring_tap.v |
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v |
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v |
output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v |
output p2f_srdy, // From pkt_parse of pkt_parse.v |
output ri_drdy, // From ring_tap of port_ring_tap.v |
output ro_srdy // From ring_tap of port_ring_tap.v |
/*AUTOOUTPUT*/ |
// Beginning of automatic outputs (from unused autoinst outputs) |
output [`LL_PG_ASZ*2-1:0] drf_page_list, // From dealloc of deallocator.v |
output drf_srdy, // From dealloc of deallocator.v |
output f2d_drdy, // From dealloc of deallocator.v |
output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v |
output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v |
output [`LL_LNP_SZ-1:0] lnp_pnp, // From alloc of allocator.v |
output lnp_srdy, // From alloc of allocator.v |
output par_srdy, // From alloc of allocator.v |
output parr_drdy, // From alloc of allocator.v |
output [`PBR_SZ-1:0] pbra_data, // From alloc of allocator.v |
output pbra_srdy, // From alloc of allocator.v |
output [`PBR_SZ-1:0] pbrd_data, // From dealloc of deallocator.v |
output pbrd_srdy, // From dealloc of deallocator.v |
output pbrr_drdy, // From dealloc of deallocator.v |
output [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data,// From pm2f_join of sd_ajoin2.v |
output pm2f_srdy, // From pm2f_join of sd_ajoin2.v |
output [`LL_PG_ASZ-1:0] rlp_rd_page, // From dealloc of deallocator.v |
output rlp_srdy, // From dealloc of deallocator.v |
output rlpr_drdy // From dealloc of deallocator.v |
// End of automatics |
); |
|
wire [`RX_USG_SZ-1:0] rx_usage; |
38,36 → 60,35
wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v |
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire crx_abort; // From con of concentrator.v |
wire crx_commit; // From con of concentrator.v |
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v |
wire crx_drdy; // From fifo_rx of sd_fifo_b.v |
wire crx_srdy; // From con of concentrator.v |
wire ctx_abort; // From oflow of egr_oflow.v |
wire ctx_commit; // From oflow of egr_oflow.v |
wire ctx_drdy; // From fifo_tx of sd_fifo_b.v |
wire ctx_srdy; // From oflow of egr_oflow.v |
wire gmii_rx_reset; // From port_clocking of port_clocking.v |
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v |
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v |
wire pdo_drdy; // From con of concentrator.v |
wire pdo_srdy; // From pkt_parse of pkt_parse.v |
wire prx_drdy; // From ring_tap of port_ring_tap.v |
wire prx_srdy; // From fifo_rx of sd_fifo_b.v |
wire ptx_drdy; // From dst of distributor.v |
wire ptx_srdy; // From fifo_tx of sd_fifo_b.v |
wire rttx_drdy; // From oflow of egr_oflow.v |
wire rttx_srdy; // From ring_tap of port_ring_tap.v |
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v |
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v |
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v |
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v |
wire rxg_drdy; // From pkt_parse of pkt_parse.v |
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v |
wire [1:0] txg_code; // From dst of distributor.v |
wire [7:0] txg_data; // From dst of distributor.v |
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v |
wire txg_srdy; // From dst of distributor.v |
wire a2f_drdy; // From pm2f_join of sd_ajoin2.v |
wire [`LL_PG_ASZ-1:0] a2f_end; // From alloc of allocator.v |
wire a2f_srdy; // From alloc of allocator.v |
wire [`LL_PG_ASZ-1:0] a2f_start; // From alloc of allocator.v |
wire crx_abort; // From con of concentrator.v |
wire crx_commit; // From con of concentrator.v |
wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v |
wire crx_drdy; // From alloc of allocator.v |
wire crx_srdy; // From con of concentrator.v |
wire gmii_rx_reset; // From port_clocking of port_clocking.v |
wire [`PAR_DATA_SZ-1:0] p2f_data; // From pkt_parse of pkt_parse.v |
wire p2f_drdy; // From pm2f_join of sd_ajoin2.v |
wire p2f_srdy; // From pkt_parse of pkt_parse.v |
wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v |
wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v |
wire pdo_drdy; // From con of concentrator.v |
wire pdo_srdy; // From pkt_parse of pkt_parse.v |
wire ptx_drdy; // From dst of distributor.v |
wire ptx_srdy; // From dealloc of deallocator.v |
wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v |
wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v |
wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v |
wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v |
wire rxg_drdy; // From pkt_parse of pkt_parse.v |
wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v |
wire [1:0] txg_code; // From dst of distributor.v |
wire [7:0] txg_data; // From dst of distributor.v |
wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v |
wire txg_srdy; // From dst of distributor.v |
// End of automatics |
|
|
74,11 → 95,11
port_clocking port_clocking |
(/*AUTOINST*/ |
// Outputs |
.gmii_rx_reset (gmii_rx_reset), |
.gmii_rx_reset (gmii_rx_reset), |
// Inputs |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk (gmii_rx_clk)); |
.clk (clk), |
.reset (reset), |
.gmii_rx_clk (gmii_rx_clk)); |
|
/* sd_rx_gigmac AUTO_TEMPLATE |
( |
88,17 → 109,19
); |
*/ |
sd_rx_gigmac rx_gigmac |
(/*AUTOINST*/ |
( |
.cfg_check_crc (1'b0), |
/*AUTOINST*/ |
// Outputs |
.rxg_srdy (rxc_rxg_srdy), // Templated |
.rxg_code (rxc_rxg_code[1:0]), // Templated |
.rxg_data (rxc_rxg_data[7:0]), // Templated |
.rxg_srdy (rxc_rxg_srdy), // Templated |
.rxg_code (rxc_rxg_code[1:0]), // Templated |
.rxg_data (rxc_rxg_data[7:0]), // Templated |
// Inputs |
.clk (gmii_rx_clk), // Templated |
.reset (gmii_rx_reset), // Templated |
.gmii_rx_dv (gmii_rx_dv), |
.gmii_rxd (gmii_rxd[7:0]), |
.rxg_drdy (rxc_rxg_drdy)); // Templated |
.clk (gmii_rx_clk), // Templated |
.reset (gmii_rx_reset), // Templated |
.gmii_rx_dv (gmii_rx_dv), |
.gmii_rxd (gmii_rxd[7:0]), |
.rxg_drdy (rxc_rxg_drdy)); // Templated |
|
/* sd_fifo_s AUTO_TEMPLATE |
( |
115,35 → 138,36
sd_fifo_s #(8+2,16,1) rx_sync_fifo |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rxc_rxg_drdy), // Templated |
.p_srdy (rxg_srdy), // Templated |
.p_data ({rxg_code,rxg_data}), // Templated |
.c_drdy (rxc_rxg_drdy), // Templated |
.p_srdy (rxg_srdy), // Templated |
.p_data ({rxg_code,rxg_data}), // Templated |
// Inputs |
.c_clk (gmii_rx_clk), // Templated |
.c_reset (gmii_rx_reset), // Templated |
.c_srdy (rxc_rxg_srdy), // Templated |
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (rxg_drdy)); // Templated |
.c_clk (gmii_rx_clk), // Templated |
.c_reset (gmii_rx_reset), // Templated |
.c_srdy (rxc_rxg_srdy), // Templated |
.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated |
.p_clk (clk), // Templated |
.p_reset (reset), // Templated |
.p_drdy (rxg_drdy)); // Templated |
|
pkt_parse #(port_num) pkt_parse |
(/*AUTOINST*/ |
( |
/*AUTOINST*/ |
// Outputs |
.rxg_drdy (rxg_drdy), |
.p2f_srdy (p2f_srdy), |
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]), |
.pdo_srdy (pdo_srdy), |
.pdo_code (pdo_code[1:0]), |
.pdo_data (pdo_data[7:0]), |
.rxg_drdy (rxg_drdy), |
.p2f_srdy (p2f_srdy), |
.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]), |
.pdo_srdy (pdo_srdy), |
.pdo_code (pdo_code[1:0]), |
.pdo_data (pdo_data[7:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.rxg_srdy (rxg_srdy), |
.rxg_code (rxg_code[1:0]), |
.rxg_data (rxg_data[7:0]), |
.p2f_drdy (p2f_drdy), |
.pdo_drdy (pdo_drdy)); |
.clk (clk), |
.reset (reset), |
.rxg_srdy (rxg_srdy), |
.rxg_code (rxg_code[1:0]), |
.rxg_data (rxg_data[7:0]), |
.p2f_drdy (p2f_drdy), |
.pdo_drdy (pdo_drdy)); |
|
/* concentrator AUTO_TEMPLATE |
( |
154,120 → 178,102
concentrator con |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (pdo_drdy), // Templated |
.p_data (crx_data[`PFW_SZ-1:0]), // Templated |
.p_srdy (crx_srdy), // Templated |
.p_commit (crx_commit), // Templated |
.p_abort (crx_abort), // Templated |
.c_drdy (pdo_drdy), // Templated |
.p_data (crx_data[`PFW_SZ-1:0]), // Templated |
.p_srdy (crx_srdy), // Templated |
.p_commit (crx_commit), // Templated |
.p_abort (crx_abort), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_data (pdo_data[7:0]), // Templated |
.c_code (pdo_code[1:0]), // Templated |
.c_srdy (pdo_srdy), // Templated |
.p_drdy (crx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.c_data (pdo_data[7:0]), // Templated |
.c_code (pdo_code[1:0]), // Templated |
.c_srdy (pdo_srdy), // Templated |
.p_drdy (crx_drdy)); // Templated |
|
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)" |
( |
.p_abort (1'b0), |
.p_commit (1'b0), |
.c_usage (@_usage), |
.p_usage (), |
.c_\(.*\) (c@_\1), |
.p_\(.*\) (p@_\1), |
); |
*/ |
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx |
/* allocator AUTO_TEMPLATE |
( |
); |
*/ |
allocator alloc |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (crx_drdy), // Templated |
.p_srdy (prx_srdy), // Templated |
.p_data (prx_data), // Templated |
.p_usage (), // Templated |
.c_usage (rx_usage), // Templated |
.crx_drdy (crx_drdy), |
.par_srdy (par_srdy), |
.parr_drdy (parr_drdy), |
.lnp_srdy (lnp_srdy), |
.lnp_pnp (lnp_pnp[`LL_LNP_SZ-1:0]), |
.pbra_data (pbra_data[`PBR_SZ-1:0]), |
.pbra_srdy (pbra_srdy), |
.a2f_start (a2f_start[`LL_PG_ASZ-1:0]), |
.a2f_end (a2f_end[`LL_PG_ASZ-1:0]), |
.a2f_srdy (a2f_srdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (crx_srdy), // Templated |
.c_commit (crx_commit), // Templated |
.c_abort (crx_abort), // Templated |
.c_data (crx_data), // Templated |
.p_drdy (prx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
.clk (clk), |
.reset (reset), |
.crx_abort (crx_abort), |
.crx_commit (crx_commit), |
.crx_data (crx_data[`PFW_SZ-1:0]), |
.crx_srdy (crx_srdy), |
.par_drdy (par_drdy), |
.parr_srdy (parr_srdy), |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), |
.lnp_drdy (lnp_drdy), |
.pbra_drdy (pbra_drdy), |
.a2f_drdy (a2f_drdy)); |
|
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (ctx_drdy), // Templated |
.p_srdy (ptx_srdy), // Templated |
.p_data (ptx_data), // Templated |
.p_usage (), // Templated |
.c_usage (tx_usage), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (ctx_srdy), // Templated |
.c_commit (ctx_commit), // Templated |
.c_abort (ctx_abort), // Templated |
.c_data (ctx_data), // Templated |
.p_drdy (ptx_drdy), // Templated |
.p_commit (1'b0), // Templated |
.p_abort (1'b0)); // Templated |
|
/* port_ring_tap AUTO_TEMPLATE |
/* sd_ajoin2 AUTO_TEMPLATE |
( |
.ro_data (ro_data[`PRW_SZ-1:0]), |
.ri_data (ri_data[`PRW_SZ-1:0]), |
.prx_\(.*\) (prx_\1), |
.ptx_\(.*\) (rttx_\1), |
); |
.c2_data ({a2f_end,a2f_start}), |
.c1_\(.*\) (p2f_\1[]), |
.c2_\(.*\) (a2f_\1[]), |
.p_\(.*\) (pm2f_\1[]), |
); |
*/ |
port_ring_tap #(port_num) ring_tap |
sd_ajoin2 #(.c1_width(`PAR_DATA_SZ), .c2_width(`LL_PG_ASZ*2)) pm2f_join |
(/*AUTOINST*/ |
// Outputs |
.ri_drdy (ri_drdy), |
.prx_drdy (prx_drdy), // Templated |
.ro_srdy (ro_srdy), |
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated |
.ptx_srdy (rttx_srdy), // Templated |
.ptx_data (rttx_data), // Templated |
.fli_drdy (fli_drdy), |
.rarb_req (rarb_req), |
.c1_drdy (p2f_drdy), // Templated |
.c2_drdy (a2f_drdy), // Templated |
.p_srdy (pm2f_srdy), // Templated |
.p_data (pm2f_data[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ri_srdy (ri_srdy), |
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated |
.prx_srdy (prx_srdy), // Templated |
.prx_data (prx_data), // Templated |
.ro_drdy (ro_drdy), |
.ptx_drdy (rttx_drdy), // Templated |
.fli_srdy (fli_srdy), |
.fli_data (fli_data[`NUM_PORTS-1:0]), |
.rarb_ack (rarb_ack)); |
.clk (clk), |
.reset (reset), |
.c1_srdy (p2f_srdy), // Templated |
.c1_data (p2f_data[(`PAR_DATA_SZ)-1:0]), // Templated |
.c2_srdy (a2f_srdy), // Templated |
.c2_data ({a2f_end,a2f_start}), // Templated |
.p_drdy (pm2f_drdy)); // Templated |
|
/* egr_oflow AUTO_TEMPLATE |
( |
.c_\(.*\) (rttx_\1[]), |
.p_\(.*\) (ctx_\1[]), |
); |
*/ |
egr_oflow oflow |
deallocator dealloc |
(/*AUTOINST*/ |
// Outputs |
.c_drdy (rttx_drdy), // Templated |
.p_srdy (ctx_srdy), // Templated |
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated |
.p_commit (ctx_commit), // Templated |
.p_abort (ctx_abort), // Templated |
.f2d_drdy (f2d_drdy), |
.rlp_srdy (rlp_srdy), |
.rlp_rd_page (rlp_rd_page[`LL_PG_ASZ-1:0]), |
.rlpr_drdy (rlpr_drdy), |
.drf_srdy (drf_srdy), |
.drf_page_list (drf_page_list[`LL_PG_ASZ*2-1:0]), |
.pbrd_data (pbrd_data[`PBR_SZ-1:0]), |
.pbrd_srdy (pbrd_srdy), |
.pbrr_drdy (pbrr_drdy), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.c_srdy (rttx_srdy), // Templated |
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated |
.tx_usage (tx_usage[`TX_USG_SZ-1:0]), |
.p_drdy (ctx_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.port_num (port_num[1:0]), |
.f2d_srdy (f2d_srdy), |
.f2d_data (f2d_data[`LL_PG_ASZ-1:0]), |
.rlp_drdy (rlp_drdy), |
.rlpr_srdy (rlpr_srdy), |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), |
.drf_drdy (drf_drdy), |
.pbrd_drdy (pbrd_drdy), |
.pbrr_srdy (pbrr_srdy), |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), |
.ptx_drdy (ptx_drdy)); |
|
/* distributor AUTO_TEMPLATE |
( |
277,29 → 283,29
distributor dst |
(/*AUTOINST*/ |
// Outputs |
.ptx_drdy (ptx_drdy), |
.p_srdy (txg_srdy), // Templated |
.p_code (txg_code[1:0]), // Templated |
.p_data (txg_data[7:0]), // Templated |
.ptx_drdy (ptx_drdy), |
.p_srdy (txg_srdy), // Templated |
.p_code (txg_code[1:0]), // Templated |
.p_data (txg_data[7:0]), // Templated |
// Inputs |
.clk (clk), |
.reset (reset), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
.p_drdy (txg_drdy)); // Templated |
.clk (clk), |
.reset (reset), |
.ptx_srdy (ptx_srdy), |
.ptx_data (ptx_data[`PFW_SZ-1:0]), |
.p_drdy (txg_drdy)); // Templated |
|
sd_tx_gigmac tx_gmii |
(/*AUTOINST*/ |
// Outputs |
.gmii_tx_en (gmii_tx_en), |
.gmii_txd (gmii_txd[7:0]), |
.txg_drdy (txg_drdy), |
.gmii_tx_en (gmii_tx_en), |
.gmii_txd (gmii_txd[7:0]), |
.txg_drdy (txg_drdy), |
// Inputs |
.clk (clk), |
.reset (reset), |
.txg_srdy (txg_srdy), |
.txg_code (txg_code[1:0]), |
.txg_data (txg_data[7:0])); |
.clk (clk), |
.reset (reset), |
.txg_srdy (txg_srdy), |
.txg_code (txg_code[1:0]), |
.txg_data (txg_data[7:0])); |
|
endmodule // port_macro |
// Local Variables: |
/trunk/examples/bridge/rtl/bridge_ex2.v
0,0 → 1,369
/*! \author Guy Hutchison |
* \brief Top level for bridge example |
* |
* 4-port bridge has 4 GMII interfaces, each one of which has its own RX clock |
* Port macros contain all packet buffering, and ring interface to communicate |
* with other port macros. |
* FIB block receives requests from all ports and sends results back to the |
* same port containing forwarding information. |
*/ |
|
module bridge_ex2 |
(input clk, //% 125 Mhz system clock |
input reset, //% Active high system reset |
/*AUTOINPUT*/ |
// Beginning of automatic inputs (from unused autoinst inputs) |
input gmii_rx_clk_0, // To p0 of port_macro.v |
input gmii_rx_clk_1, // To p1 of port_macro.v |
input gmii_rx_clk_2, // To p2 of port_macro.v |
input gmii_rx_clk_3, // To p3 of port_macro.v |
input gmii_rx_dv_0, // To p0 of port_macro.v |
input gmii_rx_dv_1, // To p1 of port_macro.v |
input gmii_rx_dv_2, // To p2 of port_macro.v |
input gmii_rx_dv_3, // To p3 of port_macro.v |
input [7:0] gmii_rxd_0, // To p0 of port_macro.v |
input [7:0] gmii_rxd_1, // To p1 of port_macro.v |
input [7:0] gmii_rxd_2, // To p2 of port_macro.v |
input [7:0] gmii_rxd_3, // To p3 of port_macro.v |
// End of automatics |
/*AUTOOUTPUT*/ |
// Beginning of automatic outputs (from unused autoinst outputs) |
output gmii_tx_en_0, // From p0 of port_macro.v |
output gmii_tx_en_1, // From p1 of port_macro.v |
output gmii_tx_en_2, // From p2 of port_macro.v |
output gmii_tx_en_3, // From p3 of port_macro.v |
output [7:0] gmii_txd_0, // From p0 of port_macro.v |
output [7:0] gmii_txd_1, // From p1 of port_macro.v |
output [7:0] gmii_txd_2, // From p2 of port_macro.v |
output [7:0] gmii_txd_3 // From p3 of port_macro.v |
// End of automatics |
); |
|
/*AUTOWIRE*/ |
// Beginning of automatic wires (for undeclared instantiated-module outputs) |
wire [(`NUM_PORTS)-1:0] drf_drdy; // From control0 of control_pipe.v |
wire [95:0] drf_page_list; // From p0 of port_macro.v, ... |
wire [3:0] drf_srdy; // From p0 of port_macro.v, ... |
wire [`LL_PG_ASZ-1:0] f2d_data_0; // From control0 of control_pipe.v |
wire [`LL_PG_ASZ-1:0] f2d_data_1; // From control0 of control_pipe.v |
wire [`LL_PG_ASZ-1:0] f2d_data_2; // From control0 of control_pipe.v |
wire [`LL_PG_ASZ-1:0] f2d_data_3; // From control0 of control_pipe.v |
wire [3:0] f2d_drdy; // From p0 of port_macro.v, ... |
wire [3:0] f2d_srdy; // From control0 of control_pipe.v |
wire [(`NUM_PORTS)-1:0] lnp_drdy; // From control0 of control_pipe.v |
wire [99:0] lnp_pnp; // From p0 of port_macro.v, ... |
wire [3:0] lnp_srdy; // From p0 of port_macro.v, ... |
wire [(`NUM_PORTS)-1:0] par_drdy; // From control0 of control_pipe.v |
wire [3:0] par_srdy; // From p0 of port_macro.v, ... |
wire [3:0] parr_drdy; // From p0 of port_macro.v, ... |
wire [(`LL_PG_ASZ)-1:0] parr_page; // From control0 of control_pipe.v |
wire [(`NUM_PORTS)-1:0] parr_srdy; // From control0 of control_pipe.v |
wire [`PBR_SZ-1:0] pbra_data_0; // From p0 of port_macro.v |
wire [`PBR_SZ-1:0] pbra_data_1; // From p1 of port_macro.v |
wire [`PBR_SZ-1:0] pbra_data_2; // From p2 of port_macro.v |
wire [`PBR_SZ-1:0] pbra_data_3; // From p3 of port_macro.v |
wire [3:0] pbra_drdy; // From pktbuf of packet_buffer.v |
wire [3:0] pbra_srdy; // From p0 of port_macro.v, ... |
wire [`PBR_SZ-1:0] pbrd_data_0; // From p0 of port_macro.v |
wire [`PBR_SZ-1:0] pbrd_data_1; // From p1 of port_macro.v |
wire [`PBR_SZ-1:0] pbrd_data_2; // From p2 of port_macro.v |
wire [`PBR_SZ-1:0] pbrd_data_3; // From p3 of port_macro.v |
wire [3:0] pbrd_drdy; // From pktbuf of packet_buffer.v |
wire [3:0] pbrd_srdy; // From p0 of port_macro.v, ... |
wire [`PFW_SZ-1:0] pbrr_data; // From pktbuf of packet_buffer.v |
wire [3:0] pbrr_drdy; // From p0 of port_macro.v, ... |
wire [3:0] pbrr_srdy; // From pktbuf of packet_buffer.v |
wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_0;// From p0 of port_macro.v |
wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_1;// From p1 of port_macro.v |
wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_2;// From p2 of port_macro.v |
wire [(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0] pm2f_data_3;// From p3 of port_macro.v |
wire [`NUM_PORTS-1:0] pm2f_drdy; // From control0 of control_pipe.v |
wire [3:0] pm2f_srdy; // From p0 of port_macro.v, ... |
wire [(`NUM_PORTS)-1:0] rlp_drdy; // From control0 of control_pipe.v |
wire [47:0] rlp_rd_page; // From p0 of port_macro.v, ... |
wire [3:0] rlp_srdy; // From p0 of port_macro.v, ... |
wire [(`LL_PG_ASZ+1)-1:0] rlpr_data; // From control0 of control_pipe.v |
wire [3:0] rlpr_drdy; // From p0 of port_macro.v, ... |
wire [(`NUM_PORTS)-1:0] rlpr_srdy; // From control0 of control_pipe.v |
// End of automatics |
|
/* port_macro AUTO_TEMPLATE |
( |
.clk (clk), |
.reset (reset), |
.p2f_srdy (p2f_srdy[@]), |
.p2f_drdy (p2f_drdy[@]), |
.fli_srdy (flo_srdy[@]), |
.fli_drdy (flo_drdy[@]), |
.fli_data (flo_data), |
.drf_srdy (drf_srdy[@]), |
.drf_drdy (drf_drdy[@]), |
.f2d_srdy (f2d_srdy[@]), |
.f2d_drdy (f2d_drdy[@]), |
.par_srdy (par_srdy[@]), |
.par_drdy (par_drdy[@]), |
.parr_srdy (parr_srdy[@]), |
.parr_drdy (parr_drdy[@]), |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), |
.lnp_srdy (lnp_srdy[@]), |
.lnp_drdy (lnp_drdy[@]), |
.rlp_srdy (rlp_srdy[@]), |
.rlp_drdy (rlp_drdy[@]), |
.rlpr_srdy (rlpr_srdy[@]), |
.rlpr_drdy (rlpr_drdy[@]), |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), |
// page size is 12 bits, use 24 bits for each drf port, 25 bits for link port |
.drf_page_list (drf_page_list[@"(- (* (+ @ 1) 24) 1)":@"(* @ 24)"]), |
.lnp_pnp (lnp_pnp[@"(- (* (+ @ 1) 25) 1)":@"(* @ 25)"]), |
// page address size is 12 bits |
.rlp_rd_page (rlp_rd_page[@"(- (* (+ @ 1) 12) 1)":@"(* @ 12)"]), |
.pm2f_srdy (pm2f_srdy[@]), |
.pm2f_drdy (pm2f_drdy[@]), |
.pbra_srdy (pbra_srdy[@]), |
.pbra_drdy (pbra_drdy[@]), |
.pbrd_srdy (pbrd_srdy[@]), |
.pbrd_drdy (pbrd_drdy[@]), |
.pbrr_srdy (pbrr_srdy[@]), |
.pbrr_drdy (pbrr_drdy[@]), |
.\(.*\) (\1_@[]), |
); |
*/ |
port_macro #(0) p0 |
(/*AUTOINST*/ |
// Outputs |
.drf_page_list (drf_page_list[23:0]), // Templated |
.drf_srdy (drf_srdy[0]), // Templated |
.f2d_drdy (f2d_drdy[0]), // Templated |
.gmii_tx_en (gmii_tx_en_0), // Templated |
.gmii_txd (gmii_txd_0[7:0]), // Templated |
.lnp_pnp (lnp_pnp[24:0]), // Templated |
.lnp_srdy (lnp_srdy[0]), // Templated |
.par_srdy (par_srdy[0]), // Templated |
.parr_drdy (parr_drdy[0]), // Templated |
.pbra_data (pbra_data_0[`PBR_SZ-1:0]), // Templated |
.pbra_srdy (pbra_srdy[0]), // Templated |
.pbrd_data (pbrd_data_0[`PBR_SZ-1:0]), // Templated |
.pbrd_srdy (pbrd_srdy[0]), // Templated |
.pbrr_drdy (pbrr_drdy[0]), // Templated |
.pm2f_data (pm2f_data_0[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated |
.pm2f_srdy (pm2f_srdy[0]), // Templated |
.rlp_rd_page (rlp_rd_page[11:0]), // Templated |
.rlp_srdy (rlp_srdy[0]), // Templated |
.rlpr_drdy (rlpr_drdy[0]), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.drf_drdy (drf_drdy[0]), // Templated |
.f2d_data (f2d_data_0[`LL_PG_ASZ-1:0]), // Templated |
.f2d_srdy (f2d_srdy[0]), // Templated |
.gmii_rx_clk (gmii_rx_clk_0), // Templated |
.gmii_rx_dv (gmii_rx_dv_0), // Templated |
.gmii_rxd (gmii_rxd_0[7:0]), // Templated |
.lnp_drdy (lnp_drdy[0]), // Templated |
.par_drdy (par_drdy[0]), // Templated |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated |
.parr_srdy (parr_srdy[0]), // Templated |
.pbra_drdy (pbra_drdy[0]), // Templated |
.pbrd_drdy (pbrd_drdy[0]), // Templated |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated |
.pbrr_srdy (pbrr_srdy[0]), // Templated |
.pm2f_drdy (pm2f_drdy[0]), // Templated |
.rlp_drdy (rlp_drdy[0]), // Templated |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated |
.rlpr_srdy (rlpr_srdy[0])); // Templated |
|
port_macro #(1) p1 |
(/*AUTOINST*/ |
// Outputs |
.drf_page_list (drf_page_list[47:24]), // Templated |
.drf_srdy (drf_srdy[1]), // Templated |
.f2d_drdy (f2d_drdy[1]), // Templated |
.gmii_tx_en (gmii_tx_en_1), // Templated |
.gmii_txd (gmii_txd_1[7:0]), // Templated |
.lnp_pnp (lnp_pnp[49:25]), // Templated |
.lnp_srdy (lnp_srdy[1]), // Templated |
.par_srdy (par_srdy[1]), // Templated |
.parr_drdy (parr_drdy[1]), // Templated |
.pbra_data (pbra_data_1[`PBR_SZ-1:0]), // Templated |
.pbra_srdy (pbra_srdy[1]), // Templated |
.pbrd_data (pbrd_data_1[`PBR_SZ-1:0]), // Templated |
.pbrd_srdy (pbrd_srdy[1]), // Templated |
.pbrr_drdy (pbrr_drdy[1]), // Templated |
.pm2f_data (pm2f_data_1[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated |
.pm2f_srdy (pm2f_srdy[1]), // Templated |
.rlp_rd_page (rlp_rd_page[23:12]), // Templated |
.rlp_srdy (rlp_srdy[1]), // Templated |
.rlpr_drdy (rlpr_drdy[1]), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.drf_drdy (drf_drdy[1]), // Templated |
.f2d_data (f2d_data_1[`LL_PG_ASZ-1:0]), // Templated |
.f2d_srdy (f2d_srdy[1]), // Templated |
.gmii_rx_clk (gmii_rx_clk_1), // Templated |
.gmii_rx_dv (gmii_rx_dv_1), // Templated |
.gmii_rxd (gmii_rxd_1[7:0]), // Templated |
.lnp_drdy (lnp_drdy[1]), // Templated |
.par_drdy (par_drdy[1]), // Templated |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated |
.parr_srdy (parr_srdy[1]), // Templated |
.pbra_drdy (pbra_drdy[1]), // Templated |
.pbrd_drdy (pbrd_drdy[1]), // Templated |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated |
.pbrr_srdy (pbrr_srdy[1]), // Templated |
.pm2f_drdy (pm2f_drdy[1]), // Templated |
.rlp_drdy (rlp_drdy[1]), // Templated |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated |
.rlpr_srdy (rlpr_srdy[1])); // Templated |
|
port_macro #(2) p2 |
(/*AUTOINST*/ |
// Outputs |
.drf_page_list (drf_page_list[71:48]), // Templated |
.drf_srdy (drf_srdy[2]), // Templated |
.f2d_drdy (f2d_drdy[2]), // Templated |
.gmii_tx_en (gmii_tx_en_2), // Templated |
.gmii_txd (gmii_txd_2[7:0]), // Templated |
.lnp_pnp (lnp_pnp[74:50]), // Templated |
.lnp_srdy (lnp_srdy[2]), // Templated |
.par_srdy (par_srdy[2]), // Templated |
.parr_drdy (parr_drdy[2]), // Templated |
.pbra_data (pbra_data_2[`PBR_SZ-1:0]), // Templated |
.pbra_srdy (pbra_srdy[2]), // Templated |
.pbrd_data (pbrd_data_2[`PBR_SZ-1:0]), // Templated |
.pbrd_srdy (pbrd_srdy[2]), // Templated |
.pbrr_drdy (pbrr_drdy[2]), // Templated |
.pm2f_data (pm2f_data_2[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated |
.pm2f_srdy (pm2f_srdy[2]), // Templated |
.rlp_rd_page (rlp_rd_page[35:24]), // Templated |
.rlp_srdy (rlp_srdy[2]), // Templated |
.rlpr_drdy (rlpr_drdy[2]), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.drf_drdy (drf_drdy[2]), // Templated |
.f2d_data (f2d_data_2[`LL_PG_ASZ-1:0]), // Templated |
.f2d_srdy (f2d_srdy[2]), // Templated |
.gmii_rx_clk (gmii_rx_clk_2), // Templated |
.gmii_rx_dv (gmii_rx_dv_2), // Templated |
.gmii_rxd (gmii_rxd_2[7:0]), // Templated |
.lnp_drdy (lnp_drdy[2]), // Templated |
.par_drdy (par_drdy[2]), // Templated |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated |
.parr_srdy (parr_srdy[2]), // Templated |
.pbra_drdy (pbra_drdy[2]), // Templated |
.pbrd_drdy (pbrd_drdy[2]), // Templated |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated |
.pbrr_srdy (pbrr_srdy[2]), // Templated |
.pm2f_drdy (pm2f_drdy[2]), // Templated |
.rlp_drdy (rlp_drdy[2]), // Templated |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated |
.rlpr_srdy (rlpr_srdy[2])); // Templated |
|
port_macro #(3) p3 |
(/*AUTOINST*/ |
// Outputs |
.drf_page_list (drf_page_list[95:72]), // Templated |
.drf_srdy (drf_srdy[3]), // Templated |
.f2d_drdy (f2d_drdy[3]), // Templated |
.gmii_tx_en (gmii_tx_en_3), // Templated |
.gmii_txd (gmii_txd_3[7:0]), // Templated |
.lnp_pnp (lnp_pnp[99:75]), // Templated |
.lnp_srdy (lnp_srdy[3]), // Templated |
.par_srdy (par_srdy[3]), // Templated |
.parr_drdy (parr_drdy[3]), // Templated |
.pbra_data (pbra_data_3[`PBR_SZ-1:0]), // Templated |
.pbra_srdy (pbra_srdy[3]), // Templated |
.pbrd_data (pbrd_data_3[`PBR_SZ-1:0]), // Templated |
.pbrd_srdy (pbrd_srdy[3]), // Templated |
.pbrr_drdy (pbrr_drdy[3]), // Templated |
.pm2f_data (pm2f_data_3[(`PAR_DATA_SZ)+(`LL_PG_ASZ*2)-1:0]), // Templated |
.pm2f_srdy (pm2f_srdy[3]), // Templated |
.rlp_rd_page (rlp_rd_page[47:36]), // Templated |
.rlp_srdy (rlp_srdy[3]), // Templated |
.rlpr_drdy (rlpr_drdy[3]), // Templated |
// Inputs |
.clk (clk), // Templated |
.reset (reset), // Templated |
.drf_drdy (drf_drdy[3]), // Templated |
.f2d_data (f2d_data_3[`LL_PG_ASZ-1:0]), // Templated |
.f2d_srdy (f2d_srdy[3]), // Templated |
.gmii_rx_clk (gmii_rx_clk_3), // Templated |
.gmii_rx_dv (gmii_rx_dv_3), // Templated |
.gmii_rxd (gmii_rxd_3[7:0]), // Templated |
.lnp_drdy (lnp_drdy[3]), // Templated |
.par_drdy (par_drdy[3]), // Templated |
.parr_page (parr_page[`LL_PG_ASZ-1:0]), // Templated |
.parr_srdy (parr_srdy[3]), // Templated |
.pbra_drdy (pbra_drdy[3]), // Templated |
.pbrd_drdy (pbrd_drdy[3]), // Templated |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), // Templated |
.pbrr_srdy (pbrr_srdy[3]), // Templated |
.pm2f_drdy (pm2f_drdy[3]), // Templated |
.rlp_drdy (rlp_drdy[3]), // Templated |
.rlpr_data (rlpr_data[`LL_PG_ASZ:0]), // Templated |
.rlpr_srdy (rlpr_srdy[3])); // Templated |
|
control_pipe control0 |
(/*AUTOINST*/ |
// Outputs |
.drf_drdy (drf_drdy[(`NUM_PORTS)-1:0]), |
.f2d_data_0 (f2d_data_0[`LL_PG_ASZ-1:0]), |
.f2d_data_1 (f2d_data_1[`LL_PG_ASZ-1:0]), |
.f2d_data_2 (f2d_data_2[`LL_PG_ASZ-1:0]), |
.f2d_data_3 (f2d_data_3[`LL_PG_ASZ-1:0]), |
.f2d_srdy (f2d_srdy[3:0]), |
.lnp_drdy (lnp_drdy[(`NUM_PORTS)-1:0]), |
.par_drdy (par_drdy[(`NUM_PORTS)-1:0]), |
.parr_page (parr_page[(`LL_PG_ASZ)-1:0]), |
.parr_srdy (parr_srdy[(`NUM_PORTS)-1:0]), |
.pm2f_drdy (pm2f_drdy[`NUM_PORTS-1:0]), |
.rlp_drdy (rlp_drdy[(`NUM_PORTS)-1:0]), |
.rlpr_data (rlpr_data[(`LL_PG_ASZ+1)-1:0]), |
.rlpr_srdy (rlpr_srdy[(`NUM_PORTS)-1:0]), |
// Inputs |
.pm2f_data_0 (pm2f_data_0[`PM2F_SZ-1:0]), |
.pm2f_data_1 (pm2f_data_1[`PM2F_SZ-1:0]), |
.pm2f_data_2 (pm2f_data_2[`PM2F_SZ-1:0]), |
.pm2f_data_3 (pm2f_data_3[`PM2F_SZ-1:0]), |
.clk (clk), |
.drf_page_list (drf_page_list[`NUM_PORTS*`LL_PG_ASZ*2-1:0]), |
.drf_srdy (drf_srdy[(`NUM_PORTS)-1:0]), |
.f2d_drdy (f2d_drdy[3:0]), |
.lnp_pnp (lnp_pnp[`LL_LNP_SZ*4-1:0]), |
.lnp_srdy (lnp_srdy[(`NUM_PORTS)-1:0]), |
.par_srdy (par_srdy[(`NUM_PORTS)-1:0]), |
.parr_drdy (parr_drdy[(`NUM_PORTS)-1:0]), |
.pm2f_srdy (pm2f_srdy[`NUM_PORTS-1:0]), |
.reset (reset), |
.rlp_rd_page (rlp_rd_page[(`NUM_PORTS)*(`LL_PG_ASZ)-1:0]), |
.rlp_srdy (rlp_srdy[(`NUM_PORTS)-1:0]), |
.rlpr_drdy (rlpr_drdy[(`NUM_PORTS)-1:0])); |
|
packet_buffer pktbuf |
(/*AUTOINST*/ |
// Outputs |
.pbra_drdy (pbra_drdy[3:0]), |
.pbrd_drdy (pbrd_drdy[3:0]), |
.pbrr_srdy (pbrr_srdy[3:0]), |
.pbrr_data (pbrr_data[`PFW_SZ-1:0]), |
// Inputs |
.clk (clk), |
.reset (reset), |
.pbra_srdy (pbra_srdy[3:0]), |
.pbra_data_0 (pbra_data_0[`PBR_SZ-1:0]), |
.pbra_data_1 (pbra_data_1[`PBR_SZ-1:0]), |
.pbra_data_2 (pbra_data_2[`PBR_SZ-1:0]), |
.pbra_data_3 (pbra_data_3[`PBR_SZ-1:0]), |
.pbrd_data_0 (pbrd_data_0[`PBR_SZ-1:0]), |
.pbrd_data_1 (pbrd_data_1[`PBR_SZ-1:0]), |
.pbrd_data_2 (pbrd_data_2[`PBR_SZ-1:0]), |
.pbrd_data_3 (pbrd_data_3[`PBR_SZ-1:0]), |
.pbrd_srdy (pbrd_srdy[3:0]), |
.pbrr_drdy (pbrr_drdy[3:0])); |
|
endmodule // bridge_ex1 |
// Local Variables: |
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks") |
// End: |