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  • This comparison shows the changes necessary to convert path 
    /ssbcc/trunk/core/9x8/peripherals
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/vivado_AXI4_Lite_Bus.py
45,6 → 45,8
ipx::remove_bus_interface {o_@BASEPORTNAME@} [ipx::current_core]
ipx::remove_bus_interface {i_@BASEPORTNAME@_signal_reset} [ipx::current_core]
ipx::remove_bus_interface {i_@BASEPORTNAME@_signal_clock} [ipx::current_core]
ipx::remove_memory_map {i_@BASEPORTNAME@} [ipx::current_core]
ipx::remove_memory_map {o_@BASEPORTNAME@} [ipx::current_core]
 
# Create the AXI4-Lite port.
ipx::add_bus_interface {@BASEPORTNAME@} [ipx::current_core]
88,10 → 90,14
body += """
# Fix the address space
ipx::add_address_space {@BASEPORTNAME@} [ipx::current_core]
set_property master_address_space_ref {@BASEPORTNAME@} [ipx::get_bus_interface @BASEPORTNAME@ [ipx::current_core]]
""";
if mode == 'master':
body += """set_property master_address_space_ref {@BASEPORTNAME@} [ipx::get_bus_interface @BASEPORTNAME@ [ipx::current_core]]
set_property range {@ADDR_WIDTH@} [ipx::get_address_space @BASEPORTNAME@ [ipx::current_core]]
set_property width {32} [ipx::get_address_space @BASEPORTNAME@ [ipx::current_core]]
""";
else:
body += "ipx::remove_address_space {@BASEPORTNAME@} [ipx::current_core]\n";
 
body += """
# Fix the reset port definition
/AXI4_Lite_Slave_DualPortRAM.v
26,6 → 26,9
reg s__axi_got_wdata = 1'b0;
reg s__axi_got_raddr = 1'b0;
reg [L__NBITS_SIZE-1:2] s__axi_addr = {(L__NBITS_SIZE-2){1'b0}};
initial o_awready = 1'b0;
initial o_wready = 1'b0;
initial o_arready = 1'b0;
always @ (posedge i_aclk)
if (~i_aresetn) begin
s__axi_idle <= 1'b1;
33,6 → 36,9
s__axi_got_wdata <= 1'b0;
s__axi_got_raddr <= 1'b0;
s__axi_addr <= {(L__NBITS_SIZE-2){1'b0}};
o_awready <= 1'b0;
o_wready <= 1'b0;
o_arready <= 1'b0;
end else begin
s__axi_idle <= s__axi_idle;
s__axi_got_waddr <= s__axi_got_waddr;
75,9 → 81,22
initial o_bvalid = 1'b0;
always @ (*)
o_bvalid = s__axi_got_wdata;
reg s__axi_arready_s = 1'b0;
always @ (posedge i_aclk)
if (~i_aresetn)
s__axi_arready_s <= 1'b0;
else
s__axi_arready_s <= o_arready;
initial o_rvalid = 1'b0;
always @ (s__axi_got_raddr)
o_rvalid = s__axi_got_raddr;
always @ (posedge i_aclk)
if (~i_aresetn)
o_rvalid <= 1'b0;
else if (s__axi_arready_s)
o_rvalid <= 1'b1;
else if (i_rready)
o_rvalid <= 1'b0;
else
o_rvalid <= o_rvalid;
// signals common to both memory architectures
reg [L__NBITS_SIZE-1:2] s__axi_addr_s = {(L__NBITS_SIZE-2){1'b0}};
always @ (posedge i_aclk)
/tb/AXI4_Lite_Slave_DualPortRAM/master.gtkw
0,0 → 1,50
[*]
[*] GTKWave Analyzer v3.3.42 (w)1999-2012 BSI
[*] Sun Mar 23 13:48:13 2014
[*]
[dumpfile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/tb.vcd"
[dumpfile_mtime] "Sun Mar 23 12:59:00 2014"
[dumpfile_size] 869113
[savefile] "/home/rsinclair/Projects/SSBCC/core/9x8/peripherals/tb/AXI4_Lite_Slave_DualPortRAM/master.gtkw"
[timestart] 20022900
[size] 1920 1171
[pos] -1 -1
*-16.801830 20420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[treeopen] tb.uut.
[sst_width] 205
[signals_width] 276
[sst_expanded] 1
[sst_vpaned_height] 353
@28
tb.uut.i_axi_lite_aclk
tb.uut.i_axi_lite_aresetn
@200
-write side
@22
tb.uut.i_axi_lite_awaddr[6:0]
tb.uut.i_axi_lite_wdata[31:0]
tb.uut.i_axi_lite_wstrb[3:0]
@28
tb.uut.o_axi_lite_awready
tb.uut.i_axi_lite_awvalid
tb.uut.o_axi_lite_wready
tb.uut.i_axi_lite_wvalid
tb.uut.i_axi_lite_bready
tb.uut.o_axi_lite_bvalid
tb.uut.o_axi_lite_bresp[1:0]
@200
-read side
@22
tb.uut.i_axi_lite_araddr[6:0]
@29
tb.uut.o_axi_lite_arready
@28
tb.uut.i_axi_lite_arvalid
tb.uut.i_axi_lite_rready
tb.uut.o_axi_lite_rvalid
tb.uut.o_axi_lite_rresp[1:0]
@22
tb.uut.o_axi_lite_rdata[31:0]
[pattern_trace] 1
[pattern_trace] 0
/tb/AXI4_Lite_Slave_DualPortRAM/tb.v
128,6 → 128,7
end
 
// Initiate reads and indicate their termination
localparam S_INIT_RREADY = 1'b1; // observed Xilinx behavior -- always high
initial s_rd_done = 1'b0;
reg [1:0] s_rd_acks = 2'b00;
reg s_arvalid = 1'b0;
137,7 → 138,7
always @ (posedge s_aclk) begin
s_rd_done <= 1'b0;
s_rd_acks <= s_rd_acks;
s_rready <= 1'b0;
s_rready <= S_INIT_RREADY;
if (s_rd_acks == 2'b11) begin
s_rd_done <= 1'b1;
s_rd_acks <= 2'b00;
205,4 → 206,9
if (s_done)
$finish;
 
//initial begin
// $dumpfile("tb.vcd");
// $dumpvars();
//end
 
endmodule
/AXI4_Lite_Slave_DualPortRAM.py
46,7 → 46,7
optionally specifies using an 8-bit RAM for the dual-port memory instantiation
Note: This is the default
ram32
optionally specifies using a 32-bit RAM for the dual-port memrory instantiation
optionally specifies using a 32-bit RAM for the dual-port memory instantiation
Note: This is required for Vivado 2013.3.\n
Vivado Users:
The peripheral creates a TCL script to facilitate turning the micro
107,6 → 107,10
if not re.match(r'[1-9]\d*$', y):
raise SSBCCException('localparam must be a numeric constant, not "%s", to be used in "size=%s" at %s' % (y,x,loc,));
y = int(y);
elif re.match(r'C_\w+$',x):
if not config.IsConstant(x):
raise SSBCCException('"size=%s" is not a constant at %s' % (x,loc,));
y = int(config.constants[x]);
elif re.match(r'[1-9]\d*$',x):
y = int(x);
else:

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