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https://opencores.org/ocsvn/ssbcc/ssbcc/trunk
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/i2c/TMP100/Xilinx/SP601/make
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i2c/TMP100/Xilinx/SP601/make
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Index: i2c/TMP100/Xilinx/SP601/sp601.v
===================================================================
--- i2c/TMP100/Xilinx/SP601/sp601.v (revision 2)
+++ i2c/TMP100/Xilinx/SP601/sp601.v (nonexistent)
@@ -1,88 +0,0 @@
-/*******************************************************************************
- *
- * Copyright 2012, Sinclair R.F., Inc.
- *
- * Top-level module to demonstrate reading four TMP100 I2C temperature sensors
- * and to display their hex outputs to a console about once per second.
- *
- ******************************************************************************/
-
-module sp601(
- // 200 MHz differential clock
- input wire ip_sysclk_p,
- input wire ip_sysclk_n,
- // I2C bus
- inout wire iop_i2c_scl,
- inout wire iop_i2c_sda,
- // UART Tx
- output wire op_usb_1_rx,
- // echo I2C bus to logic analyzer
- output wire op_i2c_scl,
- output wire op_i2c_sda
-);
-
-/*
- * Generate a 100 MHz clock from the 200 MHz oscillator.
- */
-
-wire s_sysclk;
-IBUFGDS sysclk_inst(
- .I (ip_sysclk_p),
- .IB (ip_sysclk_n),
- .O (s_sysclk)
-);
-
-wire s_divclk;
-BUFIO2 bufio2_inst(
- .I (s_sysclk),
- .IOCLK (),
- .DIVCLK (s_divclk),
- .SERDESSTROBE ()
-);
-defparam bufio2_inst.DIVIDE = 2;
-defparam bufio2_inst.DIVIDE_BYPASS = "FALSE";
-
-wire s_clk;
-BUFG sclk_inst(
- .I (s_divclk),
- .O (s_clk)
-);
-
-/*
- * Generate a synchronous reset.
- */
-
-reg [3:0] s_reset_count = 4'hF;
-always @ (posedge s_clk)
- s_reset_count <= s_reset_count - 4'd1;
-
-reg s_rst = 1'b1;
-always @ (posedge s_clk)
- if (s_reset_count == 4'd0)
- s_rst <= 1'b0;
- else
- s_rst <= s_rst;
-
-/*
- * Instantiate the micro controller.
- */
-
-i2c_tmp100 ie_inst(
- // synchronous reset and processor clock
- .i_rst (s_rst),
- .i_clk (s_clk),
- // I2C bus
- .io_scl (iop_i2c_scl),
- .io_sda (iop_i2c_sda),
- // UART_Tx port
- .o_UART_Tx (op_usb_1_rx)
-);
-
-/*
- * Copy the I2C bus to the logic analyzer outputs.
- */
-
-assign op_i2c_scl = iop_i2c_scl;
-assign op_i2c_sda = iop_i2c_sda;
-
-endmodule
i2c/TMP100/Xilinx/SP601/sp601.v
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Index: i2c/TMP100/Xilinx/SP601/00README.html
===================================================================
--- i2c/TMP100/Xilinx/SP601/00README.html (revision 2)
+++ i2c/TMP100/Xilinx/SP601/00README.html (nonexistent)
@@ -1,17 +0,0 @@
-
-
-I2C Temperature Sensor on SP601
-
-
-The SP601 does not have temperature sensors.
-Instead, I used the SP601 and the FMC XM105 daughter board to connect to a - seperate board with four TMP100s sensors on a 2.5 V I2C bus.
-The I2C SCL signal was connected to FMC_LA19_P (pin 38) and the - I2C SDA signal was connected to FMC_LA19_N (pin 40). These - signals were echoed to FMC_LA09_P (pin 37) and - FMC_LA09_N (pin 39) respectively for examination by an - Intronix Logicport logic analyzer.
-The SP601 USB UART was used to transmit the human-readable I2C temperature - measurements to a console.
- -
-Instead, I used the SP601 and the FMC XM105 daughter board to connect to a - seperate board with four TMP100s sensors on a 2.5 V I2C bus.
-The I2C SCL signal was connected to FMC_LA19_P (pin 38) and the - I2C SDA signal was connected to FMC_LA19_N (pin 40). These - signals were echoed to FMC_LA09_P (pin 37) and - FMC_LA09_N (pin 39) respectively for examination by an - Intronix Logicport logic analyzer.
-The SP601 USB UART was used to transmit the human-readable I2C temperature - measurements to a console.
- -
i2c/TMP100/Xilinx/SP601/00README.html
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Index: i2c/TMP100/Xilinx/SP601/.gitignore
===================================================================
--- i2c/TMP100/Xilinx/SP601/.gitignore (revision 2)
+++ i2c/TMP100/Xilinx/SP601/.gitignore (nonexistent)
@@ -1,37 +0,0 @@
-*.bgn
-*.bit
-*.bld
-*.csv
-*.drc
-_impact.*
-*.ipf
-*.log
-*.lso
-*.map
-*.mrp
-*.ncd
-*.ngc
-*.ngd
-*.ngm
-_ngo
-*.ngr
-*.pad
-*.par
-par_usage_statistics.html
-*.pcf
-*.prj
-*.ptwx
-*.syr
-*.txt
-*.unroutes
-*.ut
-*webtalk.*
-xlnx_auto_0_xdb
-*.xml
-_xmsgs
-*.xpi
-*.xrpt
-*.xsl
-xst
-*.xst
-*.xwbt
i2c/TMP100/Xilinx/SP601/.gitignore
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Index: i2c/TMP100/Xilinx/SP601/sp601.ucf
===================================================================
--- i2c/TMP100/Xilinx/SP601/sp601.ucf (revision 2)
+++ i2c/TMP100/Xilinx/SP601/sp601.ucf (nonexistent)
@@ -1,11 +0,0 @@
-# 200 MHz external oscillator
-NET "ip_sysclk_p" TNM_NET=ip_sysclk;
-TIMESPEC TS_ip_sysclk = PERIOD "ip_sysclk" 5 ns HIGH 50%;
-
-NET "ip_sysclk_p" LOC = "K15" | IOSTANDARD = "LVDS_25"; # sysclk_p
-NET "ip_sysclk_n" LOC = "K16" | IOSTANDARD = "LVDS_25"; # sysclk_n
-NET "op_usb_1_rx" LOC = "L12" | IOSTANDARD = "LVCMOS25"; # usb_1_rx (rx from USB UART viewpoint, tx from FPGA)
-NET "iop_i2c_scl" LOC = "N6" | IOSTANDARD = "LVCMOS25"; # FMC_LA19_P
-NET "iop_i2c_sda" LOC = "P7" | IOSTANDARD = "LVCMOS25"; # FMC_LA19_N
-NET "op_i2c_scl" LOC = "G11" | IOSTANDARD = "LVCMOS25"; # FMC_LA09_P
-NET "op_i2c_sda" LOC = "F10" | IOSTANDARD = "LVCMOS25"; # FMC_LA09_N
i2c/TMP100/Xilinx/SP601/sp601.ucf
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Index: i2c/TMP100/.gitignore
===================================================================
--- i2c/TMP100/.gitignore (revision 2)
+++ i2c/TMP100/.gitignore (nonexistent)
@@ -1,2 +0,0 @@
-*.lxt
-i2c_tmp100.v
i2c/TMP100/.gitignore
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Index: i2c/TMP100/make.iverilog
===================================================================
--- i2c/TMP100/make.iverilog (revision 2)
+++ i2c/TMP100/make.iverilog (nonexistent)
@@ -1,9 +0,0 @@
-#!/bin/bash
-
-NAME=i2c_tmp100
-
-ssbcc -P monitor_stack ${NAME}.9x8 || { echo "FATAL ERROR: SSBCC failed." > /dev/stderr; exit 1; }
-
-iverilog -o tb tb.v ${NAME}.v || { echo "FATAL ERRO: Compile failed." > /dev/stderr; exit 1; }
-
-time ./tb -lx2
i2c/TMP100/make.iverilog
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Index: i2c/TMP100/tb.v
===================================================================
--- i2c/TMP100/tb.v (revision 2)
+++ i2c/TMP100/tb.v (nonexistent)
@@ -1,89 +0,0 @@
-/*******************************************************************************
- *
- * Copyright 2012, Sinclair R.F., Inc.
- *
- * Test bench for examples/i2c_tmp100
- *
- ******************************************************************************/
-
-`timescale 1ns/1ps
-
-module tb;
-
-// 97 MHz clock
-reg s_clk = 1'b1;
-always @ (s_clk) s_clk <= #5.155 ~s_clk;
-
-reg s_rst = 1'b1;
-initial begin
- repeat (5) @ (posedge s_clk);
- s_rst <= 1'b0;
-end
-
-tri1 s_SCL;
-tri1 s_SDA;
-wire s_UART_Tx;
-i2c_tmp100 it_inst(
- // synchronous reset and processor clock
- .i_rst (s_rst),
- .i_clk (s_clk),
- // I2C ports
- .io_scl (s_SCL),
- .io_sda (s_SDA),
- // UART_Tx ports
- .o_UART_Tx (s_UART_Tx)
-);
-
-integer ix_i2c;
-reg [0:26] i2c_out = 27'b111111110_101010101_010100001;
-reg s_sensor_sda = 1'b1;
-initial begin
- @ (negedge s_SDA);
- if (s_SCL == 1'b0) begin
- $display("%13d : Malformed I2C start signal");
- $finish;
- end
- ix_i2c = 0;
- repeat (27) begin
- @ (negedge s_SCL);
- #700;
- s_sensor_sda = i2c_out[ix_i2c];
- ix_i2c = ix_i2c + 1;
- end
- s_sensor_sda = 1'b1;
-end
-assign s_SDA = (s_sensor_sda) ? 1'bz : 1'b0;
-
-localparam baud = 9600;
-localparam dt_baud = 1.0e9/baud;
-reg [8:0] deser = 9'h1FF;
-initial forever begin
- @ (negedge s_UART_Tx);
- #(dt_baud/2.0);
- repeat (9) begin
- #dt_baud;
- deser = { s_UART_Tx, deser[1+:8] };
- end
- if (deser[8] != 1'b1)
- $display("%13d : Malformed UART transmition, $time");
- else if ((8'h20 <= deser[0+:8]) && (deser[0+:8]<=8'h80))
- $display("%13d : Sent 0x%02H : %c", $time, deser[0+:8], deser[0+:8]);
- else
- $display("%13d : Sent 0x%02H", $time, deser[0+:8]);
-end
-
-// Progress meter
-initial forever begin #100_000_000; $display("%13d : progress report", $time); end
-
-// terminate after 10 msec (use 2.1e9 for 2.1 sec)
-initial begin
- while ($realtime < 1.0e7) @ (posedge s_clk);
- $finish;
-end
-
-initial begin
- $dumpfile("tb.lxt");
- $dumpvars();
-end
-
-endmodule
i2c/TMP100/tb.v
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Index: i2c/TMP100/i2c_tmp100.9x8
===================================================================
--- i2c/TMP100/i2c_tmp100.9x8 (revision 2)
+++ i2c/TMP100/i2c_tmp100.9x8 (nonexistent)
@@ -1,27 +0,0 @@
-# Copyright 2012, Sinclair R.F., Inc.
-#
-# Run a TI TMP100 I2C Temperature sensor. Report the temperature once per
-# second over a 9600 baud UART as a hex value.
-
-ARCHITECTURE core/9x8 Verilog
-
-INSTRUCTION 1024
-DATA_STACK 32
-RETURN_STACK 32
-
-MEMORY RAM ram 32
-
-PORTCOMMENT I2C bus
-PERIPHERAL open_drain inport=I_SCL \
- outport=O_SCL \
- iosignal=io_scl
-PERIPHERAL open_drain inport=I_SDA \
- outport=O_SDA \
- iosignal=io_sda
-
-PORTCOMMENT UART_Tx ports
-PERIPHERAL UART_Tx outport=O_UART_TX \
- inport=I_UART_TX \
- baudmethod=97000000/9600
-
-ASSEMBLY i2c_tmp100.s
i2c/TMP100/i2c_tmp100.9x8
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Index: i2c/TMP100/i2c_tmp100.s
===================================================================
--- i2c/TMP100/i2c_tmp100.s (revision 2)
+++ i2c/TMP100/i2c_tmp100.s (nonexistent)
@@ -1,87 +0,0 @@
-; Copyright 2012, Sinclair R.F., Inc.
-;
-; TMP100:
-; run in 400 kHz mode
-
-.constant C_TMP100_U14 ${9*16+2*2}
-.constant C_TMP100_U15 ${9*16+0*2}
-.constant C_TMP100_U16 ${9*16+6*2}
-.constant C_TMP100_U18 ${9*16+4*2}
-
-.include ../lib_i2c.s
-
-.main
-
- :infinite
- "\r\n\0"
- ${C_TMP100_U18|0x01} .call(get_i2c_temp) ; right-most displayed value
- ${C_TMP100_U16|0x01} .call(get_i2c_temp)
- ${C_TMP100_U15|0x01} .call(get_i2c_temp)
- ${C_TMP100_U14|0x01} .call(get_i2c_temp)
- :print_loop
- .outport(O_UART_TX)
- :print_wait .inport(I_UART_TX) .jumpc(print_wait)
- .jumpc(print_loop,nop) drop
- .call(wait_1_sec)
- .jump(infinite)
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;
-; Read the I2C temperature sensor and put the ascii value on the stack.
-;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-.function get_i2c_temp
- 0x20
- .call(i2c_send_start)
- .call(i2c_send_byte,swap) .jumpc(error)
- .call(i2c_read_byte) >r
- .call(i2c_read_byte) .call(byte_to_hex)
- r> .call(byte_to_hex)
- .jump(no_error)
- :error
- "----"
- :no_error
- .call(i2c_send_stop)
-.return
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;
-; Convert a byte to a two digit hex value.
-;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-.memory RAM ram
-.variable nibble_to_ascii "0123456789ABCDEF"
-
-; ( u - ascii(lower_nibble(u)) ascii(upper_nibble(u)) )
-.function byte_to_hex
-
- dup 0x0F & .fetchindexed(nibble_to_ascii)
- swap 0>> 0>> 0>> 0>> .fetchindexed(nibble_to_ascii)
-
-.return
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;
-; Wait one second with a 100 MHz clock.
-;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-.function wait_1_sec
-
- ; 100 iterations
- ${100-1} :outer
- ; 1000 iterations
- ${4-1} :mid_outer
- ${250-1} :mid_inner
- ; 1000 clock cycles (250 iterations of 4 clock loop)
- 250 :inner 1- .jumpc(inner,nop) drop
- .jumpc(mid_inner,1-) drop
- .jumpc(mid_outer,1-) drop
- .jumpc(outer,1-) drop
-
-.return
i2c/TMP100/i2c_tmp100.s
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Index: i2c/TMP100/Xilinx-SP601/00README.html
===================================================================
--- i2c/TMP100/Xilinx-SP601/00README.html (nonexistent)
+++ i2c/TMP100/Xilinx-SP601/00README.html (revision 5)
@@ -0,0 +1,17 @@
+
+
+I2C Temperature Sensor on SP601
+
+
+The SP601 does not have temperature sensors.
+Instead, I used the SP601 and the FMC XM105 daughter board to connect to a + seperate board with four TMP100s sensors on a 2.5 V I2C bus.
+The I2C SCL signal was connected to FMC_LA19_P (pin 38) and the + I2C SDA signal was connected to FMC_LA19_N (pin 40). These + signals were echoed to FMC_LA09_P (pin 37) and + FMC_LA09_N (pin 39) respectively for examination by an + Intronix Logicport logic analyzer.
+The SP601 USB UART was used to transmit the human-readable I2C temperature + measurements to a console.
+ +
+Instead, I used the SP601 and the FMC XM105 daughter board to connect to a + seperate board with four TMP100s sensors on a 2.5 V I2C bus.
+The I2C SCL signal was connected to FMC_LA19_P (pin 38) and the + I2C SDA signal was connected to FMC_LA19_N (pin 40). These + signals were echoed to FMC_LA09_P (pin 37) and + FMC_LA09_N (pin 39) respectively for examination by an + Intronix Logicport logic analyzer.
+The SP601 USB UART was used to transmit the human-readable I2C temperature + measurements to a console.
+ +
i2c/TMP100/Xilinx-SP601/00README.html
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Index: i2c/TMP100/Xilinx-SP601/.gitignore
===================================================================
--- i2c/TMP100/Xilinx-SP601/.gitignore (nonexistent)
+++ i2c/TMP100/Xilinx-SP601/.gitignore (revision 5)
@@ -0,0 +1,38 @@
+*.bgn
+*.bit
+*.bld
+*.csv
+*.drc
+_impact.*
+*.ipf
+log
+*.log
+*.lso
+*.map
+*.mrp
+*.ncd
+*.ngc
+*.ngd
+*.ngm
+_ngo
+*.ngr
+*.pad
+*.par
+par_usage_statistics.html
+*.pcf
+*.prj
+*.ptwx
+*.syr
+*.txt
+*.unroutes
+*.ut
+*webtalk.*
+xlnx_auto_0_xdb
+*.xml
+_xmsgs
+*.xpi
+*.xrpt
+*.xsl
+xst
+*.xst
+*.xwbt
Index: i2c/TMP100/Xilinx-SP601/sp601.ucf
===================================================================
--- i2c/TMP100/Xilinx-SP601/sp601.ucf (nonexistent)
+++ i2c/TMP100/Xilinx-SP601/sp601.ucf (revision 5)
@@ -0,0 +1,11 @@
+# 200 MHz external oscillator
+NET "ip_sysclk_p" TNM_NET=ip_sysclk;
+TIMESPEC TS_ip_sysclk = PERIOD "ip_sysclk" 5 ns HIGH 50%;
+
+NET "ip_sysclk_p" LOC = "K15" | IOSTANDARD = "LVDS_25"; # sysclk_p
+NET "ip_sysclk_n" LOC = "K16" | IOSTANDARD = "LVDS_25"; # sysclk_n
+NET "op_usb_1_rx" LOC = "L12" | IOSTANDARD = "LVCMOS25"; # usb_1_rx (rx from USB UART viewpoint, tx from FPGA)
+NET "iop_i2c_scl" LOC = "N6" | IOSTANDARD = "LVCMOS25"; # FMC_LA19_P
+NET "iop_i2c_sda" LOC = "P7" | IOSTANDARD = "LVCMOS25"; # FMC_LA19_N
+NET "op_i2c_scl" LOC = "G11" | IOSTANDARD = "LVCMOS25"; # FMC_LA09_P
+NET "op_i2c_sda" LOC = "F10" | IOSTANDARD = "LVCMOS25"; # FMC_LA09_N
Index: i2c/TMP100/Xilinx-SP601/sp601.v
===================================================================
--- i2c/TMP100/Xilinx-SP601/sp601.v (nonexistent)
+++ i2c/TMP100/Xilinx-SP601/sp601.v (revision 5)
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ *
+ * Copyright 2012, Sinclair R.F., Inc.
+ *
+ * Top-level module to demonstrate reading four TMP100 I2C temperature sensors
+ * and to display their hex outputs to a console about once per second.
+ *
+ ******************************************************************************/
+
+module sp601(
+ // 200 MHz differential clock
+ input wire ip_sysclk_p,
+ input wire ip_sysclk_n,
+ // I2C bus
+ inout wire iop_i2c_scl,
+ inout wire iop_i2c_sda,
+ // UART Tx
+ output wire op_usb_1_rx,
+ // echo I2C bus to logic analyzer
+ output wire op_i2c_scl,
+ output wire op_i2c_sda
+);
+
+/*
+ * Generate a 100 MHz clock from the 200 MHz oscillator.
+ */
+
+wire s_sysclk;
+IBUFGDS sysclk_inst(
+ .I (ip_sysclk_p),
+ .IB (ip_sysclk_n),
+ .O (s_sysclk)
+);
+
+wire s_divclk;
+BUFIO2 #(
+ .DIVIDE (4),
+ .DIVIDE_BYPASS ("FALSE"),
+ .USE_DOUBLER ("TRUE")
+) bufio2_inst (
+ .I (s_sysclk),
+ .IOCLK (),
+ .DIVCLK (s_divclk),
+ .SERDESSTROBE ()
+);
+
+wire s_clk;
+BUFG sclk_inst(
+ .I (s_divclk),
+ .O (s_clk)
+);
+
+/*
+ * Generate a synchronous reset.
+ */
+
+reg [3:0] s_reset_count = 4'hF;
+always @ (posedge s_clk)
+ s_reset_count <= s_reset_count - 4'd1;
+
+reg s_rst = 1'b1;
+always @ (posedge s_clk)
+ if (s_reset_count == 4'd0)
+ s_rst <= 1'b0;
+ else
+ s_rst <= s_rst;
+
+/*
+ * Instantiate the micro controller.
+ */
+
+i2c_tmp100 ie_inst(
+ // synchronous reset and processor clock
+ .i_rst (s_rst),
+ .i_clk (s_clk),
+ // I2C bus
+ .io_scl (iop_i2c_scl),
+ .io_sda (iop_i2c_sda),
+ // UART_Tx port
+ .o_UART_Tx (op_usb_1_rx)
+);
+
+/*
+ * Copy the I2C bus to the logic analyzer outputs.
+ */
+
+assign op_i2c_scl = iop_i2c_scl;
+assign op_i2c_sda = iop_i2c_sda;
+
+endmodule
i2c/TMP100/Xilinx-SP601/sp601.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: i2c/TMP100/Xilinx-SP601/make
===================================================================
--- i2c/TMP100/Xilinx-SP601/make (nonexistent)
+++ i2c/TMP100/Xilinx-SP601/make (revision 5)
@@ -0,0 +1,199 @@
+#!/bin/sh
+#
+# Make script for SP601 board.
+#
+# Usage:
+# ./make |& tee log
+
+source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+
+# Ensure the script to build the micro processor is present.
+if [ -n "`which ssbcc | sed -n -e '/^which:/p'`" ]; then
+ echo "FATAL ERROR:" > /dev/stderr;
+ echo "Could not find \"ssbcc\" required for build" > /dev/stderr;
+ exit 1;
+fi
+
+#
+# Set the build parameters.
+#
+
+NAME=sp601
+DEVICE=xc6slx16-2-csg324
+
+FILES="";
+FILES+=" ../uc/i2c_tmp100.v";
+FILES+=" ${NAME}.v";
+
+#
+# Prepatory work
+#
+
+# Build the micro processor.
+( cd ../uc; ssbcc --define-clog i2c_tmp100.9x8 ) || { echo "SSBCC failed" > /dev/stderr; exit 1; }
+
+#
+# Configure and run the synthesis
+#
+
+for fname in ${FILES}; do
+ echo "verilog work \"${fname}\"";
+done > ${NAME}.prj;
+
+mkdir -p xst/projnav.tmp;
+
+cat < ${NAME}.xst
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn ${NAME}.prj
+-ifmt mixed
+-ofn ${NAME}
+-ofmt NGC
+-p ${DEVICE}
+-top ${NAME}
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+EOF
+
+xst \
+ -ifn "${NAME}.xst" \
+ -ofn "${NAME}.syr" \
+|| { echo "XST Failed!" > /dev/stderr; exit 1; }
+
+#
+# Run through PAR
+#
+
+ngdbuild \
+ -dd _ngo \
+ -nt timestamp \
+ -uc ${NAME}.ucf \
+ -p ${DEVICE} \
+ ${NAME}.ngc ${NAME}.ngd \
+|| { echo "ngdbuild Failed!" > /dev/stderr; exit 1; }
+
+map \
+ -p ${DEVICE} \
+ -w \
+ -logic_opt off \
+ -ol high \
+ -t 1 \
+ -xt 0 \
+ -register_duplication off \
+ -r 4 \
+ -global_opt off \
+ -mt off \
+ -ir off \
+ -pr off \
+ -lc off \
+ -power off \
+ -o ${NAME}.ncd \
+ ${NAME}.ngd ${NAME}.pcf \
+|| { echo "MAP Failed!" > /dev/stderr; exit 1; }
+
+par \
+ -w \
+ -ol high \
+ -mt off \
+ ${NAME}.ncd ${NAME}.ncd ${NAME}.pcf \
+|| { echo "PAR Failed!" > /dev/stderr; exit 1; }
+
+#
+# Optionally perform timing analysis
+#
+
+if [ `false` ]; then
+ trce \
+ -v 3 \
+ -s 3 \
+ -n 3 \
+ -fastpaths \
+ -xml ${NAME}.twx \
+ ${NAME}.ncd \
+ -o ${NAME}.twr \
+ ${NAME}.pcf \
+ -ucf ${NAME}.ucf
+fi
+
+#
+# Generate the bitstream file
+#
+
+cat <${NAME}.ut
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
+EOF
+
+bitgen -f ${NAME}.ut ${NAME}.ncd \
+|| { echo "BITGEN Failed!" > /dev/stderr; exit 1; }
i2c/TMP100/Xilinx-SP601/make
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: i2c/TMP100/tb/.gitignore
===================================================================
--- i2c/TMP100/tb/.gitignore (nonexistent)
+++ i2c/TMP100/tb/.gitignore (revision 5)
@@ -0,0 +1 @@
+*.lxt
Index: i2c/TMP100/tb/tb.v
===================================================================
--- i2c/TMP100/tb/tb.v (nonexistent)
+++ i2c/TMP100/tb/tb.v (revision 5)
@@ -0,0 +1,89 @@
+/*******************************************************************************
+ *
+ * Copyright 2012, Sinclair R.F., Inc.
+ *
+ * Test bench for examples/i2c_tmp100
+ *
+ ******************************************************************************/
+
+`timescale 1ns/1ps
+
+module tb;
+
+// 97 MHz clock
+reg s_clk = 1'b1;
+always @ (s_clk) s_clk <= #5.155 ~s_clk;
+
+reg s_rst = 1'b1;
+initial begin
+ repeat (5) @ (posedge s_clk);
+ s_rst <= 1'b0;
+end
+
+tri1 s_SCL;
+tri1 s_SDA;
+wire s_UART_Tx;
+i2c_tmp100 it_inst(
+ // synchronous reset and processor clock
+ .i_rst (s_rst),
+ .i_clk (s_clk),
+ // I2C ports
+ .io_scl (s_SCL),
+ .io_sda (s_SDA),
+ // UART_Tx ports
+ .o_UART_Tx (s_UART_Tx)
+);
+
+integer ix_i2c;
+reg [0:26] i2c_out = 27'b111111110_101010101_010100001;
+reg s_sensor_sda = 1'b1;
+initial begin
+ @ (negedge s_SDA);
+ if (s_SCL == 1'b0) begin
+ $display("%13d : Malformed I2C start signal");
+ $finish;
+ end
+ ix_i2c = 0;
+ repeat (27) begin
+ @ (negedge s_SCL);
+ #700;
+ s_sensor_sda = i2c_out[ix_i2c];
+ ix_i2c = ix_i2c + 1;
+ end
+ s_sensor_sda = 1'b1;
+end
+assign s_SDA = (s_sensor_sda) ? 1'bz : 1'b0;
+
+localparam baud = 9600;
+localparam dt_baud = 1.0e9/baud;
+reg [8:0] deser = 9'h1FF;
+initial forever begin
+ @ (negedge s_UART_Tx);
+ #(dt_baud/2.0);
+ repeat (9) begin
+ #dt_baud;
+ deser = { s_UART_Tx, deser[1+:8] };
+ end
+ if (deser[8] != 1'b1)
+ $display("%13d : Malformed UART transmition, $time");
+ else if ((8'h20 <= deser[0+:8]) && (deser[0+:8]<=8'h80))
+ $display("%13d : Sent 0x%02H : %c", $time, deser[0+:8], deser[0+:8]);
+ else
+ $display("%13d : Sent 0x%02H", $time, deser[0+:8]);
+end
+
+// Progress meter
+initial forever begin #100_000_000; $display("%13d : progress report", $time); end
+
+// terminate after 10 msec (use 2.1e9 for 2.1 sec)
+initial begin
+ while ($realtime < 1.0e7) @ (posedge s_clk);
+ $finish;
+end
+
+initial begin
+ $dumpfile("tb.lxt");
+ $dumpvars();
+end
+
+endmodule
i2c/TMP100/tb/tb.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: i2c/TMP100/tb/make.iverilog
===================================================================
--- i2c/TMP100/tb/make.iverilog (nonexistent)
+++ i2c/TMP100/tb/make.iverilog (revision 5)
@@ -0,0 +1,9 @@
+#!/bin/bash
+
+NAME=i2c_tmp100
+
+( cd ../uc; ssbcc -P monitor_stack ${NAME}.9x8 ) || { echo "FATAL ERROR: SSBCC failed." > /dev/stderr; exit 1; }
+
+iverilog -o tb tb.v ../uc/${NAME}.v || { echo "FATAL ERRO: Compile failed." > /dev/stderr; exit 1; }
+
+time ./tb -lx2
i2c/TMP100/tb/make.iverilog
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: i2c/TMP100/uc/i2c_tmp100.s
===================================================================
--- i2c/TMP100/uc/i2c_tmp100.s (nonexistent)
+++ i2c/TMP100/uc/i2c_tmp100.s (revision 5)
@@ -0,0 +1,87 @@
+; Copyright 2012, 2014, Sinclair R.F., Inc.
+;
+; TMP100:
+; run in 400 kHz mode
+
+.constant C_TMP100_U14 ${9*16+2*2}
+.constant C_TMP100_U15 ${9*16+0*2}
+.constant C_TMP100_U16 ${9*16+6*2}
+.constant C_TMP100_U18 ${9*16+4*2}
+
+.include ../../lib_i2c.s
+
+.main
+
+ :infinite
+ "\r\n\0"
+ ${C_TMP100_U18|0x01} .call(get_i2c_temp) ; right-most displayed value
+ ${C_TMP100_U16|0x01} .call(get_i2c_temp)
+ ${C_TMP100_U15|0x01} .call(get_i2c_temp)
+ ${C_TMP100_U14|0x01} .call(get_i2c_temp)
+ :print_loop
+ .outport(O_UART_TX)
+ :print_wait .inport(I_UART_TX) .jumpc(print_wait)
+ .jumpc(print_loop,nop) drop
+ .call(wait_1_sec)
+ .jump(infinite)
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; Read the I2C temperature sensor and put the ascii value on the stack.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+.function get_i2c_temp
+ 0x20
+ .call(i2c_send_start)
+ .call(i2c_send_byte,swap) .jumpc(error)
+ .call(i2c_read_byte,0) >r
+ .call(i2c_read_byte,0) .call(byte_to_hex)
+ r> .call(byte_to_hex)
+ .jump(no_error)
+ :error
+ "----"
+ :no_error
+ .call(i2c_send_stop)
+.return
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; Convert a byte to a two digit hex value.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+.memory RAM ram
+.variable nibble_to_ascii "0123456789ABCDEF"
+
+; ( u - ascii(lower_nibble(u)) ascii(upper_nibble(u)) )
+.function byte_to_hex
+
+ dup 0x0F & .fetchindexed(nibble_to_ascii)
+ swap 0>> 0>> 0>> 0>> .fetchindexed(nibble_to_ascii)
+
+.return
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; Wait one second with a 100 MHz clock.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+.function wait_1_sec
+
+ ; 100 iterations
+ ${100-1} :outer
+ ; 1000 iterations
+ ${4-1} :mid_outer
+ ${250-1} :mid_inner
+ ; 1000 clock cycles (250 iterations of 4 clock loop)
+ 250 :inner 1- .jumpc(inner,nop) drop
+ .jumpc(mid_inner,1-) drop
+ .jumpc(mid_outer,1-) drop
+ .jumpc(outer,1-) drop
+
+.return
Index: i2c/TMP100/uc/.gitignore
===================================================================
--- i2c/TMP100/uc/.gitignore (nonexistent)
+++ i2c/TMP100/uc/.gitignore (revision 5)
@@ -0,0 +1,3 @@
+*.mem
+*_pkg.vhd
+i2c_tmp100.v
Index: i2c/TMP100/uc/i2c_tmp100.9x8
===================================================================
--- i2c/TMP100/uc/i2c_tmp100.9x8 (nonexistent)
+++ i2c/TMP100/uc/i2c_tmp100.9x8 (revision 5)
@@ -0,0 +1,27 @@
+# Copyright 2012, Sinclair R.F., Inc.
+#
+# Run a TI TMP100 I2C Temperature sensor. Report the temperature once per
+# second over a 9600 baud UART as a hex value.
+
+ARCHITECTURE core/9x8 Verilog
+
+INSTRUCTION 2048
+DATA_STACK 32
+RETURN_STACK 32
+
+MEMORY RAM ram 32
+
+PORTCOMMENT I2C bus
+PERIPHERAL open_drain inport=I_SCL \
+ outport=O_SCL \
+ iosignal=io_scl
+PERIPHERAL open_drain inport=I_SDA \
+ outport=O_SDA \
+ iosignal=io_sda
+
+PORTCOMMENT UART_Tx ports
+PERIPHERAL UART_Tx outport=O_UART_TX \
+ outstatus=I_UART_TX \
+ baudmethod=97_000_000/9600
+
+ASSEMBLY i2c_tmp100.s
Index: i2c/lib_i2c.s
===================================================================
--- i2c/lib_i2c.s (revision 2)
+++ i2c/lib_i2c.s (revision 5)
@@ -1,13 +1,30 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
-; Copyright 2012, Sinclair R.F., Inc.
+; Copyright 2012, 2014, Sinclair R.F., Inc.
;
; Major I2C functions:
-; i2c_send_start ( - )
-; i2c_send_byte ( u - f )
-; i2c_read_byte ( - u )
-; i2c_send_stop ( - )
+; i2c_send_start ( - ) send the start condition
+; i2c_send_restart ( - ) send a restart after ACK during write
+; i2c_send_byte ( u - f ) send a byte (address, register, data, ...)
+; i2c_read_byte ( f - u ) read a byte and either ACK (f=0) or STOP (f=1)
+; i2c_send_stop ( - ) send a stop after ACK during write
;
+; Example to set a single register (ignoring returned ACK/NACK value)
+; .call(i2c_send_start)
+; .call(i2c_send_byte,write_address) drop
+; .call(i2c_send_byte,register) drop
+; .call(i2c_send_byte,data) drop
+; .call(i2c_send_stop)
+;
+; Example to read two bytes (ignoring returned ACK/NACK value)
+; .call(i2c_send_start)
+; .call(i2c_send_byte,write_address) drop
+; .call(i2c_send_byte,register) drop
+; .call(i2c_send_restart)
+; .call(i2c_send_byte,read_address) drop
+; .call(i2c_read_byte,0)
+; .call(i2c_read_byte,1)
+;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Compute how many iterations in the quarter-clock-cycle function are required.
@@ -20,7 +37,9 @@
; 9 TOTAL
; Add 2 to ensure rounding up when evaluting the integer fraction.
; The loop is 3 clock cycles per iteration
+.IFNDEF C_I2C_QUARTER_CYCLE
.constant C_I2C_QUARTER_CYCLE ${(63-9+2)/3}
+.ENDIF
; ( - )
.function i2c_send_start
@@ -53,16 +72,25 @@
.call(i2c_clock_cycle,1)
.return
-; Read the next byte from the device.
-; ( - u )
+; Read the next byte from the device and generate an ACK or a STOP.
+; ( f - u )
.function i2c_read_byte
+ ; Read 8 bits and pack them into the returned value.
+ ; ( f - u f )
0 ${8-1} :loop
swap <<0 .call(i2c_clock_cycle,1) or swap
.jumpc(loop,1-) drop
- ; send the acknowledgment bit
- .call(i2c_clock_cycle,0)
-.return(drop)
-
+ swap
+ ; Generate the ACK/STOP based on f.
+ ; ( u f - u )
+ 0 .outport(O_SDA)
+ .call(i2c_quarter_cycle,0)
+ .call(i2c_quarter_cycle,1)
+ O_SDA outport
+ .call(i2c_quarter_cycle,1)
+ .call(i2c_quarter_cycle) ; SCL is high on STOP, low on ACK, consumes f
+.return
+
; Send a stop by bringing SDA high while SCL is high.
; ( - )
.function i2c_send_stop
/i2c/EEPROM/Xilinx/SP601/.gitignore
File deleted
i2c/EEPROM/Xilinx/SP601/.gitignore
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Author Date Id Revision
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: i2c/EEPROM/Xilinx/SP601/sp601.ucf
===================================================================
--- i2c/EEPROM/Xilinx/SP601/sp601.ucf (revision 2)
+++ i2c/EEPROM/Xilinx/SP601/sp601.ucf (nonexistent)
@@ -1,9 +0,0 @@
-# 200 MHz external oscillator
-NET "ip_sysclk_p" TNM_NET=ip_sysclk;
-TIMESPEC TS_ip_sysclk = PERIOD "ip_sysclk" 5 ns HIGH 50%;
-
-NET "ip_sysclk_p" LOC = "K15" | IOSTANDARD = "LVDS_25"; # sysclk_p
-NET "ip_sysclk_n" LOC = "K16" | IOSTANDARD = "LVDS_25"; # sysclk_n
-NET "op_usb_1_rx" LOC = "L12" | IOSTANDARD = "LVCMOS25"; # usb_1_rx (rx from USB UART viewpoint, tx from FPGA)
-NET "iop_i2c_scl" LOC = "P11" | IOSTANDARD = "LVCMOS33"; # iic_scl_main
-NET "iop_i2c_sda" LOC = "N10" | IOSTANDARD = "LVCMOS33"; # iic_sda_main
i2c/EEPROM/Xilinx/SP601/sp601.ucf
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Author Date Id Revision
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: i2c/EEPROM/Xilinx/SP601/make
===================================================================
--- i2c/EEPROM/Xilinx/SP601/make (revision 2)
+++ i2c/EEPROM/Xilinx/SP601/make (nonexistent)
@@ -1,194 +0,0 @@
-#!/bin/sh
-#
-# Make script for SP601 board.
-
-# Ensure the script to build the micro processor is present.
-if [ -n "`which ssbcc | sed -n -e '/^which:/p'`" ]; then
- echo "FATAL ERROR:" > /dev/stderr;
- echo "Could not find \"ssbcc\" required for build" > /dev/stderr;
- exit 1;
-fi
-
-#
-# Set the build parameters.
-#
-
-NAME=sp601
-DEVICE=xc6slx16-2-csg324
-
-FILES="";
-FILES+=" ../../i2c_eeprom.v";
-FILES+=" ${NAME}.v";
-
-#
-# Prepatory work
-#
-
-# Build the micro processor.
-( cd ../..; ssbcc --define-clog i2c_eeprom.9x8 ) || exit 1;
-
-#
-# Configure and run the synthesis
-#
-
-for fname in ${FILES}; do
- echo "verilog work \"${fname}\"";
-done > ${NAME}.prj;
-
-mkdir -p xst/projnav.tmp;
-
-cat < ${NAME}.xst
-set -tmpdir "xst/projnav.tmp"
-set -xsthdpdir "xst"
-run
--ifn ${NAME}.prj
--ifmt mixed
--ofn ${NAME}
--ofmt NGC
--p ${DEVICE}
--top ${NAME}
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--keep_hierarchy No
--netlist_hierarchy As_Optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case Maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc Auto
--reduce_control_sets Auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style LUT
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--shreg_min_size 2
--use_dsp48 Auto
--iobuf YES
--max_fanout 100000
--bufg 16
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob Auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
-EOF
-
-xst \
- -ifn "${NAME}.xst" \
- -ofn "${NAME}.syr" \
-|| { echo "XST Failed!"; exit 1; }
-
-#
-# Run through PAR
-#
-
-ngdbuild \
- -dd _ngo \
- -nt timestamp \
- -uc ${NAME}.ucf \
- -p ${DEVICE} \
- ${NAME}.ngc ${NAME}.ngd \
-|| { echo "ngdbuild Failed!"; exit 1; }
-
-map \
- -p ${DEVICE} \
- -w \
- -logic_opt off \
- -ol high \
- -t 1 \
- -xt 0 \
- -register_duplication off \
- -r 4 \
- -global_opt off \
- -mt off \
- -ir off \
- -pr off \
- -lc off \
- -power off \
- -o ${NAME}.ncd \
- ${NAME}.ngd ${NAME}.pcf \
-|| { echo "MAP Failed!"; exit 1; }
-
-par \
- -w \
- -ol high \
- -mt off \
- ${NAME}.ncd ${NAME}.ncd ${NAME}.pcf \
-|| { echo "PAR Failed!"; exit 1; }
-
-#
-# Optionally perform timing analysis
-#
-
-if [ `false` ]; then
- trce \
- -v 3 \
- -s 3 \
- -n 3 \
- -fastpaths \
- -xml ${NAME}.twx \
- ${NAME}.ncd \
- -o ${NAME}.twr \
- ${NAME}.pcf \
- -ucf ${NAME}.ucf
-fi
-
-#
-# Generate the bitstream file
-#
-
-cat <${NAME}.ut
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g Reset_on_err:No
--g ConfigRate:2
--g ProgPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g ExtMasterCclk_en:No
--g SPI_buswidth:1
--g TIMER_CFG:0xFFFF
--g multipin_wakeup:No
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g en_sw_gsr:No
--g drive_awake:No
--g sw_clk:Startupclk
--g sw_gwe_cycle:5
--g sw_gts_cycle:4
-EOF
-
-bitgen -f ${NAME}.ut ${NAME}.ncd \
-|| { echo "BITGEN Failed!"; exit 1; }
i2c/EEPROM/Xilinx/SP601/make
Property changes :
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\ No newline at end of property
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\ No newline at end of property
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\ No newline at end of property
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-text/plain
\ No newline at end of property
Index: i2c/EEPROM/Xilinx/SP601/sp601.v
===================================================================
--- i2c/EEPROM/Xilinx/SP601/sp601.v (revision 2)
+++ i2c/EEPROM/Xilinx/SP601/sp601.v (nonexistent)
@@ -1,77 +0,0 @@
-/*******************************************************************************
- *
- * Copyright 2012, Sinclair R.F., Inc.
- *
- * Top-level module to demonstrate I2C EEPROM write/read operation.
- *
- ******************************************************************************/
-
-module sp601(
- // 200 MHz differential clock
- input wire ip_sysclk_p,
- input wire ip_sysclk_n,
- // I2C bus
- inout wire iop_i2c_scl,
- inout wire iop_i2c_sda,
- // UART Tx
- output wire op_usb_1_rx
-);
-
-/*
- * Generate a 100 MHz clock from the 200 MHz oscillator.
- */
-
-wire s_sysclk;
-IBUFGDS sysclk_inst(
- .I (ip_sysclk_p),
- .IB (ip_sysclk_n),
- .O (s_sysclk)
-);
-
-wire s_divclk;
-BUFIO2 bufio2_inst(
- .I (s_sysclk),
- .IOCLK (),
- .DIVCLK (s_divclk),
- .SERDESSTROBE ()
-);
-defparam bufio2_inst.DIVIDE = 2;
-defparam bufio2_inst.DIVIDE_BYPASS = "FALSE";
-
-wire s_clk;
-BUFG sclk_inst(
- .I (s_divclk),
- .O (s_clk)
-);
-
-/*
- * Generate a synchronous reset.
- */
-
-reg [3:0] s_reset_count = 4'hF;
-always @ (posedge s_clk)
- s_reset_count <= s_reset_count - 4'd1;
-
-reg s_rst = 1'b1;
-always @ (posedge s_clk)
- if (s_reset_count == 4'd0)
- s_rst <= 1'b0;
- else
- s_rst <= s_rst;
-
-/*
- * Instantiate the micro controller.
- */
-
-i2c_eeprom ie_inst(
- // synchronous reset and processor clock
- .i_rst (s_rst),
- .i_clk (s_clk),
- // I2C bus
- .io_scl (iop_i2c_scl),
- .io_sda (iop_i2c_sda),
- // UART_Tx port
- .o_UART_Tx (op_usb_1_rx)
-);
-
-endmodule
i2c/EEPROM/Xilinx/SP601/sp601.v
Property changes :
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Index: i2c/EEPROM/.gitignore
===================================================================
--- i2c/EEPROM/.gitignore (revision 2)
+++ i2c/EEPROM/.gitignore (nonexistent)
@@ -1 +0,0 @@
-i2c_eeprom.v
i2c/EEPROM/.gitignore
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
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\ No newline at end of property
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## -1 +0,0 ##
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\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: i2c/EEPROM/i2c_eeprom.9x8
===================================================================
--- i2c/EEPROM/i2c_eeprom.9x8 (revision 2)
+++ i2c/EEPROM/i2c_eeprom.9x8 (nonexistent)
@@ -1,28 +0,0 @@
-# Copyright 2012, Sinclair R.F., Inc.
-#
-# Run a TI TMP100 I2C Temperature sensor. Report the temperature once per
-# second over a 9600 baud UART as a hex value.
-
-ARCHITECTURE core/9x8 Verilog
-
-INSTRUCTION 2048
-DATA_STACK 32
-RETURN_STACK 32
-
-MEMORY RAM ram 32
-MEMORY ROM messages 128
-
-PORTCOMMENT I2C bus
-PERIPHERAL open_drain inport=I_SCL \
- outport=O_SCL \
- iosignal=io_scl
-PERIPHERAL open_drain inport=I_SDA \
- outport=O_SDA \
- iosignal=io_sda
-
-PORTCOMMENT UART_Tx port
-PERIPHERAL UART_Tx outport=O_UART_TX \
- inport=I_UART_TX \
- baudmethod="100000000/115200"
-
-ASSEMBLY i2c_eeprom.s
i2c/EEPROM/i2c_eeprom.9x8
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Author Date Id Revision
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: i2c/EEPROM/i2c_eeprom.s
===================================================================
--- i2c/EEPROM/i2c_eeprom.s (revision 2)
+++ i2c/EEPROM/i2c_eeprom.s (nonexistent)
@@ -1,95 +0,0 @@
-; Copyright 2012, Sinclair R.F., Inc.
-;
-; I2C EEPROM design example:
-; Write a 16-byte string to the EEPROM and then read and display it.
-
-.constant C_I2C_EEPROM_ADDR ${0xa*16+0x4*2}
-
-.include ../lib_i2c.s
-
-.memory RAM ram
-.variable ram__msg 0*16
-
-.memory ROM messages
-.variable msg__bad_device_number N"Bad Device Number"
-.variable msg__write_address_rejected N"Write Address Rejected"
-.variable msg__rejected_data N"Data Rejected"
-.variable msg__read_address_rejected N"Read Address Rejected"
-.variable msg__read_state_rejected N"Read State Rejected"
-
-.main
-
- ; Write a 16-byte, null-terminated string to the EEPROM.
- C"Hello World!!\r\n\0"
- .call(i2c_send_start)
- .call(i2c_send_byte,${C_I2C_EEPROM_ADDR|0}) .jumpc(error__bad_device_number)
- .call(i2c_send_byte,0) .jumpc(error__write_address_rejected)
- :write_loop
- 1- .call(i2c_send_byte,swap) .jumpc(error__rejected_data)
- .jumpc(write_loop,nop) drop
- .call(i2c_send_stop)
-
- ;
- ; Read the null-terminated string from the EEPROM (after the write cycle finishes)
- ;
-
- ; Put the address on the bus until the EEPROM acknowledges it.
- :write_wait
- .call(i2c_send_start)
- ${C_I2C_EEPROM_ADDR|0} .call(i2c_send_byte) 0= .jumpc(write_wait_done)
- .call(i2c_send_stop)
- .jump(write_wait)
- :write_wait_done
-
- ; Send the start address for the reads followed by a start (with no stop)
- 0 .call(i2c_send_byte) .jumpc(error__read_address_rejected)
- .call(i2c_send_restart)
-
- ; Put the EEPROM into the read state
- ${C_I2C_EEPROM_ADDR|1} .call(i2c_send_byte) .jumpc(error__read_state_rejected)
-
- ; Read the EEPROM and write each byte to memory until the null terminator is
- ; encountered. Add the CRLF pair
- ram__msg >r
- :read_loop
- .call(i2c_read_byte)
- dup r> .store+(ram) >r .jumpc(read_loop)
- r> drop
-
- ; Send the string copied from the EEPROM to the UART.
- ram__msg
- :uart_loop .fetch+(ram) over 0= .jumpc(uart_done)
- swap .outport(O_UART_TX)
- :uart_wait .inport(I_UART_TX) .jumpc(uart_wait)
- .jump(uart_loop)
- :uart_done
- drop drop .jump(infinite)
-
- :error__bad_device_number
- .jump(error_with_clear,msg__bad_device_number)
- :error__write_address_rejected
- .jump(error_with_clear,msg__write_address_rejected)
- :error__rejected_data
- .jump(error_with_clear,msg__rejected_data)
- :error__read_address_rejected
- .jump(error_print_done,msg__read_address_rejected)
- :error__read_state_rejected
- .jump(error_print_done,msg__read_state_rejected)
- ; Print the error message and then wait forever.
- :error_with_clear
- >r
- ; clear the count-encoded string from the data stack
- :clear 1- .jumpc(clear,nip) drop
- ; read and display the error message
- r>
- :error_print_loop
- .fetch+(messages) over 0= .jumpc(error_print_done)
- swap .outport(O_UART_TX)
- :error_print_wait .inport(I_UART_TX) .jumpc(error_print_wait)
- .jump(error_print_loop)
- :error_print_done
- drop drop
-
- :infinite
- .jump(infinite)
-
i2c/EEPROM/i2c_eeprom.s
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Author Date Id Revision
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-text/plain
\ No newline at end of property
Index: i2c/EEPROM/Xilinx-SP601/.gitignore
===================================================================
--- i2c/EEPROM/Xilinx-SP601/.gitignore (nonexistent)
+++ i2c/EEPROM/Xilinx-SP601/.gitignore (revision 5)
@@ -0,0 +1,38 @@
+*.bit
+*.bgn
+*.bld
+*.csv
+*.drc
+_impact.*
+*.ipf
+log
+*.log
+*.lso
+*.map
+*.mrp
+*.ncd
+*.ngc
+*.ngd
+*.ngm
+_ngo
+*.ngr
+*.pad
+*.par
+par_usage_statistics.html
+*.pcf
+*.prj
+*.ptwx
+*.syr
+*.txt
+*.unroutes
+*.ut
+*webtalk.*
+xlnx_auto_0_xdb
+*.xml
+_xmsgs
+*.xpi
+*.xrpt
+*.xsl
+xst
+*.xst
+*.xwbt
Index: i2c/EEPROM/Xilinx-SP601/sp601.ucf
===================================================================
--- i2c/EEPROM/Xilinx-SP601/sp601.ucf (nonexistent)
+++ i2c/EEPROM/Xilinx-SP601/sp601.ucf (revision 5)
@@ -0,0 +1,9 @@
+# 200 MHz external oscillator
+NET "ip_sysclk_p" TNM_NET=ip_sysclk;
+TIMESPEC TS_ip_sysclk = PERIOD "ip_sysclk" 5 ns HIGH 50%;
+
+NET "ip_sysclk_p" LOC = "K15" | IOSTANDARD = "LVDS_25"; # sysclk_p
+NET "ip_sysclk_n" LOC = "K16" | IOSTANDARD = "LVDS_25"; # sysclk_n
+NET "op_usb_1_rx" LOC = "L12" | IOSTANDARD = "LVCMOS25"; # usb_1_rx (rx from USB UART viewpoint, tx from FPGA)
+NET "iop_i2c_scl" LOC = "P11" | IOSTANDARD = "LVCMOS33"; # iic_scl_main
+NET "iop_i2c_sda" LOC = "N10" | IOSTANDARD = "LVCMOS33"; # iic_sda_main
Index: i2c/EEPROM/Xilinx-SP601/sp601.v
===================================================================
--- i2c/EEPROM/Xilinx-SP601/sp601.v (nonexistent)
+++ i2c/EEPROM/Xilinx-SP601/sp601.v (revision 5)
@@ -0,0 +1,79 @@
+/*******************************************************************************
+ *
+ * Copyright 2012, Sinclair R.F., Inc.
+ *
+ * Top-level module to demonstrate I2C EEPROM write/read operation.
+ *
+ ******************************************************************************/
+
+module sp601(
+ // 200 MHz differential clock
+ input wire ip_sysclk_p,
+ input wire ip_sysclk_n,
+ // I2C bus
+ inout wire iop_i2c_scl,
+ inout wire iop_i2c_sda,
+ // UART Tx
+ output wire op_usb_1_rx
+);
+
+/*
+ * Generate a 100 MHz clock from the 200 MHz oscillator.
+ */
+
+wire s_sysclk;
+IBUFGDS sysclk_inst(
+ .I (ip_sysclk_p),
+ .IB (ip_sysclk_n),
+ .O (s_sysclk)
+);
+
+wire s_divclk;
+BUFIO2 #(
+ .DIVIDE (4),
+ .DIVIDE_BYPASS ("FALSE"),
+ .USE_DOUBLER ("TRUE")
+) bufio2_inst (
+ .I (s_sysclk),
+ .IOCLK (),
+ .DIVCLK (s_divclk),
+ .SERDESSTROBE ()
+);
+
+wire s_clk;
+BUFG sclk_inst(
+ .I (s_divclk),
+ .O (s_clk)
+);
+
+/*
+ * Generate a synchronous reset.
+ */
+
+reg [3:0] s_reset_count = 4'hF;
+always @ (posedge s_clk)
+ s_reset_count <= s_reset_count - 4'd1;
+
+reg s_rst = 1'b1;
+always @ (posedge s_clk)
+ if (s_reset_count == 4'd0)
+ s_rst <= 1'b0;
+ else
+ s_rst <= s_rst;
+
+/*
+ * Instantiate the micro controller.
+ */
+
+i2c_eeprom ie_inst(
+ // synchronous reset and processor clock
+ .i_rst (s_rst),
+ .i_clk (s_clk),
+ // I2C bus
+ .io_scl (iop_i2c_scl),
+ .io_sda (iop_i2c_sda),
+ // UART_Tx port
+ .o_UART_Tx (op_usb_1_rx)
+);
+
+endmodule
i2c/EEPROM/Xilinx-SP601/sp601.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: i2c/EEPROM/Xilinx-SP601/make
===================================================================
--- i2c/EEPROM/Xilinx-SP601/make (nonexistent)
+++ i2c/EEPROM/Xilinx-SP601/make (revision 5)
@@ -0,0 +1,199 @@
+#!/bin/sh
+#
+# Make script for SP601 board.
+#
+# Usage:
+# ./make |& tee log
+
+source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+
+# Ensure the script to build the micro processor is present.
+if [ -n "`which ssbcc | sed -n -e '/^which:/p'`" ]; then
+ echo "FATAL ERROR:" > /dev/stderr;
+ echo "Could not find \"ssbcc\" required for build" > /dev/stderr;
+ exit 1;
+fi
+
+#
+# Set the build parameters.
+#
+
+NAME=sp601
+DEVICE=xc6slx16-2-csg324
+
+FILES="";
+FILES+=" ../uc/i2c_eeprom.v";
+FILES+=" ${NAME}.v";
+
+#
+# Prepatory work
+#
+
+# Build the micro processor.
+( cd ../uc; ssbcc --define-clog i2c_eeprom.9x8 ) || { echo "SSBCC failed" > /dev/stderr; exit 1; }
+
+#
+# Configure and run the synthesis
+#
+
+for fname in ${FILES}; do
+ echo "verilog work \"${fname}\"";
+done > ${NAME}.prj;
+
+mkdir -p xst/projnav.tmp;
+
+cat < ${NAME}.xst
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn ${NAME}.prj
+-ifmt mixed
+-ofn ${NAME}
+-ofmt NGC
+-p ${DEVICE}
+-top ${NAME}
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+EOF
+
+xst \
+ -ifn "${NAME}.xst" \
+ -ofn "${NAME}.syr" \
+|| { echo "XST Failed!" > /dev/stderr; exit 1; }
+
+#
+# Run through PAR
+#
+
+ngdbuild \
+ -dd _ngo \
+ -nt timestamp \
+ -uc ${NAME}.ucf \
+ -p ${DEVICE} \
+ ${NAME}.ngc ${NAME}.ngd \
+|| { echo "ngdbuild Failed!" > /dev/stderr; exit 1; }
+
+map \
+ -p ${DEVICE} \
+ -w \
+ -logic_opt off \
+ -ol high \
+ -t 1 \
+ -xt 0 \
+ -register_duplication off \
+ -r 4 \
+ -global_opt off \
+ -mt off \
+ -ir off \
+ -pr off \
+ -lc off \
+ -power off \
+ -o ${NAME}.ncd \
+ ${NAME}.ngd ${NAME}.pcf \
+|| { echo "MAP Failed!" > /dev/stderr; exit 1; }
+
+par \
+ -w \
+ -ol high \
+ -mt off \
+ ${NAME}.ncd ${NAME}.ncd ${NAME}.pcf \
+|| { echo "PAR Failed!" > /dev/stderr; exit 1; }
+
+#
+# Optionally perform timing analysis
+#
+
+if [ `false` ]; then
+ trce \
+ -v 3 \
+ -s 3 \
+ -n 3 \
+ -fastpaths \
+ -xml ${NAME}.twx \
+ ${NAME}.ncd \
+ -o ${NAME}.twr \
+ ${NAME}.pcf \
+ -ucf ${NAME}.ucf
+fi
+
+#
+# Generate the bitstream file
+#
+
+cat <${NAME}.ut
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
+EOF
+
+bitgen -f ${NAME}.ut ${NAME}.ncd \
+|| { echo "BITGEN Failed!" > /dev/stderr; exit 1; }
i2c/EEPROM/Xilinx-SP601/make
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: i2c/EEPROM/uc/.gitignore
===================================================================
--- i2c/EEPROM/uc/.gitignore (nonexistent)
+++ i2c/EEPROM/uc/.gitignore (revision 5)
@@ -0,0 +1,3 @@
+*.mem
+*_pkg.vhd
+i2c_eeprom.v
Index: i2c/EEPROM/uc/i2c_eeprom.s
===================================================================
--- i2c/EEPROM/uc/i2c_eeprom.s (nonexistent)
+++ i2c/EEPROM/uc/i2c_eeprom.s (revision 5)
@@ -0,0 +1,95 @@
+; Copyright 2012, Sinclair R.F., Inc.
+;
+; I2C EEPROM design example:
+; Write a 16-byte string to the EEPROM and then read and display it.
+
+.constant C_I2C_EEPROM_ADDR ${0xa*16+0x4*2}
+
+.include ../../lib_i2c.s
+
+.memory RAM ram
+.variable ram__msg 0*16
+
+.memory ROM messages
+.variable msg__bad_device_number N"Bad Device Number"
+.variable msg__write_address_rejected N"Write Address Rejected"
+.variable msg__rejected_data N"Data Rejected"
+.variable msg__read_address_rejected N"Read Address Rejected"
+.variable msg__read_state_rejected N"Read State Rejected"
+
+.main
+
+ ; Write a 16-byte, null-terminated string to the EEPROM.
+ C"Hello World!!\r\n\0"
+ .call(i2c_send_start)
+ .call(i2c_send_byte,${C_I2C_EEPROM_ADDR|0}) .jumpc(error__bad_device_number)
+ .call(i2c_send_byte,0) .jumpc(error__write_address_rejected)
+ :write_loop
+ 1- .call(i2c_send_byte,swap) .jumpc(error__rejected_data)
+ .jumpc(write_loop,nop) drop
+ .call(i2c_send_stop)
+
+ ;
+ ; Read the null-terminated string from the EEPROM (after the write cycle finishes)
+ ;
+
+ ; Put the address on the bus until the EEPROM acknowledges it.
+ :write_wait
+ .call(i2c_send_start)
+ ${C_I2C_EEPROM_ADDR|0} .call(i2c_send_byte) 0= .jumpc(write_wait_done)
+ .call(i2c_send_stop)
+ .jump(write_wait)
+ :write_wait_done
+
+ ; Send the start address for the reads followed by a start (with no stop)
+ 0 .call(i2c_send_byte) .jumpc(error__read_address_rejected)
+ .call(i2c_send_restart)
+
+ ; Put the EEPROM into the read state
+ ${C_I2C_EEPROM_ADDR|1} .call(i2c_send_byte) .jumpc(error__read_state_rejected)
+
+ ; Read the EEPROM and write each byte to memory until the null terminator is
+ ; encountered. Add the CRLF pair
+ ram__msg >r
+ :read_loop
+ .call(i2c_read_byte,0)
+ dup r> .store+(ram) >r .jumpc(read_loop)
+ r> drop
+
+ ; Send the string copied from the EEPROM to the UART.
+ ram__msg
+ :uart_loop .fetch+(ram) over 0= .jumpc(uart_done)
+ swap .outport(O_UART_TX)
+ :uart_wait .inport(I_UART_TX) .jumpc(uart_wait)
+ .jump(uart_loop)
+ :uart_done
+ drop drop .jump(infinite)
+
+ :error__bad_device_number
+ .jump(error_with_clear,msg__bad_device_number)
+ :error__write_address_rejected
+ .jump(error_with_clear,msg__write_address_rejected)
+ :error__rejected_data
+ .jump(error_with_clear,msg__rejected_data)
+ :error__read_address_rejected
+ .jump(error_print_done,msg__read_address_rejected)
+ :error__read_state_rejected
+ .jump(error_print_done,msg__read_state_rejected)
+ ; Print the error message and then wait forever.
+ :error_with_clear
+ >r
+ ; clear the count-encoded string from the data stack
+ :clear 1- .jumpc(clear,nip) drop
+ ; read and display the error message
+ r>
+ :error_print_loop
+ .fetch+(messages) over 0= .jumpc(error_print_done)
+ swap .outport(O_UART_TX)
+ :error_print_wait .inport(I_UART_TX) .jumpc(error_print_wait)
+ .jump(error_print_loop)
+ :error_print_done
+ drop drop
+
+ :infinite
+ .jump(infinite)
+
Index: i2c/EEPROM/uc/i2c_eeprom.9x8
===================================================================
--- i2c/EEPROM/uc/i2c_eeprom.9x8 (nonexistent)
+++ i2c/EEPROM/uc/i2c_eeprom.9x8 (revision 5)
@@ -0,0 +1,28 @@
+# Copyright 2012, 2014, Sinclair R.F., Inc.
+#
+# Run a TI TMP100 I2C Temperature sensor. Report the temperature once per
+# second over a 9600 baud UART as a hex value.
+
+ARCHITECTURE core/9x8 Verilog
+
+INSTRUCTION 2048
+DATA_STACK 32
+RETURN_STACK 32
+
+MEMORY RAM ram 32
+MEMORY ROM messages 128
+
+PORTCOMMENT I2C bus
+PERIPHERAL open_drain inport=I_SCL \
+ outport=O_SCL \
+ iosignal=io_scl
+PERIPHERAL open_drain inport=I_SDA \
+ outport=O_SDA \
+ iosignal=io_sda
+
+PORTCOMMENT UART_Tx port
+PERIPHERAL UART_Tx outport=O_UART_TX \
+ outstatus=I_UART_TX \
+ baudmethod="100_000_000/115200"
+
+ASSEMBLY i2c_eeprom.s
Index: i2c/TCA9554/Xilinx-SP601/.gitignore
===================================================================
--- i2c/TCA9554/Xilinx-SP601/.gitignore (nonexistent)
+++ i2c/TCA9554/Xilinx-SP601/.gitignore (revision 5)
@@ -0,0 +1,36 @@
+*.bgn
+*.bit
+*.bld
+*.drc
+*.lso
+*.map
+*.mrp
+*.ncd
+*.ngc
+*.ngd
+*.ngm
+*.ngr
+*.pad
+*.par
+*.pcf
+*.prj
+*.ptwx
+*.syr
+*.unroutes
+*.ut
+*.xpi
+*.xrpt
+*.xst
+*.xwbt
+*_pad.csv
+*_pad.txt
+*_summary.xml
+*_usage.xml
+*webtalk*
+_impact.*
+_ngo
+_xmsgs
+log
+par_usage_statistics.html
+xlnx_auto_*_xdb
+xst
Index: i2c/TCA9554/Xilinx-SP601/sp601.ucf
===================================================================
--- i2c/TCA9554/Xilinx-SP601/sp601.ucf (nonexistent)
+++ i2c/TCA9554/Xilinx-SP601/sp601.ucf (revision 5)
@@ -0,0 +1,11 @@
+# 200 MHz external oscillator
+NET "pi_sysclk_p" TNM_NET=pi_sysclk;
+TIMESPEC TS_pi_sysclk = PERIOD "pi_sysclk" 5 ns HIGH 50%;
+
+# pinout
+NET "pi_sysclk_p" LOC = "K15" | IOSTANDARD = "LVDS_25"; # sysclk_p
+NET "pi_sysclk_n" LOC = "K16" | IOSTANDARD = "LVDS_25"; # sysclk_n
+NET "po_usb_1_rx" LOC = "L12" | IOSTANDARD = "LVCMOS25"; # usb_1_rx (rx from USB UART viewpoint, tx from FPGA)
+NET "pi_int" LOC = "F15" | IOSTANDARD = "LVCMOS25"; # GPIO_HDR4 (pin 2 of 2x6 header)
+NET "pio_i2c_scl" LOC = "B4" | IOSTANDARD = "LVCMOS25"; # GPIO_HDR5 (pin 4 of 2x6 header)
+NET "pio_i2c_sda" LOC = "F13" | IOSTANDARD = "LVCMOS25"; # GPIO_HDR6 (pin 6 of 2x6 header)
Index: i2c/TCA9554/Xilinx-SP601/sp601.v
===================================================================
--- i2c/TCA9554/Xilinx-SP601/sp601.v (nonexistent)
+++ i2c/TCA9554/Xilinx-SP601/sp601.v (revision 5)
@@ -0,0 +1,85 @@
+/*******************************************************************************
+ *
+ * Copyright 2012, Sinclair R.F., Inc.
+ *
+ * Top-level module to demonstrate reading four TMP100 I2C temperature sensors
+ * and to display their hex outputs to a console about once per second.
+ *
+ ******************************************************************************/
+
+module sp601(
+ // 200 MHz differential clock
+ input wire pi_sysclk_p,
+ input wire pi_sysclk_n,
+ // I2C bus
+ inout wire pio_i2c_scl,
+ inout wire pio_i2c_sda,
+ // TCA9554 interrupt
+ input wire pi_int,
+ // UART Tx
+ output wire po_usb_1_rx
+);
+
+/*
+ * Generate a 25 MHz clock from the 200 MHz oscillator.
+ * Note: The I2C bus signals don't rise enough with a 100 MHz clock (400 kHz
+ * I2C bus) and are still somewhat marginal even with the 25 MHz clock
+ * (100 kHz I2C bus).
+ */
+
+wire s_sysclk;
+IBUFGDS sysclk_inst(
+ .I (pi_sysclk_p),
+ .IB (pi_sysclk_n),
+ .O (s_sysclk)
+);
+
+wire s_divclk;
+BUFIO2 #(
+ .DIVIDE (8),
+ .DIVIDE_BYPASS ("FALSE")
+) bufio2_inst (
+ .I (s_sysclk),
+ .IOCLK (),
+ .DIVCLK (s_divclk),
+ .SERDESSTROBE ()
+);
+
+wire s_clk;
+BUFG sclk_inst(
+ .I (s_divclk),
+ .O (s_clk)
+);
+
+/*
+ * Generate a synchronous reset.
+ */
+
+reg [3:0] s_reset_count = 4'hF;
+always @ (posedge s_clk)
+ s_reset_count <= s_reset_count - 4'd1;
+
+reg s_rst = 1'b1;
+always @ (posedge s_clk)
+ if (s_reset_count == 4'd0)
+ s_rst <= 1'b0;
+ else
+ s_rst <= s_rst;
+
+/*
+ * Instantiate the micro controller.
+ */
+
+i2c_tca9554 ie_inst(
+ // synchronous reset and processor clock
+ .i_rst (s_rst),
+ .i_clk (s_clk),
+ // TCA9554 interrupt and I2C bus
+ .i_int (pi_int),
+ .io_scl (pio_i2c_scl),
+ .io_sda (pio_i2c_sda),
+ // UART_Tx port
+ .o_uart_tx (po_usb_1_rx)
+);
+
+endmodule
i2c/TCA9554/Xilinx-SP601/sp601.v
Property changes :
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Author Date Id Revision
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: i2c/TCA9554/Xilinx-SP601/make
===================================================================
--- i2c/TCA9554/Xilinx-SP601/make (nonexistent)
+++ i2c/TCA9554/Xilinx-SP601/make (revision 5)
@@ -0,0 +1,199 @@
+#!/bin/sh
+#
+# Make script for SP601 board.
+#
+# Usage:
+# ./make |& tee log
+
+source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+
+# Ensure the script to build the micro processor is present.
+if [ -n "`which ssbcc | sed -n -e '/^which:/p'`" ]; then
+ echo "FATAL ERROR:" > /dev/stderr;
+ echo "Could not find \"ssbcc\" required for build" > /dev/stderr;
+ exit 1;
+fi
+
+#
+# Set the build parameters.
+#
+
+NAME=sp601
+DEVICE=xc6slx16-2-csg324
+
+FILES="";
+FILES+=" ../uc/i2c_tca9554.v";
+FILES+=" ${NAME}.v";
+
+#
+# Prepatory work
+#
+
+# Build the micro processor.
+( cd ../uc; ssbcc --define-clog i2c_tca9554.9x8 ) || { echo "SSBCC failed" > /dev/stderr; exit 1; }
+
+#
+# Configure and run synthesis.
+#
+
+for fname in ${FILES}; do
+ echo "verilog work \"${fname}\"";
+done > ${NAME}.prj;
+
+mkdir -p xst/projnav.tmp;
+
+cat < ${NAME}.xst
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn ${NAME}.prj
+-ifmt mixed
+-ofn ${NAME}
+-ofmt NGC
+-p ${DEVICE}
+-top ${NAME}
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+EOF
+
+xst \
+ -ifn "${NAME}.xst" \
+ -ofn "${NAME}.syr" \
+|| { echo "XST Failed!" > /dev/stderr; exit 1; }
+
+#
+# Run through PAR.
+#
+
+ngdbuild \
+ -dd _ngo \
+ -nt timestamp \
+ -uc ${NAME}.ucf \
+ -p ${DEVICE} \
+ ${NAME}.ngc ${NAME}.ngd \
+|| { echo "ngdbuild Failed!" > /dev/stderr; exit 1; }
+
+map \
+ -p ${DEVICE} \
+ -w \
+ -logic_opt off \
+ -ol high \
+ -t 1 \
+ -xt 0 \
+ -register_duplication off \
+ -r 4 \
+ -global_opt off \
+ -mt off \
+ -ir off \
+ -pr off \
+ -lc off \
+ -power off \
+ -o ${NAME}.ncd \
+ ${NAME}.ngd ${NAME}.pcf \
+|| { echo "MAP Failed!" > /dev/stderr; exit 1; }
+
+par \
+ -w \
+ -ol high \
+ -mt off \
+ ${NAME}.ncd ${NAME}.ncd ${NAME}.pcf \
+|| { echo "PAR Failed!" > /dev/stderr; exit 1; }
+
+#
+# Optionally perform timing analysis.
+#
+
+if false; then
+ trce \
+ -v 3 \
+ -s 3 \
+ -n 3 \
+ -fastpaths \
+ -xml ${NAME}.twx \
+ ${NAME}.ncd \
+ -o ${NAME}.twr \
+ ${NAME}.pcf \
+ -ucf ${NAME}.ucf
+fi
+
+#
+# Generate the bitstream file
+#
+
+cat <${NAME}.ut
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
+EOF
+
+bitgen -f ${NAME}.ut ${NAME}.ncd \
+|| { echo "BITGEN Failed!" > /dev/stderr; exit 1; }
i2c/TCA9554/Xilinx-SP601/make
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: i2c/TCA9554/uc/i2c_tca9554.9x8
===================================================================
--- i2c/TCA9554/uc/i2c_tca9554.9x8 (nonexistent)
+++ i2c/TCA9554/uc/i2c_tca9554.9x8 (revision 5)
@@ -0,0 +1,28 @@
+# Copyright 2014, Sinclair R.F., Inc.
+#
+# Run a TI TCA9554 8-bit I/O exander. Read the 8-bit port when the interrupt is
+# received and report the 8-bit setting over a 9600 baud UART as a hex value.
+
+ARCHITECTURE core/9x8 Verilog
+
+INSTRUCTION 2048
+DATA_STACK 32
+RETURN_STACK 32
+
+PORTCOMMENT TCA9554 interrupt and I2C bus
+INPORT 1-bit i_int \
+ I_INT
+PERIPHERAL open_drain inport=I_SCL \
+ outport=O_SCL \
+ iosignal=io_scl
+PERIPHERAL open_drain inport=I_SDA \
+ outport=O_SDA \
+ iosignal=io_sda
+
+PORTCOMMENT UART port
+PERIPHERAL UART_Tx outsignal=o_uart_tx \
+ outport=O_UART_TX \
+ outstatus=I_UART_TX_BUSY \
+ baudmethod=25_000_000/9600
+
+ASSEMBLY i2c_tca9554.s
Index: i2c/TCA9554/uc/.gitignore
===================================================================
--- i2c/TCA9554/uc/.gitignore (nonexistent)
+++ i2c/TCA9554/uc/.gitignore (revision 5)
@@ -0,0 +1,3 @@
+*.mem
+*.v
+*_pkg.vhd
Index: i2c/TCA9554/uc/i2c_tca9554.s
===================================================================
--- i2c/TCA9554/uc/i2c_tca9554.s (nonexistent)
+++ i2c/TCA9554/uc/i2c_tca9554.s (revision 5)
@@ -0,0 +1,96 @@
+; Copyright 2014, Sinclair R.F., Inc.
+;
+; Notes:
+; - This uses a simple board with 5 on/off switches connected to the TCA9554
+; on pins P0, P1, P2, P4, and P5 and with an LED connected to P3. The 3
+; address pins are held to ground by pull-down resistors.
+; - run in 400 kHz mode
+
+.constant I2C_WR_ADDR 0x40
+.constant I2C_RD_ADDR 0x41
+
+.constant I2C_INPUT 0x00
+.constant I2C_OUTPUT 0x01
+.constant I2C_INVERT 0x02
+.constant I2C_CONFIG 0x03
+
+.include char.s
+
+.include ../../lib_i2c.s
+
+.main
+
+N"\r\nUC Started\r\n" .call(uart_tx)
+
+; Configure P3 as an output. Hang if a NACK is received.
+; Note: bit=0 ==> output, bit=1 ==> input.
+.call(i2c_send_start)
+.call(i2c_send_byte,I2C_WR_ADDR)
+.call(i2c_send_byte,I2C_CONFIG) or
+.call(i2c_send_byte,0xF7) or
+.call(i2c_send_stop)
+.jumpc(hang)
+
+; Configure P3 with a low signal to turn on the LED. Hang if a NACK is received.
+.call(i2c_send_start)
+.call(i2c_send_byte,I2C_WR_ADDR)
+.call(i2c_send_byte,I2C_OUTPUT) or
+.call(i2c_send_byte,0xF7) or
+.call(i2c_send_stop)
+.jumpc(hang)
+
+; Push the current state onto the data stack.
+.call(read_state)
+
+:infinite
+
+ ; Wait for the interrupt.
+ ; Note: This is disabled because the interrupt line either goes low for a
+ ; long time or goes low for a very short time. The observed behavior
+ ; is not consistent with the data sheet.
+ ; :wait_for_interrupt .inport(I_INT) 0= .jumpc(wait_for_interrupt)
+
+ ; Read the device state until it changes and then display the new value.
+ :wait_change .call(read_state) swap over - 0= .jumpc(wait_change)
+ >r N"\r\n" r@ .call(char__byte_to_2hex) .call(uart_tx) r>
+
+.jump(infinite)
+
+; Error stack for NACK failure.
+:hang
+ N"NACK received\r\n" .call(uart_tx)
+ :in_hang .jump(in_hang)
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; Read the switch settings.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; ( - u )
+.function read_state
+ .call(i2c_send_start)
+ .call(i2c_send_byte,I2C_WR_ADDR) drop
+ .call(i2c_send_byte,I2C_INPUT) drop
+ .call(i2c_send_restart)
+ .call(i2c_send_byte,I2C_RD_ADDR) drop
+ .call(i2c_read_byte,1)
+ .return
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; Output the null terminated string on the data stack.
+;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; ( '\0' u ... u - )
+.function uart_tx
+ :loop
+ ; Wait for the UART to not be busy (there is no output FIFO).
+ .inport(I_UART_TX_BUSY) .jumpc(loop)
+ ; Send the next character
+ .outport(O_UART_TX)
+ ; Continue the loop if the next character is not the null character.
+ .jumpc(loop,nop)
+ ; Return and drop the terminating null character.
+ .return(drop)
Index: i2c/TCA9554/README
===================================================================
--- i2c/TCA9554/README (nonexistent)
+++ i2c/TCA9554/README (revision 5)
@@ -0,0 +1,12 @@
+TI's TCA9554 is an 8-bit I2C I/O expander.
+
+This example demonstrates how to use the I2C library with this chip.
+
+Directories
+================================================================================
+uc Micro controller
+Xilinx-SP601 Xilinx Spartan-6 Eval board
+ uses the J13 GPIO header for the I2C SCL and SDA signals,
+ the TCA9554 interrupt signal, 3.3V power, and GND.
+ Note: The 3.3V power is OK because the Spartan-6 LVCMOS25 I/Os
+ are 4.1V tolerant.