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Rev 9 → Rev 10

/trunk/basic_system/software/lib/storm_soc_basic.h
0,0 → 1,161
#ifndef storm_soc_basic_h
#define storm_soc_basic_h
 
/////////////////////////////////////////////////////////////////
// storm_soc_basic.h - STORM SoC Basic Configuration
// Based on the STORM Core Processor System
//
// Created by Stephan Nolting (stnolting@googlemail.com)
// http://www.opencores.com/project,storm_core
// http://www.opencores.com/project,storm_soc
// Last modified 15. May 2012
/////////////////////////////////////////////////////////////////
 
#define REG32 (volatile unsigned long*)
 
/* Internal RAM */
#define IRAM_BASE (*(REG32 (0x00000000)))
#define IRAM_SIZE 32*1024
 
/* External RAM */
#define XRAM_BASE (*(REG32 (0x00002000)))
#define XRAM_SIZE 0//32*1024*1024
 
/* Complete RAM */
#define RAM_BASE (*(REG32 (0x00000000)))
#define RAM_SIZE IRAM_SIZE + XRAM_SIZE
 
/* Internal ROM (boot ROM) */
#define ROM_BASE (*(REG32 (0xFFF00000)))
#define ROM_SIZE 8*1024
 
/* De-Cached IO Area */
#define IO_AREA_BEGIN (*(REG32 (0xFFFF0000)))
#define IO_AREA_END (*(REG32 (0xFFFFFFFF)))
#define IO_AREA_SIZE 524288;
 
/* General Purpose IO Controller 0 */
#define GPIO0_BASE (*(REG32 (0xFFFF0000)))
#define GPIO0_SIZE 2*4
#define GPIO0_OUT (*(REG32 (0xFFFF0000)))
#define GPIO0_IN (*(REG32 (0xFFFF0004)))
 
/* UART 0 - miniUART */
#define UART0_BASE (*(REG32 (0xFFFF0018)))
#define UART0_SIZE 2*4
#define UART0_DATA (*(REG32 (0xFFFF0018)))
#define UART0_SREG (*(REG32 (0xFFFF001C)))
 
/* Mini UART */
#define CUART_TXB 0 // transmitter busy
#define CUART_RXD 1 // byte available
 
/* System Timer 0 */
#define STME0_BASE (*(REG32 (0xFFFF0020)))
#define STME0_SIZE 4*4
#define STME0_CNT (*(REG32 (0xFFFF0020)))
#define STME0_VAL (*(REG32 (0xFFFF0024)))
#define STME0_CONF (*(REG32 (0xFFFF0028)))
#define STME0_SCRT (*(REG32 (0xFFFF002C)))
 
/* SPI Controller 0 */
#define SPI0_BASE (*(REG32 (0xFFFF0030)))
#define SPI0_SIZE 8*4
#define SPI0_CONF (*(REG32 (0xFFFF0030)))
#define SPI0_PRSC (*(REG32 (0xFFFF0034)))
#define SPI0_SCSR (*(REG32 (0xFFFF0038)))
// unused location (*(REG32 (0xFFFF003C)))
#define SPI0_DAT0 (*(REG32 (0xFFFF0040)))
#define SPI0_DAT1 (*(REG32 (0xFFFF0044)))
#define SPI0_DAT2 (*(REG32 (0xFFFF0048)))
#define SPI0_DAT3 (*(REG32 (0xFFFF004C)))
 
/* Serial Peripherial Interface Controller 0 */
#define SPI_BUSY 8 // spi busy
#define SPI_RX_NEG 9 // load miso on falling edge of sclk
#define SPI_TX_NEG 10 // change mosi on falling edge of sclk
#define SPI_ACS 13 // manual/auto assert cs
 
 
#define I2C0_BASE (*(REG32 (0xFFFF0050)))
#define I2C0_SIZE 8*4
#define I2C0_CMD (*(REG32 (0xFFFF0050)))
#define I2C0_STAT (*(REG32 (0xFFFF0050)))
// unused location (*(REG32 (0xFFFF0054)))
// unused location (*(REG32 (0xFFFF0058)))
// unused location (*(REG32 (0xFFFF005C)))
#define I2C0_PRLO (*(REG32 (0xFFFF0060)))
#define I2C0_PRHI (*(REG32 (0xFFFF0064)))
#define I2C0_CTRL (*(REG32 (0xFFFF0068)))
#define I2C0_DATA (*(REG32 (0xFFFF006C)))
 
 
#define I2C_EN 7 // enable core
 
#define I2C_STA 7 // generate start condition
#define I2C_STO 6 // generate stop condition
#define I2C_RD 5 // read
#define I2C_WR 4 // write
#define I2C_ACK 3 // acknowledge
#define I2C_IACK 0 // interrupt ack
 
#define I2C_RXACK 7 // ack from slave received
#define I2C_BUSY 6 // i2c busy
#define I2C_TIP 1 // transfer in progress
 
/* PWM Controller 0 */
#define PWM0_BASE (*(REG32 (0xFFFF0070)))
#define PWM0_SIZE 2*4
#define PWM0_CONF0 (*(REG32 (0xFFFF0070)))
#define PWM0_CONF1 (*(REG32 (0xFFFF0074)))
 
/* Vector Interrupt Controller */
#define VIC_BASE (*(REG32 (0xFFFFF000)))
#define VIC_SIZE 64*4
#define VICIRQStatus (*(REG32 (0xFFFFF000)))
#define VICFIQStatus (*(REG32 (0xFFFFF004)))
#define VICRawIntr (*(REG32 (0xFFFFF008)))
#define VICIntSelect (*(REG32 (0xFFFFF00C)))
#define VICIntEnable (*(REG32 (0xFFFFF010)))
#define VICIntEnClear (*(REG32 (0xFFFFF014)))
#define VICSoftInt (*(REG32 (0xFFFFF018)))
#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
#define VICProtection (*(REG32 (0xFFFFF020)))
#define VICVectAddr (*(REG32 (0xFFFFF030)))
#define VICDefVectAddr (*(REG32 (0xFFFFF034)))
#define VICTrigLevel (*(REG32 (0xFFFFF038)))
#define VICTrigMode (*(REG32 (0xFFFFF03C)))
#define VICVectAddr0 (*(REG32 (0xFFFFF040)))
#define VICVectAddr1 (*(REG32 (0xFFFFF044)))
#define VICVectAddr2 (*(REG32 (0xFFFFF048)))
#define VICVectAddr3 (*(REG32 (0xFFFFF04C)))
#define VICVectAddr4 (*(REG32 (0xFFFFF050)))
#define VICVectAddr5 (*(REG32 (0xFFFFF054)))
#define VICVectAddr6 (*(REG32 (0xFFFFF058)))
#define VICVectAddr7 (*(REG32 (0xFFFFF05C)))
#define VICVectAddr8 (*(REG32 (0xFFFFF060)))
#define VICVectAddr9 (*(REG32 (0xFFFFF064)))
#define VICVectAddr10 (*(REG32 (0xFFFFF068)))
#define VICVectAddr11 (*(REG32 (0xFFFFF06C)))
#define VICVectAddr12 (*(REG32 (0xFFFFF070)))
#define VICVectAddr13 (*(REG32 (0xFFFFF074)))
#define VICVectAddr14 (*(REG32 (0xFFFFF078)))
#define VICVectAddr15 (*(REG32 (0xFFFFF07C)))
#define VICVectCntl0 (*(REG32 (0xFFFFF080)))
#define VICVectCntl1 (*(REG32 (0xFFFFF084)))
#define VICVectCntl2 (*(REG32 (0xFFFFF088)))
#define VICVectCntl3 (*(REG32 (0xFFFFF08C)))
#define VICVectCntl4 (*(REG32 (0xFFFFF090)))
#define VICVectCntl5 (*(REG32 (0xFFFFF094)))
#define VICVectCntl6 (*(REG32 (0xFFFFF098)))
#define VICVectCntl7 (*(REG32 (0xFFFFF09C)))
#define VICVectCntl8 (*(REG32 (0xFFFFF0A0)))
#define VICVectCntl9 (*(REG32 (0xFFFFF0A4)))
#define VICVectCntl10 (*(REG32 (0xFFFFF0A8)))
#define VICVectCntl11 (*(REG32 (0xFFFFF0AC)))
#define VICVectCntl12 (*(REG32 (0xFFFFF0B0)))
#define VICVectCntl13 (*(REG32 (0xFFFFF0B4)))
#define VICVectCntl14 (*(REG32 (0xFFFFF0B8)))
#define VICVectCntl15 (*(REG32 (0xFFFFF0BC)))
 
#endif // storm_soc_basic_h
/trunk/basic_system/software/lib/uart.h
0,0 → 1,11
#ifndef _UART_H_
#define _UART_H_
 
// Prototypes
const char *uart0_printf(const char *string);
 
void uart0_scanf(unsigned char *buffer, int length, unsigned char en_echo);
 
void uart0_print_buffer(unsigned char *buffer, int size);
 
#endif // _UART_H_
/trunk/basic_system/software/lib/utilities.h
0,0 → 1,13
#ifndef _UTILITIES_H_
#define _UTILITIES_H_
 
// Signals
#define adc_cs 6
 
// Prototypes
void long_to_hex_string(unsigned long data, unsigned char *buffer, unsigned char numbers);
unsigned int get_adc(int adc_index);
void delay(int time);
unsigned char string_cmpc(unsigned char *string1, const char *string2, unsigned char length);
 
#endif // _UTILITIES_H_
/trunk/basic_system/software/lib/storm_core.h
0,0 → 1,67
#ifndef storm_core_h
#define storm_core_h
 
////////////////////////////////////////////////////////////////////////////////
// storm_core.h - STORM Core internal definitions
//
// Created by Stephan Nolting (stnolting@googlemail.com)
// http://www.opencores.com/project,storm_core
// Last modified 11. Apr. 2012
////////////////////////////////////////////////////////////////////////////////
 
/* Processor Mode Definitions */
#define USR_MODE 0x10
#define FIQ_MODE 0x11
#define IRQ_MODE 0x12
#define SVP_MODE 0x13
#define ABT_MODE 0x17
#define UND_MODE 0x1B
#define SYS_MODE 0x1F
 
/* Current Machine Status Register */
#define CMSR_MODE_0 0 // status code / operating mode
#define CMSR_MODE_1 1
#define CMSR_MODE_2 2
#define CMSR_MODE_3 3
#define CMSR_MODE_4 4
#define CMSR_SHIN 5 // short instruction format
#define CMSR_FIQ 6 // fast int request enable
#define CMSR_IRQ 7 // int request enable
#define CMSR_DAB 8 // data abort enable
#define CMSR_IAB 9 // instruction abort enable
#define CMSR_O 28 // overflow flag
#define CMSR_C 29 // carry flag
#define CMSR_Z 30 // zero flag
#define CMSR_N 31 // negative flag
 
/* Internal System Coprocessor Register Set */
#define SYS_CP 15 // system coprocessor #
#define ID_REG_0 0 // ID register 0
#define ID_REG_1 1 // ID register 1
#define ID_REG_2 2 // ID register 2
#define SYS_CTRL_0 6 // system control register 0
#define CSTAT 8 // cache statistics register
#define ADR_FB 9 // adr feedback from bus unit -> for exception analysis
#define LFSR_POLY 11 // Internal LFSR, polynomial
#define LFSR_DATA 12 // Internal LFSR, shift register
#define SYS_IO 13 // System IO ports
 
/* CP_SYS_CTRL_0 */
#define DC_FLUSH 0 // flush d-cache
#define DC_CLEAR 1 // clear d-cache
#define IC_CLEAR 2 // flush i-cache
#define DC_WTHRU 3 // cache write-thru enable
#define DC_AUTOPR 4 // auto pre-reload d-cache page
#define IC_AUTOPR 5 // auto pre-reload i-cache page
#define CACHED_IO 6 // cached IO
#define PRTC_IO 7 // protected IO
#define DC_SYNC 8 // d-cache is sync
#define LFSR_EN 13 // enable lfsr
#define LFSR_M 14 // lfsr update mode
#define LFSR_D 15 // lfsr shift direction
#define MBC_0 16 // max bus cycle length bit 0
#define MBC_LSB 16
#define MBC_15 31 // max bus cycle length bit 15
#define MBC_MSB 31
 
#endif // storm_core_h
/trunk/basic_system/software/lib/io_driver.c
0,0 → 1,458
#include "io_driver.h"
#include "storm_core.h"
#include "storm_soc_basic.h"
 
// ###########################################################################################################################
// General Purpose IO (GENERAL_PURPOSE_CONTROLLER_0)
// ###########################################################################################################################
 
// ******************************************************************************
// Read general purpose IO pin
unsigned long io_read_gpio0_pin(unsigned char pin)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
unsigned long temp = GPIO0_IN & (1<<pin);
// set_cmsr(_cmsr);
return temp;
}
 
// ******************************************************************************
// Read general purpose IO port
unsigned long io_read_gpio0_port(void)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
unsigned long temp = GPIO0_IN;
 
// set_cmsr(_cmsr);
return temp;
}
 
// ******************************************************************************
// Set general purpose IO port
void io_set_gpio0_pin(unsigned char pin)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
GPIO0_OUT = GPIO0_OUT | (1<<pin);
 
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Clear general purpose IO port
void io_clr_gpio0_pin(unsigned char pin)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
GPIO0_OUT = GPIO0_OUT & ~(1<<pin);
 
// set_cmsr(_cmsr);
}
// ******************************************************************************
// Set general purpose IO port
void io_toggle_gpio0_pin(unsigned char pin)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
GPIO0_OUT = GPIO0_OUT ^ (1<<pin);
 
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Clear general purpose IO port
void io_set_gpio0_port(unsigned long value)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
GPIO0_OUT = value;
 
// set_cmsr(_cmsr);
}
 
 
 
// ###########################################################################################################################
// Pulse-Width-Modulation Controller
// ###########################################################################################################################
 
// ******************************************************************************
// Set pwm value
void io_set_pwm(unsigned char port, unsigned char data)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
unsigned long temp = 0;
 
// value adjustment
if(port > 7)
port = 0;
 
if(port < 4){
temp = PWM0_CONF0; // get working copy
temp = temp & ~(0xFF << (port*8)); // clear old value
temp = temp | (unsigned long)(data << (port*8)); // insert new value
PWM0_CONF0 = temp;
}
else{
port = port-4;
temp = PWM0_CONF1; // get working copy
temp = temp & ~(0xFF << (port*8)); // clear old value
temp = temp | (unsigned long)(data << (port*8)); // insert new value
PWM0_CONF1 = temp;
}
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Set pwm value
unsigned char io_get_pwm(unsigned char port)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
unsigned long temp = 0;
 
// value adjustment
if(port > 7)
port = 0;
 
if(port < 4)
temp = PWM0_CONF0; // get config register
else{
port = port-4;
temp = PWM0_CONF1; // get config register
}
 
temp = temp >> (port*8); // only keep designated byte
 
// set_cmsr(_cmsr);
return (unsigned char)temp;
}
 
 
 
// ###########################################################################################################################
// General Purpose UART "miniUART" (UART_0)
// ###########################################################################################################################
 
// ******************************************************************************
// Read one byte via UART 0
int io_uart0_read_byte(void)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
int temp;
if ((UART0_SREG & (1<<CUART_RXD)) != 0) // byte available?
temp = UART0_DATA;
else
temp = -1;
 
// set_cmsr(_cmsr);
return temp;
}
 
// ******************************************************************************
// Write one byte via UART 0
int io_uart0_send_byte(int ch)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
while((UART0_SREG & (1<<CUART_TXB)) == 0); // uart busy?
UART0_DATA = (ch & 0x000000FF);
 
// set_cmsr(_cmsr);
return ch;
}
 
 
 
// ###########################################################################################################################
// Serial Peripherial Interface (SPI_CONTROLLER_0)
// ###########################################################################################################################
 
// ******************************************************************************
// Configure SPI 0
void io_spi0_config(unsigned char auto_cs, unsigned long data_size)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
// devices update their serial input on a rising edge of sclk,
// so we need to update the mosi output of the core before
// -> at the falling edge of sclk = set SPI_TX_NEG
if(auto_cs == 1)
SPI0_CONF = (1<<SPI_ACS) | (1<<SPI_TX_NEG) | data_size; // auto assert cs
else
SPI0_CONF = (0<<SPI_ACS) | (1<<SPI_TX_NEG) | data_size; // manual assert cs
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Configure SPI 0 CLK frequency -> (sys_clk/(spi_clk*2))-1
void io_spi0_speed(unsigned long clk_divider)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
SPI0_PRSC = clk_divider; // (sys_clk/(spi_clk*2))-1;
 
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Sends/receives max 32 bits via SPI, CS and config must be done outside
unsigned long io_spi0_trans(unsigned long data)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
// spi transmission
while((SPI0_CONF & (1<<SPI_BUSY)) != 0); // wait for prev tx to finish
SPI0_DAT0 = data;
SPI0_CONF = SPI0_CONF | (1<<SPI_BUSY); // start transmitter
while((SPI0_CONF & (1<<SPI_BUSY)) != 0); // wait for rx to finish
unsigned long temp = SPI0_DAT0;
 
// set_cmsr(_cmsr);
return temp;
}
 
// ******************************************************************************
// Controls the CS of SPI0, enables a connected CS (turns it LOW)
void io_spi0_enable(unsigned char device)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
SPI0_SCSR = SPI0_SCSR | (1<<device);
 
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Controls the CS of SPI0, disables a connected CS (turns it HIGH)
void io_spi0_disable(unsigned char device)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
SPI0_SCSR = SPI0_SCSR & ~(1<<device);
 
// set_cmsr(_cmsr);
}
 
 
 
 
// ###########################################################################################################################
 
// ###########################################################################################################################
 
// ******************************************************************************
// Configure SPI 0 CLK frequency -> (sys_clk/(5*i2c_clock)-1
void io_i2c0_speed(unsigned long clk_divider)
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
I2C0_CTRL = I2C0_CTRL & ~(1<<I2C_EN); // disable i2c core
I2C0_PRLO = clk_divider;
I2C0_PRHI = clk_divider >> 8;
I2C0_CTRL = I2C0_CTRL | (1<<I2C_EN); // enable i2c core
// set_cmsr(_cmsr);
}
 
// ******************************************************************************
 
int io_i2c0_byte_transfer(unsigned char rw, // 'r' read / 'w' write cycle
unsigned char id, // device ID
unsigned long data_adr, // data address
unsigned char adr_bytes, // number of adr bytes
unsigned char data) // data byte
// ******************************************************************************
{
// unsigned long _cmsr = get_cmsr();
// set_cmsr(_cmsr | (1<<CMSR_IRQ) | (1<<CMSR_FIQ));
 
// transfer slave identification address
I2C0_DATA = id & 0xFE; // device id and write
I2C0_CMD = (1<<I2C_STA) | (1<<I2C_WR); // start condition and write cycle
while((I2C0_STAT & (1<<I2C_TIP)) != 0); // wait for transfer to finish
if((I2C0_STAT & (1<<I2C_RXACK)) != 0){ // ack received?
// set_cmsr(_cmsr);
return -1;
}
 
// transfer data address
while(adr_bytes != 0){
adr_bytes--;
if(adr_bytes == 1)
I2C0_DATA = data_adr >> 8; // high byte
else
I2C0_DATA = data_adr; // low byte
I2C0_CMD = (1<<I2C_WR); // write cycle
while((I2C0_STAT & (1<<I2C_TIP)) != 0); // wait for transfer to finish
if((I2C0_STAT & (1<<I2C_RXACK)) != 0){ // ack received?
// set_cmsr(_cmsr);
return -2;
}
}
 
if(rw == 'w'){
// write adressed byte
I2C0_DATA = data; // send data
I2C0_CMD = (1<<I2C_STO) | (1<<I2C_WR); // stop condition and write cycle
while((I2C0_STAT & (1<<I2C_TIP)) != 0); // wait for transfer to finish
if((I2C0_STAT & (1<<I2C_RXACK)) != 0){ // ack received?
// set_cmsr(_cmsr);
return -3;
}
else{
// set_cmsr(_cmsr);
return 0;
}
}
 
if(rw == 'r'){
// re-send control byte - this time with read-bit
I2C0_DATA = id | 0x01; // device id and READ
I2C0_CMD = (1<<I2C_STA) | (1<<I2C_WR); // start condition and write cycle
while((I2C0_STAT & (1<<I2C_TIP)) != 0); // wait for transfer to finish
if((I2C0_STAT & (1<<I2C_RXACK)) != 0){ // ack received?
// set_cmsr(_cmsr);
return -3;
}
// read adressed byte
I2C0_CMD = (1<<I2C_STO) | (1<<I2C_RD) | (1<<I2C_ACK);
while((I2C0_STAT & (1<<I2C_TIP)) != 0); // wait for transfer to finish
return I2C0_DATA;
}
 
// set_cmsr(_cmsr);
return -4;
}
 
 
 
 
// ###########################################################################################################################
// System
// ###########################################################################################################################
 
// ******************************************************************************
// read system coprocessor register x
unsigned long get_syscpreg(unsigned char index)
// ******************************************************************************
{
unsigned long _cp_val;
switch(index){
case ID_REG_0: asm volatile ("mrc p15,0,%0, c0, c0" : "=r" (_cp_val) : /* no inputs */ ); break;
case ID_REG_1: asm volatile ("mrc p15,0,%0, c1, c1" : "=r" (_cp_val) : /* no inputs */ ); break;
case ID_REG_2: asm volatile ("mrc p15,0,%0, c2, c2" : "=r" (_cp_val) : /* no inputs */ ); break;
case 3: asm volatile ("mrc p15,0,%0, c3, c3" : "=r" (_cp_val) : /* no inputs */ ); break;
case 4: asm volatile ("mrc p15,0,%0, c4, c4" : "=r" (_cp_val) : /* no inputs */ ); break;
case 5: asm volatile ("mrc p15,0,%0, c5, c5" : "=r" (_cp_val) : /* no inputs */ ); break;
case SYS_CTRL_0: asm volatile ("mrc p15,0,%0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); break;
case 7: asm volatile ("mrc p15,0,%0, c7, c7" : "=r" (_cp_val) : /* no inputs */ ); break;
case CSTAT: asm volatile ("mrc p15,0,%0, c8, c8" : "=r" (_cp_val) : /* no inputs */ ); break;
case ADR_FB: asm volatile ("mrc p15,0,%0, c9, c9" : "=r" (_cp_val) : /* no inputs */ ); break;
case 10: asm volatile ("mrc p15,0,%0,c10,c10" : "=r" (_cp_val) : /* no inputs */ ); break;
case LFSR_POLY: asm volatile ("mrc p15,0,%0,c11,c11" : "=r" (_cp_val) : /* no inputs */ ); break;
case LFSR_DATA: asm volatile ("mrc p15,0,%0,c12,c12" : "=r" (_cp_val) : /* no inputs */ ); break;
case SYS_IO: asm volatile ("mrc p15,0,%0,c13,c13" : "=r" (_cp_val) : /* no inputs */ ); break;
case 14: asm volatile ("mrc p15,0,%0,c14,c14" : "=r" (_cp_val) : /* no inputs */ ); break;
case 15: asm volatile ("mrc p15,0,%0,c15,c15" : "=r" (_cp_val) : /* no inputs */ ); break;
default: _cp_val = 0; break;
}
return _cp_val;
}
 
// ******************************************************************************
// write system coprocessor register x
void set_syscpreg(unsigned long _cp_val, unsigned char index)
// ******************************************************************************
{
switch(index){
// case ID_REG_0: asm volatile ("mcr p15,0,%0, c0, c0,0" : /* no outputs */ : "r" (_cp_val)); break;
// case ID_REG_1: asm volatile ("mcr p15,0,%0, c1, c1,0" : /* no outputs */ : "r" (_cp_val)); break;
// case ID_REG_2: asm volatile ("mcr p15,0,%0, c2, c2,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 3: asm volatile ("mcr p15,0,%0, c3, c3,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 4: asm volatile ("mcr p15,0,%0, c4, c4,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 5: asm volatile ("mcr p15,0,%0, c5, c5,0" : /* no outputs */ : "r" (_cp_val)); break;
case SYS_CTRL_0: asm volatile ("mcr p15,0,%0, c6, c6,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 7: asm volatile ("mcr p15,0,%0, c7, c7,0" : /* no outputs */ : "r" (_cp_val)); break;
// case CSTAT: asm volatile ("mcr p15,0,%0, c8, c8,0" : /* no outputs */ : "r" (_cp_val)); break;
// case ADR_FB: asm volatile ("mcr p15,0,%0, c9, c9,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 10: asm volatile ("mcr p15,0,%0,c10,c10,0" : /* no outputs */ : "r" (_cp_val)); break;
case LFSR_POLY: asm volatile ("mcr p15,0,%0,c11,c11,0" : /* no outputs */ : "r" (_cp_val)); break;
case LFSR_DATA: asm volatile ("mcr p15,0,%0,c12,c12,0" : /* no outputs */ : "r" (_cp_val)); break;
case SYS_IO: asm volatile ("mcr p15,0,%0,c13,c13,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 14: asm volatile ("mcr p15,0,%0,c14,c14,0" : /* no outputs */ : "r" (_cp_val)); break;
// case 15: asm volatile ("mcr p15,0,%0,c15,c15,0" : /* no outputs */ : "r" (_cp_val)); break;
default: break;
}
}
// ******************************************************************************
// read CMSR value
static inline unsigned long get_cmsr(void)
// ******************************************************************************
{
unsigned long _cmsr;
asm volatile (" mrs %0, cpsr" : "=r" (_cmsr) : /* no inputs */ );
return _cmsr;
}
 
// ******************************************************************************
// write CMSR value
static inline void set_cmsr(unsigned long _cmsr)
// ******************************************************************************
{
asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cmsr) );
}
 
// ******************************************************************************
// Enable all external INTs
void io_enable_xint(void)
// ******************************************************************************
{
unsigned long _cmsr = get_cmsr();
_cmsr = _cmsr & ~(1<<CMSR_FIQ) &~(1<<CMSR_IRQ);
set_cmsr(_cmsr);
}
 
// ******************************************************************************
// Disable all global IBTs
void io_disable_xint(void)
// ******************************************************************************
{
unsigned long _cmsr = get_cmsr();
_cmsr = _cmsr | (1<<CMSR_FIQ) | (1<<CMSR_IRQ);
set_cmsr(_cmsr);
}
/trunk/basic_system/software/lib/io_driver.h
0,0 → 1,44
#ifndef _IO_DRIVER_H_
#define _IO_DRIVER_H_
 
// System parameters
#define clk_speed 50000000 // 50MHz
 
// Prototypes
 
/* -- IO CTRL 0 -- */
unsigned long io_read_gpio0_pin(unsigned char pin);
unsigned long io_read_gpio0_port(void);
void io_set_gpio0_pin(unsigned char pin);
void io_clr_gpio0_pin(unsigned char pin);
void io_toggle_gpio0_pin(unsigned char pin);
void io_set_gpio0_port(unsigned long value);
 
/* -- PWM CTRL 0 -- */
void io_set_pwm(unsigned char port, unsigned char data);
unsigned char io_get_pwm(unsigned char port);
 
/* -- UART 0 -- */
int io_uart0_read_byte(void);
int io_uart0_send_byte(int ch);
 
/* -- SPI 0 -- */
void io_spi0_config(unsigned char auto_cs, unsigned long data_size);
void io_spi0_speed(unsigned long clk_divider);
unsigned long io_spi0_trans(unsigned long data);
void io_spi0_enable(unsigned char device);
void io_spi0_disable(unsigned char device);
 
 
void io_i2c0_speed(unsigned long clk_divider);
int io_i2c0_byte_transfer(unsigned char rw, unsigned char id, unsigned long data_adr, unsigned char adr_bytes, unsigned char data);
 
/* -- System -- */
unsigned long get_syscpreg(unsigned char index);
void set_syscpreg(unsigned long _cp_val, unsigned char index);
static inline unsigned long get_cmsr(void);
static inline void set_cmsr(unsigned long _cpsr);
void io_enable_xint(void);
void io_disable_xint(void);
 
#endif // _IO_DRIVER_H_
/trunk/basic_system/software/lib/uart.c
0,0 → 1,48
#include "uart.h"
 
// ############################################################################################
// Print text string via UART 0
const char *uart0_printf(const char *string)
// ############################################################################################
{
char ch;
 
while ((ch = *string)){
if (io_uart0_send_byte(ch)<=0)
break;
string++;
}
return string;
}
 
// ############################################################################################
// Read text string via UART 0
void uart0_scanf(unsigned char *buffer, int length, unsigned char en_echo)
// ############################################################################################
{
int temp = 0;
 
while(length > 0){
temp = io_uart0_read_byte();
if(temp != -1){
temp = (unsigned char)(temp & 0x000000FF);
*buffer++ = temp;
if(en_echo == 1)
io_uart0_send_byte(temp); // echo
length--;
}
}
}
 
// ############################################################################################
// Print character buffer via UART 0
void uart0_print_buffer(unsigned char *buffer, int size)
// ############################################################################################
{
unsigned char char_buffer = 0;
while(size > 0){
char_buffer = *buffer++;
io_uart0_send_byte((int)char_buffer);
size--;
}
}
/trunk/basic_system/software/lib/utilities.c
0,0 → 1,83
#include "utilities.h"
 
// ############################################################################################
// Convert 4/8/12/16/20/24/28/32 bit hexadecimal value to ASCII string
void long_to_hex_string(unsigned long data, // max 32 bit data word
unsigned char *buffer, // buffer to store the string
unsigned char numbers) // number of places, max 8
// ############################################################################################
{
unsigned char temp_char = 0;
unsigned long temp_data = 0;
 
// fit into range
if(numbers > 8)
numbers = 8;
if(numbers < 1)
numbers = 1;
 
while(numbers > 0){
// isolate one 4-bit value
if(numbers > 1)
temp_data = data >> ((numbers-1)*4);
else
temp_data = data;
temp_data = temp_data & 0x0000000F;
numbers--;
 
// convert 4-bit value temp_data to char temp_char
if(temp_data < 10)
temp_char = '0' + temp_data;
else
temp_char = 'A' + temp_data - 10;
 
// save character
*buffer++ = temp_char;
}
 
*buffer++ = 0; // terminate string
}
 
// ############################################################################################
// read external ADC value
unsigned int get_adc(int adc_index) // adc 0..7
// ############################################################################################
{
unsigned long temp;
 
if ((adc_index < 0) || (adc_index > 7))
return 0;
 
// config spi
io_spi0_config(1,16); // auto assert cs, 16 bit transfer
io_spi0_enable(adc_cs);
 
temp = adc_index * 2048;
io_spi0_trans(0); // dummy read
return (unsigned int)io_spi0_trans(temp);
}
 
// ############################################################################################
// simple delay routine
void delay(int time) // waits time*10000 clock ticks
// ############################################################################################
{
time = time*2500*4;
while(time > 0){
asm volatile ("NOP");
time--;
}
}
 
// ############################################################################################
// String compare, buffered string with immediate const char string
unsigned char string_cmpc(unsigned char *string1, const char *string2, unsigned char length)
// ############################################################################################
{
while(length != 0){
if(*string1++ != (unsigned char)*string2++)
return(0); // missmatch
length--;
}
return(1); // match
}
/trunk/basic_system/software/demo_program/utilities.c File deleted

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