URL https://opencores.org/ocsvn/storm_soc/storm_soc/trunk

Subversion Repositories storm_soc

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```
/storm_soc
```
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Rev 2 → Rev 3

/trunk/components/boot rom/rtl/BOOT_ROM_FILE.vhd

54,347 → 54,338

/trunk/doc/STORM SoC - Altera DE2-Board Implementation.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/implementations/Altera DE2 Board/rtl/STORM_SoC_DE2.vhd

0,0 → 1,1280

/trunk/implementations/Altera DE2 Board/rtl/STORM_SoC_DE2_TB.vhd

0,0 → 1,141

/trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.pof Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.pof

trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.pof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.sof =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.sof =================================================================== --- trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.sof (nonexistent) +++ trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.sof (revision 3)

trunk/implementations/Altera DE2 Board/syn/storm_soc_de2.sof Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.S =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.S (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.S (revision 3) @@ -0,0 +1,175 @@ + .global main // int main(void) + + .global _etext // -> .data initial values in ROM + .global _data // -> .data area in RAM + .global _edata // end of .data area + .global __bss_start // -> .bss area in RAM + .global __bss_end__ // end of .bss area + .global _stack // top of stack + +// Stack Sizes + .set UND_STACK_SIZE, 0x00000080 + .set ABT_STACK_SIZE, 0x00000080 + .set FIQ_STACK_SIZE, 0x00000080 + .set IRQ_STACK_SIZE, 0X00000080 + .set SVC_STACK_SIZE, 0x00000080 + +// Standard definitions of Mode bits and Interrupt flags in MSRs + .set MODE_USR, 0x10 // User Mode + .set MODE_FIQ, 0x11 // FIQ Mode + .set MODE_IRQ, 0x12 // IRQ Mode + .set MODE_SVC, 0x13 // Supervisor Mode + .set MODE_ABT, 0x17 // Abort Mode + .set MODE_UND, 0x1B // Undefined Mode + .set MODE_SYS, 0x1F // System Mode + + .equ FIQ_BIT, 0x40 // when FIQ bit is set, FIQ is disabled + .equ IRQ_BIT, 0x80 // when IRQ bit is set, IRQ is disabled + + .text + .code 32 + .align 2 + + .global _boot + .func _boot +_boot: + +// Runtime Interrupt Vectors +// ------------------------------------------------------------------- +Vectors: + b _start // reset - _start + ldr pc,_undf // undefined - _undf + ldr pc,_swi // SWI - _swi + ldr pc,_pabt // program abort - _pabt + ldr pc,_dabt // data abort - _dabt + nop // reserved + ldr pc,[pc,#-0xFF0] // IRQ - read the VIC + ldr pc,_fiq // FIQ - _fiq + + +// Use this group for development +_undf: .word __undf // undefined +_swi: .word __swi // SWI +_pabt: .word __pabt // program abort +_dabt: .word __dabt // data abort +_irq: .word __irq // IRQ +_fiq: .word __fiq // FIQ + +__undf: b . // undefined +__swi: b . // SWI +__pabt: b . // program abort +__dabt: b . // data abort +__irq: b . // IRQ +__fiq: b . // FIQ + + .size _boot, . - _boot + .endfunc + + +// Setup the operating mode & stack. +// ------------------------------------------------------------------- + .global _start, start, _mainCRTStartup + .func _start + +_start: +start: +_mainCRTStartup: + +// Who am I? Where am I going? + +// Initialize Interrupt System +// - Set stack location for each mode +// - Leave in System Mode with Interrupts Disabled +// ---------------------------------------------------- + ldr r0,=_stack // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#UND_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#ABT_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#FIQ_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#IRQ_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#SVC_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + +// Copy initialized data to its execution address in RAM +// ------------------------------------------------------------------- +#ifdef ROM_RUN + ldr r1,=_etext // -> ROM data start + ldr r2,=_data // -> data start + ldr r3,=_edata // -> end of data +x01: cmp r2,r3 // check if data to move + beq y01 + ldrlo r0,[r1],#4 // copy it + strlo r0,[r2],#4 + blo x01 // loop until done +y01: +#endif +// Clear .bss +// ---------- + mov r0,#0 // get a zero + ldr r1,=__bss_start // -> bss start + ldr r2,=__bss_end__ // -> bss end +x02: cmp r1,r2 // check if data to clear + beq y02 + strlo r0,[r1],#4 // clear 4 bytes + blo x02 // loop until done +y02: +// Call main program: main(0) +// -------------------------- + mov r0,#0 // no arguments (argc = 0) + mov r1,r0 + mov r2,r0 + mov fp,r0 // null frame pointer + mov r7,r0 // null frame pointer for thumb + ldr r10,=main + mov lr,pc + mov pc, r10 // enter main() + + .size _start, . - _start + .endfunc + + .global _reset, reset, exit, abort + .func _reset +_reset: +reset: +exit: +abort: + + b . // loop until reset + + .size _reset, . - _reset + .endfunc + + .end Index: trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.lst =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.lst (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/build/storm_startup_code.lst (revision 3) @@ -0,0 +1,231 @@ + 1 # 1 "build/storm_startup_code.S" + 2 # 1 "" + 1 .global main // int main(void) + 0 + 0 + 2 + 3 .global _etext // -> .data initial values in ROM + 4 .global _data // -> .data area in RAM + 5 .global _edata // end of .data area + 6 .global __bss_start // -> .bss area in RAM + 7 .global __bss_end__ // end of .bss area + 8 .global _stack // top of stack + 9 + 10 // Stack Sizes + 11 .set UND_STACK_SIZE, 0x00000080 + 12 .set ABT_STACK_SIZE, 0x00000080 + 13 .set FIQ_STACK_SIZE, 0x00000080 + 14 .set IRQ_STACK_SIZE, 0X00000080 + 15 .set SVC_STACK_SIZE, 0x00000080 + 16 + 17 // Standard definitions of Mode bits and Interrupt flags in MSRs + 18 .set MODE_USR, 0x10 // User Mode + 19 .set MODE_FIQ, 0x11 // FIQ Mode + 20 .set MODE_IRQ, 0x12 // IRQ Mode + 21 .set MODE_SVC, 0x13 // Supervisor Mode + 22 .set MODE_ABT, 0x17 // Abort Mode + 23 .set MODE_UND, 0x1B // Undefined Mode + 24 .set MODE_SYS, 0x1F // System Mode + 25 + 26 .equ FIQ_BIT, 0x40 // when FIQ bit is set, FIQ is disabled + 27 .equ IRQ_BIT, 0x80 // when IRQ bit is set, IRQ is disabled + 28 + 29 .text + 30 .code 32 + 31 .align 2 + 32 + 33 .global _boot + 34 .func _boot + 35 _boot: + 36 + 37 // Runtime Interrupt Vectors + 38 // ------------------------------------------------------------------- + 39 Vectors: + 40 0000 EAFFFFFE b _start // reset - _start + 41 0004 E59FF014 ldr pc,_undf // undefined - _undf + 42 0008 E59FF014 ldr pc,_swi // SWI - _swi + 43 000c E59FF014 ldr pc,_pabt // program abort - _pabt + 44 0010 E59FF014 ldr pc,_dabt // data abort - _dabt + 45 0014 E1A00000 nop // reserved + 46 0018 E51FFFF0 ldr pc,[pc,#-0xFF0] // IRQ - read the VIC + 47 001c E59FF010 ldr pc,_fiq // FIQ - _fiq + 48 + 49 + 50 // Use this group for development + 51 0020 00000038 _undf: .word __undf // undefined + 52 0024 0000003C _swi: .word __swi // SWI + 53 0028 00000040 _pabt: .word __pabt // program abort + 54 002c 00000044 _dabt: .word __dabt // data abort + 55 0030 00000048 _irq: .word __irq // IRQ + 56 0034 0000004C _fiq: .word __fiq // FIQ + 57 + 58 0038 EAFFFFFE __undf: b . // undefined + 59 003c EAFFFFFE __swi: b . // SWI + 60 0040 EAFFFFFE __pabt: b . // program abort + 61 0044 EAFFFFFE __dabt: b . // data abort + 62 0048 EAFFFFFE __irq: b . // IRQ + 63 004c EAFFFFFE __fiq: b . // FIQ + 64 + 66 .endfunc + 67 + 68 + 69 // Setup the operating mode & stack. + 70 // ------------------------------------------------------------------- + 71 .global _start, start, _mainCRTStartup + 72 .func _start + 73 + 74 _start: + 75 start: + 76 _mainCRTStartup: + 77 + 78 // Who am I? Where am I going? + 79 + 80 // Initialize Interrupt System + 81 // - Set stack location for each mode + 82 // - Leave in System Mode with Interrupts Disabled + 83 // ---------------------------------------------------- + 84 0050 E59F00C8 ldr r0,=_stack // Calc stack base + 85 0054 E10F1000 mrs r1,CPSR + 86 0058 E3C1107F bic r1,r1,#0x7F + 87 005c E38110DB orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode + 88 0060 E129F001 msr CPSR,r1 + 89 0064 E1A0D000 mov sp,r0 // Store stack base + 90 + 91 0068 E2400080 sub r0,r0,#UND_STACK_SIZE // Calc stack base + 92 006c E10F1000 mrs r1,CPSR + 93 0070 E3C1107F bic r1,r1,#0x7F + 94 0074 E38110D7 orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode + 95 0078 E129F001 msr CPSR,r1 + 96 007c E1A0D000 mov sp,r0 // Store stack base + 97 + 98 0080 E2400080 sub r0,r0,#ABT_STACK_SIZE // Calc stack base + 99 0084 E10F1000 mrs r1,CPSR + 100 0088 E3C1107F bic r1,r1,#0x7F + 101 008c E38110D1 orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode + 102 0090 E129F001 msr CPSR,r1 + 103 0094 E1A0D000 mov sp,r0 // Store stack base + 104 + 105 0098 E2400080 sub r0,r0,#FIQ_STACK_SIZE // Calc stack base + 106 009c E10F1000 mrs r1,CPSR + 107 00a0 E3C1107F bic r1,r1,#0x7F + 108 00a4 E38110D2 orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode + 109 00a8 E129F001 msr CPSR,r1 + 110 00ac E1A0D000 mov sp,r0 // Store stack base + 111 + 112 00b0 E2400080 sub r0,r0,#IRQ_STACK_SIZE // Calc stack base + 113 00b4 E10F1000 mrs r1,CPSR + 114 00b8 E3C1107F bic r1,r1,#0x7F + 115 00bc E38110D3 orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode + 116 00c0 E129F001 msr CPSR,r1 + 117 00c4 E1A0D000 mov sp,r0 // Store stack base + 118 + 119 00c8 E2400080 sub r0,r0,#SVC_STACK_SIZE // Calc stack base + 120 00cc E10F1000 mrs r1,CPSR + 121 00d0 E3C1107F bic r1,r1,#0x7F + 122 00d4 E38110DF orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode + 123 00d8 E129F001 msr CPSR,r1 + 124 00dc E1A0D000 mov sp,r0 // Store stack base + 125 + 126 // Copy initialized data to its execution address in RAM + 127 // ------------------------------------------------------------------- + 128 #ifdef ROM_RUN + 129 ldr r1,=_etext // -> ROM data start + 130 ldr r2,=_data // -> data start + 131 ldr r3,=_edata // -> end of data + 132 x01: cmp r2,r3 // check if data to move + 133 beq y01 + 134 ldrlo r0,[r1],#4 // copy it + 135 strlo r0,[r2],#4 + 136 blo x01 // loop until done + 137 y01: + 138 #endif + 139 // Clear .bss + 140 // ---------- + 141 00e0 E3A00000 mov r0,#0 // get a zero + 142 00e4 E59F1038 ldr r1,=__bss_start // -> bss start + 143 00e8 E59F2038 ldr r2,=__bss_end__ // -> bss end + 144 00ec E1510002 x02: cmp r1,r2 // check if data to clear + 145 00f0 0A000001 beq y02 + 146 00f4 34810004 strlo r0,[r1],#4 // clear 4 bytes + 147 00f8 3AFFFFFB blo x02 // loop until done + 148 y02: + 149 // Call main program: main(0) + 150 // -------------------------- + 151 00fc E3A00000 mov r0,#0 // no arguments (argc = 0) + 152 0100 E1A01000 mov r1,r0 + 153 0104 E1A02000 mov r2,r0 + 154 0108 E1A0B000 mov fp,r0 // null frame pointer + 155 010c E1A07000 mov r7,r0 // null frame pointer for thumb + 156 0110 E59FA014 ldr r10,=main + 157 0114 E1A0E00F mov lr,pc + 158 0118 E1A0F00A mov pc, r10 // enter main() + 159 + 161 .endfunc + 162 + 163 .global _reset, reset, exit, abort + 164 .func _reset + 165 _reset: + 166 reset: + 167 exit: + 168 abort: + 169 + 170 011c EAFFFFFE b . // loop until reset + 171 + 173 .endfunc + 174 + 175 0120 00000000 .end + 175 00000000 + 175 00000000 + 175 00000000 +DEFINED SYMBOLS + *ABS*:00000000 build/storm_startup_code.S +build/storm_startup_code.S:11 *ABS*:00000080 UND_STACK_SIZE +build/storm_startup_code.S:12 *ABS*:00000080 ABT_STACK_SIZE +build/storm_startup_code.S:13 *ABS*:00000080 FIQ_STACK_SIZE +build/storm_startup_code.S:14 *ABS*:00000080 IRQ_STACK_SIZE +build/storm_startup_code.S:15 *ABS*:00000080 SVC_STACK_SIZE +build/storm_startup_code.S:18 *ABS*:00000010 MODE_USR +build/storm_startup_code.S:19 *ABS*:00000011 MODE_FIQ +build/storm_startup_code.S:20 *ABS*:00000012 MODE_IRQ +build/storm_startup_code.S:21 *ABS*:00000013 MODE_SVC +build/storm_startup_code.S:22 *ABS*:00000017 MODE_ABT +build/storm_startup_code.S:23 *ABS*:0000001b MODE_UND +build/storm_startup_code.S:24 *ABS*:0000001f MODE_SYS +build/storm_startup_code.S:26 *ABS*:00000040 FIQ_BIT +build/storm_startup_code.S:27 *ABS*:00000080 IRQ_BIT +build/storm_startup_code.S:30 .text:00000000 $a +build/storm_startup_code.S:35 .text:00000000 _boot +build/storm_startup_code.S:39 .text:00000000 Vectors +build/storm_startup_code.S:74 .text:00000050 _start +build/storm_startup_code.S:51 .text:00000020 _undf +build/storm_startup_code.S:52 .text:00000024 _swi +build/storm_startup_code.S:53 .text:00000028 _pabt +build/storm_startup_code.S:54 .text:0000002c _dabt +build/storm_startup_code.S:56 .text:00000034 _fiq +build/storm_startup_code.S:51 .text:00000020 $d +build/storm_startup_code.S:58 .text:00000038 __undf +build/storm_startup_code.S:59 .text:0000003c __swi +build/storm_startup_code.S:60 .text:00000040 __pabt +build/storm_startup_code.S:61 .text:00000044 __dabt +build/storm_startup_code.S:55 .text:00000030 _irq +build/storm_startup_code.S:62 .text:00000048 __irq +build/storm_startup_code.S:63 .text:0000004c __fiq +build/storm_startup_code.S:58 .text:00000038 $a +build/storm_startup_code.S:75 .text:00000050 start +build/storm_startup_code.S:76 .text:00000050 _mainCRTStartup +build/storm_startup_code.S:144 .text:000000ec x02 +build/storm_startup_code.S:148 .text:000000fc y02 +build/storm_startup_code.S:165 .text:0000011c _reset +build/storm_startup_code.S:166 .text:0000011c reset +build/storm_startup_code.S:167 .text:0000011c exit +build/storm_startup_code.S:168 .text:0000011c abort +build/storm_startup_code.S:175 .text:00000120 $d + +UNDEFINED SYMBOLS +main +_etext +_data +_edata +__bss_start +__bss_end__ +_stack Index: trunk/implementations/Altera DE2 Board/software/blink_demo/build/STORMcore-RAM.ld =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/build/STORMcore-RAM.ld (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/build/STORMcore-RAM.ld (revision 3) @@ -0,0 +1,101 @@ +/***********************************************************************/ +/* */ +/* RAM.ld: Linker Script File */ +/* */ +/***********************************************************************/ +ENTRY(_start) +STACK_SIZE = 0x1000; + +/* Memory Definitions */ +MEMORY +{ + ROM (rx) : ORIGIN = 0xFFF00000, LENGTH = 0x00000800 + RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00002000 +} + +/* Section Definitions */ +SECTIONS +{ + /* first section is .text which is used for code */ + .text : + { + *storm_startup_code.o (.text) /* Startup code */ + *(.text) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } > RAM + + . = ALIGN(4); + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + .data : + { + _data = .; + *(.data) + } > RAM + + . = ALIGN(4); + _edata = . ; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + __bss_start = . ; + __bss_start__ = . ; + *(.bss) + *(COMMON) + . = ALIGN(4); + } > RAM + + . = ALIGN(4); + __bss_end__ = . ; + PROVIDE (__bss_end = .); + + .stack ALIGN(256) : + { + . += STACK_SIZE; + PROVIDE (_stack = .); + } > RAM + + _end = . ; + PROVIDE (end = .); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_extractor.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_extractor.exe =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/storm_extractor.exe (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/storm_extractor.exe (revision 3)

trunk/implementations/Altera DE2 Board/software/blink_demo/storm_extractor.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.map =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.map (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.map (revision 3) @@ -0,0 +1,210 @@ + +Allocating common symbols +Common symbol size file + +timeval 0x4 main.o + +Memory Configuration + +Name Origin Length Attributes +ROM 0xfff00000 0x00000800 xr +RAM 0x00000000 0x00002000 xrw +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD build/storm_startup_code.o +LOAD main.o +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libm.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/be\libgcc.a +START GROUP +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/be\libgcc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libg.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +END GROUP + 0x00001000 STACK_SIZE = 0x1000 + +.text 0x00000000 0x39c + *storm_startup_code.o(.text) + .text 0x00000000 0x130 build/storm_startup_code.o + 0x0000011c reset + 0x00000000 _boot + 0x00000050 _mainCRTStartup + 0x0000011c abort + 0x00000050 _start + 0x0000011c _reset + 0x0000011c exit + 0x00000050 start + *(.text) + .text 0x00000130 0x26c main.o + 0x00000168 spi0_send_byte + 0x00000244 enable_irq + 0x000001b0 uart0_send_byte + 0x00000198 uart0_read_byte + 0x00000294 main + 0x000001cc i2c0_send_byte + 0x00000264 delay + 0x00000130 timer0_isr + 0x00000254 disable_irq + *(.rodata) + *(.rodata*) + *(.glue_7) + .glue_7 0x0000039c 0x0 build/storm_startup_code.o + .glue_7 0x0000039c 0x0 main.o + *(.glue_7t) + .glue_7t 0x0000039c 0x0 build/storm_startup_code.o + .glue_7t 0x0000039c 0x0 main.o + 0x0000039c . = ALIGN (0x4) + 0x0000039c _etext = . + 0x0000039c PROVIDE (etext, .) + +.data 0x0000039c 0x0 + 0x0000039c _data = . + *(.data) + .data 0x0000039c 0x0 build/storm_startup_code.o + .data 0x0000039c 0x0 main.o + 0x0000039c . = ALIGN (0x4) + 0x0000039c _edata = . + 0x0000039c PROVIDE (edata, .) + +.bss 0x0000039c 0x4 + 0x0000039c __bss_start = . + 0x0000039c __bss_start__ = . + *(.bss) + .bss 0x0000039c 0x0 build/storm_startup_code.o + .bss 0x0000039c 0x0 main.o + *(COMMON) + COMMON 0x0000039c 0x4 main.o + 0x0000039c timeval + 0x000003a0 . = ALIGN (0x4) + 0x000003a0 . = ALIGN (0x4) + 0x000003a0 __bss_end__ = . + 0x000003a0 PROVIDE (__bss_end, .) + +.stack 0x00000400 0x1000 + 0x00001400 . = (. + STACK_SIZE) + *fill* 0x00000400 0x1000 00 + 0x00001400 PROVIDE (_stack, .) + 0x00001400 _end = . + 0x00001400 PROVIDE (end, .) + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.stab.excl + *(.stab.excl) + +.stab.exclstr + *(.stab.exclstr) + +.stab.index + *(.stab.index) + +.stab.indexstr + *(.stab.indexstr) + +.comment 0x00000000 0x1b + *(.comment) + .comment 0x00000000 0x1b main.o + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x40 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x20 build/storm_startup_code.o + .debug_aranges + 0x00000020 0x20 main.o + +.debug_pubnames + 0x00000000 0xad + *(.debug_pubnames) + .debug_pubnames + 0x00000000 0xad main.o + +.debug_info 0x00000000 0x25e + *(.debug_info .gnu.linkonce.wi.*) + .debug_info 0x00000000 0x92 build/storm_startup_code.o + .debug_info 0x00000092 0x1cc main.o + +.debug_abbrev 0x00000000 0x125 + *(.debug_abbrev) + .debug_abbrev 0x00000000 0x14 build/storm_startup_code.o + .debug_abbrev 0x00000014 0x111 main.o + +.debug_line 0x00000000 0x138 + *(.debug_line) + .debug_line 0x00000000 0x93 build/storm_startup_code.o + .debug_line 0x00000093 0xa5 main.o + +.debug_frame 0x00000000 0xb8 + *(.debug_frame) + .debug_frame 0x00000000 0xb8 main.o + +.debug_str 0x00000000 0x113 + *(.debug_str) + .debug_str 0x00000000 0x113 main.o + +.debug_loc 0x00000000 0xbb + *(.debug_loc) + .debug_loc 0x00000000 0xbb main.o + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) +OUTPUT(main.elf elf32-bigarm) + +Cross Reference Table + +Symbol File +__bss_end__ build/storm_startup_code.o +__bss_start build/storm_startup_code.o +_boot build/storm_startup_code.o +_data build/storm_startup_code.o +_edata build/storm_startup_code.o +_etext build/storm_startup_code.o +_mainCRTStartup build/storm_startup_code.o +_reset build/storm_startup_code.o +_stack build/storm_startup_code.o +_start build/storm_startup_code.o +abort build/storm_startup_code.o +delay main.o +disable_irq main.o +enable_irq main.o +exit build/storm_startup_code.o +i2c0_send_byte main.o +main main.o + build/storm_startup_code.o +reset build/storm_startup_code.o +spi0_send_byte main.o +start build/storm_startup_code.o +timer0_isr main.o +timeval main.o +uart0_read_byte main.o +uart0_send_byte main.o Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.dat =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.dat (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.dat (revision 3)

trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_core.h =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/storm_core.h (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/storm_core.h (revision 3) @@ -0,0 +1,42 @@ +#ifndef storm_core_h +#define storm_core_h + +//////////////////////////////////////////////////////////////////////////////// +// storm_core.h - STORM Core internal definitions +// +// Created by Stephan Nolting (stnolting@googlemail.com) +// http://www.opencores.com/project,storm_core +// Last modified 13. Mar. 2012 +//////////////////////////////////////////////////////////////////////////////// + +/* Internal System Coprocessor Register Set */ +#define SYS_CP 15 // system coprocessor # +#define ID_REG_0 0 // ID register 0 +#define ID_REG_1 1 // ID register 1 +#define ID_REG_2 2 // ID register 2 +#define SYS_CTRL_0 6 // system control register 0 +#define CSTAT 8 // cache statistics register +#define ADR_FB 9 // adr feedback from bus unit -> for exception analysis +#define LFSR_POLY 11 // Internal LFSR, polynomial +#define LFSR_DATA 12 // Internal LFSR, shift register +#define SYS_IO 13 // System IO ports + +/* CP_SYS_CTRL_0 */ +#define DC_FLUSH 0 // flush d-cache +#define DC_CLEAR 1 // clear d-cache +#define IC_CLEAR 2 // flush i-cache +#define DC_WTHRU 3 // cache write-thru enable +#define DC_AUTOPR 4 // auto pre-reload d-cache page +#define IC_AUTOPR 5 // auto pre-reload i-cache page +#define CACHED_IO 6 // cached IO +#define PRTC_IO 7 // protected IO +#define DC_SYNC 8 // d-cache is sync +#define LFSR_EN 13 // enable lfsr +#define LFSR_M 14 // lfsr update mode +#define LFSR_D 15 // lfsr shift direction +#define MBC_0 16 // max bus cycle length bit 0 +#define MBC_LSB 16 +#define MBC_15 31 // max bus cycle length bit 15 +#define MBC_MSB 31 + +#endif // storm_core_h Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.lss =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.lss (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.lss (revision 3) @@ -0,0 +1,592 @@ + +main.elf: file format elf32-bigarm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000039c 00000000 00000000 00008000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .bss 00000004 0000039c 0000039c 0000839c 2**2 + ALLOC + 2 .stack 00001000 00000400 00000400 0000839c 2**0 + ALLOC + 3 .comment 0000001b 00000000 00000000 0000839c 2**0 + CONTENTS, READONLY + 4 .debug_aranges 00000040 00000000 00000000 000083b8 2**3 + CONTENTS, READONLY, DEBUGGING + 5 .debug_pubnames 000000ad 00000000 00000000 000083f8 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_info 0000025e 00000000 00000000 000084a5 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_abbrev 00000125 00000000 00000000 00008703 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_line 00000138 00000000 00000000 00008828 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_frame 000000b8 00000000 00000000 00008960 2**2 + CONTENTS, READONLY, DEBUGGING + 10 .debug_str 00000113 00000000 00000000 00008a18 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_loc 000000bb 00000000 00000000 00008b2b 2**0 + CONTENTS, READONLY, DEBUGGING +Disassembly of section .text: + +00000000 <_boot>: + +// Runtime Interrupt Vectors +// ------------------------------------------------------------------- +Vectors: + b _start // reset - _start + 0: ea000012 b 50 <_mainCRTStartup> + ldr pc,_undf // undefined - _undf + 4: e59ff014 ldr pc, [pc, #20] ; 20 <_undf> + ldr pc,_swi // SWI - _swi + 8: e59ff014 ldr pc, [pc, #20] ; 24 <_swi> + ldr pc,_pabt // program abort - _pabt + c: e59ff014 ldr pc, [pc, #20] ; 28 <_pabt> + ldr pc,_dabt // data abort - _dabt + 10: e59ff014 ldr pc, [pc, #20] ; 2c <_dabt> + nop // reserved + 14: e1a00000 nop (mov r0,r0) + ldr pc,[pc,#-0xFF0] // IRQ - read the VIC + 18: e51ffff0 ldr pc, [pc, #-4080] ; fffff030 <_end+0xffffdc30> + ldr pc,_fiq // FIQ - _fiq + 1c: e59ff010 ldr pc, [pc, #16] ; 34 <_fiq> + +00000020 <_undf>: + 20: 00000038 andeq r0, r0, r8, lsr r0 + +00000024 <_swi>: + 24: 0000003c andeq r0, r0, ip, lsr r0 + +00000028 <_pabt>: + 28: 00000040 andeq r0, r0, r0, asr #32 + +0000002c <_dabt>: + 2c: 00000044 andeq r0, r0, r4, asr #32 + +00000030 <_irq>: + 30: 00000048 andeq r0, r0, r8, asr #32 + +00000034 <_fiq>: + 34: 0000004c andeq r0, r0, ip, asr #32 + +00000038 <__undf>: + + +// Use this group for development +_undf: .word __undf // undefined +_swi: .word __swi // SWI +_pabt: .word __pabt // program abort +_dabt: .word __dabt // data abort +_irq: .word __irq // IRQ +_fiq: .word __fiq // FIQ + +__undf: b . // undefined + 38: eafffffe b 38 <__undf> + +0000003c <__swi>: +__swi: b . // SWI + 3c: eafffffe b 3c <__swi> + +00000040 <__pabt>: +__pabt: b . // program abort + 40: eafffffe b 40 + +00000044 <__dabt>: +__dabt: b . // data abort + 44: eafffffe b 44 <__dabt> + +00000048 <__irq>: +__irq: b . // IRQ + 48: eafffffe b 48 <__irq> + +0000004c <__fiq>: +__fiq: b . // FIQ + 4c: eafffffe b 4c <__fiq> + +00000050 <_mainCRTStartup>: + + .size _boot, . - _boot + .endfunc + + +// Setup the operating mode & stack. +// ------------------------------------------------------------------- + .global _start, start, _mainCRTStartup + .func _start + +_start: +start: +_mainCRTStartup: + +// Who am I? Where am I going? + +// Initialize Interrupt System +// - Set stack location for each mode +// - Leave in System Mode with Interrupts Disabled +// ---------------------------------------------------- + ldr r0,=_stack // Calc stack base + 50: e59f00c8 ldr r0, [pc, #200] ; 120 <.text+0x120> + mrs r1,CPSR + 54: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + 58: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode + 5c: e38110db orr r1, r1, #219 ; 0xdb + msr CPSR,r1 + 60: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + 64: e1a0d000 mov sp, r0 + + sub r0,r0,#UND_STACK_SIZE // Calc stack base + 68: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR + 6c: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + 70: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode + 74: e38110d7 orr r1, r1, #215 ; 0xd7 + msr CPSR,r1 + 78: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + 7c: e1a0d000 mov sp, r0 + + sub r0,r0,#ABT_STACK_SIZE // Calc stack base + 80: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR + 84: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + 88: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode + 8c: e38110d1 orr r1, r1, #209 ; 0xd1 + msr CPSR,r1 + 90: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + 94: e1a0d000 mov sp, r0 + + sub r0,r0,#FIQ_STACK_SIZE // Calc stack base + 98: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR + 9c: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + a0: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode + a4: e38110d2 orr r1, r1, #210 ; 0xd2 + msr CPSR,r1 + a8: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + ac: e1a0d000 mov sp, r0 + + sub r0,r0,#IRQ_STACK_SIZE // Calc stack base + b0: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR + b4: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + b8: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode + bc: e38110d3 orr r1, r1, #211 ; 0xd3 + msr CPSR,r1 + c0: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + c4: e1a0d000 mov sp, r0 + + sub r0,r0,#SVC_STACK_SIZE // Calc stack base + c8: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR + cc: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F + d0: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode + d4: e38110df orr r1, r1, #223 ; 0xdf + msr CPSR,r1 + d8: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base + dc: e1a0d000 mov sp, r0 + +// Copy initialized data to its execution address in RAM +// ------------------------------------------------------------------- +#ifdef ROM_RUN + ldr r1,=_etext // -> ROM data start + ldr r2,=_data // -> data start + ldr r3,=_edata // -> end of data +x01: cmp r2,r3 // check if data to move + beq y01 + ldrlo r0,[r1],#4 // copy it + strlo r0,[r2],#4 + blo x01 // loop until done +y01: +#endif +// Clear .bss +// ---------- + mov r0,#0 // get a zero + e0: e3a00000 mov r0, #0 ; 0x0 + ldr r1,=__bss_start // -> bss start + e4: e59f1038 ldr r1, [pc, #56] ; 124 <.text+0x124> + ldr r2,=__bss_end__ // -> bss end + e8: e59f2038 ldr r2, [pc, #56] ; 128 <.text+0x128> + +000000ec : +x02: cmp r1,r2 // check if data to clear + ec: e1510002 cmp r1, r2 + beq y02 + f0: 0a000001 beq fc + strlo r0,[r1],#4 // clear 4 bytes + f4: 34810004 strcc r0, [r1], #4 + blo x02 // loop until done + f8: 3afffffb bcc ec + +000000fc : +y02: +// Call main program: main(0) +// -------------------------- + mov r0,#0 // no arguments (argc = 0) + fc: e3a00000 mov r0, #0 ; 0x0 + mov r1,r0 + 100: e1a01000 mov r1, r0 + mov r2,r0 + 104: e1a02000 mov r2, r0 + mov fp,r0 // null frame pointer + 108: e1a0b000 mov fp, r0 + mov r7,r0 // null frame pointer for thumb + 10c: e1a07000 mov r7, r0 + ldr r10,=main + 110: e59fa014 ldr sl, [pc, #20] ; 12c <.text+0x12c> + mov lr,pc + 114: e1a0e00f mov lr, pc + mov pc, r10 // enter main() + 118: e1a0f00a mov pc, sl + +0000011c <_reset>: + + .size _start, . - _start + .endfunc + + .global _reset, reset, exit, abort + .func _reset +_reset: +reset: +exit: +abort: + + b . // loop until reset + 11c: eafffffe b 11c <_reset> + 120: 00001400 andeq r1, r0, r0, lsl #8 + 124: 0000039c muleq r0, ip, r3 + 128: 000003a0 andeq r0, r0, r0, lsr #7 + 12c: 00000294 muleq r0, r4, r2 + +00000130 : +/* ---- IRQ: Timer ISR ---- */ +volatile unsigned long timeval; +void __attribute__ ((interrupt("IRQ"))) timer0_isr(void); +void timer0_isr(void) +{ + 130: e92d000e stmdb sp!, {r1, r2, r3} + timeval++; + 134: e59f2028 ldr r2, [pc, #40] ; 164 <.text+0x164> + 138: e5923000 ldr r3, [r2] + 13c: e2833001 add r3, r3, #1 ; 0x1 + 140: e5823000 str r3, [r2] + SSEG0_DATA = timeval; + 144: e5921000 ldr r1, [r2] + 148: e3e03a0f mvn r3, #61440 ; 0xf000 + 14c: e5031ff7 str r1, [r3, #-4087] + VICVectAddr = 0; + 150: e3a02000 mov r2, #0 ; 0x0 + 154: e2833a0f add r3, r3, #61440 ; 0xf000 + 158: e5032fcf str r2, [r3, #-4047] +} + 15c: e8bd000e ldmia sp!, {r1, r2, r3} + 160: e25ef004 subs pc, lr, #4 ; 0x4 + 164: 0000039c muleq r0, ip, r3 + +00000168 : + + +/* ---- SPI 0 Transmission ---- */ +void spi0_send_byte(int data, int slave_id) +{ + 168: e3e0ca0f mvn ip, #61440 ; 0xf000 + while((SPI0_CONF & (1<<8)) != 0); // spi busy? + 16c: e51c3fcf ldr r3, [ip, #-4047] + 170: e3130c01 tst r3, #256 ; 0x100 + 174: 1afffffc bne 16c + SPI0_DAT0 = data; + SPI0_SCSR = ~slave_id & 255; + 178: e1e02001 mvn r2, r1 + 17c: e20220ff and r2, r2, #255 ; 0xff + 180: e50c0fbf str r0, [ip, #-4031] + 184: e50c2fc7 str r2, [ip, #-4039] + SPI0_CONF = SPI0_CONF | 256; + 188: e51c3fcf ldr r3, [ip, #-4047] + 18c: e3833c01 orr r3, r3, #256 ; 0x100 + 190: e50c3fcf str r3, [ip, #-4047] +} + 194: e1a0f00e mov pc, lr + +00000198 : + + +/* ---- UART0 read byte ---- */ +int uart0_read_byte(void) +{ + if ((UART0_SREG & (1<<1)) != 0) // byte available? + 198: e3e02a0f mvn r2, #61440 ; 0xf000 + 19c: e5123fe3 ldr r3, [r2, #-4067] + 1a0: e3130002 tst r3, #2 ; 0x2 + 1a4: e3e00000 mvn r0, #0 ; 0x0 + return UART0_DATA; + 1a8: 15120fe7 ldrne r0, [r2, #-4071] + else + return -1; +} + 1ac: e1a0f00e mov pc, lr + +000001b0 : + + +/* ---- UART0 write byte ---- */ +int uart0_send_byte(char ch) +{ + 1b0: e20000ff and r0, r0, #255 ; 0xff + 1b4: e3e02a0f mvn r2, #61440 ; 0xf000 + while((UART0_SREG & (1<<0)) == 0); // uart busy? + 1b8: e5123fe3 ldr r3, [r2, #-4067] + 1bc: e3130001 tst r3, #1 ; 0x1 + 1c0: 0afffffc beq 1b8 + ch = ch & 255; + UART0_DATA = ch; + 1c4: e5020fe7 str r0, [r2, #-4071] + return (int)ch; +} + 1c8: e1a0f00e mov pc, lr + +000001cc : + + +/* ---- I2C0 write byte ---- */ +int i2c0_send_byte(char adr, int data) +{ + I2C0_CMD = (1<<7) | (1<<4); // start condition + 1cc: e3e03a0f mvn r3, #61440 ; 0xf000 + 1d0: e3a02090 mov r2, #144 ; 0x90 + 1d4: e5032faf str r2, [r3, #-4015] + 1d8: e20000ff and r0, r0, #255 ; 0xff + 1dc: e1a02003 mov r2, r3 + while((I2C0_STAT & (1<<1)) != 0); // wait for execution + 1e0: e5123faf ldr r3, [r2, #-4015] + 1e4: e3130002 tst r3, #2 ; 0x2 + 1e8: 1afffffc bne 1e0 + + I2C0_DATA = adr; + I2C0_CMD = (1<<4); // write to slave + 1ec: e3a03010 mov r3, #16 ; 0x10 + 1f0: e5020f93 str r0, [r2, #-3987] + 1f4: e5023faf str r3, [r2, #-4015] + 1f8: e3e02a0f mvn r2, #61440 ; 0xf000 + while((I2C0_STAT & (1<<7)) != 0); // wait for ack + 1fc: e5123faf ldr r3, [r2, #-4015] + 200: e3130080 tst r3, #128 ; 0x80 + 204: 1afffffc bne 1fc + + I2C0_DATA = data; + I2C0_CMD = (1<<4); // write to slave + 208: e3a03010 mov r3, #16 ; 0x10 + 20c: e5021f93 str r1, [r2, #-3987] + 210: e5023faf str r3, [r2, #-4015] + 214: e3e02a0f mvn r2, #61440 ; 0xf000 + while((I2C0_STAT & (1<<7)) != 0); // wait for ack + 218: e5123faf ldr r3, [r2, #-4015] + 21c: e3130080 tst r3, #128 ; 0x80 + 220: 1afffffc bne 218 + + I2C0_CMD = (1<<6); // stop condition + 224: e3a03040 mov r3, #64 ; 0x40 + 228: e5023faf str r3, [r2, #-4015] + 22c: e3e02a0f mvn r2, #61440 ; 0xf000 + while((I2C0_STAT & (1<<1)) != 0); // wait for execution + 230: e5123faf ldr r3, [r2, #-4015] + 234: e3130002 tst r3, #2 ; 0x2 + 238: 1afffffc bne 230 + return data; +} + 23c: e1a00001 mov r0, r1 + 240: e1a0f00e mov pc, lr + +00000244 : + + +/* ---- Enable IRQ ---- */ +void enable_irq(void) +{ + unsigned long _cpsr; + asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + 244: e10f3000 mrs r3, CPSR + _cpsr = _cpsr & ~(1<<7); + asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); + 248: e3c33080 bic r3, r3, #128 ; 0x80 + 24c: e129f003 msr CPSR_fc, r3 +} + 250: e1a0f00e mov pc, lr + +00000254 : + + +/* ---- Disable IRQ ---- */ +void disable_irq(void) +{ + unsigned long _cpsr; + asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + 254: e10f3000 mrs r3, CPSR + _cpsr = _cpsr | (1<<7); + asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); + 258: e3833080 orr r3, r3, #128 ; 0x80 + 25c: e129f003 msr CPSR_fc, r3 +} + 260: e1a0f00e mov pc, lr + +00000264 : + + +/* ---- Delay function ---- */ +void delay(int delay) +{ + int i; + for(i=0; i + 290: e1a0f00e mov pc, lr + +00000294

: +} + + +/* ---- Main function ---- */ +int main(void) +{ + int led_timer; + int data; + + // display clear + SSEG1_DATA = 0; + SSEG0_DATA = 0; + + // SPI 0 init + led_timer = 0; + SPI0_CONF = (1<<10) | (1<<9) | 8; + 294: e3a02c06 mov r2, #1536 ; 0x600 + 298: e92d4070 stmdb sp!, {r4, r5, r6, lr} + 29c: e2822008 add r2, r2, #8 ; 0x8 + 2a0: e3e04a0f mvn r4, #61440 ; 0xf000 + 2a4: e3a05000 mov r5, #0 ; 0x0 + SPI0_PRSC = 500; // 100kHz + 2a8: e3a03f7d mov r3, #500 ; 0x1f4 + 2ac: e5045fef str r5, [r4, #-4079] + spi0_send_byte(0, 255); + 2b0: e3a010ff mov r1, #255 ; 0xff + 2b4: e5045ff7 str r5, [r4, #-4087] + 2b8: e1a00005 mov r0, r5 + 2bc: e5042fcf str r2, [r4, #-4047] + 2c0: e5043fcb str r3, [r4, #-4043] + 2c4: ebffffa7 bl 168 + spi0_send_byte(0, 255); + 2c8: e1a00005 mov r0, r5 + 2cc: e3a010ff mov r1, #255 ; 0xff + 2d0: ebffffa4 bl 168 + + // I�C 0 init + I2C0_PRLO = 99; // for 100kHz + 2d4: e3a03063 mov r3, #99 ; 0x63 + I2C0_PRHI = 0; + I2C0_CTRL = (1<<7); // i2c enable + + // timer init + timeval = 0; + 2d8: e59f20b4 ldr r2, [pc, #180] ; 394 <.text+0x394> + 2dc: e5043f9f str r3, [r4, #-3999] + STME0_CNT = 0; + STME0_VAL = 50000000; // threshold value for 1s ticks + 2e0: e3a017be mov r1, #49807360 ; 0x2f80000 + 2e4: e283301d add r3, r3, #29 ; 0x1d + 2e8: e5045f9b str r5, [r4, #-3995] + 2ec: e2811a2f add r1, r1, #192512 ; 0x2f000 + 2f0: e5043f97 str r3, [r4, #-3991] + 2f4: e5825000 str r5, [r2] + STME0_CONF = (1<<2) | (1<<1) | (1<<0); // interrupt en, auto reset, timer enable + VICVectAddr0 = (unsigned long)timer0_isr; + 2f8: e59f2098 ldr r2, [pc, #152] ; 398 <.text+0x398> + 2fc: e3e00000 mvn r0, #0 ; 0x0 + 300: e2811080 add r1, r1, #128 ; 0x80 + 304: e2433079 sub r3, r3, #121 ; 0x79 + 308: e5045fdf str r5, [r4, #-4063] + 30c: e5041fdb str r1, [r4, #-4059] + 310: e5043fd7 str r3, [r4, #-4055] + 314: e5002fbf str r2, [r0, #-4031] + VICVectCntl0 = (1<<5) | 0; // enable and channel select = 0 (timer0) + 318: e2833019 add r3, r3, #25 ; 0x19 + VICIntEnable = (1<<0); // enable channel 0 (timer0) + 31c: e3a02001 mov r2, #1 ; 0x1 + 320: e5003f7f str r3, [r0, #-3967] + 324: e5002fef str r2, [r0, #-4079] + + //i2c0_send_byte(56, 0xCC); + + enable_irq(); + 328: ebffffc5 bl 244 + 32c: e1a06005 mov r6, r5 + 330: ea000001 b 33c + + while(1) + { + //disable_irq(); + data = uart0_read_byte(); + if(data > -1) + { + spi0_send_byte(data, 255); + uart0_send_byte(data); + } + if((PS2_STAT & (1<<1)) != 0) // char available? + { + PS2_STAT = 0; // ack + data = PS2_DATA; + spi0_send_byte(data, 255); + uart0_send_byte(data); + } + //enable_irq(); + led_timer++; + GPIO0_OUT = led_timer >> 16; + 334: e1a03846 mov r3, r6, asr #16 + 338: e5053fff str r3, [r5, #-4095] + 33c: ebffff95 bl 198 + 340: e2504000 subs r4, r0, #0 ; 0x0 + 344: e3e05a0f mvn r5, #61440 ; 0xf000 + 348: e2866001 add r6, r6, #1 ; 0x1 + 34c: e3a010ff mov r1, #255 ; 0xff + 350: ba000002 blt 360 + 354: ebffff83 bl 168 + 358: e20400ff and r0, r4, #255 ; 0xff + 35c: ebffff93 bl 1b0 + 360: e5153f8b ldr r3, [r5, #-3979] + 364: e3130002 tst r3, #2 ; 0x2 + 368: e3a010ff mov r1, #255 ; 0xff + 36c: 0afffff0 beq 334 + 370: e3a03000 mov r3, #0 ; 0x0 + 374: e5053f8b str r3, [r5, #-3979] + 378: e5154f8f ldr r4, [r5, #-3983] + 37c: e1a00004 mov r0, r4 + 380: e20440ff and r4, r4, #255 ; 0xff + 384: ebffff77 bl 168 + 388: e1a00004 mov r0, r4 + 38c: ebffff87 bl 1b0 + 390: eaffffe7 b 334 + 394: 0000039c muleq r0, ip, r3 + 398: 00000130 andeq r0, r0, r0, lsr r1 Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.c =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.c (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.c (revision 3) @@ -0,0 +1,154 @@ +#include "storm_core.h" +#include "storm_soc_de2.h" + +// +--------------------------+ +// | STORM SoC DE2-Board Demo | +// +--------------------------+ + + +/* ---- IRQ: Timer ISR ---- */ +volatile unsigned long timeval; +void __attribute__ ((interrupt("IRQ"))) timer0_isr(void); +void timer0_isr(void) +{ + timeval++; + SSEG0_DATA = timeval; + VICVectAddr = 0; +} + + +/* ---- SPI 0 Transmission ---- */ +void spi0_send_byte(int data, int slave_id) +{ + while((SPI0_CONF & (1<<8)) != 0); // spi busy? + SPI0_DAT0 = data; + SPI0_SCSR = ~slave_id & 255; + SPI0_CONF = SPI0_CONF | 256; +} + + +/* ---- UART0 read byte ---- */ +int uart0_read_byte(void) +{ + if ((UART0_SREG & (1<<1)) != 0) // byte available? + return UART0_DATA; + else + return -1; +} + + +/* ---- UART0 write byte ---- */ +int uart0_send_byte(char ch) +{ + while((UART0_SREG & (1<<0)) == 0); // uart busy? + ch = ch & 255; + UART0_DATA = ch; + return (int)ch; +} + + +/* ---- I2C0 write byte ---- */ +int i2c0_send_byte(char adr, int data) +{ + I2C0_CMD = (1<<7) | (1<<4); // start condition + while((I2C0_STAT & (1<<1)) != 0); // wait for execution + + I2C0_DATA = adr; + I2C0_CMD = (1<<4); // write to slave + while((I2C0_STAT & (1<<7)) != 0); // wait for ack + + I2C0_DATA = data; + I2C0_CMD = (1<<4); // write to slave + while((I2C0_STAT & (1<<7)) != 0); // wait for ack + + I2C0_CMD = (1<<6); // stop condition + while((I2C0_STAT & (1<<1)) != 0); // wait for execution + return data; +} + + +/* ---- Enable IRQ ---- */ +void enable_irq(void) +{ + unsigned long _cpsr; + asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + _cpsr = _cpsr & ~(1<<7); + asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); +} + + +/* ---- Disable IRQ ---- */ +void disable_irq(void) +{ + unsigned long _cpsr; + asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + _cpsr = _cpsr | (1<<7); + asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); +} + + +/* ---- Delay function ---- */ +void delay(int delay) +{ + int i; + for(i=0; i -1) + { + spi0_send_byte(data, 255); + uart0_send_byte(data); + } + if((PS2_STAT & (1<<1)) != 0) // char available? + { + PS2_STAT = 0; // ack + data = PS2_DATA; + spi0_send_byte(data, 255); + uart0_send_byte(data); + } + //enable_irq(); + led_timer++; + GPIO0_OUT = led_timer >> 16; + } +} Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.lst =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.lst (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.lst (revision 3) @@ -0,0 +1,552 @@ + 1 .file "main.c" + 9 .Ltext0: + 10 .align 2 + 11 .global timer0_isr + 13 timer0_isr: + 14 .LFB2: + 15 .file 1 "main.c" + 1:main.c **** #include "storm_core.h" + 2:main.c **** #include "storm_soc_de2.h" + 3:main.c **** + 4:main.c **** // +--------------------------+ + 5:main.c **** // | STORM SoC DE2-Board Demo | + 6:main.c **** // +--------------------------+ + 7:main.c **** + 8:main.c **** + 9:main.c **** /* ---- IRQ: Timer ISR ---- */ + 10:main.c **** volatile unsigned long timeval; + 11:main.c **** void __attribute__ ((interrupt("IRQ"))) timer0_isr(void); + 12:main.c **** void timer0_isr(void) + 13:main.c **** { + 16 Interrupt Service Routine. + 17 @ args = 0, pretend = 0, frame = 0 + 18 @ frame_needed = 0, uses_anonymous_args = 0 + 19 @ link register save eliminated. + 20 stmfd sp!, {r1, r2, r3} + 21 0000 E92D000E .LCFI0: + 22 .loc 1 14 0 + 14:main.c **** timeval++; + 23 , .L3 + 24 0004 E59F2028 ldr r3, [r2, #0] + 25 0008 E5923000 add r3, r3, #1 + 26 000c E2833001 str r3, [r2, #0] + 27 0010 E5823000 .loc 1 15 0 + 15:main.c **** SSEG0_DATA = timeval; + 28 r1, [r2, #0] + 29 0014 E5921000 mvn r3, #61440 + 30 0018 E3E03A0F str r1, [r3, #-4087] + 31 001c E5031FF7 .loc 1 16 0 + 16:main.c **** VICVectAddr = 0; + 32 r2, #0 + 33 0020 E3A02000 add r3, r3, #61440 + 34 0024 E2833A0F .loc 1 13 0 + 35 @ lr needed for prologue + 36 .loc 1 16 0 + 37 str r2, [r3, #-4047] + 38 0028 E5032FCF .loc 1 17 0 + 17:main.c **** } + 39 sp!, {r1, r2, r3} + 40 002c E8BD000E subs pc, lr, #4 + 41 0030 E25EF004 .L4: + 42 .align 2 + 43 .L3: + 44 .word timeval + 45 0034 00000000 .LFE2: + 47 .align 2 + 48 .global spi0_send_byte + 50 spi0_send_byte: + 51 .LFB3: + 52 .loc 1 22 0 + 18:main.c **** + 19:main.c **** + 20:main.c **** /* ---- SPI 0 Transmission ---- */ + 21:main.c **** void spi0_send_byte(int data, int slave_id) + 22:main.c **** { + 53 retend = 0, frame = 0 + 54 @ frame_needed = 0, uses_anonymous_args = 0 + 55 @ link register save eliminated. + 56 .LVL0: + 57 @ lr needed for prologue + 58 mvn ip, #61440 + 59 0038 E3E0CA0F .L7: + 60 .loc 1 23 0 + 23:main.c **** while((SPI0_CONF & (1<<8)) != 0); // spi busy? + 61 [ip, #-4047] + 62 003c E51C3FCF tst r3, #256 + 63 0040 E3130C01 bne .L7 + 64 0044 1AFFFFFC .loc 1 25 0 + 24:main.c **** SPI0_DAT0 = data; + 25:main.c **** SPI0_SCSR = ~slave_id & 255; + 65 r2, r1 + 66 0048 E1E02001 and r2, r2, #255 + 67 004c E20220FF .loc 1 24 0 + 68 str r0, [ip, #-4031] + 69 0050 E50C0FBF .loc 1 25 0 + 70 str r2, [ip, #-4039] + 71 0054 E50C2FC7 .loc 1 26 0 + 26:main.c **** SPI0_CONF = SPI0_CONF | 256; + 72 , [ip, #-4047] + 73 0058 E51C3FCF orr r3, r3, #256 + 74 005c E3833C01 str r3, [ip, #-4047] + 75 0060 E50C3FCF .loc 1 27 0 + 27:main.c **** } + 76 pc, lr + 77 0064 E1A0F00E .LFE3: + 79 .align 2 + 80 .global uart0_read_byte + 82 uart0_read_byte: + 83 .LFB4: + 84 .loc 1 32 0 + 28:main.c **** + 29:main.c **** + 30:main.c **** /* ---- UART0 read byte ---- */ + 31:main.c **** int uart0_read_byte(void) + 32:main.c **** { + 85 0, pretend = 0, frame = 0 + 86 @ frame_needed = 0, uses_anonymous_args = 0 + 87 @ link register save eliminated. + 88 .loc 1 33 0 + 33:main.c **** if ((UART0_SREG & (1<<1)) != 0) // byte available? + 89 r2, #61440 + 90 0068 E3E02A0F ldr r3, [r2, #-4067] + 91 006c E5123FE3 tst r3, #2 + 92 0070 E3130002 mvn r0, #0 + 93 0074 E3E00000 .loc 1 34 0 + 34:main.c **** return UART0_DATA; + 94 e r0, [r2, #-4071] + 95 0078 15120FE7 .loc 1 32 0 + 96 @ lr needed for prologue + 97 .loc 1 37 0 + 35:main.c **** else + 36:main.c **** return -1; + 37:main.c **** } + 98 pc, lr + 99 007c E1A0F00E .LFE4: + 101 .align 2 + 102 .global uart0_send_byte + 104 uart0_send_byte: + 105 .LFB5: + 106 .loc 1 42 0 + 38:main.c **** + 39:main.c **** + 40:main.c **** /* ---- UART0 write byte ---- */ + 41:main.c **** int uart0_send_byte(char ch) + 42:main.c **** { + 107 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 @ link register save eliminated. + 110 .LVL1: + 111 @ lr needed for prologue + 112 .loc 1 42 0 + 113 and r0, r0, #255 + 114 0080 E20000FF mvn r2, #61440 + 115 0084 E3E02A0F .L20: + 116 .loc 1 43 0 + 43:main.c **** while((UART0_SREG & (1<<0)) == 0); // uart busy? + 117 r2, #-4067] + 118 0088 E5123FE3 tst r3, #1 + 119 008c E3130001 beq .L20 + 120 0090 0AFFFFFC .loc 1 45 0 + 44:main.c **** ch = ch & 255; + 45:main.c **** UART0_DATA = ch; + 121 r0, [r2, #-4071] + 122 0094 E5020FE7 .LVL2: + 123 .loc 1 47 0 + 46:main.c **** return (int)ch; + 47:main.c **** } + 124 v pc, lr + 125 0098 E1A0F00E .LFE5: + 127 .align 2 + 128 .global i2c0_send_byte + 130 i2c0_send_byte: + 131 .LFB6: + 132 .loc 1 52 0 + 48:main.c **** + 49:main.c **** + 50:main.c **** /* ---- I2C0 write byte ---- */ + 51:main.c **** int i2c0_send_byte(char adr, int data) + 52:main.c **** { + 133 0, pretend = 0, frame = 0 + 134 @ frame_needed = 0, uses_anonymous_args = 0 + 135 @ link register save eliminated. + 136 .LVL3: + 137 .loc 1 53 0 + 53:main.c **** I2C0_CMD = (1<<7) | (1<<4); // start condition + 138 r3, #61440 + 139 009c E3E03A0F mov r2, #144 + 140 00a0 E3A02090 str r2, [r3, #-4015] + 141 00a4 E5032FAF .loc 1 52 0 + 142 @ lr needed for prologue + 143 .loc 1 52 0 + 144 and r0, r0, #255 + 145 00a8 E20000FF mov r2, r3 + 146 00ac E1A02003 .L26: + 147 .loc 1 54 0 + 54:main.c **** while((I2C0_STAT & (1<<1)) != 0); // wait for execution + 148 r2, #-4015] + 149 00b0 E5123FAF tst r3, #2 + 150 00b4 E3130002 bne .L26 + 151 00b8 1AFFFFFC .loc 1 57 0 + 55:main.c **** + 56:main.c **** I2C0_DATA = adr; + 57:main.c **** I2C0_CMD = (1<<4); // write to slave + 152 r3, #16 + 153 00bc E3A03010 .loc 1 56 0 + 154 str r0, [r2, #-3987] + 155 00c0 E5020F93 .loc 1 57 0 + 156 str r3, [r2, #-4015] + 157 00c4 E5023FAF mvn r2, #61440 + 158 00c8 E3E02A0F .L28: + 159 .loc 1 58 0 + 58:main.c **** while((I2C0_STAT & (1<<7)) != 0); // wait for ack + 160 [r2, #-4015] + 161 00cc E5123FAF tst r3, #128 + 162 00d0 E3130080 bne .L28 + 163 00d4 1AFFFFFC .loc 1 61 0 + 59:main.c **** + 60:main.c **** I2C0_DATA = data; + 61:main.c **** I2C0_CMD = (1<<4); // write to slave + 164 r3, #16 + 165 00d8 E3A03010 .loc 1 60 0 + 166 str r1, [r2, #-3987] + 167 00dc E5021F93 .loc 1 61 0 + 168 str r3, [r2, #-4015] + 169 00e0 E5023FAF mvn r2, #61440 + 170 00e4 E3E02A0F .L30: + 171 .loc 1 62 0 + 62:main.c **** while((I2C0_STAT & (1<<7)) != 0); // wait for ack + 172 [r2, #-4015] + 173 00e8 E5123FAF tst r3, #128 + 174 00ec E3130080 bne .L30 + 175 00f0 1AFFFFFC .loc 1 64 0 + 63:main.c **** + 64:main.c **** I2C0_CMD = (1<<6); // stop condition + 176 r3, #64 + 177 00f4 E3A03040 str r3, [r2, #-4015] + 178 00f8 E5023FAF mvn r2, #61440 + 179 00fc E3E02A0F .L32: + 180 .loc 1 65 0 + 65:main.c **** while((I2C0_STAT & (1<<1)) != 0); // wait for execution + 181 r3, [r2, #-4015] + 182 0100 E5123FAF tst r3, #2 + 183 0104 E3130002 bne .L32 + 184 0108 1AFFFFFC .loc 1 67 0 + 66:main.c **** return data; + 67:main.c **** } + 185 r0, r1 + 186 010c E1A00001 .LVL4: + 187 mov pc, lr + 188 0110 E1A0F00E .LFE6: + 190 .align 2 + 191 .global enable_irq + 193 enable_irq: + 194 .LFB7: + 195 .loc 1 72 0 + 68:main.c **** + 69:main.c **** + 70:main.c **** /* ---- Enable IRQ ---- */ + 71:main.c **** void enable_irq(void) + 72:main.c **** { + 196 , pretend = 0, frame = 0 + 197 @ frame_needed = 0, uses_anonymous_args = 0 + 198 @ link register save eliminated. + 199 @ lr needed for prologue + 200 .loc 1 74 0 + 73:main.c **** unsigned long _cpsr; + 74:main.c **** asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + 201 r3, cpsr + 202 0114 E10F3000 .LVL5: + 203 .loc 1 76 0 + 75:main.c **** _cpsr = _cpsr & ~(1<<7); + 76:main.c **** asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); + 204 c r3, r3, #128 + 205 0118 E3C33080 .LVL6: + 206 msr cpsr, r3 + 207 011c E129F003 .loc 1 77 0 + 77:main.c **** } + 208 pc, lr + 209 0120 E1A0F00E .LFE7: + 211 .align 2 + 212 .global disable_irq + 214 disable_irq: + 215 .LFB8: + 216 .loc 1 82 0 + 78:main.c **** + 79:main.c **** + 80:main.c **** /* ---- Disable IRQ ---- */ + 81:main.c **** void disable_irq(void) + 82:main.c **** { + 217 0, pretend = 0, frame = 0 + 218 @ frame_needed = 0, uses_anonymous_args = 0 + 219 @ link register save eliminated. + 220 @ lr needed for prologue + 221 .loc 1 84 0 + 83:main.c **** unsigned long _cpsr; + 84:main.c **** asm volatile (" mrs %0, cpsr" : "=r" (_cpsr) : /* no inputs */ ); + 222 r3, cpsr + 223 0124 E10F3000 .LVL7: + 224 .loc 1 86 0 + 85:main.c **** _cpsr = _cpsr | (1<<7); + 86:main.c **** asm volatile (" msr cpsr, %0" : /* no outputs */ : "r" (_cpsr) ); + 225 r r3, r3, #128 + 226 0128 E3833080 .LVL8: + 227 msr cpsr, r3 + 228 012c E129F003 .loc 1 87 0 + 87:main.c **** } + 229 pc, lr + 230 0130 E1A0F00E .LFE8: + 232 .align 2 + 233 .global delay + 235 delay: + 236 .LFB9: + 237 .loc 1 92 0 + 88:main.c **** + 89:main.c **** + 90:main.c **** /* ---- Delay function ---- */ + 91:main.c **** void delay(int delay) + 92:main.c **** { + 238 0, pretend = 0, frame = 0 + 239 @ frame_needed = 0, uses_anonymous_args = 0 + 240 @ link register save eliminated. + 241 .LVL9: + 242 .loc 1 94 0 + 93:main.c **** int i; + 94:main.c **** for(i=0; i -1) + 139:main.c **** { + 140:main.c **** spi0_send_byte(data, 255); + 141:main.c **** uart0_send_byte(data); + 142:main.c **** } + 143:main.c **** if((PS2_STAT & (1<<1)) != 0) // char available? + 144:main.c **** { + 145:main.c **** PS2_STAT = 0; // ack + 146:main.c **** data = PS2_DATA; + 147:main.c **** spi0_send_byte(data, 255); + 148:main.c **** uart0_send_byte(data); + 149:main.c **** } + 150:main.c **** //enable_irq(); + 151:main.c **** led_timer++; + 152:main.c **** GPIO0_OUT = led_timer >> 16; + 352 137 0 + 353 0204 E1A03846 bl uart0_read_byte + 354 0208 E5053FFF .loc 1 138 0 + 355 subs r4, r0, #0 + 356 .loc 1 143 0 + 357 020c EBFFFFFE mvn r5, #61440 + 358 .loc 1 151 0 + 359 0210 E2504000 add r6, r6, #1 + 360 .loc 1 140 0 + 361 0214 E3E05A0F mov r1, #255 + 362 .loc 1 138 0 + 363 0218 E2866001 blt .L55 + 364 .loc 1 140 0 + 365 021c E3A010FF bl spi0_send_byte + 366 .loc 1 141 0 + 367 0220 BA000002 and r0, r4, #255 + 368 bl uart0_send_byte + 369 0224 EBFFFFFE .L55: + 370 .loc 1 143 0 + 371 0228 E20400FF ldr r3, [r5, #-3979] + 372 022c EBFFFFFE tst r3, #2 + 373 .loc 1 147 0 + 374 mov r1, #255 + 375 0230 E5153F8B .loc 1 143 0 + 376 0234 E3130002 beq .L57 + 377 .loc 1 145 0 + 378 0238 E3A010FF mov r3, #0 + 379 str r3, [r5, #-3979] + 380 023c 0AFFFFF0 .loc 1 146 0 + 381 ldr r4, [r5, #-3983] + 382 0240 E3A03000 .LVL14: + 383 0244 E5053F8B .loc 1 147 0 + 384 mov r0, r4 + 385 0248 E5154F8F .LVL15: + 386 .loc 1 148 0 + 387 and r4, r4, #255 + 388 024c E1A00004 .loc 1 147 0 + 389 bl spi0_send_byte + 390 .LVL16: + 391 0250 E20440FF .loc 1 148 0 + 392 mov r0, r4 + 393 0254 EBFFFFFE bl uart0_send_byte + 394 b .L57 + 395 .L61: + 396 0258 E1A00004 .align 2 + 397 025c EBFFFFFE .L60: + 398 0260 EAFFFFE7 .word timeval + 399 .word timer0_isr + 400 .LFE10: + 402 0264 00000000 .comm timeval,4,4 + 403 0268 00000000 .section .debug_frame,"",%progbits + 404 .Lframe0: + 405 .4byte .LECIE0-.LSCIE0 + 406 .LSCIE0: + 517 .4byte .LFB2-.Ltext0 +DEFINED SYMBOLS + *ABS*:00000000 main.c +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:13 .text:00000000 timer0_isr +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:21 .text:00000000 $a +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:45 .text:00000034 $d + *COM*:00000004 timeval +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:51 .text:00000038 spi0_send_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:59 .text:00000038 $a +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:83 .text:00000068 uart0_read_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:105 .text:00000080 uart0_send_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:131 .text:0000009c i2c0_send_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:194 .text:00000114 enable_irq +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:215 .text:00000124 disable_irq +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:236 .text:00000134 delay +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:269 .text:00000164 main +C:\Users\STNOLT~1\AppData\Local\Temp/ccMVaaaa.s:402 .text:00000264 $d + +NO UNDEFINED SYMBOLS Index: trunk/implementations/Altera DE2 Board/software/blink_demo/.dep/main.o.d =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/.dep/main.o.d (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/.dep/main.o.d (revision 3) @@ -0,0 +1,5 @@ +main.o: main.c storm_core.h storm_soc_de2.h + +storm_core.h: + +storm_soc_de2.h: Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.hex =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.hex (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.hex (revision 3) @@ -0,0 +1,60 @@ +:10000000EA000012E59FF014E59FF014E59FF0145C +:10001000E59FF014E1A00000E51FFFF0E59FF01060 +:10002000000000380000003C0000004000000044D8 +:10003000000000480000004CEAFFFFFEEAFFFFFE60 +:10004000EAFFFFFEEAFFFFFEEAFFFFFEEAFFFFFE18 +:10005000E59F00C8E10F1000E3C1107FE38110DBD2 +:10006000E129F001E1A0D000E2400080E10F1000A2 +:10007000E3C1107FE38110D7E129F001E1A0D000B6 +:10008000E2400080E10F1000E3C1107FE38110D156 +:10009000E129F001E1A0D000E2400080E10F100072 +:1000A000E3C1107FE38110D2E129F001E1A0D0008B +:1000B000E2400080E10F1000E3C1107FE38110D324 +:1000C000E129F001E1A0D000E2400080E10F100042 +:1000D000E3C1107FE38110DFE129F001E1A0D0004E +:1000E000E3A00000E59F1038E59F2038E1510002B1 +:1000F0000A000001348100043AFFFFFBE3A0000086 +:10010000E1A01000E1A02000E1A0B000E1A070009B +:10011000E59FA014E1A0E00FE1A0F00AEAFFFFFED6 +:10012000000014000000039C000003A000000294E3 +:10013000E92D000EE59F2028E5923000E283300192 +:10014000E5823000E5921000E3E03A0FE5031FF787 +:10015000E3A02000E2833A0FE5032FCFE8BD000EB5 +:10016000E25EF0040000039CE3E0CA0FE51C3FCF11 +:10017000E3130C011AFFFFFCE1E02001E20220FF83 +:10018000E50C0FBFE50C2FC7E51C3FCFE3833C0117 +:10019000E50C3FCFE1A0F00EE3E02A0FE5123FE3CC +:1001A000E3130002E3E0000015120FE7E1A0F00EF8 +:1001B000E20000FFE3E02A0FE5123FE3E313000152 +:1001C0000AFFFFFCE5020FE7E1A0F00EE3E03A0FC3 +:1001D000E3A02090E5032FAFE20000FFE1A02003A1 +:1001E000E5123FAFE31300021AFFFFFCE3A030105B +:1001F000E5020F93E5023FAFE3E02A0FE5123FAFC0 +:10020000E31300801AFFFFFCE3A03010E5021F9308 +:10021000E5023FAFE3E02A0FE5123FAFE3130080B2 +:100220001AFFFFFCE3A03040E5023FAFE3E02A0FF6 +:10023000E5123FAFE31300021AFFFFFCE1A000014B +:10024000E1A0F00EE10F3000E3C33080E129F003BC +:10025000E1A0F00EE10F3000E3833080E129F003EC +:10026000E1A0F00EE0603280E0800103E080010058 +:10027000E1A00200E3500000D1A0F00EE3A03000A6 +:10028000E1A00000E2833001E15300001AFFFFFB10 +:10029000E1A0F00EE3A02C06E92D4070E2822008D8 +:1002A000E3E04A0FE3A05000E3A03F7DE5045FEFE9 +:1002B000E3A010FFE5045FF7E1A00005E5042FCF00 +:1002C000E5043FCBEBFFFFA7E1A00005E3A010FF93 +:1002D000EBFFFFA4E3A03063E59F20B4E5043F9F5C +:1002E000E3A017BEE283301DE5045F9BE2811A2F75 +:1002F000E5043F97E5825000E59F2098E3E0000089 +:10030000E2811080E2433079E5045FDFE5041FDB22 +:10031000E5043FD7E5002FBFE2833019E3A02001B9 +:10032000E5003F7FE5002FEFEBFFFFC5E1A0600593 +:10033000EA000001E1A03846E5053FFFEBFFFF952D +:10034000E2504000E3E05A0FE2866001E3A010FFB4 +:10035000BA000002EBFFFF83E20400FFEBFFFF9314 +:10036000E5153F8BE3130002E3A010FF0AFFFFF047 +:10037000E3A03000E5053F8BE5154F8FE1A00004B9 +:10038000E20440FFEBFFFF77E1A00004EBFFFF87F3 +:0C039000EAFFFFE70000039C00000130C2 +:0400000300000050A9 +:00000001FF Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_soc_de2.h =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/storm_soc_de2.h (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/storm_soc_de2.h (revision 3) @@ -0,0 +1,173 @@ +#ifndef storm_soc_h +#define storm_soc_h + +///////////////////////////////////////////////////////////////// +// storm_soc_de2.h - STORM SoC for Altera DE2-Board +// Based on the STORM Core Processor System +// +// Created by Stephan Nolting (stnolting@googlemail.com) +// http://www.opencores.com/project,storm_core +// http://www.opencores.com/project,storm_soc +// Last modified 07. Mar. 2012 +///////////////////////////////////////////////////////////////// + +#define REG32 (volatile unsigned int*) + +/* Internal RAM */ +#define IRAM_BASE (*(REG32 (0x00000000))) +#define IRAM_SIZE 8*1024 + +/* External RAM */ +#define XRAM_BASE (*(REG32 (0x00002000))) +#define XRAM_SIZE 8*1024*1024 + +/* Complete RAM */ +#define RAM_BASE (*(REG32 (0x00000000))) +#define RAM_SIZE IRAM_SIZE+XRAM_SIZE + +/* Internal ROM (boot ROM) */ +#define ROM_BASE (*(REG32 (0xFFF00000))) +#define ROM_SIZE 2*1024 + +/* De-Cached IO Area */ +#define IO_AREA_BEGIN (*(REG32 (0xFFFF0000))) +#define IO_AREA_END (*(REG32 (0xFFFFFFFF))) +#define IO_AREA_SIZE 524288; + +/* General Purpose IO Controller 0 */ +#define GPIO0_BASE (*(REG32 (0xFFFF0000))) +#define GPIO0_SIZE 2*4 +#define GPIO0_OUT (*(REG32 (0xFFFF0000))) +#define GPIO0_IN (*(REG32 (0xFFFF0004))) + +/* Seven Segment Controller 0 */ +#define SSEG0_BASE (*(REG32 (0xFFFF0008))) +#define SSEG0_SIZE 2*4 +#define SSEG0_DATA (*(REG32 (0xFFFF0008))) +#define SSEG0_CTRL (*(REG32 (0xFFFF000C))) + +/* Seven Segment Controller 1 */ +#define SSEG1_BASE (*(REG32 (0xFFFF0010))) +#define SSEG1_SIZE 2*4 +#define SSEG1_DATA (*(REG32 (0xFFFF0010))) +#define SSEG1_CTRL (*(REG32 (0xFFFF0014))) + +/* UART 0 - miniUART */ +#define UART0_BASE (*(REG32 (0xFFFF0018))) +#define UART0_SIZE 2*4 +#define UART0_DATA (*(REG32 (0xFFFF0018))) +#define UART0_SREG (*(REG32 (0xFFFF001C))) + +/* System Timer 0 */ +#define STME0_BASE (*(REG32 (0xFFFF0020))) +#define STME0_SIZE 4*4 +#define STME0_CNT (*(REG32 (0xFFFF0020))) +#define STME0_VAL (*(REG32 (0xFFFF0024))) +#define STME0_CONF (*(REG32 (0xFFFF0028))) +#define STME0_SCRT (*(REG32 (0xFFFF002C))) + +/* SPI 0 */ +#define SPI0_BASE (*(REG32 (0xFFFF0030))) +#define SPI0_SIZE 8*4 +#define SPI0_CONF (*(REG32 (0xFFFF0030))) +#define SPI0_PRSC (*(REG32 (0xFFFF0034))) +#define SPI0_SCSR (*(REG32 (0xFFFF0038))) +// unused location (*(REG32 (0xFFFF003C))) +#define SPI0_DAT0 (*(REG32 (0xFFFF0040))) +#define SPI0_DAT1 (*(REG32 (0xFFFF0044))) +#define SPI0_DAT2 (*(REG32 (0xFFFF0048))) +#define SPI0_DAT3 (*(REG32 (0xFFFF004C))) + +/* I�C 0 */ +#define I2C0_BASE (*(REG32 (0xFFFF0050))) +#define I2C0_SIZE 8*4 +#define I2C0_CMD (*(REG32 (0xFFFF0050))) +#define I2C0_STAT (*(REG32 (0xFFFF0050))) +// unused location (*(REG32 (0xFFFF0054))) +// unused location (*(REG32 (0xFFFF0058))) +// unused location (*(REG32 (0xFFFF005C))) +#define I2C0_PRLO (*(REG32 (0xFFFF0060))) +#define I2C0_PRHI (*(REG32 (0xFFFF0064))) +#define I2C0_CTRL (*(REG32 (0xFFFF0068))) +#define I2C0_DATA (*(REG32 (0xFFFF006C))) + +/* Ps2 Interface */ +#define PS2_BASE (*(REG32 (0xFFFF0070))) +#define PS2_SIZE 2*4 +#define PS2_DATA (*(REG32 (0xFFFF0070))) +#define PS2_STAT (*(REG32 (0xFFFF0074))) + +/* External Memory CTRL */ +#define XMC_BASE (*(REG32 (0xFFFFEF00))) +#define XMC_SIZE 20*4 +#define XMC_CSR (*(REG32 (0xFFFFEF00))) +#define XMC_POC (*(REG32 (0xFFFFEF04))) +#define XMC_BA_MASK (*(REG32 (0xFFFFEF08))) +// unused location (*(REG32 (0xFFFFEF0C))) +#define XMC_CSC0 (*(REG32 (0xFFFFEF10))) +#define XMC_TMS0 (*(REG32 (0xFFFFEF14))) +#define XMC_CSC1 (*(REG32 (0xFFFFEF18))) +#define XMC_TMS1 (*(REG32 (0xFFFFEF1C))) +#define XMC_CSC2 (*(REG32 (0xFFFFEF20))) +#define XMC_TMS2 (*(REG32 (0xFFFFEF24))) +#define XMC_CSC3 (*(REG32 (0xFFFFEF28))) +#define XMC_TMS3 (*(REG32 (0xFFFFEF2C))) +#define XMC_CSC4 (*(REG32 (0xFFFFEF30))) +#define XMC_TMS4 (*(REG32 (0xFFFFEF34))) +#define XMC_CSC5 (*(REG32 (0xFFFFEF38))) +#define XMC_TMS5 (*(REG32 (0xFFFFEF3C))) +#define XMC_CSC6 (*(REG32 (0xFFFFEF40))) +#define XMC_TMS6 (*(REG32 (0xFFFFEF44))) +#define XMC_CSC7 (*(REG32 (0xFFFFEF48))) +#define XMC_TMS7 (*(REG32 (0xFFFFEF4C))) + +/* Vector Interrupt Controller */ +#define VIC_BASE (*(REG32 (0xFFFFF000))) +#define VIC_SIZE 64*4 +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) +#define VICTrigLevel (*(REG32 (0xFFFFF038))) +#define VICTrigMode (*(REG32 (0xFFFFF03C))) +#define VICVectAddr0 (*(REG32 (0xFFFFF040))) +#define VICVectAddr1 (*(REG32 (0xFFFFF044))) +#define VICVectAddr2 (*(REG32 (0xFFFFF048))) +#define VICVectAddr3 (*(REG32 (0xFFFFF04C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF050))) +#define VICVectAddr5 (*(REG32 (0xFFFFF054))) +#define VICVectAddr6 (*(REG32 (0xFFFFF058))) +#define VICVectAddr7 (*(REG32 (0xFFFFF05C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF060))) +#define VICVectAddr9 (*(REG32 (0xFFFFF064))) +#define VICVectAddr10 (*(REG32 (0xFFFFF068))) +#define VICVectAddr11 (*(REG32 (0xFFFFF06C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF070))) +#define VICVectAddr13 (*(REG32 (0xFFFFF074))) +#define VICVectAddr14 (*(REG32 (0xFFFFF078))) +#define VICVectAddr15 (*(REG32 (0xFFFFF07C))) +#define VICVectCntl0 (*(REG32 (0xFFFFF080))) +#define VICVectCntl1 (*(REG32 (0xFFFFF084))) +#define VICVectCntl2 (*(REG32 (0xFFFFF088))) +#define VICVectCntl3 (*(REG32 (0xFFFFF08C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF090))) +#define VICVectCntl5 (*(REG32 (0xFFFFF094))) +#define VICVectCntl6 (*(REG32 (0xFFFFF098))) +#define VICVectCntl7 (*(REG32 (0xFFFFF09C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF0A0))) +#define VICVectCntl9 (*(REG32 (0xFFFFF0A4))) +#define VICVectCntl10 (*(REG32 (0xFFFFF0A8))) +#define VICVectCntl11 (*(REG32 (0xFFFFF0AC))) +#define VICVectCntl12 (*(REG32 (0xFFFFF0B0))) +#define VICVectCntl13 (*(REG32 (0xFFFFF0B4))) +#define VICVectCntl14 (*(REG32 (0xFFFFF0B8))) +#define VICVectCntl15 (*(REG32 (0xFFFFF0BC))) + +#endif // storm_soc_h Index: trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.txt =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.txt (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/storm_program.txt (revision 3) @@ -0,0 +1,232 @@ +000000 => x"EA000012", +000001 => x"E59FF014", +000002 => x"E59FF014", +000003 => x"E59FF014", +000004 => x"E59FF014", +000005 => x"E1A00000", +000006 => x"E51FFFF0", +000007 => x"E59FF010", +000008 => x"00000038", +000009 => x"0000003C", +000010 => x"00000040", +000011 => x"00000044", +000012 => x"00000048", +000013 => x"0000004C", +000014 => x"EAFFFFFE", +000015 => x"EAFFFFFE", +000016 => x"EAFFFFFE", +000017 => x"EAFFFFFE", +000018 => x"EAFFFFFE", +000019 => x"EAFFFFFE", +000020 => x"E59F00C8", +000021 => x"E10F1000", +000022 => x"E3C1107F", +000023 => x"E38110DB", +000024 => x"E129F001", +000025 => x"E1A0D000", +000026 => x"E2400080", +000027 => x"E10F1000", +000028 => x"E3C1107F", +000029 => x"E38110D7", +000030 => x"E129F001", +000031 => x"E1A0D000", +000032 => x"E2400080", +000033 => x"E10F1000", +000034 => x"E3C1107F", +000035 => x"E38110D1", +000036 => x"E129F001", +000037 => x"E1A0D000", +000038 => x"E2400080", +000039 => x"E10F1000", +000040 => x"E3C1107F", +000041 => x"E38110D2", +000042 => x"E129F001", +000043 => x"E1A0D000", +000044 => x"E2400080", +000045 => x"E10F1000", +000046 => x"E3C1107F", +000047 => x"E38110D3", +000048 => x"E129F001", +000049 => x"E1A0D000", +000050 => x"E2400080", +000051 => x"E10F1000", +000052 => x"E3C1107F", +000053 => x"E38110DF", +000054 => x"E129F001", +000055 => x"E1A0D000", +000056 => x"E3A00000", +000057 => x"E59F1038", +000058 => x"E59F2038", +000059 => x"E1510002", +000060 => x"0A000001", +000061 => x"34810004", +000062 => x"3AFFFFFB", +000063 => x"E3A00000", +000064 => x"E1A01000", +000065 => x"E1A02000", +000066 => x"E1A0B000", +000067 => x"E1A07000", +000068 => x"E59FA014", +000069 => x"E1A0E00F", +000070 => x"E1A0F00A", +000071 => x"EAFFFFFE", +000072 => x"00001400", +000073 => x"0000039C", +000074 => x"000003A0", +000075 => x"00000294", +000076 => x"E92D000E", +000077 => x"E59F2028", +000078 => x"E5923000", +000079 => x"E2833001", +000080 => x"E5823000", +000081 => x"E5921000", +000082 => x"E3E03A0F", +000083 => x"E5031FF7", +000084 => x"E3A02000", +000085 => x"E2833A0F", +000086 => x"E5032FCF", +000087 => x"E8BD000E", +000088 => x"E25EF004", +000089 => x"0000039C", +000090 => x"E3E0CA0F", +000091 => x"E51C3FCF", +000092 => x"E3130C01", +000093 => x"1AFFFFFC", +000094 => x"E1E02001", +000095 => x"E20220FF", +000096 => x"E50C0FBF", +000097 => x"E50C2FC7", +000098 => x"E51C3FCF", +000099 => x"E3833C01", +000100 => x"E50C3FCF", +000101 => x"E1A0F00E", +000102 => x"E3E02A0F", +000103 => x"E5123FE3", +000104 => x"E3130002", +000105 => x"E3E00000", +000106 => x"15120FE7", +000107 => x"E1A0F00E", +000108 => x"E20000FF", +000109 => x"E3E02A0F", +000110 => x"E5123FE3", +000111 => x"E3130001", +000112 => x"0AFFFFFC", +000113 => x"E5020FE7", +000114 => x"E1A0F00E", +000115 => x"E3E03A0F", +000116 => x"E3A02090", +000117 => x"E5032FAF", +000118 => x"E20000FF", +000119 => x"E1A02003", +000120 => x"E5123FAF", +000121 => x"E3130002", +000122 => x"1AFFFFFC", +000123 => x"E3A03010", +000124 => x"E5020F93", +000125 => x"E5023FAF", +000126 => x"E3E02A0F", +000127 => x"E5123FAF", +000128 => x"E3130080", +000129 => x"1AFFFFFC", +000130 => x"E3A03010", +000131 => x"E5021F93", +000132 => x"E5023FAF", +000133 => x"E3E02A0F", +000134 => x"E5123FAF", +000135 => x"E3130080", +000136 => x"1AFFFFFC", +000137 => x"E3A03040", +000138 => x"E5023FAF", +000139 => x"E3E02A0F", +000140 => x"E5123FAF", +000141 => x"E3130002", +000142 => x"1AFFFFFC", +000143 => x"E1A00001", +000144 => x"E1A0F00E", +000145 => x"E10F3000", +000146 => x"E3C33080", +000147 => x"E129F003", +000148 => x"E1A0F00E", +000149 => x"E10F3000", +000150 => x"E3833080", +000151 => x"E129F003", +000152 => x"E1A0F00E", +000153 => x"E0603280", +000154 => x"E0800103", +000155 => x"E0800100", +000156 => x"E1A00200", +000157 => x"E3500000", +000158 => x"D1A0F00E", +000159 => x"E3A03000", +000160 => x"E1A00000", +000161 => x"E2833001", +000162 => x"E1530000", +000163 => x"1AFFFFFB", +000164 => x"E1A0F00E", +000165 => x"E3A02C06", +000166 => x"E92D4070", +000167 => x"E2822008", +000168 => x"E3E04A0F", +000169 => x"E3A05000", +000170 => x"E3A03F7D", +000171 => x"E5045FEF", +000172 => x"E3A010FF", +000173 => x"E5045FF7", +000174 => x"E1A00005", +000175 => x"E5042FCF", +000176 => x"E5043FCB", +000177 => x"EBFFFFA7", +000178 => x"E1A00005", +000179 => x"E3A010FF", +000180 => x"EBFFFFA4", +000181 => x"E3A03063", +000182 => x"E59F20B4", +000183 => x"E5043F9F", +000184 => x"E3A017BE", +000185 => x"E283301D", +000186 => x"E5045F9B", +000187 => x"E2811A2F", +000188 => x"E5043F97", +000189 => x"E5825000", +000190 => x"E59F2098", +000191 => x"E3E00000", +000192 => x"E2811080", +000193 => x"E2433079", +000194 => x"E5045FDF", +000195 => x"E5041FDB", +000196 => x"E5043FD7", +000197 => x"E5002FBF", +000198 => x"E2833019", +000199 => x"E3A02001", +000200 => x"E5003F7F", +000201 => x"E5002FEF", +000202 => x"EBFFFFC5", +000203 => x"E1A06005", +000204 => x"EA000001", +000205 => x"E1A03846", +000206 => x"E5053FFF", +000207 => x"EBFFFF95", +000208 => x"E2504000", +000209 => x"E3E05A0F", +000210 => x"E2866001", +000211 => x"E3A010FF", +000212 => x"BA000002", +000213 => x"EBFFFF83", +000214 => x"E20400FF", +000215 => x"EBFFFF93", +000216 => x"E5153F8B", +000217 => x"E3130002", +000218 => x"E3A010FF", +000219 => x"0AFFFFF0", +000220 => x"E3A03000", +000221 => x"E5053F8B", +000222 => x"E5154F8F", +000223 => x"E1A00004", +000224 => x"E20440FF", +000225 => x"EBFFFF77", +000226 => x"E1A00004", +000227 => x"EBFFFF87", +000228 => x"EAFFFFE7", +000229 => x"0000039C", +000230 => x"00000130", +others => x"F0013007" Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/blink_demo/main.elf =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/main.elf (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/main.elf (revision 3)

trunk/implementations/Altera DE2 Board/software/blink_demo/main.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/blink_demo/Makefile =================================================================== --- trunk/implementations/Altera DE2 Board/software/blink_demo/Makefile (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/blink_demo/Makefile (revision 3) @@ -0,0 +1,431 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Martin Thomas, Kaiserslautern, Germany +# +# +# based on the WinAVR makefile written by Eric B. Weddington, J�rg Wunsch, et al. +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device, using lpc21isp +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# +# Changelog: +# - 17. Feb. 2005 - added thumb-interwork support (mth) +# - 28. Apr. 2005 - added C++ support (mth) +# - 29. Arp. 2005 - changed handling for lst-Filename (mth) +# - 22. Jan. 2012 - modified to handle storm core project +# + +# MCU name and submodel +MCU = arm7m +SUBMDL = STORMcore + + +THUMB = +THUMB_IW = + + +## Create RAM-Image +RUN_MODE = RAM_RUN + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = main + + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +#SRC = + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = $(TARGET).c + +# List C++ source files here. +# use file-extension cpp for C++-files +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files +# CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = build/storm_startup_code.S + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = 2 + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +#EXTRAINCDIRS = ./include +EXTRAINCDIRS = + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + + +# Compiler flags. +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wcast-qual -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +#CFLAGS += -Wa,-adhlns=$(<:.c=.lst) +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS = -Wstrict-prototypes -Wmissing-declarations +CONLYFLAGS += -Wmissing-prototypes -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +# flags only for C++ (arm-elf-g++) +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +##ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + +#Additional libraries. + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc +NEWLIBCLPC = + +MATH_LIB = -lm + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc + +# Set Linker-Script Depending On Selected Memory +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-Tbuild/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-Tbuild/$(SUBMDL)-ROM.ld +endif + + + +# --------------------------------------------------------------------------- +# Flash-Programming support using lpc21isp by Martin Maurer + +# Settings and variables: +LPC21ISP = lpc21isp +#LPC21ISP = lpc21isp_beta +LPC21ISP_PORT = com1 +LPC21ISP_BAUD = 115200 +LPC21ISP_XTAL = 14746 +LPC21ISP_FLASHFILE = $(TARGET).hex +# verbose output: +## LPC21ISP_DEBUG = -debug +# enter bootloader via RS232 DTR/RTS (only if hardware supports this +# feature - see Philips AppNote): +LPC21ISP_CONTROL = -control + + +# --------------------------------------------------------------------------- + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = arm-elf-gcc -mbig-endian +CPP = arm-elf-g++ +OBJCOPY = arm-elf-objcopy +OBJDUMP = arm-elf-objdump +SIZE = arm-elf-size +NM = arm-elf-nm +REMOVE = rm -f +COPY = cp + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_EXTRACT = Extracting bootloader program file: +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished cmp end + +build: elf hex lss + +elf: $(TARGET).elf +hex: $(TARGET).hex +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Extract memory file. +cmp: + @echo + @echo $(MSG_EXTRACT) + storm_extractor.exe $(TARGET).elf + @echo + + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + + +# Program the device. +program: $(TARGET).hex + @echo + @echo $(MSG_LPC21_RESETREMINDER) + $(LPC21ISP) $(LPC21ISP_CONTROL) $(LPC21ISP_DEBUG) $(LPC21ISP_FLASHFILE) $(LPC21ISP_PORT) $(LPC21ISP_BAUD) $(LPC21ISP_XTAL) + + +# Create final output files (.hex, .eep) from ELF output file. +# TODO: handling the .eeprom-section should be redundant +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) a.out + $(REMOVE) storm_program.txt + $(REMOVE) storm_program.dat + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVE) .dep/* + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex lss sym clean clean_list program + Index: trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.S =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.S (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.S (revision 3) @@ -0,0 +1,175 @@ + .global main // int main(void) + + .global _etext // -> .data initial values in ROM + .global _data // -> .data area in RAM + .global _edata // end of .data area + .global __bss_start // -> .bss area in RAM + .global __bss_end__ // end of .bss area + .global _stack // top of stack + +// Stack Sizes + .set UND_STACK_SIZE, 0x00000080 + .set ABT_STACK_SIZE, 0x00000080 + .set FIQ_STACK_SIZE, 0x00000080 + .set IRQ_STACK_SIZE, 0X00000080 + .set SVC_STACK_SIZE, 0x00000080 + +// Standard definitions of Mode bits and Interrupt flags in MSRs + .set MODE_USR, 0x10 // User Mode + .set MODE_FIQ, 0x11 // FIQ Mode + .set MODE_IRQ, 0x12 // IRQ Mode + .set MODE_SVC, 0x13 // Supervisor Mode + .set MODE_ABT, 0x17 // Abort Mode + .set MODE_UND, 0x1B // Undefined Mode + .set MODE_SYS, 0x1F // System Mode + + .equ FIQ_BIT, 0x40 // when FIQ bit is set, FIQ is disabled + .equ IRQ_BIT, 0x80 // when IRQ bit is set, IRQ is disabled + + .text + .code 32 + .align 2 + + .global _boot + .func _boot +_boot: + +// Runtime Interrupt Vectors +// ------------------------------------------------------------------- +Vectors: + b _start // reset - _start + ldr pc,_undf // undefined - _undf + ldr pc,_swi // SWI - _swi + ldr pc,_pabt // program abort - _pabt + ldr pc,_dabt // data abort - _dabt + nop // reserved + ldr pc,[pc,#-0xFF0] // IRQ - read the VIC + ldr pc,_fiq // FIQ - _fiq + + +// Use this group for development +_undf: .word __undf // undefined +_swi: .word __swi // SWI +_pabt: .word __pabt // program abort +_dabt: .word __dabt // data abort +_irq: .word __irq // IRQ +_fiq: .word __fiq // FIQ + +__undf: b . // undefined +__swi: b . // SWI +__pabt: b . // program abort +__dabt: b . // data abort +__irq: b . // IRQ +__fiq: b . // FIQ + + .size _boot, . - _boot + .endfunc + + +// Setup the operating mode & stack. +// ------------------------------------------------------------------- + .global _start, start, _mainCRTStartup + .func _start + +_start: +start: +_mainCRTStartup: + +// Who am I? Where am I going? + +// Initialize Interrupt System +// - Set stack location for each mode +// - Leave in System Mode with Interrupts Disabled +// ---------------------------------------------------- + ldr r0,=_stack // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#UND_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#ABT_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#FIQ_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#IRQ_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + + sub r0,r0,#SVC_STACK_SIZE // Calc stack base + mrs r1,CPSR + bic r1,r1,#0x7F + orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode + msr CPSR,r1 + mov sp,r0 // Store stack base + +// Copy initialized data to its execution address in RAM +// ------------------------------------------------------------------- +#ifdef ROM_RUN + ldr r1,=_etext // -> ROM data start + ldr r2,=_data // -> data start + ldr r3,=_edata // -> end of data +x01: cmp r2,r3 // check if data to move + beq y01 + ldrlo r0,[r1],#4 // copy it + strlo r0,[r2],#4 + blo x01 // loop until done +y01: +#endif +// Clear .bss +// ---------- + mov r0,#0 // get a zero + ldr r1,=__bss_start // -> bss start + ldr r2,=__bss_end__ // -> bss end +x02: cmp r1,r2 // check if data to clear + beq y02 + strlo r0,[r1],#4 // clear 4 bytes + blo x02 // loop until done +y02: +// Call main program: main(0) +// -------------------------- + mov r0,#0 // no arguments (argc = 0) + mov r1,r0 + mov r2,r0 + mov fp,r0 // null frame pointer + mov r7,r0 // null frame pointer for thumb + ldr r10,=main + mov lr,pc + mov pc, r10 // enter main() + + .size _start, . - _start + .endfunc + + .global _reset, reset, exit, abort + .func _reset +_reset: +reset: +exit: +abort: + + b . // loop until reset + + .size _reset, . - _reset + .endfunc + + .end Index: trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.lst =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.lst (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/build/storm_startup_code.lst (revision 3) @@ -0,0 +1,234 @@ + 1 # 1 "build/storm_startup_code.S" + 2 # 1 "" + 1 .global main // int main(void) + 0 + 0 + 2 + 3 .global _etext // -> .data initial values in ROM + 4 .global _data // -> .data area in RAM + 5 .global _edata // end of .data area + 6 .global __bss_start // -> .bss area in RAM + 7 .global __bss_end__ // end of .bss area + 8 .global _stack // top of stack + 9 + 10 // Stack Sizes + 11 .set UND_STACK_SIZE, 0x00000080 + 12 .set ABT_STACK_SIZE, 0x00000080 + 13 .set FIQ_STACK_SIZE, 0x00000080 + 14 .set IRQ_STACK_SIZE, 0X00000080 + 15 .set SVC_STACK_SIZE, 0x00000080 + 16 + 17 // Standard definitions of Mode bits and Interrupt flags in MSRs + 18 .set MODE_USR, 0x10 // User Mode + 19 .set MODE_FIQ, 0x11 // FIQ Mode + 20 .set MODE_IRQ, 0x12 // IRQ Mode + 21 .set MODE_SVC, 0x13 // Supervisor Mode + 22 .set MODE_ABT, 0x17 // Abort Mode + 23 .set MODE_UND, 0x1B // Undefined Mode + 24 .set MODE_SYS, 0x1F // System Mode + 25 + 26 .equ FIQ_BIT, 0x40 // when FIQ bit is set, FIQ is disabled + 27 .equ IRQ_BIT, 0x80 // when IRQ bit is set, IRQ is disabled + 28 + 29 .text + 30 .code 32 + 31 .align 2 + 32 + 33 .global _boot + 34 .func _boot + 35 _boot: + 36 + 37 // Runtime Interrupt Vectors + 38 // ------------------------------------------------------------------- + 39 Vectors: + 40 0000 EAFFFFFE b _start // reset - _start + 41 0004 E59FF014 ldr pc,_undf // undefined - _undf + 42 0008 E59FF014 ldr pc,_swi // SWI - _swi + 43 000c E59FF014 ldr pc,_pabt // program abort - _pabt + 44 0010 E59FF014 ldr pc,_dabt // data abort - _dabt + 45 0014 E1A00000 nop // reserved + 46 0018 E51FFFF0 ldr pc,[pc,#-0xFF0] // IRQ - read the VIC + 47 001c E59FF010 ldr pc,_fiq // FIQ - _fiq + 48 + 49 + 50 // Use this group for development + 51 0020 00000038 _undf: .word __undf // undefined + 52 0024 0000003C _swi: .word __swi // SWI + 53 0028 00000040 _pabt: .word __pabt // program abort + 54 002c 00000044 _dabt: .word __dabt // data abort + 55 0030 00000048 _irq: .word __irq // IRQ + 56 0034 0000004C _fiq: .word __fiq // FIQ + 57 + 58 0038 EAFFFFFE __undf: b . // undefined + 59 003c EAFFFFFE __swi: b . // SWI + 60 0040 EAFFFFFE __pabt: b . // program abort + 61 0044 EAFFFFFE __dabt: b . // data abort + 62 0048 EAFFFFFE __irq: b . // IRQ + 63 004c EAFFFFFE __fiq: b . // FIQ + 64 + 66 .endfunc + 67 + 68 + 69 // Setup the operating mode & stack. + 70 // ------------------------------------------------------------------- + 71 .global _start, start, _mainCRTStartup + 72 .func _start + 73 + 74 _start: + 75 start: + 76 _mainCRTStartup: + 77 + 78 // Who am I? Where am I going? + 79 + 80 // Initialize Interrupt System + 81 // - Set stack location for each mode + 82 // - Leave in System Mode with Interrupts Disabled + 83 // ---------------------------------------------------- + 84 0050 E59F00E8 ldr r0,=_stack // Calc stack base + 85 0054 E10F1000 mrs r1,CPSR + 86 0058 E3C1107F bic r1,r1,#0x7F + 87 005c E38110DB orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode + 88 0060 E129F001 msr CPSR,r1 + 89 0064 E1A0D000 mov sp,r0 // Store stack base + 90 + 91 0068 E2400080 sub r0,r0,#UND_STACK_SIZE // Calc stack base + 92 006c E10F1000 mrs r1,CPSR + 93 0070 E3C1107F bic r1,r1,#0x7F + 94 0074 E38110D7 orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode + 95 0078 E129F001 msr CPSR,r1 + 96 007c E1A0D000 mov sp,r0 // Store stack base + 97 + 98 0080 E2400080 sub r0,r0,#ABT_STACK_SIZE // Calc stack base + 99 0084 E10F1000 mrs r1,CPSR + 100 0088 E3C1107F bic r1,r1,#0x7F + 101 008c E38110D1 orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode + 102 0090 E129F001 msr CPSR,r1 + 103 0094 E1A0D000 mov sp,r0 // Store stack base + 104 + 105 0098 E2400080 sub r0,r0,#FIQ_STACK_SIZE // Calc stack base + 106 009c E10F1000 mrs r1,CPSR + 107 00a0 E3C1107F bic r1,r1,#0x7F + 108 00a4 E38110D2 orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode + 109 00a8 E129F001 msr CPSR,r1 + 110 00ac E1A0D000 mov sp,r0 // Store stack base + 111 + 112 00b0 E2400080 sub r0,r0,#IRQ_STACK_SIZE // Calc stack base + 113 00b4 E10F1000 mrs r1,CPSR + 114 00b8 E3C1107F bic r1,r1,#0x7F + 115 00bc E38110D3 orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode + 116 00c0 E129F001 msr CPSR,r1 + 117 00c4 E1A0D000 mov sp,r0 // Store stack base + 118 + 119 00c8 E2400080 sub r0,r0,#SVC_STACK_SIZE // Calc stack base + 120 00cc E10F1000 mrs r1,CPSR + 121 00d0 E3C1107F bic r1,r1,#0x7F + 122 00d4 E38110DF orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode + 123 00d8 E129F001 msr CPSR,r1 + 124 00dc E1A0D000 mov sp,r0 // Store stack base + 125 + 126 // Copy initialized data to its execution address in RAM + 127 // ------------------------------------------------------------------- + 128 #ifdef ROM_RUN + 129 00e0 E59F105C ldr r1,=_etext // -> ROM data start + 130 00e4 E59F205C ldr r2,=_data // -> data start + 131 00e8 E59F305C ldr r3,=_edata // -> end of data + 132 00ec E1520003 x01: cmp r2,r3 // check if data to move + 133 00f0 0A000002 beq y01 + 134 00f4 34910004 ldrlo r0,[r1],#4 // copy it + 135 00f8 34820004 strlo r0,[r2],#4 + 136 00fc 3AFFFFFA blo x01 // loop until done + 137 y01: + 138 #endif + 139 // Clear .bss + 140 // ---------- + 141 0100 E3A00000 mov r0,#0 // get a zero + 142 0104 E59F1044 ldr r1,=__bss_start // -> bss start + 143 0108 E59F2044 ldr r2,=__bss_end__ // -> bss end + 144 010c E1510002 x02: cmp r1,r2 // check if data to clear + 145 0110 0A000001 beq y02 + 146 0114 34810004 strlo r0,[r1],#4 // clear 4 bytes + 147 0118 3AFFFFFB blo x02 // loop until done + 148 y02: + 149 // Call main program: main(0) + 150 // -------------------------- + 151 011c E3A00000 mov r0,#0 // no arguments (argc = 0) + 152 0120 E1A01000 mov r1,r0 + 153 0124 E1A02000 mov r2,r0 + 154 0128 E1A0B000 mov fp,r0 // null frame pointer + 155 012c E1A07000 mov r7,r0 // null frame pointer for thumb + 156 0130 E59FA020 ldr r10,=main + 157 0134 E1A0E00F mov lr,pc + 158 0138 E1A0F00A mov pc, r10 // enter main() + 159 + 161 .endfunc + 162 + 163 .global _reset, reset, exit, abort + 164 .func _reset + 165 _reset: + 166 reset: + 167 exit: + 168 abort: + 169 + 170 013c EAFFFFFE b . // loop until reset + 171 + 173 .endfunc + 174 + 175 0140 00000000 .end + 175 00000000 + 175 00000000 + 175 00000000 + 175 00000000 +DEFINED SYMBOLS + *ABS*:00000000 build/storm_startup_code.S +build/storm_startup_code.S:11 *ABS*:00000080 UND_STACK_SIZE +build/storm_startup_code.S:12 *ABS*:00000080 ABT_STACK_SIZE +build/storm_startup_code.S:13 *ABS*:00000080 FIQ_STACK_SIZE +build/storm_startup_code.S:14 *ABS*:00000080 IRQ_STACK_SIZE +build/storm_startup_code.S:15 *ABS*:00000080 SVC_STACK_SIZE +build/storm_startup_code.S:18 *ABS*:00000010 MODE_USR +build/storm_startup_code.S:19 *ABS*:00000011 MODE_FIQ +build/storm_startup_code.S:20 *ABS*:00000012 MODE_IRQ +build/storm_startup_code.S:21 *ABS*:00000013 MODE_SVC +build/storm_startup_code.S:22 *ABS*:00000017 MODE_ABT +build/storm_startup_code.S:23 *ABS*:0000001b MODE_UND +build/storm_startup_code.S:24 *ABS*:0000001f MODE_SYS +build/storm_startup_code.S:26 *ABS*:00000040 FIQ_BIT +build/storm_startup_code.S:27 *ABS*:00000080 IRQ_BIT +build/storm_startup_code.S:30 .text:00000000 $a +build/storm_startup_code.S:35 .text:00000000 _boot +build/storm_startup_code.S:39 .text:00000000 Vectors +build/storm_startup_code.S:74 .text:00000050 _start +build/storm_startup_code.S:51 .text:00000020 _undf +build/storm_startup_code.S:52 .text:00000024 _swi +build/storm_startup_code.S:53 .text:00000028 _pabt +build/storm_startup_code.S:54 .text:0000002c _dabt +build/storm_startup_code.S:56 .text:00000034 _fiq +build/storm_startup_code.S:51 .text:00000020 $d +build/storm_startup_code.S:58 .text:00000038 __undf +build/storm_startup_code.S:59 .text:0000003c __swi +build/storm_startup_code.S:60 .text:00000040 __pabt +build/storm_startup_code.S:61 .text:00000044 __dabt +build/storm_startup_code.S:55 .text:00000030 _irq +build/storm_startup_code.S:62 .text:00000048 __irq +build/storm_startup_code.S:63 .text:0000004c __fiq +build/storm_startup_code.S:58 .text:00000038 $a +build/storm_startup_code.S:75 .text:00000050 start +build/storm_startup_code.S:76 .text:00000050 _mainCRTStartup +build/storm_startup_code.S:132 .text:000000ec x01 +build/storm_startup_code.S:137 .text:00000100 y01 +build/storm_startup_code.S:144 .text:0000010c x02 +build/storm_startup_code.S:148 .text:0000011c y02 +build/storm_startup_code.S:165 .text:0000013c _reset +build/storm_startup_code.S:166 .text:0000013c reset +build/storm_startup_code.S:167 .text:0000013c exit +build/storm_startup_code.S:168 .text:0000013c abort +build/storm_startup_code.S:175 .text:00000140 $d + +UNDEFINED SYMBOLS +main +_etext +_data +_edata +__bss_start +__bss_end__ +_stack Index: trunk/implementations/Altera DE2 Board/software/bootloader/build/STORMcore-ROM.ld =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/build/STORMcore-ROM.ld (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/build/STORMcore-ROM.ld (revision 3) @@ -0,0 +1,127 @@ +/***********************************************************************/ +/* */ +/* ROM.ld: Linker Script File */ +/* */ +/***********************************************************************/ +ENTRY(_boot) +STACK_SIZE = 0x2000; + +/* Memory Definitions */ +MEMORY +{ + ROM (rx) : ORIGIN = 0xFFF00000, LENGTH = 0x00000800 + RAM (rw) : ORIGIN = 0x00000000, LENGTH = 0x00002000 +} + +/* Section Definitions */ +SECTIONS +{ + /* first section is .text which is used for code */ + .text : + { + *storm_startup_code.o (.text) /* Startup code */ + *(.text) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + } > ROM + + . = ALIGN(4); + + /* .ctors .dtors are used for c++ constructors/destructors */ + /* added by Martin Thomas 4/2005 based on Anglia Design example */ + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } >ROM + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } >ROM + + . = ALIGN(4); + /* mthomas - end */ + + + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + .data : AT (_etext) + { + _data = .; + *(.data) + SORT(CONSTRUCTORS) /* mt 4/2005 */ + } > RAM + + . = ALIGN(4); + _edata = . ; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + __bss_start = . ; + __bss_start__ = . ; + *(.bss) + *(COMMON) + . = ALIGN(4); + } > RAM + + . = ALIGN(4); + __bss_end__ = . ; + PROVIDE (__bss_end = .); + + /* .stack ALIGN(256) : */ + .stack : + { + . = ALIGN(256); + . += STACK_SIZE; + PROVIDE (_stack = .); + } > RAM + + _end = . ; + PROVIDE (end = .); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_extractor.exe =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_extractor.exe =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/storm_extractor.exe (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/storm_extractor.exe (revision 3)

trunk/implementations/Altera DE2 Board/software/bootloader/storm_extractor.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.map =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.map (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.map (revision 3) @@ -0,0 +1,214 @@ + +Memory Configuration + +Name Origin Length Attributes +ROM 0xfff00000 0x00000800 xr +RAM 0x00000000 0x00002000 rw +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD build/storm_startup_code.o +LOAD main.o +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libm.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/be\libgcc.a +START GROUP +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/be\libgcc.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libg.a +LOAD c:/winarm/bin/../lib/gcc/arm-elf/4.1.1/../../../../arm-elf/lib/be\libc.a +END GROUP + 0x00002000 STACK_SIZE = 0x2000 + +.text 0xfff00000 0x52c + *storm_startup_code.o(.text) + .text 0xfff00000 0x15c build/storm_startup_code.o + 0xfff0013c reset + 0xfff00000 _boot + 0xfff00050 _mainCRTStartup + 0xfff0013c abort + 0xfff00050 _start + 0xfff0013c _reset + 0xfff0013c exit + 0xfff00050 start + *(.text) + .text 0xfff0015c 0x2d0 main.o + 0xfff00258 program_loader + 0xfff0021c jump_app + 0xfff00174 uart0_send_byte + 0xfff0015c uart0_read_byte + 0xfff00190 uart0_printf + 0xfff001c8 mem_dump + 0xfff002e4 main + *(.rodata) + *(.rodata*) + .rodata.str1.4 + 0xfff0042c 0x100 main.o + *(.glue_7) + .glue_7 0xfff0052c 0x0 build/storm_startup_code.o + .glue_7 0xfff0052c 0x0 main.o + *(.glue_7t) + .glue_7t 0xfff0052c 0x0 build/storm_startup_code.o + .glue_7t 0xfff0052c 0x0 main.o + 0xfff0052c . = ALIGN (0x4) + +.ctors 0xfff0052c 0x0 + 0xfff0052c PROVIDE (__ctors_start__, .) + *(SORT(.ctors.*)) + *(.ctors) + 0xfff0052c PROVIDE (__ctors_end__, .) + +.dtors 0xfff0052c 0x0 + 0xfff0052c PROVIDE (__dtors_start__, .) + *(SORT(.dtors.*)) + *(.dtors) + 0xfff0052c PROVIDE (__dtors_end__, .) + 0xfff0052c . = ALIGN (0x4) + 0xfff0052c _etext = . + 0xfff0052c PROVIDE (etext, .) + +.data 0x00000000 0x0 load address 0xfff0052c + 0x00000000 _data = . + *(.data) + .data 0x00000000 0x0 build/storm_startup_code.o + .data 0x00000000 0x0 main.o + 0x00000000 . = ALIGN (0x4) + 0x00000000 _edata = . + 0x00000000 PROVIDE (edata, .) + +.bss 0x00000000 0x0 + 0x00000000 __bss_start = . + 0x00000000 __bss_start__ = . + *(.bss) + .bss 0x00000000 0x0 build/storm_startup_code.o + .bss 0x00000000 0x0 main.o + *(COMMON) + 0x00000000 . = ALIGN (0x4) + 0x00000000 . = ALIGN (0x4) + 0x00000000 __bss_end__ = . + 0x00000000 PROVIDE (__bss_end, .) + +.stack 0x00000000 0x2000 + 0x00000000 . = ALIGN (0x100) + 0x00002000 . = (. + STACK_SIZE) + *fill* 0x00000000 0x2000 00 + 0x00002000 PROVIDE (_stack, .) + 0x00002000 _end = . + 0x00002000 PROVIDE (end, .) + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.stab.excl + *(.stab.excl) + +.stab.exclstr + *(.stab.exclstr) + +.stab.index + *(.stab.index) + +.stab.indexstr + *(.stab.indexstr) + +.comment 0x00000000 0x1b + *(.comment) + .comment 0x00000000 0x1b main.o + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x40 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x20 build/storm_startup_code.o + .debug_aranges + 0x00000020 0x20 main.o + +.debug_pubnames + 0x00000000 0x81 + *(.debug_pubnames) + .debug_pubnames + 0x00000000 0x81 main.o + +.debug_info 0x00000000 0x271 + *(.debug_info .gnu.linkonce.wi.*) + .debug_info 0x00000000 0x92 build/storm_startup_code.o + .debug_info 0x00000092 0x1df main.o + +.debug_abbrev 0x00000000 0x11d + *(.debug_abbrev) + .debug_abbrev 0x00000000 0x14 build/storm_startup_code.o + .debug_abbrev 0x00000014 0x109 main.o + +.debug_line 0x00000000 0x167 + *(.debug_line) + .debug_line 0x00000000 0x99 build/storm_startup_code.o + .debug_line 0x00000099 0xce main.o + +.debug_frame 0x00000000 0xb8 + *(.debug_frame) + .debug_frame 0x00000000 0xb8 main.o + +.debug_str 0x00000000 0x10e + *(.debug_str) + .debug_str 0x00000000 0x10e main.o + +.debug_loc 0x00000000 0x1b7 + *(.debug_loc) + .debug_loc 0x00000000 0x1b7 main.o + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) +OUTPUT(main.elf elf32-bigarm) + +Cross Reference Table + +Symbol File +__bss_end__ build/storm_startup_code.o +__bss_start build/storm_startup_code.o +_boot build/storm_startup_code.o +_data build/storm_startup_code.o +_edata build/storm_startup_code.o +_etext build/storm_startup_code.o +_mainCRTStartup build/storm_startup_code.o +_reset build/storm_startup_code.o +_stack build/storm_startup_code.o +_start build/storm_startup_code.o +abort build/storm_startup_code.o +exit build/storm_startup_code.o +jump_app main.o +main main.o + build/storm_startup_code.o +mem_dump main.o +program_loader main.o +reset build/storm_startup_code.o +start build/storm_startup_code.o +uart0_printf main.o +uart0_read_byte main.o +uart0_send_byte main.o Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_core.h =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/storm_core.h (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/storm_core.h (revision 3) @@ -0,0 +1,42 @@ +#ifndef storm_core_h +#define storm_core_h + +//////////////////////////////////////////////////////////////////////////////// +// storm_core.h - STORM Core internal definitions +// +// Created by Stephan Nolting (stnolting@googlemail.com) +// http://www.opencores.com/project,storm_core +// Last modified 13. Mar. 2012 +//////////////////////////////////////////////////////////////////////////////// + +/* Internal System Coprocessor Register Set */ +#define SYS_CP 15 // system coprocessor # +#define ID_REG_0 0 // ID register 0 +#define ID_REG_1 1 // ID register 1 +#define ID_REG_2 2 // ID register 2 +#define SYS_CTRL_0 6 // system control register 0 +#define CSTAT 8 // cache statistics register +#define ADR_FB 9 // adr feedback from bus unit -> for exception analysis +#define LFSR_POLY 11 // Internal LFSR, polynomial +#define LFSR_DATA 12 // Internal LFSR, shift register +#define SYS_IO 13 // System IO ports + +/* CP_SYS_CTRL_0 */ +#define DC_FLUSH 0 // flush d-cache +#define DC_CLEAR 1 // clear d-cache +#define IC_CLEAR 2 // flush i-cache +#define DC_WTHRU 3 // cache write-thru enable +#define DC_AUTOPR 4 // auto pre-reload d-cache page +#define IC_AUTOPR 5 // auto pre-reload i-cache page +#define CACHED_IO 6 // cached IO +#define PRTC_IO 7 // protected IO +#define DC_SYNC 8 // d-cache is sync +#define LFSR_EN 13 // enable lfsr +#define LFSR_M 14 // lfsr update mode +#define LFSR_D 15 // lfsr shift direction +#define MBC_0 16 // max bus cycle length bit 0 +#define MBC_LSB 16 +#define MBC_15 31 // max bus cycle length bit 15 +#define MBC_MSB 31 + +#endif // storm_core_h Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.dat =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.dat =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.dat (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.dat (revision 3)

trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.dat Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.lss =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.lss (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.lss (revision 3) @@ -0,0 +1,720 @@ + +main.elf: file format elf32-bigarm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000052c fff00000 fff00000 00008000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .stack 00002000 00000000 00000000 00000074 2**0 + ALLOC + 2 .comment 0000001b 00000000 00000000 0000852c 2**0 + CONTENTS, READONLY + 3 .debug_aranges 00000040 00000000 00000000 00008548 2**3 + CONTENTS, READONLY, DEBUGGING + 4 .debug_pubnames 00000081 00000000 00000000 00008588 2**0 + CONTENTS, READONLY, DEBUGGING + 5 .debug_info 00000271 00000000 00000000 00008609 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_abbrev 0000011d 00000000 00000000 0000887a 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_line 00000167 00000000 00000000 00008997 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_frame 000000b8 00000000 00000000 00008b00 2**2 + CONTENTS, READONLY, DEBUGGING + 9 .debug_str 0000010e 00000000 00000000 00008bb8 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_loc 000001b7 00000000 00000000 00008cc6 2**0 + CONTENTS, READONLY, DEBUGGING +Disassembly of section .text: + +fff00000 <_boot>: + +// Runtime Interrupt Vectors +// ------------------------------------------------------------------- +Vectors: + b _start // reset - _start +fff00000: ea000012 b fff00050 <_mainCRTStartup> + ldr pc,_undf // undefined - _undf +fff00004: e59ff014 ldr pc, [pc, #20] ; fff00020 <_undf> + ldr pc,_swi // SWI - _swi +fff00008: e59ff014 ldr pc, [pc, #20] ; fff00024 <_swi> + ldr pc,_pabt // program abort - _pabt +fff0000c: e59ff014 ldr pc, [pc, #20] ; fff00028 <_pabt> + ldr pc,_dabt // data abort - _dabt +fff00010: e59ff014 ldr pc, [pc, #20] ; fff0002c <_dabt> + nop // reserved +fff00014: e1a00000 nop (mov r0,r0) + ldr pc,[pc,#-0xFF0] // IRQ - read the VIC +fff00018: e51ffff0 ldr pc, [pc, #-4080] ; ffeff030 <_stack+0xffefd030> + ldr pc,_fiq // FIQ - _fiq +fff0001c: e59ff010 ldr pc, [pc, #16] ; fff00034 <_fiq> + +fff00020 <_undf>: +fff00020: fff00038 undefined instruction 0xfff00038 + +fff00024 <_swi>: +fff00024: fff0003c undefined instruction 0xfff0003c + +fff00028 <_pabt>: +fff00028: fff00040 undefined instruction 0xfff00040 + +fff0002c <_dabt>: +fff0002c: fff00044 undefined instruction 0xfff00044 + +fff00030 <_irq>: +fff00030: fff00048 undefined instruction 0xfff00048 + +fff00034 <_fiq>: +fff00034: fff0004c undefined instruction 0xfff0004c + +fff00038 <__undf>: + + +// Use this group for development +_undf: .word __undf // undefined +_swi: .word __swi // SWI +_pabt: .word __pabt // program abort +_dabt: .word __dabt // data abort +_irq: .word __irq // IRQ +_fiq: .word __fiq // FIQ + +__undf: b . // undefined +fff00038: eafffffe b fff00038 <__undf> + +fff0003c <__swi>: +__swi: b . // SWI +fff0003c: eafffffe b fff0003c <__swi> + +fff00040 <__pabt>: +__pabt: b . // program abort +fff00040: eafffffe b fff00040 <__pabt> + +fff00044 <__dabt>: +__dabt: b . // data abort +fff00044: eafffffe b fff00044 <__dabt> + +fff00048 <__irq>: +__irq: b . // IRQ +fff00048: eafffffe b fff00048 <__irq> + +fff0004c <__fiq>: +__fiq: b . // FIQ +fff0004c: eafffffe b fff0004c <__fiq> + +fff00050 <_mainCRTStartup>: + + .size _boot, . - _boot + .endfunc + + +// Setup the operating mode & stack. +// ------------------------------------------------------------------- + .global _start, start, _mainCRTStartup + .func _start + +_start: +start: +_mainCRTStartup: + +// Who am I? Where am I going? + +// Initialize Interrupt System +// - Set stack location for each mode +// - Leave in System Mode with Interrupts Disabled +// ---------------------------------------------------- + ldr r0,=_stack // Calc stack base +fff00050: e59f00e8 ldr r0, [pc, #232] ; fff00140 <.text+0x140> + mrs r1,CPSR +fff00054: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff00058: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_UND|IRQ_BIT|FIQ_BIT // Change to Undefined Instruction mode +fff0005c: e38110db orr r1, r1, #219 ; 0xdb + msr CPSR,r1 +fff00060: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff00064: e1a0d000 mov sp, r0 + + sub r0,r0,#UND_STACK_SIZE // Calc stack base +fff00068: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR +fff0006c: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff00070: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_ABT|IRQ_BIT|FIQ_BIT // Change to Abort Mode +fff00074: e38110d7 orr r1, r1, #215 ; 0xd7 + msr CPSR,r1 +fff00078: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff0007c: e1a0d000 mov sp, r0 + + sub r0,r0,#ABT_STACK_SIZE // Calc stack base +fff00080: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR +fff00084: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff00088: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_FIQ|IRQ_BIT|FIQ_BIT // Change to FIQ Mode +fff0008c: e38110d1 orr r1, r1, #209 ; 0xd1 + msr CPSR,r1 +fff00090: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff00094: e1a0d000 mov sp, r0 + + sub r0,r0,#FIQ_STACK_SIZE // Calc stack base +fff00098: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR +fff0009c: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff000a0: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_IRQ|IRQ_BIT|FIQ_BIT // Change to IRQ Mode +fff000a4: e38110d2 orr r1, r1, #210 ; 0xd2 + msr CPSR,r1 +fff000a8: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff000ac: e1a0d000 mov sp, r0 + + sub r0,r0,#IRQ_STACK_SIZE // Calc stack base +fff000b0: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR +fff000b4: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff000b8: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_SVC|IRQ_BIT|FIQ_BIT // Change to Supervisor Mode +fff000bc: e38110d3 orr r1, r1, #211 ; 0xd3 + msr CPSR,r1 +fff000c0: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff000c4: e1a0d000 mov sp, r0 + + sub r0,r0,#SVC_STACK_SIZE // Calc stack base +fff000c8: e2400080 sub r0, r0, #128 ; 0x80 + mrs r1,CPSR +fff000cc: e10f1000 mrs r1, CPSR + bic r1,r1,#0x7F +fff000d0: e3c1107f bic r1, r1, #127 ; 0x7f + orr r1,r1,#MODE_SYS|IRQ_BIT|FIQ_BIT // Change to System Mode +fff000d4: e38110df orr r1, r1, #223 ; 0xdf + msr CPSR,r1 +fff000d8: e129f001 msr CPSR_fc, r1 + mov sp,r0 // Store stack base +fff000dc: e1a0d000 mov sp, r0 + +// Copy initialized data to its execution address in RAM +// ------------------------------------------------------------------- +#ifdef ROM_RUN + ldr r1,=_etext // -> ROM data start +fff000e0: e59f105c ldr r1, [pc, #92] ; fff00144 <.text+0x144> + ldr r2,=_data // -> data start +fff000e4: e59f205c ldr r2, [pc, #92] ; fff00148 <.text+0x148> + ldr r3,=_edata // -> end of data +fff000e8: e59f305c ldr r3, [pc, #92] ; fff0014c <.text+0x14c> + +fff000ec : +x01: cmp r2,r3 // check if data to move +fff000ec: e1520003 cmp r2, r3 + beq y01 +fff000f0: 0a000002 beq fff00100 + ldrlo r0,[r1],#4 // copy it +fff000f4: 34910004 ldrcc r0, [r1], #4 + strlo r0,[r2],#4 +fff000f8: 34820004 strcc r0, [r2], #4 + blo x01 // loop until done +fff000fc: 3afffffa bcc fff000ec + +fff00100 : +y01: +#endif +// Clear .bss +// ---------- + mov r0,#0 // get a zero +fff00100: e3a00000 mov r0, #0 ; 0x0 + ldr r1,=__bss_start // -> bss start +fff00104: e59f1044 ldr r1, [pc, #68] ; fff00150 <.text+0x150> + ldr r2,=__bss_end__ // -> bss end +fff00108: e59f2044 ldr r2, [pc, #68] ; fff00154 <.text+0x154> + +fff0010c : +x02: cmp r1,r2 // check if data to clear +fff0010c: e1510002 cmp r1, r2 + beq y02 +fff00110: 0a000001 beq fff0011c + strlo r0,[r1],#4 // clear 4 bytes +fff00114: 34810004 strcc r0, [r1], #4 + blo x02 // loop until done +fff00118: 3afffffb bcc fff0010c + +fff0011c : +y02: +// Call main program: main(0) +// -------------------------- + mov r0,#0 // no arguments (argc = 0) +fff0011c: e3a00000 mov r0, #0 ; 0x0 + mov r1,r0 +fff00120: e1a01000 mov r1, r0 + mov r2,r0 +fff00124: e1a02000 mov r2, r0 + mov fp,r0 // null frame pointer +fff00128: e1a0b000 mov fp, r0 + mov r7,r0 // null frame pointer for thumb +fff0012c: e1a07000 mov r7, r0 + ldr r10,=main +fff00130: e59fa020 ldr sl, [pc, #32] ; fff00158 <.text+0x158> + mov lr,pc +fff00134: e1a0e00f mov lr, pc + mov pc, r10 // enter main() +fff00138: e1a0f00a mov pc, sl + +fff0013c <_reset>: + + .size _start, . - _start + .endfunc + + .global _reset, reset, exit, abort + .func _reset +_reset: +reset: +exit: +abort: + + b . // loop until reset +fff0013c: eafffffe b fff0013c <_reset> +fff00140: 00002000 andeq r2, r0, r0 +fff00144: fff0052c undefined instruction 0xfff0052c +fff00148: 00000000 andeq r0, r0, r0 +fff0014c: fff0052c undefined instruction 0xfff0052c +fff00150: 00000000 andeq r0, r0, r0 +fff00154: fff0052c undefined instruction 0xfff0052c +fff00158: fff002e4 undefined instruction 0xfff002e4 + +fff0015c : + +/* ---- UART0 read byte ---- */ +int uart0_read_byte(void) +{ + if ((UART0_SREG & 2) != 0) // byte available? +fff0015c: e3e02a0f mvn r2, #61440 ; 0xf000 +fff00160: e5123fe3 ldr r3, [r2, #-4067] +fff00164: e3130002 tst r3, #2 ; 0x2 +fff00168: e3e00000 mvn r0, #0 ; 0x0 + return UART0_DATA; +fff0016c: 15120fe7 ldrne r0, [r2, #-4071] + else + return -1; +} +fff00170: e1a0f00e mov pc, lr + +fff00174 : + + +/* ---- UART0 write byte ---- */ +int uart0_send_byte(char ch) +{ +fff00174: e20000ff and r0, r0, #255 ; 0xff +fff00178: e3e02a0f mvn r2, #61440 ; 0xf000 + while((UART0_SREG & 1) == 0); // uart busy? +fff0017c: e5123fe3 ldr r3, [r2, #-4067] +fff00180: e3130001 tst r3, #1 ; 0x1 +fff00184: 0afffffc beq fff0017c + ch = ch & 255; + UART0_DATA = ch; +fff00188: e5020fe7 str r0, [r2, #-4071] + return (int)ch; +} +fff0018c: e1a0f00e mov pc, lr + +fff00190 : + + +/* ---- UART0 send string ---- */ +const char *uart0_printf(const char *string) +{ +fff00190: e92d4010 stmdb sp!, {r4, lr} +fff00194: e1a04000 mov r4, r0 + char ch; + while ((ch = *string)) { +fff00198: e5d00000 ldrb r0, [r0] +fff0019c: e3500000 cmp r0, #0 ; 0x0 +fff001a0: 1a000003 bne fff001b4 +fff001a4: ea000005 b fff001c0 +fff001a8: e5f40001 ldrb r0, [r4, #1]! +fff001ac: e3500000 cmp r0, #0 ; 0x0 +fff001b0: 0a000002 beq fff001c0 + if (uart0_send_byte(ch)<0) break; +fff001b4: ebffffee bl fff00174 +fff001b8: e3500000 cmp r0, #0 ; 0x0 +fff001bc: aafffff9 bge fff001a8 + string++; + } + return string; +} +fff001c0: e1a00004 mov r0, r4 +fff001c4: e8bd8010 ldmia sp!, {r4, pc} + +fff001c8 : + + +/* ---- Memory Dump ---- */ +void mem_dump(void) +{ +fff001c8: e92d4030 stmdb sp!, {r4, r5, lr} +fff001cc: e3a05000 mov r5, #0 ; 0x0 + unsigned long word_buffer; + unsigned long *data_pointer = 0; + + while(data_pointer != RAM_SIZE) + { + word_buffer = *data_pointer; +fff001d0: e4954004 ldr r4, [r5], #4 + uart0_send_byte(word_buffer >> 24); +fff001d4: e1a00c24 mov r0, r4, lsr #24 +fff001d8: ebffffe5 bl fff00174 + uart0_send_byte(word_buffer >> 16); +fff001dc: e1a00824 mov r0, r4, lsr #16 +fff001e0: e20000ff and r0, r0, #255 ; 0xff +fff001e4: ebffffe2 bl fff00174 + uart0_send_byte(word_buffer >> 8); +fff001e8: e1a00424 mov r0, r4, lsr #8 +fff001ec: e20000ff and r0, r0, #255 ; 0xff + uart0_send_byte(word_buffer >> 0); +fff001f0: e20440ff and r4, r4, #255 ; 0xff +fff001f4: ebffffde bl fff00174 +fff001f8: e1a00004 mov r0, r4 +fff001fc: ebffffdc bl fff00174 +fff00200: e3a03502 mov r3, #8388608 ; 0x800000 +fff00204: e2833a02 add r3, r3, #8192 ; 0x2000 +fff00208: e1550003 cmp r5, r3 +fff0020c: 1affffef bne fff001d0 + data_pointer++; + } + while(1) + asm volatile ("NOP"); +fff00210: e1a00000 nop (mov r0,r0) +fff00214: e1a00000 nop (mov r0,r0) +fff00218: eafffffc b fff00210 + +fff0021c : +} + + +/* ---- Jump to application ---- */ +void jump_app(void) +{ + unsigned long _cp_val; + + SSEG0_CTRL = 0; // deactivate status display +fff0021c: e3e02a0f mvn r2, #61440 ; 0xf000 +fff00220: e3a03000 mov r3, #0 ; 0x0 +fff00224: e5023ff3 str r3, [r2, #-4083] +fff00228: e52de004 str lr, [sp, #-4]! + SSEG1_CTRL = 0; // deactivate counter display +fff0022c: e5023feb str r3, [r2, #-4075] + + uart0_printf("\r\nStarting application...\r\n"); +fff00230: e59f001c ldr r0, [pc, #28] ; fff00254 <.text+0x254> +fff00234: ebffffd5 bl fff00190 + + asm volatile ("mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); +fff00238: ee163f16 mrc 15, 0, r3, cr6, cr6, {0} + _cp_val = _cp_val & ~(1<<3); // disable write-through strategy + asm volatile ("mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); +fff0023c: e3c33008 bic r3, r3, #8 ; 0x8 +fff00240: ee063f16 mcr 15, 0, r3, cr6, cr6, {0} + + asm volatile ("mov PC, #0"); // jump to application +fff00244: e3a0f000 mov pc, #0 ; 0x0 + while(1) + asm volatile ("NOP"); +fff00248: e1a00000 nop (mov r0,r0) +fff0024c: e1a00000 nop (mov r0,r0) +fff00250: eafffffc b fff00248 +fff00254: fff0042c undefined instruction 0xfff0042c + +fff00258 : +} + + +/* ---- Download Program ---- */ +void program_loader(void) +{ +fff00258: e92d40f0 stmdb sp!, {r4, r5, r6, r7, lr} + int timer, data, shift; + unsigned long _cp_val; + unsigned long word_buffer; + unsigned long *data_pointer; + + uart0_printf("\r\nWaiting for data\r\n"); +fff0025c: e59f0078 ldr r0, [pc, #120] ; fff002dc <.text+0x2dc> +fff00260: ebffffca bl fff00190 + + SSEG0_CTRL = 118963166; // show 'LoAd' screen +fff00264: e59f2074 ldr r2, [pc, #116] ; fff002e0 <.text+0x2e0> + SSEG1_CTRL = 0; // deactivate counter display +fff00268: e3a01000 mov r1, #0 ; 0x0 +fff0026c: e3e03a0f mvn r3, #61440 ; 0xf000 +fff00270: e3a04626 mov r4, #39845888 ; 0x2600000 +fff00274: e5032ff3 str r2, [r3, #-4083] +fff00278: e2844b96 add r4, r4, #153600 ; 0x25800 +fff0027c: e5031feb str r1, [r3, #-4075] +fff00280: e1a06001 mov r6, r1 +fff00284: e2844c02 add r4, r4, #512 ; 0x200 +fff00288: e3a05020 mov r5, #32 ; 0x20 +fff0028c: e1a07001 mov r7, r1 + + data_pointer = 0; // beginning of RAM + shift = 32; + word_buffer = 0; + timer = timeout; + while(timer != 0) // timer loop + { + data = uart0_read_byte(); +fff00290: ebffffb1 bl fff0015c + if(data == -1) +fff00294: e3700001 cmn r0, #1 ; 0x1 +fff00298: 0a00000b beq fff002cc + timer--; + else // byte received + { + // reset timer + timer = timeout; + // construct 32-bit memory entry + shift = shift - 8; +fff0029c: e2455008 sub r5, r5, #8 ; 0x8 + word_buffer = word_buffer | (data << shift); +fff002a0: e1866510 orr r6, r6, r0, lsl r5 + if(shift == 0) // word completed +fff002a4: e3550000 cmp r5, #0 ; 0x0 + { + // store memory entry + *data_pointer = word_buffer; +fff002a8: 04876004 streq r6, [r7], #4 + data_pointer = data_pointer + 1; +fff002ac: 02855020 addeq r5, r5, #32 ; 0x20 +fff002b0: 03a06000 moveq r6, #0 ; 0x0 +fff002b4: ebffffa8 bl fff0015c + word_buffer = 0; + shift = 32; + } + } + } + jump_app(); +fff002b8: e3a04626 mov r4, #39845888 ; 0x2600000 +fff002bc: e2844b96 add r4, r4, #153600 ; 0x25800 +fff002c0: e3700001 cmn r0, #1 ; 0x1 +fff002c4: e2844c02 add r4, r4, #512 ; 0x200 +fff002c8: 1afffff3 bne fff0029c +fff002cc: e2544001 subs r4, r4, #1 ; 0x1 +fff002d0: 1affffee bne fff00290 +} +fff002d4: e8bd40f0 ldmia sp!, {r4, r5, r6, r7, lr} +fff002d8: eaffffcf b fff0021c +fff002dc: fff00448 undefined instruction 0xfff00448 +fff002e0: 07173bde undefined + +fff002e4

: + + +/* ---- Main function ---- */ +int main(void) +{ + int timer, data; + unsigned long _cp_val; + unsigned long *data_pointer; + + SSEG0_CTRL = 261566072; // show 'boot' screen +fff002e4: e59f3120 ldr r3, [pc, #288] ; fff0040c <.text+0x40c> +fff002e8: e3e01a0f mvn r1, #61440 ; 0xf000 + SSEG1_CTRL = 0; // clear counter display +fff002ec: e3a02000 mov r2, #0 ; 0x0 +fff002f0: e5013ff3 str r3, [r1, #-4083] +fff002f4: e92d4030 stmdb sp!, {r4, r5, lr} +fff002f8: e5012feb str r2, [r1, #-4075] + + // enable write-through -> flush-cache required + asm volatile (" mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); +fff002fc: ee163f16 mrc 15, 0, r3, cr6, cr6, {0} +//_cp_val = _cp_val | (1<<0) | (1<<3); + _cp_val = _cp_val | (1<<3); + asm volatile (" mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); +fff00300: e3833008 orr r3, r3, #8 ; 0x8 +fff00304: ee063f16 mcr 15, 0, r3, cr6, cr6, {0} + + // configure external memory controller + XMC_CSR = 0x0B000600; // refresh prescaler || refresh interval + XMC_BA_MASK = 255; + // Trfc, Trp, Trcd, Twr, Burst length = pog, opmode, cas lat = 2, burst type = seq, burst length = 8 + XMC_TMS0 = 0x04138023; // = (4<<24) || (1<<20) || (1<<17) || (4<<15) || (0<<9) || (0<<7) || (2<<4) || (0<<3) || (3<<0); +fff00308: e3a0c641 mov ip, #68157440 ; 0x4100000 +fff0030c: e28cc90e add ip, ip, #229376 ; 0x38000 +fff00310: e3a0140b mov r1, #184549376 ; 0xb000000 + // Base addr, no parity, row open, bank-col addr , wp = 0, size = ?, b_width = 16, type = sdram, en + XMC_CSC0 = 0x00000411; // = (0<<16) || (0<<11) || (1<<10) || (0<<9) || (0<<8) || (0<<6) || (1<<4) || (0<<1) || (1<<0); +fff00314: e3a04e41 mov r4, #1040 ; 0x410 +fff00318: e3e02a01 mvn r2, #4096 ; 0x1000 +fff0031c: e2811c06 add r1, r1, #1536 ; 0x600 +fff00320: e28cc023 add ip, ip, #35 ; 0x23 +fff00324: e3a030ff mov r3, #255 ; 0xff +fff00328: e2844001 add r4, r4, #1 ; 0x1 +fff0032c: e50210ff str r1, [r2, #-255] + + uart0_printf("\r\nSTORM Core Processor System - by Stephan Nolting\r\n"); +fff00330: e59f00d8 ldr r0, [pc, #216] ; fff00410 <.text+0x410> +fff00334: e50230f7 str r3, [r2, #-247] +fff00338: e502c0eb str ip, [r2, #-235] +fff0033c: e50240ef str r4, [r2, #-239] +fff00340: ebffff92 bl fff00190 + uart0_printf("Bootloader for STORM SoC on Altera DE2-Board\r\n"); +fff00344: e59f00c8 ldr r0, [pc, #200] ; fff00414 <.text+0x414> +fff00348: ebffff90 bl fff00190 + uart0_printf("Version: 19.03.2012\r\n"); +fff0034c: e59f00c4 ldr r0, [pc, #196] ; fff00418 <.text+0x418> +fff00350: ebffff8e bl fff00190 + + uart0_printf("\r\n0: RAM dump\r\n"); +fff00354: e59f00c0 ldr r0, [pc, #192] ; fff0041c <.text+0x41c> +fff00358: ebffff8c bl fff00190 + uart0_printf("1: Load via UART\r\n"); +fff0035c: e59f00bc ldr r0, [pc, #188] ; fff00420 <.text+0x420> +fff00360: ebffff8a bl fff00190 + uart0_printf("x: Jump to application\r\n"); +fff00364: e59f00b8 ldr r0, [pc, #184] ; fff00424 <.text+0x424> +fff00368: ebffff88 bl fff00190 + uart0_printf("\r\nSelect: "); +fff0036c: e59f00b4 ldr r0, [pc, #180] ; fff00428 <.text+0x428> +fff00370: ebffff86 bl fff00190 +fff00374: e3a04626 mov r4, #39845888 ; 0x2600000 +fff00378: e2844b96 add r4, r4, #153600 ; 0x25800 +fff0037c: e2844c02 add r4, r4, #512 ; 0x200 +fff00380: e3e05a0f mvn r5, #61440 ; 0xf000 +fff00384: ea00000b b fff003b8 + + timer = timeout; + while(timer != 0) + { + data = uart0_read_byte(); + if(data == '1') // start program downloader + { + uart0_send_byte((char)data); + program_loader(); + } + else if((data == 'x') || ((GPIO0_IN & (1<<16)) == 0)) // start application +fff00388: e3500078 cmp r0, #120 ; 0x78 +fff0038c: 0a000019 beq fff003f8 +fff00390: e5153ffb ldr r3, [r5, #-4091] +fff00394: e3130801 tst r3, #65536 ; 0x10000 +fff00398: 0a000016 beq fff003f8 + { + uart0_send_byte((char)data); + break; + } + else if(data == '0') // print memory content +fff0039c: e3500030 cmp r0, #48 ; 0x30 + { + uart0_send_byte((char)data); + mem_dump(); + } + else + timer--; +fff003a0: 12444001 subne r4, r4, #1 ; 0x1 +fff003a4: 0a000010 beq fff003ec + SSEG1_DATA = timer >> 18; +fff003a8: e1a03944 mov r3, r4, asr #18 +fff003ac: e3540000 cmp r4, #0 ; 0x0 +fff003b0: e5053fef str r3, [r5, #-4079] +fff003b4: 0a000009 beq fff003e0 +fff003b8: ebffff67 bl fff0015c +fff003bc: e3500031 cmp r0, #49 ; 0x31 +fff003c0: e1a02000 mov r2, r0 +fff003c4: 1affffef bne fff00388 +fff003c8: ebffff69 bl fff00174 +fff003cc: ebffffa1 bl fff00258 +fff003d0: e1a03944 mov r3, r4, asr #18 +fff003d4: e3540000 cmp r4, #0 ; 0x0 +fff003d8: e5053fef str r3, [r5, #-4079] +fff003dc: 1afffff5 bne fff003b8 + } + jump_app(); +fff003e0: ebffff8d bl fff0021c +} +fff003e4: e3a00000 mov r0, #0 ; 0x0 +fff003e8: e8bd8030 ldmia sp!, {r4, r5, pc} +fff003ec: ebffff60 bl fff00174 +fff003f0: ebffff74 bl fff001c8 +fff003f4: eaffffeb b fff003a8 +fff003f8: e20200ff and r0, r2, #255 ; 0xff +fff003fc: ebffff5c bl fff00174 +fff00400: ebffff85 bl fff0021c +fff00404: e3a00000 mov r0, #0 ; 0x0 +fff00408: e8bd8030 ldmia sp!, {r4, r5, pc} +fff0040c: 0f972e78 svceq 0x00972e78 +fff00410: fff00460 undefined instruction 0xfff00460 +fff00414: fff00498 undefined instruction 0xfff00498 +fff00418: fff004c8 undefined instruction 0xfff004c8 +fff0041c: fff004e0 undefined instruction 0xfff004e0 +fff00420: fff004f0 undefined instruction 0xfff004f0 +fff00424: fff00504 undefined instruction 0xfff00504 +fff00428: fff00520 undefined instruction 0xfff00520 +fff0042c: 0d0a5374 stceq 3, cr5, [sl, #-464] +fff00430: 61727469 cmnvs r2, r9, ror #8 +fff00434: 6e672061 cdpvs 0, 6, cr2, cr7, cr1, {3} +fff00438: 70706c69 rsbvcs r6, r0, r9, ror #24 +fff0043c: 63617469 cmnvs r1, #1761607680 ; 0x69000000 +fff00440: 6f6e2e2e svcvs 0x006e2e2e +fff00444: 2e0d0a00 fmacscs s0, s26, s0 +fff00448: 0d0a5761 stceq 7, cr5, [sl, #-388] +fff0044c: 6974696e ldmvsdb r4!, {r1, r2, r3, r5, r6, r8, fp, sp, lr}^ +fff00450: 6720666f strvs r6, [r0, -pc, ror #12]! +fff00454: 72206461 eorvc r6, r0, #1627389952 ; 0x61000000 +fff00458: 74610d0a strvcbt r0, [r1], #-3338 +fff0045c: 00000000 andeq r0, r0, r0 +fff00460: 0d0a5354 stceq 3, cr5, [sl, #-336] +fff00464: 4f524d20 svcmi 0x00524d20 +fff00468: 436f7265 cmnmi pc, #1342177286 ; 0x50000006 +fff0046c: 2050726f subcss r7, r0, pc, ror #4 +fff00470: 63657373 cmnvs r5, #-872415231 ; 0xcc000001 +fff00474: 6f722053 svcvs 0x00722053 +fff00478: 79737465 ldmvcdb r3!, {r0, r2, r5, r6, sl, ip, sp, lr}^ +fff0047c: 6d202d20 stcvs 13, cr2, [r0, #-128]! +fff00480: 62792053 rsbvss r2, r9, #83 ; 0x53 +fff00484: 74657068 strvcbt r7, [r5], #-104 +fff00488: 616e204e cmnvs lr, lr, asr #32 +fff0048c: 6f6c7469 svcvs 0x006c7469 +fff00490: 6e670d0a cdpvs 13, 6, cr0, cr7, cr10, {0} +fff00494: 00000000 andeq r0, r0, r0 +fff00498: 426f6f74 rsbmi r6, pc, #464 ; 0x1d0 +fff0049c: 6c6f6164 stfvse f6, [pc], #-400 +fff004a0: 65722066 ldrvsb r2, [r2, #-102]! +fff004a4: 6f722053 svcvs 0x00722053 +fff004a8: 544f524d strplb r5, [pc], #589 ; fff004b0 <.text+0x4b0> +fff004ac: 20536f43 subcss r6, r3, r3, asr #30 +fff004b0: 206f6e20 rsbcs r6, pc, r0, lsr #28 +fff004b4: 416c7465 cmnmi ip, r5, ror #8 +fff004b8: 72612044 rsbvc r2, r1, #68 ; 0x44 +fff004bc: 45322d42 ldrmi r2, [r2, #-3394]! +fff004c0: 6f617264 svcvs 0x00617264 +fff004c4: 0d0a0000 stceq 0, cr0, [sl] +fff004c8: 56657273 undefined +fff004cc: 696f6e3a stmvsdb pc!, {r1, r3, r4, r5, r9, sl, fp, sp, lr}^ +fff004d0: 2031392e eorcss r3, r1, lr, lsr #18 +fff004d4: 30332e32 eorccs r2, r3, r2, lsr lr +fff004d8: 3031320d eorccs r3, r1, sp, lsl #4 +fff004dc: 0a000000 beq fff004e4 <.text+0x4e4> +fff004e0: 0d0a303a stceq 0, cr3, [sl, #-232] +fff004e4: 2052414d subcss r4, r2, sp, asr #2 +fff004e8: 2064756d rsbcs r7, r4, sp, ror #10 +fff004ec: 700d0a00 andvc r0, sp, r0, lsl #20 +fff004f0: 313a204c teqcc sl, ip, asr #32 +fff004f4: 6f616420 svcvs 0x00616420 +fff004f8: 76696120 strvcbt r6, [r9], -r0, lsr #2 +fff004fc: 55415254 strplb r5, [r1, #-596] +fff00500: 0d0a0000 stceq 0, cr0, [sl] +fff00504: 783a204a ldmvcda sl!, {r1, r3, r6, sp} +fff00508: 756d7020 strvcb r7, [sp, #-32]! +fff0050c: 746f2061 strvcbt r2, [pc], #97 ; fff00514 <.text+0x514> +fff00510: 70706c69 rsbvcs r6, r0, r9, ror #24 +fff00514: 63617469 cmnvs r1, #1761607680 ; 0x69000000 +fff00518: 6f6e0d0a svcvs 0x006e0d0a +fff0051c: 00000000 andeq r0, r0, r0 +fff00520: 0d0a5365 stceq 3, cr5, [sl, #-404] +fff00524: 6c656374 stcvsl 3, cr6, [r5], #-464 +fff00528: 3a200000 bcc 700530 <_stack+0x6fe530> Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.lst =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.lst (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.lst (revision 3) @@ -0,0 +1,691 @@ + 1 .file "main.c" + 9 .Ltext0: + 10 .align 2 + 11 .global uart0_read_byte + 13 uart0_read_byte: + 14 .LFB2: + 15 .file 1 "main.c" + 1:main.c **** #include "storm_core.h" + 2:main.c **** #include "storm_soc_de2.h" + 3:main.c **** + 4:main.c **** // +-------------------------------------------+ + 5:main.c **** // | STORM SoC Bootloader for Altera DE2-Board | + 6:main.c **** // +-------------------------------------------+ + 7:main.c **** + 8:main.c **** + 9:main.c **** /* ---- Constants ---- */ + 10:main.c **** #define timeout 40000000 + 11:main.c **** + 12:main.c **** + 13:main.c **** /* ---- Function Prototypes ---- */ + 14:main.c **** int uart0_read_byte(void); + 15:main.c **** int uart0_send_byte(char ch); + 16:main.c **** const char *uart0_printf(const char *string); + 17:main.c **** void mem_dump(void); + 18:main.c **** void jump_app(void); + 19:main.c **** void program_loader(void); + 20:main.c **** int main(void); + 21:main.c **** + 22:main.c **** + 23:main.c **** /* ---- UART0 read byte ---- */ + 24:main.c **** int uart0_read_byte(void) + 25:main.c **** { + 16 args = 0, pretend = 0, frame = 0 + 17 @ frame_needed = 0, uses_anonymous_args = 0 + 18 @ link register save eliminated. + 19 .loc 1 26 0 + 26:main.c **** if ((UART0_SREG & 2) != 0) // byte available? + 20 r2, #61440 + 21 0000 E3E02A0F ldr r3, [r2, #-4067] + 22 0004 E5123FE3 tst r3, #2 + 23 0008 E3130002 mvn r0, #0 + 24 000c E3E00000 .loc 1 27 0 + 27:main.c **** return UART0_DATA; + 25 e r0, [r2, #-4071] + 26 0010 15120FE7 .loc 1 25 0 + 27 @ lr needed for prologue + 28 .loc 1 30 0 + 28:main.c **** else + 29:main.c **** return -1; + 30:main.c **** } + 29 pc, lr + 30 0014 E1A0F00E .LFE2: + 32 .align 2 + 33 .global uart0_send_byte + 35 uart0_send_byte: + 36 .LFB3: + 37 .loc 1 35 0 + 31:main.c **** + 32:main.c **** + 33:main.c **** /* ---- UART0 write byte ---- */ + 34:main.c **** int uart0_send_byte(char ch) + 35:main.c **** { + 38 0, pretend = 0, frame = 0 + 39 @ frame_needed = 0, uses_anonymous_args = 0 + 40 @ link register save eliminated. + 41 .LVL0: + 42 @ lr needed for prologue + 43 .loc 1 35 0 + 44 and r0, r0, #255 + 45 0018 E20000FF mvn r2, #61440 + 46 001c E3E02A0F .L8: + 47 .loc 1 36 0 + 36:main.c **** while((UART0_SREG & 1) == 0); // uart busy? + 48 r2, #-4067] + 49 0020 E5123FE3 tst r3, #1 + 50 0024 E3130001 beq .L8 + 51 0028 0AFFFFFC .loc 1 38 0 + 37:main.c **** ch = ch & 255; + 38:main.c **** UART0_DATA = ch; + 52 r0, [r2, #-4071] + 53 002c E5020FE7 .LVL1: + 54 .loc 1 40 0 + 39:main.c **** return (int)ch; + 40:main.c **** } + 55 v pc, lr + 56 0030 E1A0F00E .LFE3: + 58 .align 2 + 59 .global uart0_printf + 61 uart0_printf: + 62 .LFB4: + 63 .loc 1 45 0 + 41:main.c **** + 42:main.c **** + 43:main.c **** /* ---- UART0 send string ---- */ + 44:main.c **** const char *uart0_printf(const char *string) + 45:main.c **** { + 64 0, pretend = 0, frame = 0 + 65 @ frame_needed = 0, uses_anonymous_args = 0 + 66 .LVL2: + 67 stmfd sp!, {r4, lr} + 68 0034 E92D4010 .LCFI0: + 69 .loc 1 45 0 + 70 mov r4, r0 + 71 0038 E1A04000 .loc 1 47 0 + 46:main.c **** char ch; + 47:main.c **** while ((ch = *string)) { + 72 , [r0, #0] @ zero_extendqisi2 + 73 003c E5D00000 .LVL3: + 74 cmp r0, #0 + 75 0040 E3500000 bne .L19 + 76 0044 1A000003 b .L15 + 77 0048 EA000005 .LVL4: + 78 .L21: + 79 ldrb r0, [r4, #1]! @ zero_extendqisi2 + 80 004c E5F40001 .LVL5: + 81 cmp r0, #0 + 82 0050 E3500000 beq .L15 + 83 0054 0A000002 .L19: + 84 .loc 1 48 0 + 48:main.c **** if (uart0_send_byte(ch)<0) break; + 85 d_byte + 86 0058 EBFFFFFE .LVL6: + 87 cmp r0, #0 + 88 005c E3500000 bge .L21 + 89 0060 AAFFFFF9 .LVL7: + 90 .L15: + 91 .loc 1 52 0 + 49:main.c **** string++; + 50:main.c **** } + 51:main.c **** return string; + 52:main.c **** } + 92 , r4 + 93 0064 E1A00004 .LVL8: + 94 ldmfd sp!, {r4, pc} + 95 0068 E8BD8010 .LFE4: + 97 .align 2 + 98 .global mem_dump + 100 mem_dump: + 101 .LFB5: + 102 .loc 1 57 0 + 53:main.c **** + 54:main.c **** + 55:main.c **** /* ---- Memory Dump ---- */ + 56:main.c **** void mem_dump(void) + 57:main.c **** { + 103 , pretend = 0, frame = 0 + 104 @ frame_needed = 0, uses_anonymous_args = 0 + 105 stmfd sp!, {r4, r5, lr} + 106 006c E92D4030 .LCFI1: + 107 .loc 1 57 0 + 108 mov r5, #0 + 109 0070 E3A05000 .LVL9: + 110 .L23: + 111 .loc 1 63 0 + 58:main.c **** unsigned long word_buffer; + 59:main.c **** unsigned long *data_pointer = 0; + 60:main.c **** + 61:main.c **** while(data_pointer != RAM_SIZE) + 62:main.c **** { + 63:main.c **** word_buffer = *data_pointer; + 112 [r5], #4 + 113 0074 E4954004 .LVL10: + 114 .loc 1 64 0 + 64:main.c **** uart0_send_byte(word_buffer >> 24); + 115 v r0, r4, lsr #24 + 116 0078 E1A00C24 bl uart0_send_byte + 117 007c EBFFFFFE .loc 1 65 0 + 65:main.c **** uart0_send_byte(word_buffer >> 16); + 118 v r0, r4, lsr #16 + 119 0080 E1A00824 and r0, r0, #255 + 120 0084 E20000FF bl uart0_send_byte + 121 0088 EBFFFFFE .loc 1 66 0 + 66:main.c **** uart0_send_byte(word_buffer >> 8); + 122 r0, r4, lsr #8 + 123 008c E1A00424 and r0, r0, #255 + 124 0090 E20000FF .loc 1 67 0 + 67:main.c **** uart0_send_byte(word_buffer >> 0); + 125 d r4, r4, #255 + 126 0094 E20440FF .LVL11: + 127 .loc 1 66 0 + 128 bl uart0_send_byte + 129 0098 EBFFFFFE .loc 1 67 0 + 130 mov r0, r4 + 131 009c E1A00004 bl uart0_send_byte + 132 00a0 EBFFFFFE .loc 1 61 0 + 133 mov r3, #8388608 + 134 00a4 E3A03502 add r3, r3, #8192 + 135 00a8 E2833A02 cmp r5, r3 + 136 00ac E1550003 bne .L23 + 137 00b0 1AFFFFEF .L27: + 138 .loc 1 71 0 + 68:main.c **** data_pointer++; + 69:main.c **** } + 70:main.c **** while(1) + 71:main.c **** asm volatile ("NOP"); + 139 L27 + 140 00b4 E1A00000 .LFE5: + 142 00bc EAFFFFFC .section .rodata.str1.4,"aMS",%progbits,1 + 143 .align 2 + 144 .LC0: + 145 .ascii "\015\012Starting application...\015\012\000" + 146 .text + 147 .align 2 + 148 0000 0D0A5374 .global jump_app + 148 61727469 + 148 6E672061 + 148 70706C69 + 148 63617469 + 150 jump_app: + 151 .LFB6: + 152 .loc 1 77 0 + 153 @ args = 0, pretend = 0, frame = 0 + 154 @ frame_needed = 0, uses_anonymous_args = 0 + 72:main.c **** } + 73:main.c **** + 74:main.c **** + 75:main.c **** /* ---- Jump to application ---- */ + 76:main.c **** void jump_app(void) + 77:main.c **** { + 155 n r2, #61440 + 156 mov r3, #0 + 157 str r3, [r2, #-4083] + 78:main.c **** unsigned long _cp_val; + 79:main.c **** + 80:main.c **** SSEG0_CTRL = 0; // deactivate status display + 158 oc 1 77 0 + 159 00c0 E3E02A0F str lr, [sp, #-4]! + 160 00c4 E3A03000 .LCFI2: + 161 00c8 E5023FF3 .loc 1 81 0 + 162 str r3, [r2, #-4075] + 163 00cc E52DE004 .loc 1 83 0 + 164 ldr r0, .L31 + 81:main.c **** SSEG1_CTRL = 0; // deactivate counter display + 165 t0_printf + 166 00d0 E5023FEB .loc 1 85 0 + 82:main.c **** + 83:main.c **** uart0_printf("\r\nStarting application...\r\n"); + 167 rc p15, 0, r3, c6, c6 + 168 00d4 E59F001C .LVL12: + 169 00d8 EBFFFFFE .loc 1 87 0 + 84:main.c **** + 85:main.c **** asm volatile ("mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); + 170 c r3, r3, #8 + 171 00dc EE163F16 .LVL13: + 172 mcr p15, 0, r3, c6, c6, 0 + 86:main.c **** _cp_val = _cp_val & ~(1<<3); // disable write-through strategy + 87:main.c **** asm volatile ("mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); + 173 oc 1 89 0 + 174 00e0 E3C33008 mov PC, #0 + 175 .L29: + 176 00e4 EE063F16 .loc 1 91 0 + 88:main.c **** + 89:main.c **** asm volatile ("mov PC, #0"); // jump to application + 177 + 178 00e8 E3A0F000 NOP + 179 b .L29 + 90:main.c **** while(1) + 91:main.c **** asm volatile ("NOP"); + 180 32: + 181 00ec E1A00000 .align 2 + 182 00f0 E1A00000 .L31: + 183 00f4 EAFFFFFC .word .LC0 + 184 .LFE6: + 186 .section .rodata.str1.4 + 187 00f8 00000000 .align 2 + 188 .LC1: + 189 .ascii "\015\012Waiting for data\015\012\000" + 190 .text + 191 .align 2 + 192 .global program_loader + 194 program_loader: + 195 .LFB7: + 196 .loc 1 97 0 + 197 @ args = 0, pretend = 0, frame = 0 + 198 @ frame_needed = 0, uses_anonymous_args = 0 + 199 stmfd sp!, {r4, r5, r6, r7, lr} + 92:main.c **** } + 93:main.c **** + 94:main.c **** + 95:main.c **** /* ---- Download Program ---- */ + 96:main.c **** void program_loader(void) + 97:main.c **** { + 200 0 + 201 ldr r0, .L49 + 202 bl uart0_printf + 203 00fc E92D40F0 .loc 1 105 0 + 204 ldr r2, .L49+4 + 98:main.c **** int timer, data, shift; + 99:main.c **** unsigned long _cp_val; + 100:main.c **** unsigned long word_buffer; + 101:main.c **** unsigned long *data_pointer; + 102:main.c **** + 103:main.c **** uart0_printf("\r\nWaiting for data\r\n"); + 205 1 106 0 + 206 0100 E59F0078 mov r1, #0 + 207 0104 EBFFFFFE .loc 1 105 0 + 104:main.c **** + 105:main.c **** SSEG0_CTRL = 118963166; // show 'LoAd' screen + 208 n r3, #61440 + 209 0108 E59F2074 .loc 1 106 0 + 106:main.c **** SSEG1_CTRL = 0; // deactivate counter display + 210 ov r4, #39845888 + 211 010c E3A01000 .LVL14: + 212 .loc 1 105 0 + 213 0110 E3E03A0F str r2, [r3, #-4083] + 214 .loc 1 106 0 + 215 0114 E3A04626 add r4, r4, #153600 + 216 str r1, [r3, #-4075] + 217 mov r6, r1 + 218 0118 E5032FF3 .LVL15: + 219 add r4, r4, #512 + 220 011c E2844B96 mov r5, #32 + 221 0120 E5031FEB .LVL16: + 222 0124 E1A06001 mov r7, r1 + 223 .LVL17: + 224 0128 E2844C02 .LVL18: + 225 012c E3A05020 .L47: + 226 .loc 1 114 0 + 227 0130 E1A07001 bl uart0_read_byte + 228 .LVL19: + 229 .LVL20: + 230 .loc 1 115 0 + 107:main.c **** + 108:main.c **** data_pointer = 0; // beginning of RAM + 109:main.c **** shift = 32; + 110:main.c **** word_buffer = 0; + 111:main.c **** timer = timeout; + 112:main.c **** while(timer != 0) // timer loop + 113:main.c **** { + 114:main.c **** data = uart0_read_byte(); + 231 + 232 0134 EBFFFFFE .L35: + 233 .loc 1 122 0 + 234 sub r5, r5, #8 + 115:main.c **** if(data == -1) + 235 oc 1 123 0 + 236 0138 E3700001 orr r6, r6, r0, asl r5 + 237 013c 0A00000B .loc 1 124 0 + 238 cmp r5, #0 + 116:main.c **** timer--; + 117:main.c **** else // byte received + 118:main.c **** { + 119:main.c **** // reset timer + 120:main.c **** timer = timeout; + 121:main.c **** // construct 32-bit memory entry + 122:main.c **** shift = shift - 8; + 239 c 1 127 0 + 240 0140 E2455008 streq r6, [r7], #4 + 123:main.c **** word_buffer = word_buffer | (data << shift); + 241 loc 1 128 0 + 242 0144 E1866510 addeq r5, r5, #32 + 124:main.c **** if(shift == 0) // word completed + 243 oveq r6, #0 + 244 0148 E3550000 .loc 1 114 0 + 125:main.c **** { + 126:main.c **** // store memory entry + 127:main.c **** *data_pointer = word_buffer; + 245 l uart0_read_byte + 246 014c 04876004 .LVL21: + 128:main.c **** data_pointer = data_pointer + 1; + 247 loc 1 134 0 + 248 0150 02855020 mov r4, #39845888 + 249 0154 03A06000 add r4, r4, #153600 + 250 .LVL22: + 251 0158 EBFFFFFE .loc 1 115 0 + 252 cmn r0, #1 + 129:main.c **** word_buffer = 0; + 130:main.c **** shift = 32; + 131:main.c **** } + 132:main.c **** } + 133:main.c **** } + 134:main.c **** jump_app(); + 253 1 134 0 + 254 015c E3A04626 add r4, r4, #512 + 255 0160 E2844B96 .loc 1 115 0 + 256 bne .L35 + 257 .L48: + 258 0164 E3700001 .loc 1 112 0 + 259 subs r4, r4, #1 + 260 0168 E2844C02 bne .L47 + 261 .loc 1 135 0 + 262 016c 1AFFFFF3 ldmfd sp!, {r4, r5, r6, r7, lr} + 263 .loc 1 134 0 + 264 b jump_app + 265 0170 E2544001 .LVL23: + 266 0174 1AFFFFEE .L50: + 135:main.c **** } + 267 : + 268 0178 E8BD40F0 .word .LC1 + 269 .word 118963166 + 270 017c EAFFFFFE .LFE7: + 272 .section .rodata.str1.4 + 273 .align 2 + 274 .LC2: + 275 0180 0000001C .ascii "\015\012STORM Core Processor System - by Stephan No" + 276 0184 07173BDE .ascii "lting\015\012\000" + 277 .align 2 + 278 .LC3: + 279 .ascii "Bootloader for STORM SoC on Altera DE2-Board\015\012" + 280 0031 000000 .ascii "\000" + 281 .align 2 + 282 0034 0D0A5354 .LC4: + 282 4F524D20 + 282 436F7265 + 282 2050726F + 282 63657373 + 283 0061 6C74696E .ascii "Version: 19.03.2012\015\012\000" + 283 670D0A00 + 284 0069 000000 .align 2 + 285 .LC5: + 286 006c 426F6F74 .ascii "\015\0120: RAM dump\015\012\000" + 286 6C6F6164 + 286 65722066 + 286 6F722053 + 286 544F524D + 287 009a 00 .align 2 + 288 009b 00 .LC6: + 289 .ascii "1: Load via UART\015\012\000" + 290 009c 56657273 .align 2 + 290 696F6E3A + 290 2031392E + 290 30332E32 + 290 3031320D + 291 00b2 0000 .LC7: + 292 .ascii "x: Jump to application\015\012\000" + 293 00b4 0D0A303A .align 2 + 293 2052414D + 293 2064756D + 293 700D0A00 + 294 .LC8: + 295 .ascii "\015\012Select: \000" + 296 00c4 313A204C .text + 296 6F616420 + 296 76696120 + 296 55415254 + 296 0D0A00 + 297 00d7 00 .align 2 + 298 .global main + 300 00f1 000000 main: + 301 .LFB8: + 302 00f4 0D0A5365 .loc 1 140 0 + 302 6C656374 + 302 3A2000 + 303 00ff 00 @ args = 0, pretend = 0, frame = 0 + 304 @ frame_needed = 0, uses_anonymous_args = 0 + 305 .loc 1 145 0 + 306 ldr r3, .L65 + 307 mvn r1, #61440 + 308 .loc 1 146 0 + 136:main.c **** + 137:main.c **** + 138:main.c **** /* ---- Main function ---- */ + 139:main.c **** int main(void) + 140:main.c **** { + 309 4083] + 310 .loc 1 140 0 + 311 stmfd sp!, {r4, r5, lr} + 141:main.c **** int timer, data; + 142:main.c **** unsigned long _cp_val; + 143:main.c **** unsigned long *data_pointer; + 144:main.c **** + 145:main.c **** SSEG0_CTRL = 261566072; // show 'boot' screen + 312 FI4: + 313 0188 E59F3120 .loc 1 146 0 + 314 018c E3E01A0F str r2, [r1, #-4075] + 146:main.c **** SSEG1_CTRL = 0; // clear counter display + 315 oc 1 149 0 + 316 0190 E3A02000 mrc p15, 0, r3, c6, c6 + 317 .LVL24: + 318 0194 E5013FF3 .loc 1 152 0 + 319 orr r3, r3, #8 + 320 0198 E92D4030 .LVL25: + 321 mcr p15, 0, r3, c6, c6, 0 + 322 .loc 1 158 0 + 323 019c E5012FEB mov ip, #68157440 + 147:main.c **** + 148:main.c **** // enable write-through -> flush-cache required + 149:main.c **** asm volatile (" mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); + 324 ip, #229376 + 325 01a0 EE163F16 .loc 1 155 0 + 326 mov r1, #184549376 + 150:main.c **** //_cp_val = _cp_val | (1<<0) | (1<<3); + 151:main.c **** _cp_val = _cp_val | (1<<3); + 152:main.c **** asm volatile (" mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); + 327 oc 1 160 0 + 328 01a4 E3833008 mov r4, #1040 + 329 .loc 1 155 0 + 330 01a8 EE063F16 mvn r2, #4096 + 153:main.c **** + 154:main.c **** // configure external memory controller + 155:main.c **** XMC_CSR = 0x0B000600; // refresh prescaler || refresh interval + 156:main.c **** XMC_BA_MASK = 255; + 157:main.c **** // Trfc, Trp, Trcd, Twr, Burst length = pog, opmode, cas lat = 2, burst type = seq, burst length + 158:main.c **** XMC_TMS0 = 0x04138023; // = (4<<24) || (1<<20) || (1<<17) || (4<<15) || (0<<9) || (0<<7) || (2<<4 + 331 r1, r1, #1536 + 332 01ac E3A0C641 .loc 1 158 0 + 333 01b0 E28CC90E add ip, ip, #35 + 334 .loc 1 156 0 + 335 01b4 E3A0140B mov r3, #255 + 159:main.c **** // Base addr, no parity, row open, bank-col addr , wp = 0, size = ?, b_width = 16, type = sdram, + 160:main.c **** XMC_CSC0 = 0x00000411; // = (0<<16) || (0<<11) || (1<<10) || (0<<9) || (0<<8) || (0<<6) || (1<<4) + 336 1 160 0 + 337 01b8 E3A04E41 add r4, r4, #1 + 338 .loc 1 155 0 + 339 01bc E3E02A01 str r1, [r2, #-255] + 340 01c0 E2811C06 .loc 1 162 0 + 341 ldr r0, .L65+4 + 342 01c4 E28CC023 .loc 1 156 0 + 343 str r3, [r2, #-247] + 344 01c8 E3A030FF .loc 1 158 0 + 345 str ip, [r2, #-235] + 346 01cc E2844001 .loc 1 160 0 + 347 str r4, [r2, #-239] + 348 01d0 E50210FF .loc 1 162 0 + 161:main.c **** + 162:main.c **** uart0_printf("\r\nSTORM Core Processor System - by Stephan Nolting\r\n"); + 349 ntf + 350 01d4 E59F00D8 .loc 1 163 0 + 351 ldr r0, .L65+8 + 352 01d8 E50230F7 bl uart0_printf + 353 .loc 1 164 0 + 354 01dc E502C0EB ldr r0, .L65+12 + 355 bl uart0_printf + 356 01e0 E50240EF .loc 1 166 0 + 357 ldr r0, .L65+16 + 358 01e4 EBFFFFFE bl uart0_printf + 163:main.c **** uart0_printf("Bootloader for STORM SoC on Altera DE2-Board\r\n"); + 359 7 0 + 360 01e8 E59F00C8 ldr r0, .L65+20 + 361 01ec EBFFFFFE bl uart0_printf + 164:main.c **** uart0_printf("Version: 19.03.2012\r\n"); + 362 oc 1 168 0 + 363 01f0 E59F00C4 ldr r0, .L65+24 + 364 01f4 EBFFFFFE bl uart0_printf + 165:main.c **** + 166:main.c **** uart0_printf("\r\n0: RAM dump\r\n"); + 365 oc 1 169 0 + 366 01f8 E59F00C0 ldr r0, .L65+28 + 367 01fc EBFFFFFE bl uart0_printf + 167:main.c **** uart0_printf("1: Load via UART\r\n"); + 368 v r4, #39845888 + 369 0200 E59F00BC .LVL26: + 370 0204 EBFFFFFE add r4, r4, #153600 + 168:main.c **** uart0_printf("x: Jump to application\r\n"); + 371 d r4, r4, #512 + 372 0208 E59F00B8 mvn r5, #61440 + 373 020c EBFFFFFE b .L52 + 169:main.c **** uart0_printf("\r\nSelect: "); + 374 L27: + 375 0210 E59F00B4 .L53: + 376 0214 EBFFFFFE .loc 1 180 0 + 377 0218 E3A04626 cmp r0, #120 + 378 beq .L56 + 379 021c E2844B96 .LVL28: + 380 0220 E2844C02 ldr r3, [r5, #-4091] + 381 0224 E3E05A0F tst r3, #65536 + 382 0228 EA00000B beq .L56 + 383 .loc 1 185 0 + 384 cmp r0, #48 + 170:main.c **** + 171:main.c **** timer = timeout; + 172:main.c **** while(timer != 0) + 173:main.c **** { + 174:main.c **** data = uart0_read_byte(); + 175:main.c **** if(data == '1') // start program downloader + 176:main.c **** { + 177:main.c **** uart0_send_byte((char)data); + 178:main.c **** program_loader(); + 179:main.c **** } + 180:main.c **** else if((data == 'x') || ((GPIO0_IN & (1<<16)) == 0)) // start application + 385 0 + 386 022c E3500078 subne r4, r4, #1 + 387 0230 0A000019 .loc 1 185 0 + 388 beq .L64 + 389 0234 E5153FFB .L55: + 390 0238 E3130801 .loc 1 192 0 + 391 023c 0A000016 mov r3, r4, asr #18 + 181:main.c **** { + 182:main.c **** uart0_send_byte((char)data); + 183:main.c **** break; + 184:main.c **** } + 185:main.c **** else if(data == '0') // print memory content + 392 172 0 + 393 0240 E3500030 cmp r4, #0 + 186:main.c **** { + 187:main.c **** uart0_send_byte((char)data); + 188:main.c **** mem_dump(); + 189:main.c **** } + 190:main.c **** else + 191:main.c **** timer--; + 394 loc 1 192 0 + 395 0244 12444001 str r3, [r5, #-4079] + 396 .loc 1 172 0 + 397 0248 0A000010 beq .L59 + 398 .L52: + 192:main.c **** SSEG1_DATA = timer >> 18; + 399 1 174 0 + 400 024c E1A03944 bl uart0_read_byte + 401 .LVL29: + 402 0250 E3540000 .LVL30: + 403 .loc 1 175 0 + 404 0254 E5053FEF cmp r0, #49 + 405 .LVL31: + 406 0258 0A000009 .loc 1 174 0 + 407 mov r2, r0 + 408 .LVL32: + 409 025c EBFFFFFE .loc 1 175 0 + 410 bne .L53 + 411 .loc 1 177 0 + 412 bl uart0_send_byte + 413 0260 E3500031 .LVL33: + 414 .loc 1 178 0 + 415 bl program_loader + 416 0264 E1A02000 .loc 1 192 0 + 417 mov r3, r4, asr #18 + 418 .loc 1 172 0 + 419 0268 1AFFFFEF cmp r4, #0 + 420 .loc 1 192 0 + 421 026c EBFFFFFE str r3, [r5, #-4079] + 422 .loc 1 172 0 + 423 bne .L52 + 424 0270 EBFFFFFE .LVL34: + 425 .L59: + 426 0274 E1A03944 .loc 1 194 0 + 427 bl jump_app + 428 0278 E3540000 .LVL35: + 429 .loc 1 195 0 + 430 027c E5053FEF mov r0, #0 + 431 ldmfd sp!, {r4, r5, pc} + 432 0280 1AFFFFF5 .LVL36: + 433 .L64: + 434 .loc 1 187 0 + 193:main.c **** } + 194:main.c **** jump_app(); + 435 188 0 + 436 0284 EBFFFFFE bl mem_dump + 437 b .L55 + 195:main.c **** } + 438 L38: + 439 0288 E3A00000 .L56: + 440 028c E8BD8030 .loc 1 182 0 + 441 and r0, r2, #255 + 442 .LVL39: + 443 bl uart0_send_byte + 444 0290 EBFFFFFE .LVL40: + 445 .loc 1 194 0 + 446 bl jump_app + 447 0294 EBFFFFFE .loc 1 195 0 + 448 0298 EAFFFFEB mov r0, #0 + 449 ldmfd sp!, {r4, r5, pc} + 450 .L66: + 451 .align 2 + 452 029c E20200FF .L65: + 453 .word 261566072 + 454 02a0 EBFFFFFE .word .LC2 + 455 .word .LC3 + 456 .word .LC4 + 457 02a4 EBFFFFFE .word .LC5 + 458 .word .LC6 + 459 02a8 E3A00000 .word .LC7 + 460 02ac E8BD8030 .word .LC8 + 461 .LFE8: + 463 .section .debug_frame,"",%progbits + 464 02b0 0F972E78 .Lframe0: + 465 02b4 00000034 .4byte .LECIE0-.LSCIE0 + 466 02b8 0000006C .LSCIE0: + 467 02bc 0000009C .4byte 0xffffffff + 468 02c0 000000B4 .byte 0x1 + 469 02c4 000000C4 .ascii "\000" + 470 02c8 000000D8 .uleb128 0x1 + 471 02cc 000000F4 .sleb128 -4 + 472 .byte 0xe + 473 .byte 0xc + 594 .4byte .LFB4-.Ltext0 +DEFINED SYMBOLS + *ABS*:00000000 main.c +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:13 .text:00000000 uart0_read_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:21 .text:00000000 $a +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:36 .text:00000018 uart0_send_byte +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:62 .text:00000034 uart0_printf +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:101 .text:0000006c mem_dump +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:153 .text:000000c0 jump_app +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:187 .text:000000f8 $d +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:198 .text:000000fc program_loader +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:203 .text:000000fc $a +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:275 .text:00000180 $d +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:307 .text:00000188 main +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:313 .text:00000188 $a +C:\Users\STNOLT~1\AppData\Local\Temp/ccuAaaaa.s:464 .text:000002b0 $d + +NO UNDEFINED SYMBOLS Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.c =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.c (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.c (revision 3) @@ -0,0 +1,195 @@ +#include "storm_core.h" +#include "storm_soc_de2.h" + +// +-------------------------------------------+ +// | STORM SoC Bootloader for Altera DE2-Board | +// +-------------------------------------------+ + + +/* ---- Constants ---- */ +#define timeout 40000000 + + +/* ---- Function Prototypes ---- */ +int uart0_read_byte(void); +int uart0_send_byte(char ch); +const char *uart0_printf(const char *string); +void mem_dump(void); +void jump_app(void); +void program_loader(void); +int main(void); + + +/* ---- UART0 read byte ---- */ +int uart0_read_byte(void) +{ + if ((UART0_SREG & 2) != 0) // byte available? + return UART0_DATA; + else + return -1; +} + + +/* ---- UART0 write byte ---- */ +int uart0_send_byte(char ch) +{ + while((UART0_SREG & 1) == 0); // uart busy? + ch = ch & 255; + UART0_DATA = ch; + return (int)ch; +} + + +/* ---- UART0 send string ---- */ +const char *uart0_printf(const char *string) +{ + char ch; + while ((ch = *string)) { + if (uart0_send_byte(ch)<0) break; + string++; + } + return string; +} + + +/* ---- Memory Dump ---- */ +void mem_dump(void) +{ + unsigned long word_buffer; + unsigned long *data_pointer = 0; + + while(data_pointer != RAM_SIZE) + { + word_buffer = *data_pointer; + uart0_send_byte(word_buffer >> 24); + uart0_send_byte(word_buffer >> 16); + uart0_send_byte(word_buffer >> 8); + uart0_send_byte(word_buffer >> 0); + data_pointer++; + } + while(1) + asm volatile ("NOP"); +} + + +/* ---- Jump to application ---- */ +void jump_app(void) +{ + unsigned long _cp_val; + + SSEG0_CTRL = 0; // deactivate status display + SSEG1_CTRL = 0; // deactivate counter display + + uart0_printf("\r\nStarting application...\r\n"); + + asm volatile ("mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); + _cp_val = _cp_val & ~(1<<3); // disable write-through strategy + asm volatile ("mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); + + asm volatile ("mov PC, #0"); // jump to application + while(1) + asm volatile ("NOP"); +} + + +/* ---- Download Program ---- */ +void program_loader(void) +{ + int timer, data, shift; + unsigned long _cp_val; + unsigned long word_buffer; + unsigned long *data_pointer; + + uart0_printf("\r\nWaiting for data\r\n"); + + SSEG0_CTRL = 118963166; // show 'LoAd' screen + SSEG1_CTRL = 0; // deactivate counter display + + data_pointer = 0; // beginning of RAM + shift = 32; + word_buffer = 0; + timer = timeout; + while(timer != 0) // timer loop + { + data = uart0_read_byte(); + if(data == -1) + timer--; + else // byte received + { + // reset timer + timer = timeout; + // construct 32-bit memory entry + shift = shift - 8; + word_buffer = word_buffer | (data << shift); + if(shift == 0) // word completed + { + // store memory entry + *data_pointer = word_buffer; + data_pointer = data_pointer + 1; + word_buffer = 0; + shift = 32; + } + } + } + jump_app(); +} + + +/* ---- Main function ---- */ +int main(void) +{ + int timer, data; + unsigned long _cp_val; + unsigned long *data_pointer; + + SSEG0_CTRL = 261566072; // show 'boot' screen + SSEG1_CTRL = 0; // clear counter display + + // enable write-through -> flush-cache required + asm volatile (" mrc p15, 0, %0, c6, c6" : "=r" (_cp_val) : /* no inputs */ ); +//_cp_val = _cp_val | (1<<0) | (1<<3); + _cp_val = _cp_val | (1<<3); + asm volatile (" mcr p15, 0, %0, c6, c6, 0" : /* no outputs */ : "r" (_cp_val)); + + // configure external memory controller + XMC_CSR = 0x0B000600; // refresh prescaler || refresh interval + XMC_BA_MASK = 255; + // Trfc, Trp, Trcd, Twr, Burst length = pog, opmode, cas lat = 2, burst type = seq, burst length = 8 + XMC_TMS0 = 0x04138023; // = (4<<24) || (1<<20) || (1<<17) || (4<<15) || (0<<9) || (0<<7) || (2<<4) || (0<<3) || (3<<0); + // Base addr, no parity, row open, bank-col addr , wp = 0, size = ?, b_width = 16, type = sdram, en + XMC_CSC0 = 0x00000411; // = (0<<16) || (0<<11) || (1<<10) || (0<<9) || (0<<8) || (0<<6) || (1<<4) || (0<<1) || (1<<0); + + uart0_printf("\r\nSTORM Core Processor System - by Stephan Nolting\r\n"); + uart0_printf("Bootloader for STORM SoC on Altera DE2-Board\r\n"); + uart0_printf("Version: 19.03.2012\r\n"); + + uart0_printf("\r\n0: RAM dump\r\n"); + uart0_printf("1: Load via UART\r\n"); + uart0_printf("x: Jump to application\r\n"); + uart0_printf("\r\nSelect: "); + + timer = timeout; + while(timer != 0) + { + data = uart0_read_byte(); + if(data == '1') // start program downloader + { + uart0_send_byte((char)data); + program_loader(); + } + else if((data == 'x') || ((GPIO0_IN & (1<<16)) == 0)) // start application + { + uart0_send_byte((char)data); + break; + } + else if(data == '0') // print memory content + { + uart0_send_byte((char)data); + mem_dump(); + } + else + timer--; + SSEG1_DATA = timer >> 18; + } + jump_app(); +} Index: trunk/implementations/Altera DE2 Board/software/bootloader/.dep/main.o.d =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/.dep/main.o.d (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/.dep/main.o.d (revision 3) @@ -0,0 +1,5 @@ +main.o: main.c storm_core.h storm_soc_de2.h + +storm_core.h: + +storm_soc_de2.h: Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.hex =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.hex (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.hex (revision 3) @@ -0,0 +1,86 @@ +:02000004FFF00B +:10000000EA000012E59FF014E59FF014E59FF0145C +:10001000E59FF014E1A00000E51FFFF0E59FF01060 +:10002000FFF00038FFF0003CFFF00040FFF000441C +:10003000FFF00048FFF0004CEAFFFFFEEAFFFFFE82 +:10004000EAFFFFFEEAFFFFFEEAFFFFFEEAFFFFFE18 +:10005000E59F00E8E10F1000E3C1107FE38110DBB2 +:10006000E129F001E1A0D000E2400080E10F1000A2 +:10007000E3C1107FE38110D7E129F001E1A0D000B6 +:10008000E2400080E10F1000E3C1107FE38110D156 +:10009000E129F001E1A0D000E2400080E10F100072 +:1000A000E3C1107FE38110D2E129F001E1A0D0008B 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+:1004D0002031392E30332E323031320D0A000000F7 +:1004E0000D0A303A2052414D2064756D700D0A009E +:1004F000313A204C6F616420766961205541525435 +:100500000D0A0000783A204A756D7020746F2061E2 +:1005100070706C69636174696F6E0D0A0000000091 +:0C0520000D0A53656C6563743A200000FE +:04000005FFF0000008 +:00000001FF Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_soc_de2.h =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/storm_soc_de2.h (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/storm_soc_de2.h (revision 3) @@ -0,0 +1,173 @@ +#ifndef storm_soc_h +#define storm_soc_h + +///////////////////////////////////////////////////////////////// +// storm_soc_de2.h - STORM SoC for Altera DE2-Board +// Based on the STORM Core Processor System +// +// Created by Stephan Nolting (stnolting@googlemail.com) +// http://www.opencores.com/project,storm_core +// http://www.opencores.com/project,storm_soc +// Last modified 07. Mar. 2012 +///////////////////////////////////////////////////////////////// + +#define REG32 (volatile unsigned int*) + +/* Internal RAM */ +#define IRAM_BASE (*(REG32 (0x00000000))) +#define IRAM_SIZE 8*1024 + +/* External RAM */ +#define XRAM_BASE (*(REG32 (0x00002000))) +#define XRAM_SIZE 8*1024*1024 + +/* Complete RAM */ +#define RAM_BASE (*(REG32 (0x00000000))) +#define RAM_SIZE IRAM_SIZE+XRAM_SIZE + +/* Internal ROM (boot ROM) */ +#define ROM_BASE (*(REG32 (0xFFF00000))) +#define ROM_SIZE 2*1024 + +/* De-Cached IO Area */ +#define IO_AREA_BEGIN (*(REG32 (0xFFFF0000))) +#define IO_AREA_END (*(REG32 (0xFFFFFFFF))) +#define IO_AREA_SIZE 524288; + +/* General Purpose IO Controller 0 */ +#define GPIO0_BASE (*(REG32 (0xFFFF0000))) +#define GPIO0_SIZE 2*4 +#define GPIO0_OUT (*(REG32 (0xFFFF0000))) +#define GPIO0_IN (*(REG32 (0xFFFF0004))) + +/* Seven Segment Controller 0 */ +#define SSEG0_BASE (*(REG32 (0xFFFF0008))) +#define SSEG0_SIZE 2*4 +#define SSEG0_DATA (*(REG32 (0xFFFF0008))) +#define SSEG0_CTRL (*(REG32 (0xFFFF000C))) + +/* Seven Segment Controller 1 */ +#define SSEG1_BASE (*(REG32 (0xFFFF0010))) +#define SSEG1_SIZE 2*4 +#define SSEG1_DATA (*(REG32 (0xFFFF0010))) +#define SSEG1_CTRL (*(REG32 (0xFFFF0014))) + +/* UART 0 - miniUART */ +#define UART0_BASE (*(REG32 (0xFFFF0018))) +#define UART0_SIZE 2*4 +#define UART0_DATA (*(REG32 (0xFFFF0018))) +#define UART0_SREG (*(REG32 (0xFFFF001C))) + +/* System Timer 0 */ +#define STME0_BASE (*(REG32 (0xFFFF0020))) +#define STME0_SIZE 4*4 +#define STME0_CNT (*(REG32 (0xFFFF0020))) +#define STME0_VAL (*(REG32 (0xFFFF0024))) +#define STME0_CONF (*(REG32 (0xFFFF0028))) +#define STME0_SCRT (*(REG32 (0xFFFF002C))) + +/* SPI 0 */ +#define SPI0_BASE (*(REG32 (0xFFFF0030))) +#define SPI0_SIZE 8*4 +#define SPI0_CONF (*(REG32 (0xFFFF0030))) +#define SPI0_PRSC (*(REG32 (0xFFFF0034))) +#define SPI0_SCSR (*(REG32 (0xFFFF0038))) +// unused location (*(REG32 (0xFFFF003C))) +#define SPI0_DAT0 (*(REG32 (0xFFFF0040))) +#define SPI0_DAT1 (*(REG32 (0xFFFF0044))) +#define SPI0_DAT2 (*(REG32 (0xFFFF0048))) +#define SPI0_DAT3 (*(REG32 (0xFFFF004C))) + +/* I�C 0 */ +#define I2C0_BASE (*(REG32 (0xFFFF0050))) +#define I2C0_SIZE 8*4 +#define I2C0_CMD (*(REG32 (0xFFFF0050))) +#define I2C0_STAT (*(REG32 (0xFFFF0050))) +// unused location (*(REG32 (0xFFFF0054))) +// unused location (*(REG32 (0xFFFF0058))) +// unused location (*(REG32 (0xFFFF005C))) +#define I2C0_PRLO (*(REG32 (0xFFFF0060))) +#define I2C0_PRHI (*(REG32 (0xFFFF0064))) +#define I2C0_CTRL (*(REG32 (0xFFFF0068))) +#define I2C0_DATA (*(REG32 (0xFFFF006C))) + +/* Ps2 Interface */ +#define PS2_BASE (*(REG32 (0xFFFF0070))) +#define PS2_SIZE 2*4 +#define PS2_DATA (*(REG32 (0xFFFF0070))) +#define PS2_STAT (*(REG32 (0xFFFF0074))) + +/* External Memory CTRL */ +#define XMC_BASE (*(REG32 (0xFFFFEF00))) +#define XMC_SIZE 20*4 +#define XMC_CSR (*(REG32 (0xFFFFEF00))) +#define XMC_POC (*(REG32 (0xFFFFEF04))) +#define XMC_BA_MASK (*(REG32 (0xFFFFEF08))) +// unused location (*(REG32 (0xFFFFEF0C))) +#define XMC_CSC0 (*(REG32 (0xFFFFEF10))) +#define XMC_TMS0 (*(REG32 (0xFFFFEF14))) +#define XMC_CSC1 (*(REG32 (0xFFFFEF18))) +#define XMC_TMS1 (*(REG32 (0xFFFFEF1C))) +#define XMC_CSC2 (*(REG32 (0xFFFFEF20))) +#define XMC_TMS2 (*(REG32 (0xFFFFEF24))) +#define XMC_CSC3 (*(REG32 (0xFFFFEF28))) +#define XMC_TMS3 (*(REG32 (0xFFFFEF2C))) +#define XMC_CSC4 (*(REG32 (0xFFFFEF30))) +#define XMC_TMS4 (*(REG32 (0xFFFFEF34))) +#define XMC_CSC5 (*(REG32 (0xFFFFEF38))) +#define XMC_TMS5 (*(REG32 (0xFFFFEF3C))) +#define XMC_CSC6 (*(REG32 (0xFFFFEF40))) +#define XMC_TMS6 (*(REG32 (0xFFFFEF44))) +#define XMC_CSC7 (*(REG32 (0xFFFFEF48))) +#define XMC_TMS7 (*(REG32 (0xFFFFEF4C))) + +/* Vector Interrupt Controller */ +#define VIC_BASE (*(REG32 (0xFFFFF000))) +#define VIC_SIZE 64*4 +#define VICIRQStatus (*(REG32 (0xFFFFF000))) +#define VICFIQStatus (*(REG32 (0xFFFFF004))) +#define VICRawIntr (*(REG32 (0xFFFFF008))) +#define VICIntSelect (*(REG32 (0xFFFFF00C))) +#define VICIntEnable (*(REG32 (0xFFFFF010))) +#define VICIntEnClear (*(REG32 (0xFFFFF014))) +#define VICSoftInt (*(REG32 (0xFFFFF018))) +#define VICSoftIntClear (*(REG32 (0xFFFFF01C))) +#define VICProtection (*(REG32 (0xFFFFF020))) +#define VICVectAddr (*(REG32 (0xFFFFF030))) +#define VICDefVectAddr (*(REG32 (0xFFFFF034))) +#define VICTrigLevel (*(REG32 (0xFFFFF038))) +#define VICTrigMode (*(REG32 (0xFFFFF03C))) +#define VICVectAddr0 (*(REG32 (0xFFFFF040))) +#define VICVectAddr1 (*(REG32 (0xFFFFF044))) +#define VICVectAddr2 (*(REG32 (0xFFFFF048))) +#define VICVectAddr3 (*(REG32 (0xFFFFF04C))) +#define VICVectAddr4 (*(REG32 (0xFFFFF050))) +#define VICVectAddr5 (*(REG32 (0xFFFFF054))) +#define VICVectAddr6 (*(REG32 (0xFFFFF058))) +#define VICVectAddr7 (*(REG32 (0xFFFFF05C))) +#define VICVectAddr8 (*(REG32 (0xFFFFF060))) +#define VICVectAddr9 (*(REG32 (0xFFFFF064))) +#define VICVectAddr10 (*(REG32 (0xFFFFF068))) +#define VICVectAddr11 (*(REG32 (0xFFFFF06C))) +#define VICVectAddr12 (*(REG32 (0xFFFFF070))) +#define VICVectAddr13 (*(REG32 (0xFFFFF074))) +#define VICVectAddr14 (*(REG32 (0xFFFFF078))) +#define VICVectAddr15 (*(REG32 (0xFFFFF07C))) +#define VICVectCntl0 (*(REG32 (0xFFFFF080))) +#define VICVectCntl1 (*(REG32 (0xFFFFF084))) +#define VICVectCntl2 (*(REG32 (0xFFFFF088))) +#define VICVectCntl3 (*(REG32 (0xFFFFF08C))) +#define VICVectCntl4 (*(REG32 (0xFFFFF090))) +#define VICVectCntl5 (*(REG32 (0xFFFFF094))) +#define VICVectCntl6 (*(REG32 (0xFFFFF098))) +#define VICVectCntl7 (*(REG32 (0xFFFFF09C))) +#define VICVectCntl8 (*(REG32 (0xFFFFF0A0))) +#define VICVectCntl9 (*(REG32 (0xFFFFF0A4))) +#define VICVectCntl10 (*(REG32 (0xFFFFF0A8))) +#define VICVectCntl11 (*(REG32 (0xFFFFF0AC))) +#define VICVectCntl12 (*(REG32 (0xFFFFF0B0))) +#define VICVectCntl13 (*(REG32 (0xFFFFF0B4))) +#define VICVectCntl14 (*(REG32 (0xFFFFF0B8))) +#define VICVectCntl15 (*(REG32 (0xFFFFF0BC))) + +#endif // storm_soc_h Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.elf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/implementations/Altera DE2 Board/software/bootloader/main.elf =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/main.elf (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/main.elf (revision 3)

trunk/implementations/Altera DE2 Board/software/bootloader/main.elf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.txt =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.txt (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/storm_program.txt (revision 3) @@ -0,0 +1,332 @@ +000000 => x"EA000012", +000001 => x"E59FF014", +000002 => x"E59FF014", +000003 => x"E59FF014", +000004 => x"E59FF014", +000005 => x"E1A00000", +000006 => x"E51FFFF0", +000007 => x"E59FF010", +000008 => x"FFF00038", +000009 => x"FFF0003C", +000010 => x"FFF00040", +000011 => x"FFF00044", +000012 => x"FFF00048", +000013 => x"FFF0004C", +000014 => x"EAFFFFFE", +000015 => x"EAFFFFFE", +000016 => x"EAFFFFFE", +000017 => x"EAFFFFFE", +000018 => x"EAFFFFFE", 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x"0A000002", +000061 => x"34910004", +000062 => x"34820004", +000063 => x"3AFFFFFA", +000064 => x"E3A00000", +000065 => x"E59F1044", +000066 => x"E59F2044", +000067 => x"E1510002", +000068 => x"0A000001", +000069 => x"34810004", +000070 => x"3AFFFFFB", +000071 => x"E3A00000", +000072 => x"E1A01000", +000073 => x"E1A02000", +000074 => x"E1A0B000", +000075 => x"E1A07000", +000076 => x"E59FA020", +000077 => x"E1A0E00F", +000078 => x"E1A0F00A", +000079 => x"EAFFFFFE", +000080 => x"00002000", +000081 => x"FFF0052C", +000082 => x"00000000", +000083 => x"FFF0052C", +000084 => x"00000000", +000085 => x"FFF0052C", +000086 => x"FFF002E4", +000087 => x"E3E02A0F", +000088 => x"E5123FE3", +000089 => x"E3130002", +000090 => x"E3E00000", +000091 => x"15120FE7", +000092 => x"E1A0F00E", +000093 => x"E20000FF", +000094 => x"E3E02A0F", +000095 => x"E5123FE3", +000096 => x"E3130001", +000097 => x"0AFFFFFC", +000098 => x"E5020FE7", +000099 => x"E1A0F00E", +000100 => x"E92D4010", +000101 => x"E1A04000", +000102 => x"E5D00000", +000103 => x"E3500000", +000104 => x"1A000003", +000105 => x"EA000005", +000106 => x"E5F40001", +000107 => x"E3500000", +000108 => x"0A000002", +000109 => x"EBFFFFEE", +000110 => x"E3500000", +000111 => x"AAFFFFF9", +000112 => x"E1A00004", +000113 => x"E8BD8010", +000114 => x"E92D4030", +000115 => x"E3A05000", +000116 => x"E4954004", +000117 => x"E1A00C24", +000118 => x"EBFFFFE5", +000119 => x"E1A00824", +000120 => x"E20000FF", +000121 => x"EBFFFFE2", +000122 => x"E1A00424", +000123 => x"E20000FF", +000124 => x"E20440FF", +000125 => x"EBFFFFDE", +000126 => x"E1A00004", +000127 => x"EBFFFFDC", +000128 => x"E3A03502", +000129 => x"E2833A02", +000130 => x"E1550003", +000131 => x"1AFFFFEF", +000132 => x"E1A00000", +000133 => x"E1A00000", +000134 => x"EAFFFFFC", +000135 => x"E3E02A0F", +000136 => x"E3A03000", +000137 => x"E5023FF3", +000138 => x"E52DE004", +000139 => x"E5023FEB", +000140 => x"E59F001C", +000141 => x"EBFFFFD5", +000142 => x"EE163F16", +000143 => x"E3C33008", +000144 => x"EE063F16", +000145 => x"E3A0F000", +000146 => x"E1A00000", +000147 => x"E1A00000", +000148 => x"EAFFFFFC", +000149 => x"FFF0042C", +000150 => x"E92D40F0", +000151 => x"E59F0078", +000152 => x"EBFFFFCA", +000153 => x"E59F2074", +000154 => x"E3A01000", +000155 => x"E3E03A0F", +000156 => x"E3A04626", +000157 => x"E5032FF3", +000158 => x"E2844B96", +000159 => x"E5031FEB", +000160 => x"E1A06001", +000161 => x"E2844C02", +000162 => x"E3A05020", +000163 => x"E1A07001", +000164 => x"EBFFFFB1", +000165 => x"E3700001", +000166 => x"0A00000B", +000167 => x"E2455008", +000168 => x"E1866510", +000169 => x"E3550000", +000170 => x"04876004", +000171 => x"02855020", +000172 => x"03A06000", +000173 => x"EBFFFFA8", +000174 => x"E3A04626", +000175 => x"E2844B96", +000176 => x"E3700001", +000177 => x"E2844C02", +000178 => x"1AFFFFF3", +000179 => x"E2544001", +000180 => x"1AFFFFEE", +000181 => x"E8BD40F0", +000182 => x"EAFFFFCF", +000183 => x"FFF00448", +000184 => x"07173BDE", +000185 => x"E59F3120", +000186 => x"E3E01A0F", +000187 => x"E3A02000", +000188 => x"E5013FF3", +000189 => x"E92D4030", +000190 => x"E5012FEB", +000191 => x"EE163F16", +000192 => x"E3833008", +000193 => x"EE063F16", +000194 => x"E3A0C641", +000195 => x"E28CC90E", +000196 => x"E3A0140B", +000197 => x"E3A04E41", +000198 => x"E3E02A01", +000199 => x"E2811C06", +000200 => x"E28CC023", +000201 => x"E3A030FF", +000202 => x"E2844001", +000203 => x"E50210FF", +000204 => x"E59F00D8", +000205 => x"E50230F7", +000206 => x"E502C0EB", +000207 => x"E50240EF", +000208 => x"EBFFFF92", +000209 => x"E59F00C8", +000210 => x"EBFFFF90", +000211 => x"E59F00C4", +000212 => x"EBFFFF8E", +000213 => x"E59F00C0", +000214 => x"EBFFFF8C", +000215 => x"E59F00BC", +000216 => x"EBFFFF8A", +000217 => x"E59F00B8", +000218 => x"EBFFFF88", +000219 => x"E59F00B4", +000220 => x"EBFFFF86", +000221 => x"E3A04626", +000222 => x"E2844B96", +000223 => x"E2844C02", +000224 => x"E3E05A0F", +000225 => x"EA00000B", +000226 => x"E3500078", +000227 => x"0A000019", +000228 => x"E5153FFB", +000229 => x"E3130801", +000230 => x"0A000016", +000231 => x"E3500030", +000232 => x"12444001", +000233 => x"0A000010", +000234 => x"E1A03944", +000235 => x"E3540000", +000236 => x"E5053FEF", +000237 => x"0A000009", +000238 => x"EBFFFF67", +000239 => x"E3500031", +000240 => x"E1A02000", +000241 => x"1AFFFFEF", +000242 => x"EBFFFF69", +000243 => x"EBFFFFA1", +000244 => x"E1A03944", +000245 => x"E3540000", +000246 => x"E5053FEF", +000247 => x"1AFFFFF5", +000248 => x"EBFFFF8D", +000249 => x"E3A00000", +000250 => x"E8BD8030", +000251 => x"EBFFFF60", +000252 => x"EBFFFF74", +000253 => x"EAFFFFEB", +000254 => x"E20200FF", +000255 => x"EBFFFF5C", +000256 => x"EBFFFF85", +000257 => x"E3A00000", +000258 => x"E8BD8030", +000259 => x"0F972E78", +000260 => x"FFF00460", +000261 => x"FFF00498", +000262 => x"FFF004C8", +000263 => x"FFF004E0", +000264 => x"FFF004F0", +000265 => x"FFF00504", +000266 => x"FFF00520", +000267 => x"0D0A5374", +000268 => x"61727469", +000269 => x"6E672061", +000270 => x"70706C69", +000271 => x"63617469", +000272 => x"6F6E2E2E", +000273 => x"2E0D0A00", +000274 => x"0D0A5761", +000275 => x"6974696E", +000276 => x"6720666F", +000277 => x"72206461", +000278 => x"74610D0A", +000279 => x"00000000", +000280 => x"0D0A5354", +000281 => x"4F524D20", +000282 => x"436F7265", +000283 => x"2050726F", +000284 => x"63657373", +000285 => x"6F722053", +000286 => x"79737465", +000287 => x"6D202D20", +000288 => x"62792053", +000289 => x"74657068", +000290 => x"616E204E", +000291 => x"6F6C7469", +000292 => x"6E670D0A", +000293 => x"00000000", +000294 => x"426F6F74", +000295 => x"6C6F6164", +000296 => x"65722066", +000297 => x"6F722053", +000298 => x"544F524D", +000299 => x"20536F43", +000300 => x"206F6E20", +000301 => x"416C7465", +000302 => x"72612044", +000303 => x"45322D42", +000304 => x"6F617264", +000305 => x"0D0A0000", +000306 => x"56657273", +000307 => x"696F6E3A", +000308 => x"2031392E", +000309 => x"30332E32", +000310 => x"3031320D", +000311 => x"0A000000", +000312 => x"0D0A303A", +000313 => x"2052414D", +000314 => x"2064756D", +000315 => x"700D0A00", +000316 => x"313A204C", +000317 => x"6F616420", +000318 => x"76696120", +000319 => x"55415254", +000320 => x"0D0A0000", +000321 => x"783A204A", +000322 => x"756D7020", +000323 => x"746F2061", +000324 => x"70706C69", +000325 => x"63617469", +000326 => x"6F6E0D0A", +000327 => x"00000000", +000328 => x"0D0A5365", +000329 => x"6C656374", +000330 => x"3A200000", +others => x"F0013007" Index: trunk/implementations/Altera DE2 Board/software/bootloader/Makefile =================================================================== --- trunk/implementations/Altera DE2 Board/software/bootloader/Makefile (nonexistent) +++ trunk/implementations/Altera DE2 Board/software/bootloader/Makefile (revision 3) @@ -0,0 +1,431 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# WinARM template makefile +# by Martin Thomas, Kaiserslautern, Germany +# +# +# based on the WinAVR makefile written by Eric B. Weddington, J�rg Wunsch, et al. +# Released to the Public Domain +# Please read the make user manual! +# +# +# On command line: +# +# make all = Make software. +# +# make clean = Clean out built project files. +# +# make program = Download the hex file to the device, using lpc21isp +# +# (TODO: make filename.s = Just compile filename.c into the assembler code only) +# +# To rebuild project do "make clean" then "make all". +# +# Changelog: +# - 17. Feb. 2005 - added thumb-interwork support (mth) +# - 28. Apr. 2005 - added C++ support (mth) +# - 29. Arp. 2005 - changed handling for lst-Filename (mth) +# - 22. Jan. 2012 - modified to handle storm core project +# + +# MCU name and submodel +MCU = arm7m +SUBMDL = STORMcore + + +THUMB = +THUMB_IW = + + +## Create ROM-Image +RUN_MODE = ROM_RUN + + +# Output format. (can be srec, ihex, binary) +FORMAT = ihex + + +# Target file name (without extension). +TARGET = main + + +# List C source files here. (C dependencies are automatically generated.) +# use file-extension c for "c-only"-files +#SRC = + +# List C source files here which must be compiled in ARM-Mode. +# use file-extension c for "c-only"-files +SRCARM = $(TARGET).c + +# List C++ source files here. +# use file-extension cpp for C++-files +CPPSRC = + +# List C++ source files here which must be compiled in ARM-Mode. +# use file-extension cpp for C++-files +# CPPSRCARM = $(TARGET).cpp +CPPSRCARM = + +# List Assembler source files here. +# Make them always end in a capital .S. Files ending in a lowercase .s +# will not be considered source files but generated files (assembler +# output from the compiler), and will be deleted upon "make clean"! +# Even though the DOS/Win* filesystem matches both .s and .S the same, +# it will preserve the spelling of the filenames, and gcc itself does +# care about how the name is spelled on its command-line. +ASRC = + +# List Assembler source files here which must be assembled in ARM-Mode.. +ASRCARM = build/storm_startup_code.S + +# Optimization level, can be [0, 1, 2, 3, s]. +# 0 = turn off optimization. s = optimize for size. +# (Note: 3 is not always the best optimization level. See avr-libc FAQ.) +OPT = 2 + +# Debugging format. +# Native formats for AVR-GCC's -g are stabs [default], or dwarf-2. +# AVR (extended) COFF requires stabs, plus an avr-objcopy run. +#DEBUG = stabs +DEBUG = dwarf-2 + +# List any extra directories to look for include files here. +# Each directory must be seperated by a space. +#EXTRAINCDIRS = ./include +EXTRAINCDIRS = + +# Compiler flag to set the C Standard level. +# c89 - "ANSI" C +# gnu89 - c89 plus GCC extensions +# c99 - ISO C99 standard (not yet fully implemented) +# gnu99 - c99 plus GCC extensions +CSTANDARD = -std=gnu99 + +# Place -D or -U options for C here +CDEFS = -D$(RUN_MODE) + +# Place -I options here +CINCS = + +# Place -D or -U options for ASM here +ADEFS = -D$(RUN_MODE) + + +# Compiler flags. +# -g*: generate debugging information +# -O*: optimization level +# -f...: tuning, see GCC manual and avr-libc documentation +# -Wall...: warning level +# -Wa,...: tell GCC to pass this to the assembler. +# -adhlns...: create assembler listing +# +# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) +CFLAGS = -g$(DEBUG) +CFLAGS += $(CDEFS) $(CINCS) +CFLAGS += -O$(OPT) +CFLAGS += -Wall -Wcast-align -Wcast-qual -Wimplicit +CFLAGS += -Wpointer-arith -Wswitch +CFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused +#CFLAGS += -Wa,-adhlns=$(<:.c=.lst) +CFLAGS += -Wa,-adhlns=$(subst $(suffix $<),.lst,$<) +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +# flags only for C +CONLYFLAGS = -Wstrict-prototypes -Wmissing-declarations +CONLYFLAGS += -Wmissing-prototypes -Wnested-externs +CONLYFLAGS += $(CSTANDARD) + +# flags only for C++ (arm-elf-g++) +CPPFLAGS = + +# Assembler flags. +# -Wa,...: tell GCC to pass this to the assembler. +# -ahlms: create listing +# -gstabs: have the assembler create line number information; note that +# for use in COFF files, additional information about filenames +# and function names needs to be present in the assembler source +# files -- see avr-libc docs [FIXME: not yet described there] +##ASFLAGS = -Wa,-adhlns=$(<:.S=.lst),-gstabs +ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:.S=.lst),-g$(DEBUG) + +#Additional libraries. + +#Support for newlibc-lpc (file: libnewlibc-lpc.a) +#NEWLIBLPC = -lnewlib-lpc +NEWLIBCLPC = + +MATH_LIB = -lm + +# Linker flags. +# -Wl,...: tell GCC to pass this to linker. +# -Map: create map file +# --cref: add cross reference to map file +LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref +LDFLAGS += -lc +LDFLAGS += $(NEWLIBLPC) $(MATH_LIB) +LDFLAGS += -lc -lgcc + +# Set Linker-Script Depending On Selected Memory +ifeq ($(RUN_MODE),RAM_RUN) +LDFLAGS +=-Tbuild/$(SUBMDL)-RAM.ld +else +LDFLAGS +=-Tbuild/$(SUBMDL)-ROM.ld +endif + + + +# --------------------------------------------------------------------------- +# Flash-Programming support using lpc21isp by Martin Maurer + +# Settings and variables: +LPC21ISP = lpc21isp +#LPC21ISP = lpc21isp_beta +LPC21ISP_PORT = com1 +LPC21ISP_BAUD = 115200 +LPC21ISP_XTAL = 14746 +LPC21ISP_FLASHFILE = $(TARGET).hex +# verbose output: +## LPC21ISP_DEBUG = -debug +# enter bootloader via RS232 DTR/RTS (only if hardware supports this +# feature - see Philips AppNote): +LPC21ISP_CONTROL = -control + + +# --------------------------------------------------------------------------- + +# Define directories, if needed. +## DIRARM = c:/WinARM/ +## DIRARMBIN = $(DIRAVR)/bin/ +## DIRAVRUTILS = $(DIRAVR)/utils/bin/ + +# Define programs and commands. +SHELL = sh +CC = arm-elf-gcc -mbig-endian +CPP = arm-elf-g++ +OBJCOPY = arm-elf-objcopy +OBJDUMP = arm-elf-objdump +SIZE = arm-elf-size +NM = arm-elf-nm +REMOVE = rm -f +COPY = cp + + +# Define Messages +# English +MSG_ERRORS_NONE = Errors: none +MSG_BEGIN = -------- begin -------- +MSG_END = -------- end -------- +MSG_EXTRACT = Extracting bootloader program file: +MSG_SIZE_BEFORE = Size before: +MSG_SIZE_AFTER = Size after: +MSG_FLASH = Creating load file for Flash: +MSG_EXTENDED_LISTING = Creating Extended Listing: +MSG_SYMBOL_TABLE = Creating Symbol Table: +MSG_LINKING = Linking: +MSG_COMPILING = Compiling C: +MSG_COMPILING_ARM = "Compiling C (ARM-only):" +MSG_COMPILINGCPP = Compiling C++: +MSG_COMPILINGCPP_ARM = "Compiling C++ (ARM-only):" +MSG_ASSEMBLING = Assembling: +MSG_ASSEMBLING_ARM = "Assembling (ARM-only):" +MSG_CLEANING = Cleaning project: +MSG_LPC21_RESETREMINDER = You may have to bring the target in bootloader-mode now. + + +# Define all object files. +COBJ = $(SRC:.c=.o) +AOBJ = $(ASRC:.S=.o) +COBJARM = $(SRCARM:.c=.o) +AOBJARM = $(ASRCARM:.S=.o) +CPPOBJ = $(CPPSRC:.cpp=.o) +CPPOBJARM = $(CPPSRCARM:.cpp=.o) + +# Define all listing files. +LST = $(ASRC:.S=.lst) $(ASRCARM:.S=.lst) $(SRC:.c=.lst) $(SRCARM:.c=.lst) +LST += $(CPPSRC:.cpp=.lst) $(CPPSRCARM:.cpp=.lst) + +# Compiler flags to generate dependency files. +### GENDEPFLAGS = -Wp,-M,-MP,-MT,$(*F).o,-MF,.dep/$(@F).d +GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d + +# Combine all necessary flags and optional flags. +# Add target processor to flags. +ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. $(CFLAGS) $(GENDEPFLAGS) +ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) -I. -x assembler-with-cpp $(ASFLAGS) + + +# Default target. +all: begin gccversion sizebefore build sizeafter finished cmp end + +build: elf hex lss + +elf: $(TARGET).elf +hex: $(TARGET).hex +lss: $(TARGET).lss +sym: $(TARGET).sym + +# Extract memory file. +cmp: + @echo + @echo $(MSG_EXTRACT) + storm_extractor.exe $(TARGET).elf + @echo + + +# Eye candy. +begin: + @echo + @echo $(MSG_BEGIN) + +finished: + @echo $(MSG_ERRORS_NONE) + +end: + @echo $(MSG_END) + @echo + + +# Display size of file. +HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex +ELFSIZE = $(SIZE) -A $(TARGET).elf +sizebefore: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); echo; fi + +sizeafter: + @if [ -f $(TARGET).elf ]; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); echo; fi + + +# Display compiler version information. +gccversion : + @$(CC) --version + + +# Program the device. +program: $(TARGET).hex + @echo + @echo $(MSG_LPC21_RESETREMINDER) + $(LPC21ISP) $(LPC21ISP_CONTROL) $(LPC21ISP_DEBUG) $(LPC21ISP_FLASHFILE) $(LPC21ISP_PORT) $(LPC21ISP_BAUD) $(LPC21ISP_XTAL) + + +# Create final output files (.hex, .eep) from ELF output file. +# TODO: handling the .eeprom-section should be redundant +%.hex: %.elf + @echo + @echo $(MSG_FLASH) $@ + $(OBJCOPY) -O $(FORMAT) $< $@ + + +# Create extended listing file from ELF output file. +# testing: option -C +%.lss: %.elf + @echo + @echo $(MSG_EXTENDED_LISTING) $@ + $(OBJDUMP) -h -S -C $< > $@ + + +# Create a symbol table from ELF output file. +%.sym: %.elf + @echo + @echo $(MSG_SYMBOL_TABLE) $@ + $(NM) -n $< > $@ + + +# Link: create ELF output file from object files. +.SECONDARY : $(TARGET).elf +.PRECIOUS : $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) +%.elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) + @echo + @echo $(MSG_LINKING) $@ + $(CC) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) +# $(CPP) $(THUMB) $(ALL_CFLAGS) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) + +# Compile: create object files from C source files. ARM/Thumb +$(COBJ) : %.o : %.c + @echo + @echo $(MSG_COMPILING) $< + $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C source files. ARM-only +$(COBJARM) : %.o : %.c + @echo + @echo $(MSG_COMPILING_ARM) $< + $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM/Thumb +$(CPPOBJ) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP) $< + $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + +# Compile: create object files from C++ source files. ARM-only +$(CPPOBJARM) : %.o : %.cpp + @echo + @echo $(MSG_COMPILINGCPP_ARM) $< + $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ + + +# Compile: create assembler files from C source files. ARM/Thumb +## does not work - TODO - hints welcome +##$(COBJ) : %.s : %.c +## $(CC) $(THUMB) -S $(ALL_CFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM/Thumb +$(AOBJ) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING) $< + $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ + + +# Assemble: create object files from assembler source files. ARM-only +$(AOBJARM) : %.o : %.S + @echo + @echo $(MSG_ASSEMBLING_ARM) $< + $(CC) -c $(ALL_ASFLAGS) $< -o $@ + + +# Target: clean project. +clean: begin clean_list finished end + + +clean_list : + @echo + @echo $(MSG_CLEANING) + $(REMOVE) $(TARGET).hex + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).elf + $(REMOVE) $(TARGET).map + $(REMOVE) $(TARGET).obj + $(REMOVE) $(TARGET).a90 + $(REMOVE) $(TARGET).sym + $(REMOVE) $(TARGET).lnk + $(REMOVE) $(TARGET).lss + $(REMOVE) a.out + $(REMOVE) storm_program.txt + $(REMOVE) storm_program.dat + $(REMOVE) $(COBJ) + $(REMOVE) $(CPPOBJ) + $(REMOVE) $(AOBJ) + $(REMOVE) $(COBJARM) + $(REMOVE) $(CPPOBJARM) + $(REMOVE) $(AOBJARM) + $(REMOVE) $(LST) + $(REMOVE) $(SRC:.c=.s) + $(REMOVE) $(SRC:.c=.d) + $(REMOVE) $(SRCARM:.c=.s) + $(REMOVE) $(SRCARM:.c=.d) + $(REMOVE) $(CPPSRC:.cpp=.s) + $(REMOVE) $(CPPSRC:.cpp=.d) + $(REMOVE) $(CPPSRCARM:.cpp=.s) + $(REMOVE) $(CPPSRCARM:.cpp=.d) + $(REMOVE) .dep/* + + +# Include the dependency files. +-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) + + +# Listing of phony targets. +.PHONY : all begin finish end sizebefore sizeafter gccversion \ +build elf hex lss sym clean clean_list program +

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