URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- This comparison shows the changes necessary to convert path
/t48/branches
- from Rev 332 to Rev 333
- ↔ Reverse comparison
Rev 332 → Rev 333
/wip_t2x/bench/vhdl/tb_t8022-c.vhd
0,0 → 1,21
------------------------------------------------------------------------------- |
-- |
-- The testbench for t8022. |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration tb_t8022_behav_c0 of tb_t8022 is |
|
for behav |
|
for t8022_b : t8022 |
use configuration work.t8022_struct_c0; |
end for; |
|
end for; |
|
end tb_t8022_behav_c0; |
/wip_t2x/bench/vhdl/tb_t8022.vhd
0,0 → 1,191
------------------------------------------------------------------------------- |
-- |
-- The testbench for t8022. |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity tb_t8022 is |
|
end tb_t8022; |
|
|
use work.t48_core_comp_pack.generic_ram_ena; |
use work.t48_system_comp_pack.t8022; |
|
use work.t48_tb_pack.all; |
|
architecture behav of tb_t8022 is |
|
-- clock period, 11 MHz |
constant period_c : time := 90 ns; |
|
component lpm_rom |
generic ( |
LPM_WIDTH : positive; |
LPM_TYPE : string := "LPM_ROM"; |
LPM_WIDTHAD : positive; |
LPM_NUMWORDS : natural := 0; |
LPM_FILE : string; |
LPM_ADDRESS_CONTROL : string := "REGISTERED"; |
LPM_OUTDATA : string := "REGISTERED"; |
LPM_HINT : string := "UNUSED" |
); |
port ( |
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0); |
inclock : in std_logic; |
outclock : in std_logic; |
memenab : in std_logic; |
q : out std_logic_vector(LPM_WIDTH-1 downto 0) |
); |
end component; |
|
signal xtal_s : std_logic; |
signal res_s : std_logic; |
signal ale_s : std_logic; |
signal prog_n_s : std_logic; |
|
signal p0_b : std_logic_vector( 7 downto 0); |
signal p1_b : std_logic_vector( 7 downto 0); |
signal p2_b : std_logic_vector( 7 downto 0); |
|
signal an0_s : std_logic_vector( 7 downto 0); |
signal an1_s : std_logic_vector( 7 downto 0); |
|
signal zero_s : std_logic; |
signal one_s : std_logic; |
|
begin |
|
zero_s <= '0'; |
one_s <= '1'; |
|
p2_b <= (others => 'H'); |
p1_b <= (others => 'H'); |
p0_b <= (others => 'H'); |
|
an0_s <= "01101001"; |
an1_s <= "10010110"; |
|
t8022_b : t8022 |
port map ( |
xtal_i => xtal_s, |
reset_i => res_s, |
ale_o => ale_s, |
t0_i => p1_b(0), |
t1_i => p1_b(1), |
p2_b => p2_b, |
p1_b => p1_b, |
p0_b => p0_b, |
prog_n_o => prog_n_s, |
an0_i => an0_s, |
an1_i => an1_s |
); |
|
|
----------------------------------------------------------------------------- |
-- The clock generator |
-- |
clk_gen: process |
begin |
xtal_s <= '0'; |
wait for period_c/2; |
xtal_s <= '1'; |
wait for period_c/2; |
end process clk_gen; |
-- |
----------------------------------------------------------------------------- |
|
|
----------------------------------------------------------------------------- |
-- The reset generator |
-- |
res_gen: process |
begin |
res_s <= '1'; |
wait for 5 * period_c; |
res_s <= '0'; |
wait; |
end process res_gen; |
-- |
----------------------------------------------------------------------------- |
|
|
----------------------------------------------------------------------------- |
-- End of simulation detection |
-- |
eos: process |
begin |
|
outer: loop |
wait on tb_accu_s; |
if tb_accu_s = "10101010" then |
wait on tb_accu_s; |
if tb_accu_s = "01010101" then |
wait on tb_accu_s; |
if tb_accu_s = "00000001" then |
-- wait for instruction strobe of this move |
wait until tb_istrobe_s'event and tb_istrobe_s = '1'; |
-- wait for next strobe |
wait until tb_istrobe_s'event and tb_istrobe_s = '1'; |
assert false |
report "Simulation Result: PASS." |
severity note; |
else |
assert false |
report "Simulation Result: FAIL." |
severity note; |
end if; |
|
assert false |
report "End of simulation reached." |
severity failure; |
|
end if; |
end if; |
end loop; |
|
end process eos; |
-- |
----------------------------------------------------------------------------- |
|
end behav; |
/wip_t2x/rtl/vhdl/adc-c.vhd
0,0 → 1,16
------------------------------------------------------------------------------- |
-- |
-- The T48 SAR ADC. |
-- |
-- Copyright (c) 2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration t48_adc_rtl_c0 of t48_adc is |
|
for rtl |
end for; |
|
end t48_adc_rtl_c0; |
/wip_t2x/rtl/vhdl/adc.vhd
0,0 → 1,199
------------------------------------------------------------------------------- |
-- |
-- The T48 SAR ADC. |
-- |
-- Copyright (c) 2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.t48_pack.word_t; |
use work.t48_pack.mstate_t; |
|
entity t48_adc is |
|
port ( |
clk_i : in std_logic; |
res_i : in std_logic; |
en_clk_i : in boolean; |
ale_i : in boolean; |
mstate_i : in mstate_t; |
sel_an0_i : in boolean; |
sel_an1_i : in boolean; |
read_adc_i : in boolean; |
data_o : out word_t; |
sel_an_o : out std_logic; |
sh_o : out std_logic; |
sar_o : out std_logic_vector(7 downto 0); |
comp_i : in std_logic |
); |
|
end t48_adc; |
|
|
use work.t48_pack.all; |
|
architecture rtl of t48_adc is |
|
type adc_state_t is (ADC_SH, |
ADC_B7, ADC_B6, ADC_B5, ADC_B4, |
ADC_B3, ADC_B2, ADC_B1, ADC_B0); |
signal adc_state_q : adc_state_t; |
|
signal ale_q : boolean; |
|
signal sar_q, crr_q : word_t; |
|
signal start_conv_s : boolean; |
|
begin |
|
start_conv_s <= sel_an0_i or sel_an1_i; |
|
process (res_i, clk_i) |
begin |
if res_i = res_active_c then |
ale_q <= false; |
sar_q <= (others => '0'); |
crr_q <= (others => '0'); |
sel_an_o <= '0'; |
adc_state_q <= ADC_SH; |
|
elsif clk_i'event and clk_i = clk_active_c then |
if ale_i then |
ale_q <= true; |
elsif en_clk_i then |
ale_q <= ale_i; |
end if; |
|
if en_clk_i then |
if sel_an0_i then |
sel_an_o <= '0'; |
elsif sel_an1_i then |
sel_an_o <= '1'; |
end if; |
|
case adc_state_q is |
when ADC_SH => |
if ale_q then |
adc_state_q <= ADC_B7; |
sar_q <= "10000000"; |
end if; |
|
when ADC_B7 => |
if mstate_i = MSTATE1 then |
sar_q(7) <= comp_i; |
sar_q(6) <= '1'; |
adc_state_q <= ADC_B6; |
end if; |
|
when ADC_B6 => |
if mstate_i = MSTATE3 then |
sar_q(6) <= comp_i; |
sar_q(5) <= '1'; |
adc_state_q <= ADC_B5; |
end if; |
|
when ADC_B5 => |
if mstate_i = MSTATE1 then |
sar_q(5) <= comp_i; |
sar_q(4) <= '1'; |
adc_state_q <= ADC_B4; |
end if; |
|
when ADC_B4 => |
if mstate_i = MSTATE3 then |
sar_q(4) <= comp_i; |
sar_q(3) <= '1'; |
adc_state_q <= ADC_B3; |
end if; |
|
when ADC_B3 => |
if mstate_i = MSTATE1 then |
sar_q(3) <= comp_i; |
sar_q(2) <= '1'; |
adc_state_q <= ADC_B2; |
end if; |
|
when ADC_B2 => |
if mstate_i = MSTATE3 then |
sar_q(2) <= comp_i; |
sar_q(1) <= '1'; |
adc_state_q <= ADC_B1; |
end if; |
|
when ADC_B1 => |
if mstate_i = MSTATE1 then |
sar_q(1) <= comp_i; |
sar_q(0) <= '1'; |
adc_state_q <= ADC_B0; |
end if; |
|
when ADC_B0 => |
if mstate_i = MSTATE3 then |
sar_q(0) <= comp_i; |
crr_q <= sar_q(7 downto 1) & comp_i; |
adc_state_q <= ADC_SH; |
end if; |
|
when others => |
adc_state_q <= ADC_SH; |
|
end case; |
-- |
if start_conv_s then |
adc_state_q <= ADC_SH; |
end if; |
|
end if; |
end if; |
end process; |
|
|
----------------------------------------------------------------------------- |
-- Outpu mapping |
----------------------------------------------------------------------------- |
sh_o <= '1' when adc_state_q = ADC_SH and ale_q and en_clk_i else '0'; |
sar_o <= sar_q; |
data_o <= crr_q |
when read_adc_i else |
(others => bus_idle_level_c); |
|
end rtl; |
/wip_t2x/rtl/vhdl/decoder.vhd
1936,7 → 1936,7
-- Mnemonic SEL_AN - MCS22 ---------------------------------------------- |
when MN_SEL_AN => |
if clk_mstate_i = MSTATE3 then |
if opc_opcode_q(4) = '0' then |
if opc_opcode_q(4) = '1' then |
adc_sel_an0_o <= true; |
else |
adc_sel_an1_o <= true; |
/wip_t2x/rtl/vhdl/decoder_pack-p.vhd
702,8 → 702,8
multi_cycle_v := true; |
|
-- Mnemonic SEL_AN ------------------------------------------------------ |
when "10000101" | -- SEL AN0 |
"10010101" => -- SEL AN1 |
when "10010101" | -- SEL AN0 |
"10000101" => -- SEL AN1 |
mnemonic_v := MN_SEL_AN; |
multi_cycle_v := true; |
|
/wip_t2x/rtl/vhdl/system/t48_system_comp_pack-p.vhd
352,4 → 352,44
); |
end component; |
|
component t8022_notri |
generic ( |
gate_port_input_g : integer := 1 |
); |
|
port ( |
xtal_i : in std_logic; |
xtal_en_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p0_i : in std_logic_vector( 7 downto 0); |
p0_o : out std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
an0_i : in std_logic_vector( 7 downto 0); |
an1_i : in std_logic_vector( 7 downto 0) |
); |
end component; |
|
component t8022 |
port ( |
xtal_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_b : inout std_logic_vector( 7 downto 0); |
p1_b : inout std_logic_vector( 7 downto 0); |
p0_b : inout std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
an0_i : in std_logic_vector( 7 downto 0); |
an1_i : in std_logic_vector( 7 downto 0) |
); |
end component; |
|
end t48_system_comp_pack; |
/wip_t2x/rtl/vhdl/system/t8022-c.vhd
0,0 → 1,21
------------------------------------------------------------------------------- |
-- |
-- T8022 Microcontroller System |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration t8022_struct_c0 of t8022 is |
|
for struct |
|
for t8022_notri_b : t8022_notri |
use configuration work.t8022_notri_struct_c0; |
end for; |
|
end for; |
|
end t8022_struct_c0; |
/wip_t2x/rtl/vhdl/system/t8022.vhd
0,0 → 1,153
------------------------------------------------------------------------------- |
-- |
-- T8022 Microcontroller System |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity t8022 is |
|
port ( |
xtal_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_b : inout std_logic_vector( 7 downto 0); |
p1_b : inout std_logic_vector( 7 downto 0); |
p0_b : inout std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
an0_i : in std_logic_vector( 7 downto 0); |
an1_i : in std_logic_vector( 7 downto 0) |
); |
|
end t8022; |
|
|
library ieee; |
use ieee.numeric_std.all; |
|
use work.t48_system_comp_pack.t8022_notri; |
|
architecture struct of t8022 is |
|
signal p2_s : std_logic_vector( 7 downto 0); |
signal p1_s : std_logic_vector( 7 downto 0); |
signal p0_s : std_logic_vector( 7 downto 0); |
|
signal vdd_s : std_logic; |
|
begin |
|
vdd_s <= '1'; |
|
t8022_notri_b : t8022_notri |
generic map ( |
-- we don't need explicit gating of input ports |
-- this is done implicitely by the bidirectional pads |
gate_port_input_g => 0 |
) |
|
port map ( |
xtal_i => xtal_i, |
xtal_en_i => vdd_s, |
reset_i => reset_i, |
ale_o => ale_o, |
t0_i => t0_i, |
t1_i => t1_i, |
p2_i => p2_b, |
p2_o => p2_s, |
p1_i => p1_b, |
p1_o => p1_s, |
p0_i => p0_b, |
p0_o => p0_s, |
prog_n_o => prog_n_o, |
an0_i => an0_i, |
an1_i => an1_i |
); |
|
----------------------------------------------------------------------------- |
-- Process bidirs |
-- |
-- Purpose: |
-- Assign bidirectional signals. |
-- |
bidirs: process (p0_b, p0_s, |
p1_b, p1_s, |
p2_b, p2_s) |
|
function port_bidir_f(port_value : in std_logic_vector; |
low_imp : in std_logic) return std_logic_vector is |
variable result_v : std_logic_vector(port_value'range); |
begin |
for idx in port_value'high downto port_value'low loop |
if low_imp = '1' then |
result_v(idx) := port_value(idx); |
elsif port_value(idx) = '0' then |
result_v(idx) := '0'; |
else |
result_v(idx) := 'Z'; |
end if; |
end loop; |
|
return result_v; |
end; |
|
begin |
-- Port 0 ----------------------------------------------------------------- |
p0_b <= port_bidir_f(port_value => p0_s, |
low_imp => '0'); |
|
-- Port 1 ----------------------------------------------------------------- |
p1_b <= port_bidir_f(port_value => p1_s, |
low_imp => '0'); |
|
-- Port 2 ----------------------------------------------------------------- |
p2_b <= port_bidir_f(port_value => p2_s, |
low_imp => '0'); |
|
end process bidirs; |
-- |
----------------------------------------------------------------------------- |
|
|
end struct; |
/wip_t2x/rtl/vhdl/system/t8022_notri-c.vhd
0,0 → 1,29
------------------------------------------------------------------------------- |
-- |
-- T8022 Microcontroller System |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
------------------------------------------------------------------------------- |
|
configuration t8022_notri_struct_c0 of t8022_notri is |
|
for struct |
|
for rom_2k_b : t49_rom |
use configuration work.t49_rom_lpm_c0; |
end for; |
|
for ram_64_b : generic_ram_ena |
use configuration work.generic_ram_ena_rtl_c0; |
end for; |
|
for t22_core_b : t22_core |
use configuration work.t22_core_struct_c0; |
end for; |
|
end for; |
|
end t8022_notri_struct_c0; |
/wip_t2x/rtl/vhdl/system/t8022_notri.vhd
0,0 → 1,228
------------------------------------------------------------------------------- |
-- |
-- T8022 Microcontroller System |
-- 8022 toplevel without tri-states |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity t8022_notri is |
|
generic ( |
gate_port_input_g : integer := 1 |
); |
|
port ( |
xtal_i : in std_logic; |
xtal_en_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p0_i : in std_logic_vector( 7 downto 0); |
p0_o : out std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
an0_i : in std_logic_vector( 7 downto 0); |
an1_i : in std_logic_vector( 7 downto 0) |
); |
|
end t8022_notri; |
|
|
library ieee; |
use ieee.numeric_std.all; |
|
use work.t48_core_comp_pack.t22_core; |
use work.t48_core_comp_pack.t49_rom; |
use work.t48_core_comp_pack.generic_ram_ena; |
|
architecture struct of t8022_notri is |
|
-- Address width of internal ROM |
constant rom_addr_width_c : natural := 11; |
|
signal reset_s : std_logic; |
|
signal xtal3_s : std_logic; |
signal dmem_addr_s : std_logic_vector( 7 downto 0); |
signal dmem_we_s : std_logic; |
signal dmem_data_from_s : std_logic_vector( 7 downto 0); |
signal dmem_data_to_s : std_logic_vector( 7 downto 0); |
signal pmem_addr_s : std_logic_vector(11 downto 0); |
signal pmem_data_s : std_logic_vector( 7 downto 0); |
|
signal p0_in_s, |
p0_out_s : std_logic_vector( 7 downto 0); |
signal p1_in_s, |
p1_out_s : std_logic_vector( 7 downto 0); |
signal p2_in_s, |
p2_out_s : std_logic_vector( 7 downto 0); |
|
signal adc_sel_an_s : std_logic; |
signal adc_sh_s : std_logic; |
signal adc_sar_s : std_logic_vector( 7 downto 0); |
signal adc_comp_s : std_logic; |
|
signal vdd_s : std_logic; |
|
begin |
|
vdd_s <= '1'; |
|
reset_s <= not reset_i; |
|
----------------------------------------------------------------------------- |
-- Check generics for valid values. |
----------------------------------------------------------------------------- |
-- pragma translate_off |
assert gate_port_input_g = 0 or gate_port_input_g = 1 |
report "gate_port_input_g must be either 1 or 0!" |
severity failure; |
-- pragma translate_on |
|
|
t22_core_b : t22_core |
generic map ( |
xtal_div_3_g => 1, |
register_mnemonic_g => 1, |
sample_t1_state_g => 4 |
) |
port map ( |
xtal_i => xtal_i, |
xtal_en_i => xtal_en_i, |
reset_i => reset_s, |
ale_o => ale_o, |
t0_i => t0_i, |
t1_i => t1_i, |
p2_i => p2_in_s, |
p2_o => p2_out_s, |
p1_i => p1_in_s, |
p1_o => p1_out_s, |
p0_i => p0_in_s, |
p0_o => p0_out_s, |
prog_n_o => prog_n_o, |
adc_sel_an_o => adc_sel_an_s, |
adc_sh_o => adc_sh_s, |
adc_sar_o => adc_sar_s, |
adc_comp_i => adc_comp_s, |
clk_i => xtal_i, |
en_clk_i => xtal3_s, |
xtal3_o => xtal3_s, |
dmem_addr_o => dmem_addr_s, |
dmem_we_o => dmem_we_s, |
dmem_data_i => dmem_data_from_s, |
dmem_data_o => dmem_data_to_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_s |
); |
|
|
----------------------------------------------------------------------------- |
-- Simple ADC model, takes unsigned 8 bit vectors as input. |
----------------------------------------------------------------------------- |
adc_block: block |
signal an_q : std_logic_vector(an0_i'range); |
begin |
|
sample_hold_p: process (xtal_i) |
begin |
if rising_edge(xtal_i) then |
if adc_sh_s = '1' then |
if adc_sel_an_s = '0' then |
an_q <= an0_i; |
else |
an_q <= an1_i; |
end if; |
end if; |
end if; |
end process sample_hold_p; |
|
adc_comp_s <= '1' when unsigned(an_q) >= unsigned(adc_sar_s) else '0'; |
|
end block; |
|
----------------------------------------------------------------------------- |
-- Gate port 0, 1 and 2 input bus with respetive output value |
----------------------------------------------------------------------------- |
gate_ports: if gate_port_input_g = 1 generate |
p0_in_s <= p0_i and p0_out_s; |
p1_in_s <= p1_i and p1_out_s; |
p2_in_s <= p2_i and p2_out_s; |
end generate; |
|
pass_ports: if gate_port_input_g = 0 generate |
p0_in_s <= p0_i; |
p1_in_s <= p1_i; |
p2_in_s <= p2_i; |
end generate; |
|
p0_o <= p0_out_s; |
p1_o <= p1_out_s; |
p2_o <= p2_out_s; |
|
|
rom_2k_b : t49_rom |
port map ( |
clk_i => xtal_i, |
rom_addr_i => pmem_addr_s(rom_addr_width_c-1 downto 0), |
rom_data_o => pmem_data_s |
); |
|
ram_64_b : generic_ram_ena |
generic map ( |
addr_width_g => 6, |
data_width_g => 8 |
) |
port map ( |
clk_i => xtal_i, |
a_i => dmem_addr_s(5 downto 0), |
we_i => dmem_we_s, |
ena_i => vdd_s, |
d_i => dmem_data_to_s, |
d_o => dmem_data_from_s |
); |
|
end struct; |
/wip_t2x/rtl/vhdl/t22_core-c.vhd
0,0 → 1,65
------------------------------------------------------------------------------- |
-- |
-- T22 Microcontroller Core |
-- |
------------------------------------------------------------------------------- |
|
configuration t22_core_struct_c0 of t22_core is |
|
for struct |
|
for adc_b : t48_adc |
use configuration work.t48_adc_rtl_c0; |
end for; |
|
for alu_b : t48_alu |
use configuration work.t48_alu_rtl_c0; |
end for; |
|
for bus_mux_b : t48_bus_mux |
use configuration work.t48_bus_mux_rtl_c0; |
end for; |
|
for clock_ctrl_b : t48_clock_ctrl |
use configuration work.t48_clock_ctrl_rtl_c0; |
end for; |
|
for cond_branch_b : t48_cond_branch |
use configuration work.t48_cond_branch_rtl_c0; |
end for; |
|
for decoder_b : t48_decoder |
use configuration work.t48_decoder_rtl_c0; |
end for; |
|
for dmem_ctrl_b : t48_dmem_ctrl |
use configuration work.t48_dmem_ctrl_rtl_c0; |
end for; |
|
for timer_b : t48_timer |
use configuration work.t48_timer_rtl_c0; |
end for; |
|
for p0_b : t48_p1 |
use configuration work.t48_p1_rtl_c0; |
end for; |
|
for p1_b : t48_p1 |
use configuration work.t48_p1_rtl_c0; |
end for; |
|
for p2_b : t48_p2 |
use configuration work.t48_p2_rtl_c0; |
end for; |
|
for pmem_ctrl_b : t48_pmem_ctrl |
use configuration work.t48_pmem_ctrl_rtl_c0; |
end for; |
|
for psw_b : t48_psw |
use configuration work.t48_psw_rtl_c0; |
end for; |
|
end for; |
|
end t22_core_struct_c0; |
/wip_t2x/rtl/vhdl/t22_core.vhd
0,0 → 1,613
------------------------------------------------------------------------------- |
-- |
-- T22 Microcontroller Core |
-- |
-- Copyright (c) 2004-2023, Arnim Laeuger (arniml@opencores.org) |
-- |
-- All rights reserved |
-- |
-- Redistribution and use in source and synthezised forms, with or without |
-- modification, are permitted provided that the following conditions are met: |
-- |
-- Redistributions of source code must retain the above copyright notice, |
-- this list of conditions and the following disclaimer. |
-- |
-- Redistributions in synthesized form must reproduce the above copyright |
-- notice, this list of conditions and the following disclaimer in the |
-- documentation and/or other materials provided with the distribution. |
-- |
-- Neither the name of the author nor the names of other contributors may |
-- be used to endorse or promote products derived from this software without |
-- specific prior written permission. |
-- |
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
-- POSSIBILITY OF SUCH DAMAGE. |
-- |
-- Please report bugs to the author, but before you do so, please |
-- make sure that this is not a derivative work and that |
-- you have the latest version of this file. |
-- |
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
-- Limitations : |
-- ============= |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity t22_core is |
|
generic ( |
-- divide XTAL1 by 3 to derive Clock States |
xtal_div_3_g : integer := 1; |
-- store mnemonic in flip-flops (registered-out) |
register_mnemonic_g : integer := 1; |
-- state in which T1 is sampled (3 or 4) |
sample_t1_state_g : integer := 4 |
); |
|
port ( |
-- T22 Interface ---------------------------------------------------------- |
xtal_i : in std_logic; |
xtal_en_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p0_i : in std_logic_vector( 7 downto 0); |
p0_o : out std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
-- ADC Interface ---------------------------------------------------------- |
adc_sel_an_o : out std_logic; |
adc_sh_o : out std_logic; |
adc_sar_o : out std_logic_vector( 7 downto 0); |
adc_comp_i : in std_logic; |
-- Core Interface --------------------------------------------------------- |
clk_i : in std_logic; |
en_clk_i : in std_logic; |
xtal3_o : out std_logic; |
dmem_addr_o : out std_logic_vector( 7 downto 0); |
dmem_we_o : out std_logic; |
dmem_data_i : in std_logic_vector( 7 downto 0); |
dmem_data_o : out std_logic_vector( 7 downto 0); |
pmem_addr_o : out std_logic_vector(11 downto 0); |
pmem_data_i : in std_logic_vector( 7 downto 0) |
); |
|
end t22_core; |
|
|
use work.t48_alu_pack.alu_op_t; |
use work.t48_cond_branch_pack.branch_conditions_t; |
use work.t48_cond_branch_pack.comp_value_t; |
use work.t48_dmem_ctrl_pack.dmem_addr_ident_t; |
use work.t48_pmem_ctrl_pack.pmem_addr_ident_t; |
use work.t48_comp_pack.all; |
use work.t48_pack.res_active_c; |
use work.t48_pack.clk_active_c; |
use work.t48_pack.bus_idle_level_c; |
use work.t48_pack.word_t; |
use work.t48_pack.pmem_addr_t; |
use work.t48_pack.mstate_t; |
use work.t48_pack.to_stdLogic; |
use work.t48_pack.to_boolean; |
|
architecture struct of t22_core is |
|
signal t48_data_s : word_t; |
|
signal xtal_en_s : boolean; |
signal en_clk_s : boolean; |
|
signal t0_s, t1_s : std_logic; |
|
-- ALU signals |
signal alu_data_s : word_t; |
signal alu_write_accu_s : boolean; |
signal alu_write_shadow_s : boolean; |
signal alu_write_temp_reg_s : boolean; |
signal alu_read_alu_s : boolean; |
signal alu_carry_s : std_logic; |
signal alu_aux_carry_s : std_logic; |
signal alu_op_s : alu_op_t; |
signal alu_use_carry_s : boolean; |
signal alu_da_high_s : boolean; |
signal alu_da_overflow_s : boolean; |
signal alu_accu_low_s : boolean; |
signal alu_p06_temp_reg_s : boolean; |
signal alu_p60_temp_reg_s : boolean; |
|
-- Clock Controller signals |
signal clk_multi_cycle_s : boolean; |
signal clk_assert_psen_s : boolean; |
signal clk_assert_prog_s : boolean; |
signal clk_assert_rd_s : boolean; |
signal clk_assert_wr_s : boolean; |
signal clk_mstate_s : mstate_t; |
signal clk_second_cycle_s : boolean; |
signal prog_s : boolean; |
signal ale_s : boolean; |
signal xtal3_s : boolean; |
|
-- Conditional Branch Logic signals |
signal cnd_compute_take_s : boolean; |
signal cnd_branch_cond_s : branch_conditions_t; |
signal cnd_take_branch_s : boolean; |
signal cnd_comp_value_s : comp_value_t; |
signal cnd_f1_s : std_logic; |
signal cnd_tf_s : std_logic; |
|
-- Data Memory Controller signals |
signal dm_write_dmem_addr_s : boolean; |
signal dm_write_dmem_s : boolean; |
signal dm_read_dmem_s : boolean; |
signal dm_addr_type_s : dmem_addr_ident_t; |
signal dm_data_s : word_t; |
|
-- Decoder signals |
signal dec_data_s : word_t; |
|
-- Port 0 signals |
signal p0_write_p0_s : boolean; |
signal p0_read_p0_s : boolean; |
signal p0_data_s : word_t; |
|
-- Port 1 signals |
signal p1_write_p1_s : boolean; |
signal p1_read_p1_s : boolean; |
signal p1_data_s : word_t; |
|
-- Port 2 signals |
signal p2_write_p2_s : boolean; |
signal p2_write_exp_s : boolean; |
signal p2_read_p2_s : boolean; |
signal p2_read_exp_s : boolean; |
signal p2_output_pch_s : boolean; |
signal p2_data_s : word_t; |
|
-- Program Memory Controller signals |
signal pm_write_pcl_s : boolean; |
signal pm_read_pcl_s : boolean; |
signal pm_write_pch_s : boolean; |
signal pm_read_pch_s : boolean; |
signal pm_read_pmem_s : boolean; |
signal pm_inc_pc_s : boolean; |
signal pm_write_pmem_addr_s : boolean; |
signal pm_data_s : word_t; |
signal pm_addr_type_s : pmem_addr_ident_t; |
signal pmem_addr_s : pmem_addr_t; |
|
-- PSW signals |
signal psw_read_psw_s : boolean; |
signal psw_read_sp_s : boolean; |
signal psw_write_psw_s : boolean; |
signal psw_write_sp_s : boolean; |
signal psw_carry_s : std_logic; |
signal psw_aux_carry_s : std_logic; |
signal psw_f0_s : std_logic; |
signal psw_bs_s : std_logic; |
signal psw_special_data_s : std_logic; |
signal psw_inc_stackp_s : boolean; |
signal psw_dec_stackp_s : boolean; |
signal psw_write_carry_s : boolean; |
signal psw_write_aux_carry_s : boolean; |
signal psw_write_f0_s : boolean; |
signal psw_write_bs_s : boolean; |
signal psw_data_s : word_t; |
|
-- Timer signals |
signal tim_overflow_s : boolean; |
signal tim_of_s : std_logic; |
signal tim_read_timer_s : boolean; |
signal tim_write_timer_s : boolean; |
signal tim_start_t_s : boolean; |
signal tim_start_cnt_s : boolean; |
signal tim_stop_tcnt_s : boolean; |
signal tim_data_s : word_t; |
|
-- ADC signals |
signal adc_sel_an0_s : boolean; |
signal adc_sel_an1_s : boolean; |
signal adc_read_adc_s : boolean; |
signal adc_data_s : word_t; |
|
signal xtal_mcs2x_q : boolean; |
|
signal false_s : boolean; |
signal vdd_s : std_logic; |
signal gnd_s : std_logic; |
|
begin |
|
false_s <= false; |
vdd_s <= '1'; |
gnd_s <= '0'; |
|
en_clk_s <= to_boolean(en_clk_i); |
|
t0_s <= |
-- pragma translate_off |
To_X01Z |
-- pragma translate_on |
(t0_i); |
t1_s <= |
-- pragma translate_off |
To_X01Z |
-- pragma translate_on |
(t1_i); |
|
----------------------------------------------------------------------------- |
-- MCS-2x clocking |
-- The documents say the MCS-2x has 10 machine cycles instead of 5 in MCS-48. |
-- Divide incoming xtal_en_i by 2 for compatibility. |
----------------------------------------------------------------------------- |
process (reset_i, xtal_i) |
begin |
if reset_i = res_active_c then |
xtal_mcs2x_q <= false; |
elsif xtal_i'event and xtal_i = clk_active_c then |
if xtal_en_i = '1' then |
xtal_mcs2x_q <= not xtal_mcs2x_q; |
end if; |
end if; |
end process; |
-- |
xtal_en_s <= to_boolean(xtal_en_i) and xtal_mcs2x_q; |
|
adc_b : t48_adc |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
ale_i => ale_s, |
mstate_i => clk_mstate_s, |
sel_an0_i => adc_sel_an0_s, |
sel_an1_i => adc_sel_an1_s, |
read_adc_i => adc_read_adc_s, |
data_o => adc_data_s, |
sel_an_o => adc_sel_an_o, |
sh_o => adc_sh_o, |
sar_o => adc_sar_o, |
comp_i => adc_comp_i |
); |
|
alu_b : t48_alu |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
data_o => alu_data_s, |
write_accu_i => alu_write_accu_s, |
write_shadow_i => alu_write_shadow_s, |
write_temp_reg_i => alu_write_temp_reg_s, |
read_alu_i => alu_read_alu_s, |
carry_i => psw_carry_s, |
carry_o => alu_carry_s, |
aux_carry_o => alu_aux_carry_s, |
alu_op_i => alu_op_s, |
use_carry_i => alu_use_carry_s, |
da_high_i => alu_da_high_s, |
da_overflow_o => alu_da_overflow_s, |
accu_low_i => alu_accu_low_s, |
p06_temp_reg_i => alu_p06_temp_reg_s, |
p60_temp_reg_i => alu_p60_temp_reg_s |
); |
|
bus_mux_b : t48_bus_mux |
port map ( |
adc_data_i => adc_data_s, |
alu_data_i => alu_data_s, |
dec_data_i => dec_data_s, |
dm_data_i => dm_data_s, |
pm_data_i => pm_data_s, |
p0_data_i => p0_data_s, |
p1_data_i => p1_data_s, |
p2_data_i => p2_data_s, |
psw_data_i => psw_data_s, |
tim_data_i => tim_data_s, |
data_o => t48_data_s |
); |
|
clock_ctrl_b : t48_clock_ctrl |
generic map ( |
xtal_div_3_g => xtal_div_3_g |
) |
port map ( |
clk_i => clk_i, |
xtal_i => xtal_i, |
xtal_en_i => xtal_en_s, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
xtal3_o => xtal3_s, |
t0_o => open, |
multi_cycle_i => clk_multi_cycle_s, |
assert_psen_i => clk_assert_psen_s, |
assert_prog_i => clk_assert_prog_s, |
assert_rd_i => clk_assert_rd_s, |
assert_wr_i => clk_assert_wr_s, |
mstate_o => clk_mstate_s, |
second_cycle_o => clk_second_cycle_s, |
ale_o => ale_s, |
psen_o => open, |
prog_o => prog_s, |
rd_o => open, |
wr_o => open |
); |
|
cond_branch_b : t48_cond_branch |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
compute_take_i => cnd_compute_take_s, |
branch_cond_i => cnd_branch_cond_s, |
take_branch_o => cnd_take_branch_s, |
accu_i => alu_data_s, |
t0_i => t0_s, |
t1_i => t1_s, |
int_n_i => vdd_s, |
f0_i => psw_f0_s, |
f1_i => cnd_f1_s, |
tf_i => cnd_tf_s, |
carry_i => psw_carry_s, |
comp_value_i => cnd_comp_value_s |
); |
|
decoder_b : t48_decoder |
generic map ( |
register_mnemonic_g => register_mnemonic_g, |
is_mcs2x_g => 1, |
is_mcs2x_type_2_g => 1 |
) |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
xtal_i => xtal_i, |
xtal_en_i => xtal_en_s, |
ea_i => gnd_s, |
ale_i => ale_s, |
int_n_i => t0_s, |
t0_dir_o => open, |
data_i => t48_data_s, |
data_o => dec_data_s, |
alu_write_accu_o => alu_write_accu_s, |
alu_write_shadow_o => alu_write_shadow_s, |
alu_write_temp_reg_o => alu_write_temp_reg_s, |
alu_read_alu_o => alu_read_alu_s, |
bus_write_bus_o => open, |
bus_read_bus_o => open, |
dm_write_dmem_addr_o => dm_write_dmem_addr_s, |
dm_write_dmem_o => dm_write_dmem_s, |
dm_read_dmem_o => dm_read_dmem_s, |
p0_write_p0_o => p0_write_p0_s, |
p0_read_p0_o => p0_read_p0_s, |
p1_write_p1_o => p1_write_p1_s, |
p1_read_p1_o => p1_read_p1_s, |
pm_write_pcl_o => pm_write_pcl_s, |
p2_write_p2_o => p2_write_p2_s, |
p2_write_exp_o => p2_write_exp_s, |
p2_read_p2_o => p2_read_p2_s, |
pm_read_pcl_o => pm_read_pcl_s, |
pm_write_pch_o => pm_write_pch_s, |
pm_read_pch_o => pm_read_pch_s, |
pm_read_pmem_o => pm_read_pmem_s, |
psw_read_psw_o => psw_read_psw_s, |
psw_read_sp_o => psw_read_sp_s, |
psw_write_psw_o => psw_write_psw_s, |
psw_write_sp_o => psw_write_sp_s, |
alu_carry_i => alu_carry_s, |
alu_op_o => alu_op_s, |
alu_use_carry_o => alu_use_carry_s, |
alu_da_high_o => alu_da_high_s, |
alu_da_overflow_i => alu_da_overflow_s, |
alu_accu_low_o => alu_accu_low_s, |
alu_p06_temp_reg_o => alu_p06_temp_reg_s, |
alu_p60_temp_reg_o => alu_p60_temp_reg_s, |
bus_output_pcl_o => open, |
bus_bidir_bus_o => open, |
clk_multi_cycle_o => clk_multi_cycle_s, |
clk_assert_psen_o => clk_assert_psen_s, |
clk_assert_prog_o => clk_assert_prog_s, |
clk_assert_rd_o => clk_assert_rd_s, |
clk_assert_wr_o => clk_assert_wr_s, |
clk_mstate_i => clk_mstate_s, |
clk_second_cycle_i => clk_second_cycle_s, |
cnd_compute_take_o => cnd_compute_take_s, |
cnd_branch_cond_o => cnd_branch_cond_s, |
cnd_take_branch_i => cnd_take_branch_s, |
cnd_comp_value_o => cnd_comp_value_s, |
cnd_f1_o => cnd_f1_s, |
cnd_tf_o => cnd_tf_s, |
dm_addr_type_o => dm_addr_type_s, |
tim_read_timer_o => tim_read_timer_s, |
tim_write_timer_o => tim_write_timer_s, |
tim_start_t_o => tim_start_t_s, |
tim_start_cnt_o => tim_start_cnt_s, |
tim_stop_tcnt_o => tim_stop_tcnt_s, |
p1_read_reg_o => open, |
p2_read_reg_o => open, |
p2_read_exp_o => p2_read_exp_s, |
p2_output_pch_o => p2_output_pch_s, |
pm_inc_pc_o => pm_inc_pc_s, |
pm_write_pmem_addr_o => pm_write_pmem_addr_s, |
pm_addr_type_o => pm_addr_type_s, |
psw_special_data_o => psw_special_data_s, |
psw_carry_i => psw_carry_s, |
psw_aux_carry_i => psw_aux_carry_s, |
psw_f0_i => psw_f0_s, |
psw_inc_stackp_o => psw_inc_stackp_s, |
psw_dec_stackp_o => psw_dec_stackp_s, |
psw_write_carry_o => psw_write_carry_s, |
psw_write_aux_carry_o => psw_write_aux_carry_s, |
psw_write_f0_o => psw_write_f0_s, |
psw_write_bs_o => psw_write_bs_s, |
tim_overflow_i => tim_overflow_s, |
adc_sel_an0_o => adc_sel_an0_s, |
adc_sel_an1_o => adc_sel_an1_s, |
adc_read_adc_o => adc_read_adc_s |
); |
|
dmem_ctrl_b : t48_dmem_ctrl |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
write_dmem_addr_i => dm_write_dmem_addr_s, |
write_dmem_i => dm_write_dmem_s, |
read_dmem_i => dm_read_dmem_s, |
addr_type_i => dm_addr_type_s, |
bank_select_i => psw_bs_s, |
data_o => dm_data_s, |
dmem_data_i => dmem_data_i, |
dmem_addr_o => dmem_addr_o, |
dmem_we_o => dmem_we_o, |
dmem_data_o => dmem_data_o |
); |
|
timer_b : t48_timer |
generic map ( |
sample_t1_state_g => sample_t1_state_g |
) |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
t1_i => t1_s, |
clk_mstate_i => clk_mstate_s, |
data_i => t48_data_s, |
data_o => tim_data_s, |
read_timer_i => tim_read_timer_s, |
write_timer_i => tim_write_timer_s, |
start_t_i => tim_start_t_s, |
start_cnt_i => tim_start_cnt_s, |
stop_tcnt_i => tim_stop_tcnt_s, |
overflow_o => tim_of_s |
); |
|
tim_overflow_s <= to_boolean(tim_of_s); |
|
p0_b : t48_p1 |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
data_o => p0_data_s, |
write_p1_i => p0_write_p0_s, |
read_p1_i => p0_read_p0_s, |
read_reg_i => false_s, -- MCS21x always reads pins |
p1_i => p0_i, |
p1_o => p0_o, |
p1_low_imp_o => open |
); |
|
p1_b : t48_p1 |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
data_o => p1_data_s, |
write_p1_i => p1_write_p1_s, |
read_p1_i => p1_read_p1_s, |
read_reg_i => false_s, -- MCS21x always reads pins |
p1_i => p1_i, |
p1_o => p1_o, |
p1_low_imp_o => open |
); |
|
p2_b : t48_p2 |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
xtal_i => xtal_i, |
xtal_en_i => xtal_en_s, |
data_i => t48_data_s, |
data_o => p2_data_s, |
write_p2_i => p2_write_p2_s, |
write_exp_i => p2_write_exp_s, |
read_p2_i => p2_read_p2_s, |
read_reg_i => false_s, -- MCS21x always reads pins |
read_exp_i => p2_read_exp_s, |
output_pch_i => p2_output_pch_s, |
pch_i => pmem_addr_s(11 downto 8), |
p2_i => p2_i, |
p2_o => p2_o, |
p2l_low_imp_o => open, |
p2h_low_imp_o => open |
); |
|
pmem_ctrl_b : t48_pmem_ctrl |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
data_o => pm_data_s, |
write_pcl_i => pm_write_pcl_s, |
read_pcl_i => pm_read_pcl_s, |
write_pch_i => pm_write_pch_s, |
read_pch_i => pm_read_pch_s, |
inc_pc_i => pm_inc_pc_s, |
write_pmem_addr_i => pm_write_pmem_addr_s, |
addr_type_i => pm_addr_type_s, |
read_pmem_i => pm_read_pmem_s, |
pmem_addr_o => pmem_addr_s, |
pmem_data_i => pmem_data_i |
); |
|
psw_b : t48_psw |
port map ( |
clk_i => clk_i, |
res_i => reset_i, |
en_clk_i => en_clk_s, |
data_i => t48_data_s, |
data_o => psw_data_s, |
read_psw_i => psw_read_psw_s, |
read_sp_i => psw_read_sp_s, |
write_psw_i => psw_write_psw_s, |
write_sp_i => psw_write_sp_s, |
special_data_i => psw_special_data_s, |
inc_stackp_i => psw_inc_stackp_s, |
dec_stackp_i => psw_dec_stackp_s, |
write_carry_i => psw_write_carry_s, |
write_aux_carry_i => psw_write_aux_carry_s, |
write_f0_i => psw_write_f0_s, |
write_bs_i => psw_write_bs_s, |
carry_o => psw_carry_s, |
aux_carry_i => alu_aux_carry_s, |
aux_carry_o => psw_aux_carry_s, |
f0_o => psw_f0_s, |
bs_o => psw_bs_s |
); |
|
|
----------------------------------------------------------------------------- |
-- Output Mapping. |
----------------------------------------------------------------------------- |
ale_o <= to_stdLogic(ale_s); |
prog_n_o <= to_stdLogic(not prog_s); |
xtal3_o <= to_stdLogic(xtal3_s); |
pmem_addr_o <= pmem_addr_s; |
|
end struct; |
/wip_t2x/rtl/vhdl/t48_comp_pack-p.vhd
26,6 → 26,24
|
package t48_comp_pack is |
|
component t48_adc |
port ( |
clk_i : in std_logic; |
res_i : in std_logic; |
en_clk_i : in boolean; |
ale_i : in boolean; |
mstate_i : in mstate_t; |
sel_an0_i : in boolean; |
sel_an1_i : in boolean; |
read_adc_i : in boolean; |
data_o : out word_t; |
sel_an_o : out std_logic; |
sh_o : out std_logic; |
sar_o : out std_logic_vector(7 downto 0); |
comp_i : in std_logic |
); |
end component; |
|
component t48_alu |
port ( |
clk_i : in std_logic; |
52,6 → 70,7
|
component t48_bus_mux |
port ( |
adc_data_i : in word_t := (others => bus_idle_level_c); |
alu_data_i : in word_t := (others => bus_idle_level_c); |
bus_data_i : in word_t := (others => bus_idle_level_c); |
dec_data_i : in word_t := (others => bus_idle_level_c); |
62,7 → 81,6
p2_data_i : in word_t := (others => bus_idle_level_c); |
psw_data_i : in word_t := (others => bus_idle_level_c); |
tim_data_i : in word_t := (others => bus_idle_level_c); |
adc_data_i : in word_t := (others => bus_idle_level_c); |
data_o : out word_t |
); |
end component; |
/wip_t2x/rtl/vhdl/t48_core_comp_pack-p.vhd
135,6 → 135,43
); |
end component; |
|
component t22_core |
generic ( |
xtal_div_3_g : integer := 1; |
register_mnemonic_g : integer := 1; |
sample_t1_state_g : integer := 4 |
); |
|
port ( |
xtal_i : in std_logic; |
xtal_en_i : in std_logic; |
reset_i : in std_logic; |
ale_o : out std_logic; |
t0_i : in std_logic; |
t1_i : in std_logic; |
p2_i : in std_logic_vector( 7 downto 0); |
p2_o : out std_logic_vector( 7 downto 0); |
p1_i : in std_logic_vector( 7 downto 0); |
p1_o : out std_logic_vector( 7 downto 0); |
p0_i : in std_logic_vector( 7 downto 0); |
p0_o : out std_logic_vector( 7 downto 0); |
prog_n_o : out std_logic; |
adc_sel_an_o : out std_logic; |
adc_sh_o : out std_logic; |
adc_sar_o : out std_logic_vector( 7 downto 0); |
adc_comp_i : in std_logic; |
clk_i : in std_logic; |
en_clk_i : in std_logic; |
xtal3_o : out std_logic; |
dmem_addr_o : out std_logic_vector( 7 downto 0); |
dmem_we_o : out std_logic; |
dmem_data_i : in std_logic_vector( 7 downto 0); |
dmem_data_o : out std_logic_vector( 7 downto 0); |
pmem_addr_o : out std_logic_vector(11 downto 0); |
pmem_data_i : in std_logic_vector( 7 downto 0) |
); |
end component; |
|
component generic_ram_ena |
generic ( |
addr_width_g : integer := 10; |
/wip_t2x/sim/rtl_sim/Makefile.ghdl
42,6 → 42,16
t8021 = $(LIB_WORK)/t8021.o |
tb_t8021_behav_c0 = $(LIB_WORK)/tb_t8021-c.o |
tb_t8021 = $(LIB_WORK)/tb_t8021.o |
adc_rtl_c0 = $(LIB_WORK)/adc-c.o |
adc = $(LIB_WORK)/adc.o |
t22_core_struct_c0 = $(LIB_WORK)/t22_core-c.o |
t22_core = $(LIB_WORK)/t22_core.o |
t8022_notri_struct_c0 = $(LIB_WORK)/t8022_notri-c.o |
t8022_notri = $(LIB_WORK)/t8022_notri.o |
t8022_struct_c0 = $(LIB_WORK)/t8022-c.o |
t8022 = $(LIB_WORK)/t8022.o |
tb_t8022_behav_c0 = $(LIB_WORK)/tb_t8022-c.o |
tb_t8022 = $(LIB_WORK)/tb_t8022.o |
|
upi41_db_bus_rtl_c0 = $(LIB_WORK)/upi41_db_bus-c.o |
upi41_db_bus = $(LIB_WORK)/upi41_db_bus.o |
170,6 → 180,7
tb_t8041a_elab = tb_t8041a_behav_c0 |
tb_t8042ah_elab = tb_t8042ah_behav_c0 |
tb_t8021_elab = tb_t8021_behav_c0 |
tb_t8022_elab = tb_t8022_behav_c0 |
# |
############################################################################## |
|
204,11 → 215,14
$(tb_t8021_elab) : $(tb_t8021_behav_c0) |
$(ELABORATE) tb_t8021_behav_c0 |
|
$(tb_t8022_elab) : $(tb_t8022_behav_c0) |
$(ELABORATE) tb_t8022_behav_c0 |
|
.PHONY: elaborate |
elaborate: $(LIB_WORK) $(tb_elab) $(tb_t8048_elab) $(tb_t8039_elab) \ |
$(tb_t8048_t8243_elab) $(tb_t8243_elab) \ |
$(tb_t8041_elab) $(tb_t8041a_elab) $(tb_t8042ah_elab) \ |
$(tb_t8021_elab) |
$(tb_t8021_elab) $(tb_t8022_elab) |
# |
############################################################################## |
|
/wip_t2x/sim/rtl_sim/Makefile.hier
648,3 → 648,78
$(t48_tb_pack) \ |
$(tb_t8021) |
$(ANALYZE) $< |
|
$(adc) : $(RTL_DIR)/adc.vhd \ |
$(t48_pack) |
$(ANALYZE) $< |
|
$(adc_rtl_c0) : $(RTL_DIR)/adc-c.vhd \ |
$(adc) |
$(ANALYZE) $< |
|
$(t22_core) : $(RTL_DIR)/t22_core.vhd \ |
$(decoder_pack) \ |
$(t48_comp_pack) \ |
$(pmem_ctrl_pack) \ |
$(dmem_ctrl_pack) \ |
$(cond_branch_pack) \ |
$(t48_pack) \ |
$(alu_pack) |
$(ANALYZE) $< |
|
$(t22_core_struct_c0) : $(RTL_DIR)/t22_core-c.vhd \ |
$(psw_rtl_c0) \ |
$(pmem_ctrl_rtl_c0) \ |
$(p2_rtl_c0) \ |
$(p1_rtl_c0) \ |
$(timer_rtl_c0) \ |
$(dmem_ctrl_rtl_c0) \ |
$(decoder_rtl_c0) \ |
$(cond_branch_rtl_c0) \ |
$(clock_ctrl_rtl_c0) \ |
$(bus_mux_rtl_c0) \ |
$(alu_rtl_c0) \ |
$(adc_rtl_c0) \ |
$(decoder_pack) \ |
$(t48_comp_pack) \ |
$(pmem_ctrl_pack) \ |
$(dmem_ctrl_pack) \ |
$(cond_branch_pack) \ |
$(t48_pack) \ |
$(alu_pack) \ |
$(t22_core-struct) \ |
$(t22_core) |
$(ANALYZE) $< |
|
$(t8022_notri) : $(RTL_DIR)/system/t8022_notri.vhd \ |
$(t48_core_comp_pack) |
$(ANALYZE) $< |
|
$(t8022_notri_struct_c0) : $(RTL_DIR)/system/t8022_notri-c.vhd \ |
$(t22_core_struct_c0) \ |
$(generic_ram_ena_rtl_c0) \ |
$(t49_rom_lpm_c0) \ |
$(t48_core_comp_pack) \ |
$(t8022_notri) |
$(ANALYZE) $< |
|
$(t8022) : $(RTL_DIR)/system/t8022.vhd \ |
$(t48_system_comp_pack) |
$(ANALYZE) $< |
|
$(t8022_struct_c0) : $(RTL_DIR)/system/t8022-c.vhd \ |
$(t8022_notri_struct_c0) \ |
$(t8022) |
$(ANALYZE) $< |
|
$(tb_t8022) : $(BENCH_DIR)/tb_t8022.vhd \ |
$(t48_tb_pack) \ |
$(t48_core_comp_pack) \ |
$(t48_system_comp_pack) |
$(ANALYZE) $< |
|
$(tb_t8022_behav_c0) : $(BENCH_DIR)/tb_t8022-c.vhd \ |
$(t8022_struct_c0) \ |
$(t48_tb_pack) \ |
$(tb_t8022) |
$(ANALYZE) $< |
/wip_t2x/sw/run_regression.pl
33,6 → 33,7
# no_t41a : don't execute the t8041a testbench tb_t8041a_behav_c0 |
# no_t42ah : don't execute the t8042ah testbench tb_t8042ah_behav_c0 |
# no_t21 : don't execute the t8021 testbench tb_t8021_behav_c0 |
# no_t22 : don't execute the t8021 testbench tb_t8022_behav_c0 |
# no_dump_compare : don't include testcell when running dump compares |
# io_exp : use the testbenches containing the t8243 IO expander |
# tb_t8243_behav_c0 |
74,7 → 75,8
't41' => './tb_t8041_behav_c0', |
't41a' => './tb_t8041a_behav_c0', |
't42ah' => './tb_t8042ah_behav_c0', |
't21' => './tb_t8021_behav_c0'); |
't21' => './tb_t8021_behav_c0', |
't22' => './tb_t8022_behav_c0'); |
my %ghdl_io_expanders = ('gen' => './tb_t8243_behav_c0', |
't48' => './tb_t8048_t8243_behav_c0'); |
my $ghdl_simulator_opt = '--assert-level=error --stop-time=20ms'; |
/wip_t2x/sw/verif/black_box/mb/int/no_t22
--- wip_t2x/sw/verif/black_box/mcs2x/call/test.asm (revision 332)
+++ wip_t2x/sw/verif/black_box/mcs2x/call/test.asm (revision 333)
@@ -2,7 +2,7 @@
;; Test MCS2x CALL with simple program.
;; *******************************************************************
- INCLUDE "cpu.inc"
+ CPU 8021
INCLUDE "pass_fail.inc"
ORG 0
/wip_t2x/sw/verif/black_box/mcs2x/movp/test.asm
1,6 → 1,4
;; ******************************************************************* |
;; $Id: test.asm 295 2009-04-01 19:32:48Z arniml $ |
;; |
;; Test MOVP A, @ A |
;; ******************************************************************* |
|
/wip_t2x/sw/verif/black_box/mcs2x/p0/test.asm
2,24 → 2,23
;; Test MCS2x P0. |
;; ******************************************************************* |
|
INCLUDE "cpu.inc" |
CPU 8021 |
INCLUDE "pass_fail.inc" |
INCLUDE "mcs2x_opcodes.inc" |
|
ORG 0 |
|
;; Start of test |
mov a, #055H |
m2outlp0 |
outl p0, a |
clr a |
m2inp0 |
in a, p0 |
xrl a, #055H |
jnz fail |
|
mov a, #0AAH |
m2outlp0 |
outl p0, a |
clr a |
m2inp0 |
in a, p0 |
xrl a, #0AAH |
jnz fail |
|
/wip_t2x/sw/verif/black_box/mcs2x/rad/no_t48
--- wip_t2x/sw/verif/black_box/mcs2x/rad/test.asm (nonexistent)
+++ wip_t2x/sw/verif/black_box/mcs2x/rad/test.asm (revision 333)
@@ -0,0 +1,31 @@
+ ;; *******************************************************************
+ ;; Test MCS-22 RAD.
+ ;; *******************************************************************
+
+ CPU 8022
+ INCLUDE "pass_fail.inc"
+
+ ORG 0
+
+ ;; Start of test
+ sel an0
+ nop
+ nop
+ nop
+ rad
+ xrl a, #069H
+ jnz fail
+
+ sel an1
+ nop
+ nop
+ nop
+ rad
+ xrl a, #096H
+ jnz fail
+
+ jmp pass
+
+fail: FAIL
+
+pass: PASS
/wip_t2x/sw/verif/black_box/rl/no_t22
--- wip_t2x/sw/verif/black_box/tx/t0/t0/test.asm (revision 332)
+++ wip_t2x/sw/verif/black_box/tx/t0/t0/test.asm (revision 333)
@@ -11,9 +11,11 @@
;; Start of test
jnt0 fail
- anl P1, #0FEH
+ mov a, #0FEH
+ outl P1, a
jt0 fail
- orl P1, #001H
+ mov a, #0FFH
+ outl P1, a
jt0 pass
fail: FAIL
/wip_t2x/sw/verif/include/mcs2x_opcodes.inc
File deleted