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  • This comparison shows the changes necessary to convert path 
    /t48/tags/rel_0_6_1_beta/sw
    from Rev 256 to Rev 292
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  •

Rev 256 → Rev 292

/verif/white_box/p2_io_exp/no_dump_compare --- verif/white_box/p2_io_exp/test.asm (nonexistent) +++ verif/white_box/p2_io_exp/test.asm (revision 292) @@ -0,0 +1,43 @@ + ;; ******************************************************************* + ;; $Id: test.asm,v 1.1 2005-11-01 21:07:41 arniml Exp $ + ;; + ;; ******************************************************************* + + INCLUDE "cpu.inc" + INCLUDE "pass_fail.inc" + + ORG 0 + + ;; Start of test + jmp start + + +start: + call test_code + sel mb0 + + +pass: PASS + +fail: FAIL + + + + ORG 0400H +test_code: + ;; write to P2 + mov a, #089h + outl p2, a + + ;; use expander + mov a, #00ch + movd p5, a + + ;; write to P2 + mov a, #098h + outl p2, a + + ;; use expander + movd a, p6 + + ret
/verif/white_box/int_on_mb1/test.asm
0,0 → 1,59
;; *******************************************************************
;; $Id: test.asm,v 1.1 2005-10-31 10:05:13 arniml Exp $
;;
;; Test interrupt on code in Program Memory Bank 1.
;; => Bug report "Problem with INT and JMP"
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
test_byte: equ 020h
 
ORG 0
 
;; Start of test
jmp start
 
;; interrupt hits djnz instruction with opcode 0EAh
;; bus conflict results on interrupt vector address 002h
;; -> retr instruction placed here, so test finds FAIL
retr
 
ORG 3
;; interrupt executed
mov r0, #test_byte
mov a, #0ffh
mov @r0, a
retr
 
start:
;; enable interrupt
en i
 
;; clear test byte
mov r1, #test_byte
clr a
mov @r1, a
 
call program_memory_bank_1
sel mb0
 
;; check if interrupt was successful
mov a, @r1
jz fail
 
 
pass: PASS
 
fail: FAIL
 
ORG 0800H
program_memory_bank_1:
;; spend some time and wait for interrupt
mov r2, #020h
djnz r2, $
 
ret
/verif/white_box/int_on_jmp/test.asm
0,0 → 1,91
;; *******************************************************************
;; $Id: test.asm,v 1.1 2005-09-07 21:41:05 arniml Exp $
;;
;; Test interrupt on JMP in Program Memory Bank 1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
test_byte: equ 020h
 
ORG 0
 
;; Start of test
jmp start
 
ORG 3
;; check that interrupt hit JMP instruction
;; stack must contain target of JMP instruction at
;; location jmp_instruction
mov r0, #00ah
mov a, @r0
;; check low byte of program counter on stack
xrl a, #000h
jnz fail
inc r0
mov a, @r0
anl a, #00fh
;; check high byte of program counter on stack
mov r0, a
xrl a, #009h ; target of PASS case?
jz int_goon
mov a, r0
xrl a, #001h ; target of FAIL case?
jnz fail
 
int_goon:
;; interrupt hit correct instruction
mov r0, #test_byte
mov a, #0ffh
mov @r0, a
retr
 
start:
;; enable interrupt
en i
 
;; clear test byte
mov r1, #test_byte
clr a
mov @r1, a
 
call program_memory_bank_1
sel mb0
 
;; check if interrupt was successful
mov a, @r1
jz fail
 
 
pass: PASS
 
fail: FAIL
ORG 0100H
;; program flow continues in fail case at address 0100h
;; after interrupt
;; i.e. bit 11 of address is erroneously cleared.
 
;; make sure that jump to fail reaches memory bank 0
sel mb0
jmp fail
 
 
ORG 0800H
program_memory_bank_1:
;; spend some time and wait for interrupt
mov r2, #013h
djnz r2, $
 
jmp_instruction:
;; interrupt must hit this JMP (checked by examining stack
;; in interrupt handler)
jmp test_jmp
ret
 
ORG 0900H
test_jmp:
;; program flow continues in pass case here after interrupt
ret
/verif/white_box/int_on_call/test.asm
0,0 → 1,91
;; *******************************************************************
;; $Id: test.asm,v 1.1 2005-09-07 20:24:30 arniml Exp $
;;
;; Test interrupt on CALL in Program Memory Bank 1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
test_byte: equ 020h
 
ORG 0
 
;; Start of test
jmp start
 
ORG 3
;; check that interrupt hit CALL instruction
;; stack must contain target of CALL instruction at
;; location call_instruction
mov r0, #00ch
mov a, @r0
;; check low byte of program counter on stack
xrl a, #000h
jnz fail
inc r0
mov a, @r0
anl a, #00fh
;; check high byte of program counter on stack
mov r0, a
xrl a, #009h ; target of PASS case?
jz int_goon
mov a, r0
xrl a, #001h ; target of FAIL case?
jnz fail
 
int_goon:
;; interrupt hit correct instruction
mov r0, #test_byte
mov a, #0ffh
mov @r0, a
retr
 
start:
;; enable interrupt
en i
 
;; clear test byte
mov r1, #test_byte
clr a
mov @r1, a
 
call program_memory_bank_1
sel mb0
 
;; check if interrupt was successful
mov a, @r1
jz fail
 
 
pass: PASS
 
fail: FAIL
ORG 0100H
;; program flow continues in fail case at address 0100h
;; after interrupt
;; i.e. bit 11 of address is erroneously cleared.
 
;; make sure that jump to fail reaches memory bank 0
sel mb0
jmp fail
 
 
ORG 0800H
program_memory_bank_1:
;; spend some time and wait for interrupt
mov r2, #013h
djnz r2, $
 
call_instruction:
;; interrupt must hit this CALL (checked by examining stack
;; in interrupt handler)
call test_call
ret
 
ORG 0900H
test_call:
;; program flow continues in pass case here after interrupt
ret
/verif/white_box/pc_wrap_bit11/test.asm
0,0 → 1,45
;; *******************************************************************
;; $Id: test.asm,v 1.1 2005-06-08 19:05:39 arniml Exp $
;;
;; Test wrap-around of Program Counter on bits 10 - 0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; decide whether this is the first time that the test
;; executes from address 0
in a, P1
jnz first_time
 
;; came here for the second time
;; -> that's great!
jmp pass
 
first_time:
clr a
outl P1, a ; tag P1 -> lock this path
;; jump to external Program Memory
jmp end_of_first_2k
 
pass: PASS
 
fail: FAIL
 
 
;; end of first 2k program memory
ORG 07FEH
end_of_first_2k:
nop
nop
;; no wrap-around to address 0
 
 
ORG 0800H
 
jmp fail
 
/verif/white_box/psen_rd_wr_timing/test.asm
0,0 → 1,59
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-09-12 00:28:58 arniml Exp $
;;
;; Test overlap of PSEN and RD/WR.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; access external memory
mov r0, #0FFH
mov a, #001H
movx @r0, a
 
;; jump to external Program Memory
jmp extern_rom
 
pass: PASS
 
fail: FAIL
 
 
ORG 0800H
extern_rom:
;; write to external memory
mov r0, #010H
mov a, #0A5H
movx @r0, a
cpl a
mov r1, a
inc r0
movx @r0, a
 
;; read back data
movx a, @r0
cpl a
add a, r1
cpl a
jz read_next
jmp fail
 
read_next:
mov a, r1
cpl a
mov r1, a
dec r0
movx a, @r0
cpl a
add a, r1
cpl a
jz read_ok
jmp fail
 
read_ok:
jmp pass
/verif/white_box/p1_port_reg_conflict/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail in i8039 emulator.
/verif/white_box/p1_port_reg_conflict/test.asm
0,0 → 1,119
;; *******************************************************************
;; $Id: test.asm,v 1.1 2004-05-17 14:34:41 arniml Exp $
;;
;; Test P1 conflict for reading port or output register.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; access testbench peripherals
mov r0, #0FFH
mov a, #002H
movx @r0, a
 
;; check functionality of P1 testbench peripheral
in a, p1
inc a
jnz fail
 
mov r0, #000H
;; extern write 00H to P1
clr a
movx @r0, a
in a, p1
jnz fail
;; extern write 0AAH to P1
mov a, #0AAH
movx @r0, a
clr a
in a, p1
add a, #056H
jnz fail
;; extern write 055H to P1
mov a, #055H
movx @r0, a
clr a
in a, p1
add a, #0ABH
jnz fail
 
;; reset extern P1 to 0FFH
dec a
movx @r0, a
 
;;
;; Start of real test
;;
 
;; Test ORL
 
;; set internal P1 to 0AAH
mov a, #0AAH
outl p1, a
in a, p1
add a, #056H
jnz fail
 
;; extern write 055H to P1
mov a, #055H
movx @r0, a
 
in a, p1
jnz fail
 
;; set internal P1 to 0ABH, setting P1[0] to 1
orl P1, #001H
in a, p1
dec a
jnz fail
 
;; reset extern P1 to 0FFH
dec a
movx @r0, a
 
;; compare P1 vs. 0ABH
in a, p1
cpl a
add a, #0ABH
cpl a
jnz fail
 
;; reset intern P1 to 0FFH
dec a
outl p1, a
 
;; set internal P1 to 055H
mov a, #055H
outl p1, a
clr a
in a, p1
add a, #0ABH
jnz fail
 
;; external write 0AAH to P1
mov a, #0AAH
movx @r0, a
 
;; set internal P1 to 054H
anl P1, #0FEH
 
;; reset extern P1 to 0FFH
mov a, #0FFH
movx @r0, a
 
;; compare P1 vs. 054H
in a, p1
cpl a
add a, #054H
cpl a
jnz fail
 
 
pass: PASS
 
fail: FAIL
/verif/white_box/p2_port_reg_conflict/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail for i8039 emulator.
/verif/white_box/p2_port_reg_conflict/test.asm
0,0 → 1,119
;; *******************************************************************
;; $Id: test.asm,v 1.1 2004-05-17 13:47:32 arniml Exp $
;;
;; Test P2 conflict for reading port or output register.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; access testbench peripherals
mov r0, #0FFH
mov a, #002H
movx @r0, a
 
;; check functionality of P2 testbench peripheral
in a, p2
inc a
jnz fail
 
mov r0, #001H
;; extern write 00H to P2
clr a
movx @r0, a
in a, p2
jnz fail
;; extern write 0AAH to P2
mov a, #0AAH
movx @r0, a
clr a
in a, p2
add a, #056H
jnz fail
;; extern write 055H to P2
mov a, #055H
movx @r0, a
clr a
in a, p2
add a, #0ABH
jnz fail
 
;; reset extern P2 to 0FFH
dec a
movx @r0, a
 
;;
;; Start of real test
;;
 
;; Test ORL
 
;; set internal P2 to 0AAH
mov a, #0AAH
outl p2, a
in a, p2
add a, #056H
jnz fail
 
;; extern write 055H to P2
mov a, #055H
movx @r0, a
 
in a, p2
jnz fail
 
;; set internal P2 to 0ABH, setting P2[0] to 1
orl P2, #001H
in a, p2
dec a
jnz fail
 
;; reset extern P2 to 0FFH
dec a
movx @r0, a
 
;; compare P2 vs. 0ABH
in a, p2
cpl a
add a, #0ABH
cpl a
jnz fail
 
;; reset intern P2 to 0FFH
dec a
outl p2, a
 
;; set internal P2 to 055H
mov a, #055H
outl p2, a
clr a
in a, p2
add a, #0ABH
jnz fail
 
;; external write 0AAH to P2
mov a, #0AAH
movx @r0, a
 
;; set internal P2 to 054H
anl P2, #0FEH
 
;; reset extern P2 to 0FFH
mov a, #0FFH
movx @r0, a
 
;; compare P2 vs. 054H
in a, p2
cpl a
add a, #054H
cpl a
jnz fail
 
 
pass: PASS
 
fail: FAIL
/verif/black_box/ins/test.asm
0,0 → 1,37
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-10-25 19:33:13 arniml Exp $
;;
;; Test INS A, BUS.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; deselect external memory
mov r0, #0FFH
clr a
movx @r0, a
 
mov a, #055H
outl bus, a
 
clr a
ins a, bus
add a, #0ABH
jnz fail
 
mov a, #0AAH
outl bus, a
 
clr a
ins a, bus
add a, #056H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/ins/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail in i8039 emulator.
/verif/black_box/cnt/int/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/verif/black_box/cnt/int/test.asm
0,0 → 1,113
;; *******************************************************************
;; $Id: test.asm,v 1.1 2004-05-16 16:25:14 arniml Exp $
;;
;; Test Counter Interrupt.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
jmp start
nop
jmp fail
jmp fail
jmp counter_int
jmp fail
 
;; Start of test
start: mov a, #0FEH
mov t, a
 
mov r0, #000H
 
strt cnt
en tcnti
 
jtf fail
 
;; apply falling edge on T1 -> T = 0FFH
anl P1, #0FDH
call check_cnt_idle
mov a, t
inc a
jnz fail
;; apply rising edge on T1
orl P1, #002H
call check_cnt_idle
mov a, t
inc a
jnz fail
 
;; apply falling edge on T1 -> T = 000H
anl P1, #0FDH
jtf goon
jmp fail
goon: mov a, r0
inc a
jnz fail
mov r0, a
jtf fail
;; apply rising edge on T1
orl P1, #002H
call check_cnt_idle
 
;; apply falling edge on T1 -> T = 001H
anl P1, #0FDH
call check_cnt_idle
mov a, t
dec a
jnz fail
;; apply rising edge on T1
orl P1, #002H
call check_cnt_idle
mov a, t
dec a
jnz fail
 
;; apply falling edge on T1 -> T = 002H
anl P1, #0FDH
call check_cnt_idle
mov a, t
dec a
dec a
jnz fail
;; apply rising edge on T1
orl P1, #002H
call check_cnt_idle
mov a, t
dec a
dec a
jnz fail
 
;; disable interrupt and trigger overflow
dis tcnti
mov a, #0FFH
mov t, a
call check_cnt_idle
 
;; apply falling edge on T1 -> T = 000H
anl P1, #0FDH
jtf goon2
jmp fail
goon2: mov a, r0
jnz fail
mov a, t
jnz fail
 
 
pass: PASS
 
fail: FAIL
 
 
check_cnt_idle:
jtf fail
mov a, r0
jnz fail
ret
 
 
counter_int:
mov r0, #0FFH
retr
/verif/black_box/cnt/cnt/test.asm
0,0 → 1,82
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-05-16 16:25:46 arniml Exp $
;;
;; Test Counter.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FEH
mov t, a
 
strt cnt
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
jtf fail
mov a, t
cpl a
add a, #0FFH
cpl a
jnz fail
 
;; apply rising edge on T1
orl P1, #002H
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
jtf goon
jmp fail
goon: jtf fail
mov a, t
jnz fail
 
;; apply rising edge on T1
orl P1, #002H
jtf fail
 
;; apply falling edge on T1
anl P1, #0FDH
jtf fail
mov a, t
dec a
jnz fail
 
;; check inactivity of counter
stop tcnt
mov a, #0FFH
mov t, a
 
;; apply rising edge on T1
orl P1, #002H
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
jtf fail
;; apply rising edge on T1
orl P1, #002H
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
jtf fail
 
strt cnt
;; apply rising edge on T1
orl P1, #002H
jtf fail
;; apply falling edge on T1
anl P1, #0FDH
jtf goon2
jmp fail
 
goon2:
 
pass: PASS
 
fail: FAIL
/verif/black_box/int/simple_int_retr/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/verif/black_box/int/simple_int_retr/test.asm
0,0 → 1,48
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test simple interrupt/RETR requences.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jmp start_user
 
 
ORG 3
cpl f1
cpl f0
mov r1, #060H
int_loop:
djnz r1, int_loop
jf1 int_goon
jmp fail
int_goon:
dis i
retr
 
 
ORG 020H
start_user:
mov r0, #080H
en i
nop
loop1: djnz r0, loop1
jf0 fail
jf1 goon1
jmp fail
 
goon1: mov r0, #080H
cpl f1
en i
loop2: djnz r0, loop2
jf0 fail
jf1 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/int/jni/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/verif/black_box/int/jni/test.asm
0,0 → 1,21
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test JNI.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jni fail
 
mov r0, #000H
poll: jni pass
djnz r0, poll
 
fail: FAIL
 
pass: PASS
/verif/black_box/int/simple_jump_to/test.asm
0,0 → 1,28
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test a simple jump to interrupt.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jmp start_user
 
 
ORG 3
jmp pass
 
 
ORG 010H
start_user:
en i
mov r0, #080H
loop: djnz r0, loop
 
fail: FAIL
 
pass: PASS
/verif/black_box/orl/bus/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail in i8039 emulator.
/verif/black_box/orl/bus/test.asm
0,0 → 1,29
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test ORL BUS, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
outl bus, a
 
cpl a
ins a, bus
jnz fail
 
orl bus, #0AAH
jnz fail
 
ins a, bus
add a, #056H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/orl/pp/test.asm
0,0 → 1,40
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test ORL Pp, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
outl p1, a
outl p2, a
 
cpl a
in a, p1
jnz fail
 
cpl a
in a, p2
jnz fail
 
orl P1, #0AAH
jnz fail
orl P2, #055H
jnz fail
 
in a, p1
add a, #056H
jnz fail
 
in a, p2
add a, #0ABH
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/orl/rr/test.asm
0,0 → 1,149
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test ORL A, Rr with RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, #(1 << 0)
orl a, r0
cpl a
jnz fail_p3
clr a
orl a, r0
add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 1)
orl a, r1
cpl a
jnz fail_p3
clr a
orl a, r1
add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 2)
orl a, r2
cpl a
jnz fail_p3
clr a
orl a, r2
add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 3)
orl a, r3
cpl a
jnz fail_p3
clr a
orl a, r3
add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 4)
orl a, r4
cpl a
jnz fail_p3
clr a
orl a, r4
add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 5)
orl a, r5
cpl a
jnz fail_p3
clr a
orl a, r5
add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 6)
orl a, r6
cpl a
jnz fail_p3
clr a
orl a, r6
add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 7)
orl a, r7
cpl a
jnz fail_p3
clr a
orl a, r7
add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH
jnz fail_p3
 
ret
 
fail_p3:
FAIL
/verif/black_box/orl/a_data/test.asm
0,0 → 1,32
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test ORL A, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
clr a
orl a, #0FFH
jz fail
orl a, #0FFH
jz fail
 
clr a
orl a, #055H
add a, #0ABH
jnz fail
 
clr a
orl a, #023H
orl a, #088H
add a, #055H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/orl/ind_rr/test.asm
0,0 → 1,92
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test ORL A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testR0R1 MACRO pos
inc r0
inc r1
mov a, #(1 << pos)
orl a, @r0
cpl a
jnz fail
clr a
orl a, @r0
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
mov a, #(1 << pos)
orl a, @r1
cpl a
jnz fail
clr a
orl a, @r1
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
jmp goon
 
ORG 256
;;
goon: mov r0, #00FH
mov r1, #01FH
testR0R1 0
testR0R1 1
testR0R1 2
testR0R1 3
testR0R1 4
testR0R1 5
testR0R1 6
testR0R1 7
 
pass: PASS
 
fail: FAIL
/verif/black_box/rb/int/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/verif/black_box/rb/int/test.asm
0,0 → 1,228
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-04-15 22:01:51 arniml Exp $
;;
;; Test interrupts in conjunction with RB-switching.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
jmp start
nop
jmp interrupt
jmp fail
jmp fail
jmp fail
 
 
;; Start of test
start:
;; fill RB0
clr a
call fill
 
;; fill RB1
sel rb1
mov a, #010H
call fill
sel rb0
 
;; set up interrupt
clr f1
;; sync on next interrupt
call sync_on_int
 
mov r0, #000H
en i
loop1: jf1 goon1
djnz r0, loop1
jmp fail
 
goon1:
dis i
clr f1
 
;; check BS implicitely
;; r0 must not be zero
mov a, r0
jz fail
 
;; check RB1
sel rb1
call check_0
 
;; check RB0
sel rb0
call check_rb0
 
pass: PASS
 
fail: FAIL
 
 
ORG 0200H
interrupt:
sel rb1
mov r0, a
 
call check_rb1
 
clr a
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
xch a, r0
 
cpl f1
 
retr
 
 
ORG 0300H
 
fill: add a, #0B0H
mov r0, a
inc a
mov r1, a
inc a
mov r2, a
inc a
mov r3, a
inc a
mov r4, a
inc a
mov r5, a
inc a
mov r6, a
inc a
mov r7, a
ret
 
check_0:
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
ret
 
;; synchronize on interrupt
;; use r7 for timeout detection
sync_on_int:
mov a, r7 ; save r7
mov r7, #000H
wait_int1:
jni sync_on_int2
djnz r7, wait_int1
jmp fail_p3
 
sync_on_int2:
mov r7, #000H
wait_int2:
jni still_int
mov r7, a ; restore r7
call clr_int
retr
still_int:
djnz r7, wait_int2
jmp fail_p3
 
clr_int:
;; clear latched interrupt request with RETR!
retr
 
check_rb1:
mov a, #(~0C1H & 0FFH)
add a, r1
cpl a
jnz fail_p3
 
mov a, #(~0C2H & 0FFH)
add a, r2
cpl a
jnz fail_p3
 
mov a, #(~0C3H & 0FFH)
add a, r3
cpl a
jnz fail_p3
 
mov a, #(~0C4H & 0FFH)
add a, r4
cpl a
jnz fail_p3
 
mov a, #(~0C5H & 0FFH)
add a, r5
cpl a
jnz fail_p3
 
mov a, #(~0C6H & 0FFH)
add a, r6
cpl a
jnz fail_p3
 
mov a, #(~0C7H & 0FFH)
add a, r7
cpl a
jnz fail_p3
 
ret
 
check_rb0:
mov a, #(~0B1H & 0FFH)
add a, r1
cpl a
jnz fail_p3
 
mov a, #(~0B2H & 0FFH)
add a, r2
cpl a
jnz fail_p3
 
mov a, #(~0B3H & 0FFH)
add a, r3
cpl a
jnz fail_p3
 
mov a, #(~0B4H & 0FFH)
add a, r4
cpl a
jnz fail_p3
 
mov a, #(~0B5H & 0FFH)
add a, r5
cpl a
jnz fail_p3
 
mov a, #(~0B6H & 0FFH)
add a, r6
cpl a
jnz fail_p3
 
mov a, #(~0B7H & 0FFH)
add a, r7
cpl a
jnz fail_p3
 
ret
 
fail_p3:
FAIL
/verif/black_box/rb/misc/test.asm
0,0 → 1,142
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test several operations in conjunction with RB-switching.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill data memory with 0
clr a
mov r0, a
fill_loop:
mov @r0, a
djnz r0, fill_loop
 
;; set up both register banks with indirect writes
mov r0, #01FH
mov r1, #008H
fill_rb1_loop:
mov a, r0
mov @r0, a
dec r0
djnz r1, fill_rb1_loop
 
mov r0, #007H
fill_rb0_loop:
mov a, r0
mov @r0, a
djnz r0, fill_rb0_loop
mov a, r0
mov @r0, a
 
;; check RB0
call check_rb0
 
;; check RB1
sel rb1
call check_rb1
 
;; check RB0 again
sel rb0
call check_rb0
 
;; check memory between RB0 and RB1 for 0
mov r0, #00EH ; check 14 bytes
mov r1, #00AH ; starting from address A
chk_loop1:
mov a, @r1
jnz fail
inc r1
djnz r0, chk_loop1
 
;; check memory above RB1 for 0
mov r0, #0100H - 0020H ; check 256-32 bytes
mov r1, #020H ; starting from address 20H
chk_loop2:
mov a, @r1
jnz fail
inc r1
djnz r0, chk_loop2
 
;; now use RB1 to indirect address register 0-7
mov r1, #001H ; restore r1
mov r0, #000H ; restore r0, set trap
sel rb1
mov r0, #007H
ind_chk_loop:
mov a, @r0
cpl a
add a, r0
cpl a
jnz fail
djnz r0, ind_chk_loop
 
 
pass: PASS
 
fail: FAIL
 
 
 
ORG 0300H
check_rb0:
mov a, r0
jnz fail_p3
mov a,r1
add a, #0FFH
jnz fail_p3
mov a,r2
add a, #0FEH
jnz fail_p3
mov a,r3
add a, #0FDH
jnz fail_p3
mov a,r4
add a, #0FCH
jnz fail_p3
mov a,r5
add a, #0FBH
jnz fail_p3
mov a,r6
add a, #0FAH
jnz fail_p3
mov a,r7
add a, #0F9H
jnz fail_p3
ret
 
check_rb1:
mov a, r0
add a, #0E8H
jnz fail_p3
mov a,r1
add a, #0E7H
jnz fail_p3
mov a,r2
add a, #0E6H
jnz fail_p3
mov a,r3
add a, #0E5H
jnz fail_p3
mov a,r4
add a, #0E4H
jnz fail_p3
mov a,r5
add a, #0E3H
jnz fail_p3
mov a,r6
add a, #0E2H
jnz fail_p3
mov a,r7
add a, #0E1H
jnz fail_p3
ret
 
fail_p3:
FAIL
/verif/black_box/expander/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail for i8039 emulator.
/verif/black_box/expander/test.asm
0,0 → 1,88
;; *******************************************************************
;; $Id: test.asm,v 1.1 2004-05-01 11:56:57 arniml Exp $
;;
;; Test Expander port functionality.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #00AH
movd p4, a
mov a, #005H
movd p5, a
mov a, #00BH
movd p6, a
mov a, #000H
movd p7, a
 
;; check P4
movd a, p4
orl a, #0F5H
inc a
;jnz fail
mov a, #0F5H
orld p4, a
movd a, p4
inc a
;jnz fail
mov a, #0FEH
anld p4, a
movd a, p4
add a, #0F2H
;jnz fail
 
;; check P5
movd a, p5
orl a, #0FAH
inc a
;jnz fail
mov a, #0FAH
orld p5, a
movd a, p5
inc a
;jnz fail
mov a, #0FDH
anld p5, a
movd a, p5
add a, #0F3H
;jnz fail
 
;; check P6
movd a, p6
orl a, #0F4H
inc a
;jnz fail
mov a, #0F4H
orld p6, a
movd a, p6
inc a
;jnz fail
mov a, #0F8H
anld p6, a
movd a, p6
add a, #0F8H
;jnz fail
 
;; check P7
movd a, p7
orl a, #0FFH
inc a
;jnz fail
mov a, #0FFH
orld p7, a
movd a, p7
inc a
;jnz fail
mov a, #0F7H
anld p7, a
movd a, p7
add a, #0F9H
;jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/outl/bus/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail in i8039 emulator.
/verif/black_box/outl/bus/test.asm
0,0 → 1,20
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test OUTL BUS, A
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #055H
outl bus, a
cpl a
outl bus, a
 
pass: PASS
 
fail: FAIL
/verif/black_box/outl/pp/test.asm
0,0 → 1,20
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test OUTL Pp, A
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #055H
outl p1, a
mov a, #0AAH
outl p2, a
 
pass: PASS
 
fail: FAIL
/verif/black_box/tim/int/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/verif/black_box/tim/int/test.asm
0,0 → 1,41
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test Timer Interrupt.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
jmp start
nop
jmp fail
jmp fail
jmp timer_int
jmp fail
 
;; Start of test
start: mov a, #0F8H
mov t, a
clr a
mov r0, a
mov r1, a
 
en tcnti
jtf fail
 
strt t
 
loop: mov a, r0
jnz pass
djnz r1, loop
 
fail: FAIL
 
pass: PASS
 
 
timer_int:
mov r0, #0FFH
retr
/verif/black_box/tim/t/test.asm
0,0 → 1,110
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test Timer.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0F8H
mov t, a
 
strt t
jtf fail
 
mov r0, #000H
poll1: jtf goon1
djnz r0, poll1
jmp fail
 
goon1: mov a, t
jnz fail
mov r0, #000H
poll2: mov a, t
add a, #0FBH
jz goon2
djnz r0, poll2
 
goon2: stop tcnt
clr a
mov t, a
strt t
 
mov a, t
jnz fail
 
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
 
mov a, t
dec a
jnz fail
 
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
 
mov a, t
dec a
dec a
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/movx/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External RAM is not modelled in i8039 emulator.
/verif/black_box/movx/test.asm
0,0 → 1,60
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-05-17 14:42:09 arniml Exp $
;;
;; Test MOVX A, @ Rr for RB0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r0, #0FEH
fill_loop1:
mov a, r0
movx @r0, a
djnz r0, fill_loop1
 
;; check memory
mov a, r0
jnz fail
mov r0, #0FEH
mov r1, #002H
check_loop1:
clr a
movx a, @r1
add a, r0
jnz fail
inc r1
dec r0
mov a, r0
dec a
jnz check_loop1
 
 
 
mov r1, #0FEH
mov a, #002H
fill_loop2:
movx @r1, a
inc a
djnz r1, fill_loop2
 
;; check memory
mov a, r1
jnz fail
mov r0, #0FEH
check_loop2:
clr a
movx a, @r0
add a, r0
jnz fail
dec r0
mov a, r0
dec a
jnz check_loop2
 
pass: PASS
 
fail: FAIL
/verif/black_box/anl/bus/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
External ports not modelled in detail in i8039 emulator.
/verif/black_box/anl/bus/test.asm
0,0 → 1,30
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ANL BUS, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
outl bus, a
 
clr a
ins a, bus
inc a
jnz fail
 
anl bus, #0AAH
jnz fail
 
ins a, bus
add a, #056H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/anl/pp/test.asm
0,0 → 1,41
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ANL Pp, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
outl p1, a
outl p2, a
 
clr a
in a, p1
inc a
jnz fail
 
in a, p2
inc a
jnz fail
 
anl P1, #0AAH
jnz fail
anl P2, #055H
jnz fail
 
in a, p1
add a, #056H
jnz fail
 
in a, p2
add a, #0ABH
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/anl/rr/test.asm
0,0 → 1,140
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ANL A, Rr for RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, #(1 << 0)
anl a, r0
jnz fail_p3
mov a, #0FFH
anl a, r0
add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 1)
anl a, r1
jnz fail_p3
mov a, #0FFH
anl a, r1
add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 2)
anl a, r2
jnz fail_p3
mov a, #0FFH
anl a, r2
add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 3)
anl a, r3
jnz fail_p3
mov a, #0FFH
anl a, r3
add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 4)
anl a, r4
jnz fail_p3
mov a, #0FFH
anl a, r4
add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 5)
anl a, r5
jnz fail_p3
mov a, #0FFH
anl a, r5
add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 6)
anl a, r6
jnz fail_p3
mov a, #0FFH
anl a, r6
add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 7)
anl a, r7
jnz fail_p3
mov a, #0FFH
anl a, r7
add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH
jnz fail_p3
ret
 
 
fail_p3: FAIL
/verif/black_box/anl/a_data/test.asm
0,0 → 1,32
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ANL A, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
anl a, #000H
jnz fail
anl a, #000H
jnz fail
 
mov a, #0FFH
anl a, #055H
add a, #0ABH
jnz fail
 
mov a, #0FFH
anl a, #0B6H
anl a, #023H
add a, #0DEH
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/anl/ind_rr/test.asm
0,0 → 1,90
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ANL A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testR0R1 MACRO pos
inc r0
inc r1
mov a, #(1 << pos)
anl a, @r0
jnz fail
mov a, #0FFH
anl a, @r0
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
mov a, #(1 << pos)
anl a, @r1
jnz fail
mov a, #0FFH
anl a, @r1
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
jmp goon
 
ORG 256
;;
goon: mov r0, #00FH
mov r1, #01FH
testR0R1 0
testR0R1 1
testR0R1 2
testR0R1 3
testR0R1 4
testR0R1 5
testR0R1 6
testR0R1 7
 
pass: PASS
 
fail: FAIL
/verif/black_box/mb/int/test.asm
0,0 → 1,62
;; *******************************************************************
;; $Id: test.asm,v 1.4 2004-07-03 14:35:11 arniml Exp $
;;
;; Test Program Memory bank selector with interrupts.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
jmp start
ORG 3
jmp interrupt & 07FFH
 
ORG 7
jmp fail
 
;; Start of test
start:
sel mb1
mov r0, #000H
en i
poll: jf1 goon1
djnz r0, poll
jmp fail
goon1:
 
call test_mb1 & 07FFH
 
pass: PASS
 
fail: FAIL
 
ORG 0232H
jmp fail
interrupt:
call trick_mb
cpl f1
retr
 
ORG 0250H
trick_mb:
ret
 
ORG 0260H
jmp fail
 
 
ORG 0A32H
jmp fail_hi
jmp fail_hi
jmp fail_hi
 
ORG 0A50H
jmp fail_hi
 
ORG 0A60H
test_mb1:
ret
 
fail_hi:
FAIL
/verif/black_box/mb/call_jmp/test.asm
0,0 → 1,125
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test Program Memory bank selector with CALL and JMP.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
sel mb1
call call1 & 07FFH
sel mb1
jmp jmp1 & 07FFH
;; trap
nop
jmp fail
nop
jmp fail
;;
jmp2: sel mb1
call call3 & 07FFH
sel mb1
jmp jmp3 & 07FFH
;; trap
nop
jmp fail
nop
jmp fail
;;
jmp4: sel mb1
call call5 & 07FFH
sel mb1
jmp jmp5 & 07FFH
;; trap
nop
jmp fail
nop
jmp fail
jmp6:
 
pass: PASS
 
fail: FAIL
 
ORG 0100H
 
;; trap
jmp fail
;;
call2: sel mb1
ret
;; trap
jmp fail
;;
call4: sel mb0
ret
;; trap
jmp fail
;;
call6: sel mb1
ret
 
 
 
ORG 0800H
 
;; trap
nop
jmp fail_hi
nop
jmp fail_hi
;;
jmp1: sel mb0
call call2 | 0800H
sel mb0
jmp jmp2 | 0800H
;; trap
nop
jmp fail_hi
nop
jmp fail_hi
;;
jmp3: sel mb0
call call4 | 0800H
sel mb0
jmp jmp4 | 0800H
;; trap
nop
jmp fail_hi
nop
jmp fail_hi
;;
jmp5: sel mb0
call call6 | 0800H
sel mb0
jmp jmp6 | 0800H
;; trap
nop
jmp fail_hi
nop
jmp fail_hi
 
 
fail_hi:
FAIL
 
 
ORG 0900H
call1: sel mb0
ret
;; trap
jmp fail_hi
;;
call3: sel mb1
ret
;; trap
jmp fail_hi
;;
call5: sel mb0
ret
;; trap
jmp fail_hi
/verif/black_box/da/test.asm
0,0 → 1,171
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-04-07 22:09:35 arniml Exp $
;;
;; Test DA A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r7, #000H
 
;; testcase from "Single Component MCS-48 System"
mov a, #09BH
da a
jnc fail
mov r0, a
mov a, psw
jb6 fail
mov a, r0
cpl a
add a, #001H
cpl a
jnz fail
 
;; a value that should not be changed
;; upper nibble: no overflow
;; lower nibble: no overflow
mov a, #037H
add a, r7 ; clear C and AC
da a
jc fail
mov r0, a
mov a, psw
jb6 fail
mov a, r0
cpl a
add a, #037H
cpl a
jnz fail
 
;; upper nibble: no overflow
;; lower nibble: overflow
mov a, #04AH
add a, r7 ; clear C and AC
da a
jc fail
mov r0, a
mov a, psw
jb6 fail
mov a, r0
cpl a
add a, #050H
cpl a
jnz fail
 
;; upper nibble: overflow
;; lower nibble: no overflow
mov a, #0C1H
add a, r7 ; clear C and AC
da a
jnc fail
mov r0, a
mov a, psw
jb6 fail
mov a, r0
cpl a
add a, #021H
cpl a
jnz fail
 
;; upper nibble: overflow
;; lower nibble: overflow
mov a, #0DEH
add a, r7 ; clear C and AC
da a
jnc fail
mov r0, a
mov a, psw
jb6 fail
mov a, r0
cpl a
add a, #044H
cpl a
jnz fail
 
 
;; ******************************************************************
;; Next round with Auxiliary Carry
;; ******************************************************************
 
add a, r7 ; clear C and AC
;; upper nibble: no overflow
;; lower nibble: no overflow
mov a, #029H ; add two BCD numbers
add a, #019H ; result: 042H, but should be 48 BCD
jc fail
mov r0, a
mov a, psw
jb6 goon1
jmp fail
goon1: mov a, r0
da a
jc fail
cpl a
add a, #048H
cpl a
jnz fail
 
add a, r7 ; clear C and AC
;; upper nibble: overflow
;; lower nibble: no overflow
mov a, #067H ; add two BCD numbers
add a, #059H ; result: 0C0H, but should be 126 BCD
jc fail
mov r0, a
mov a, psw
jb6 goon2
jmp fail
goon2: mov a, r0
clr c ; clear Carry, make set Carry by da testable
da a
jnc fail
cpl a
add a, #026H
cpl a
jnz fail
 
add a, r7 ; clear C and AC
;; upper nibble: no overflow
;; lower nibble: overflow
mov a, #01FH ; this is not a BCD number!
add a, #033H ; reault: 052H, reveals 58 BCD
jc fail
mov r0, a
mov a, psw
jb6 goon3
jmp fail
goon3: mov a, r0
da a
jc fail
cpl a
add a, #058H
cpl a
jnz fail
 
add a, r7 ; clear C and AC
;; upper nibble: overflow
;; lower nibble: overflow
mov a, #0EEH ; this is not a BCD number!
add a, #0C5H ; result: 1B3H. reveals 119 BCD
jnc fail
mov r0, a
mov a, psw
jb6 goon4
jmp fail
goon4: mov a, r0
clr c ; clear Carry, make set Carry by da testable
da a
jnc fail
cpl a
add a, #019H
cpl a
jnz fail
 
 
pass: PASS
 
fail: FAIL
/verif/black_box/xchd/test.asm
0,0 → 1,121
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-04-06 18:12:57 arniml Exp $
;;
;; Test XCHD A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testR0R1 MACRO pos
inc r0
inc r1
mov a, @r0
cpl a
add a, #((~((pos+7) # 8) << 4) & 0F0H) | (pos & 00FH)
cpl a
jnz fail
mov a, @r1
cpl a
add a, #((~((pos+7) # 8) << 4) & 0F0H) | (pos & 00FH)
cpl a
jnz fail
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0F0H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0E1H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0D2H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0C3H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0B4H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0A5H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #096H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #087H
mov @r0, a
mov @r1, a
 
dec r0
xchd a, @r0
dec r0
xchd a, @r0
dec r0
xchd a, @r0
dec r0
xchd a, @r0
dec r0
xchd a, @r0
dec r0
xchd a, @r0
dec r0
xchd a, @r0
mov r0, #017H
xchd a, @r0
 
mov a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
dec r1
xchd a, @r1
mov r1, #027H
xchd a, @r1
 
jmp goon
 
ORG 256
;;
goon: mov r0, #00FH
mov r1, #01FH
testR0R1 1
testR0R1 2
testR0R1 3
testR0R1 4
testR0R1 5
testR0R1 6
testR0R1 7
testR0R1 0
 
pass: PASS
 
fail: FAIL
/verif/black_box/xch/ind_rr/test.asm
0,0 → 1,121
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-04-04 13:28:33 arniml Exp $
;;
;; Test XCH A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testR0R1 MACRO pos
inc r0
inc r1
mov a, @r0
cpl a
add a, #~(1 << pos) & 0FFH
cpl a
jnz fail
mov a, @r1
cpl a
add a, #~(1 << pos) & 0FFH
cpl a
jnz fail
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
dec r0
xch a, @r0
dec r0
xch a, @r0
dec r0
xch a, @r0
dec r0
xch a, @r0
dec r0
xch a, @r0
dec r0
xch a, @r0
dec r0
xch a, @r0
mov r0, #017H
xch a, @r0
 
mov a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
dec r1
xch a, @r1
mov r1, #027H
xch a, @r1
 
jmp goon
 
ORG 256
;;
goon: mov r0, #00FH
mov r1, #01FH
testR0R1 1
testR0R1 2
testR0R1 3
testR0R1 4
testR0R1 5
testR0R1 6
testR0R1 7
testR0R1 0
 
pass: PASS
 
fail: FAIL
/verif/black_box/xch/rr/test.asm
0,0 → 1,119
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test XCH A, Rr for RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, r7
xch a, r6
xch a, r5
xch a, r4
xch a, r3
xch a, r2
xch a, r1
xch a, r0
xch a, r7
 
mov a, r0
add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH
jnz fail_p3
 
mov a, r1
add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH
jnz fail_p3
 
mov a, r2
add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH
jnz fail_p3
 
mov a, r3
add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH
jnz fail_p3
 
mov a, r4
add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH
jnz fail_p3
 
mov a, r5
add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH
jnz fail_p3
 
mov a, r6
add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH
jnz fail_p3
 
mov a, r7
add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH
jnz fail_p3
 
ret
 
fail_p3:
FAIL
/verif/black_box/psw/test.asm
0,0 → 1,61
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-29 20:09:50 arniml Exp $
;;
;; Test several commands related to PSW.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, psw
anl a, #0F7H
jnz fail
 
dec a
mov psw, a
mov a, psw
inc a
jnz fail
 
mov psw, a
mov a, psw
anl a, #0F7H
jnz fail
 
cpl f0
jf0 ok_1
jmp fail
ok_1: mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~028H + 1) & 0FFH
jnz fail
 
clr f0
jnc fail
mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~088H + 1) & 0FFH
jnz fail
 
clr c
jc fail
sel rb1
mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~018H + 1) & 0FFH
jnz fail
 
cpl c
jc fail
sel rb0
mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~08H + 1) & 0FFH
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/call/simple/test.asm
0,0 → 1,62
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-29 20:09:47 arniml Exp $
;;
;; Test CALL addr with simple program.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, psw
 
clr c
call1: call goon1
 
jmp fail
 
ORG 039FH
 
goon1: mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #~009H + 1
jnz fail
 
call2: call goon2
 
jmp fail
 
goon2: clr c
mov a, psw
anl a, #~040H ; mask AC, tested separately with DA
add a, #~00AH + 1
jnz fail
 
;; check stack contents
mov r0, #008H
mov a, @r0
add a, #(~(call1+2 & 0FFH) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~((call1+2) >> 8) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
add a, #(~(call2+2 & 0FFH) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
anl a, #~040H ; mask AC, tested separately with DA
add a, #(~((call2+2) >> 8 | 080H) + 1) & 0FFH
jnz fail
pass: PASS
 
fail: FAIL
/verif/black_box/call/call_ret/test.asm
0,0 → 1,104
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CALL + RET(R) with simple program.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r0, #008H
call recursive
 
call1: call sub1
jc fail
jf0 fail
jf1 ok_1
jmp fail
ok_1:
;; check stack contents
mov r0, #008H
mov a, @r0
add a, #(~(call1+2 & 0FFH) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
add a, #(~((call1+2) >> 8) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
add a, #(~(call2+2 & 0FFH) + 1) & 0FFH
jnz fail
 
inc r0
mov a, @r0
add a, #(~((call2+2) >> 8 | 0A0H) + 1) & 0FFH
jnz fail
 
 
clr c
clr f0
clr f1
call sub3
jc fail
jf0 fail
 
pass: PASS
 
fail: FAIL
 
 
 
ORG 0156H
recursive:
dec r0
mov a, r0
jz rec_end
call recursive
rec_end:
ret
 
 
ORG 0245H
 
sub1: cpl f0
cpl f1
cpl c
call2: call sub2
jf0 sub1_1
jmp fail2
sub1_1: jnc fail2
retr
 
sub2: jf0 sub2_1
jmp fail2
sub2_1: clr f0
jnc fail2
clr c
retr
 
fail2: FAIL
 
 
ORG 0311H
 
sub3: cpl f0
cpl c
call sub4
jf0 fail3
jc fail3
ret
 
sub4: jf0 sub4_1
jmp fail3
sub4_1: clr f0
jnc fail3
clr c
ret
 
fail3: FAIL
/verif/black_box/jnz/test.asm
0,0 → 1,49
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:37:12 arniml Exp $
;;
;; Test JNZ instruction.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
jnz fail
 
mov a, #001H
jnz ok_01
jmp fail
 
ok_01: mov a, #002H
jnz ok_02
jmp fail
 
ok_02: mov a, #004H
jnz ok_04
jmp fail
 
ok_04: mov a, #008H
jnz ok_08
jmp fail
 
ok_08: mov a, #010H
jnz ok_10
jmp fail
 
ok_10: mov a, #020H
jnz ok_20
jmp fail
 
ok_20: mov a, #040H
jnz ok_40
jmp fail
 
ok_40: mov a, #080H
jnz pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/jz/test.asm
0,0 → 1,43
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:34:14 arniml Exp $
;;
;; Test JZ instruction.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
jz ok_0
jmp fail
 
ok_0: mov a, #001H
jz fail
 
mov a, #002H
jz fail
 
mov a, #004H
jz fail
 
mov a, #008H
jz fail
 
mov a, #010H
jz fail
 
mov a, #020H
jz fail
 
mov a, #040H
jz fail
 
mov a, #080H
jz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/mov/a_rr/data_00/test.asm
0,0 → 1,63
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:35:51 arniml Exp $
;;
;; Test MOV A, Rr for RB0 with 0x00.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #055H
mov r0, #000H
mov r1, #0FFH
mov r2, #0FFH
mov r3, #0FFH
mov r4, #0FFH
mov r5, #0FFH
mov r6, #0FFH
mov r7, #0FFH
 
mov a, r0
jnz fail
 
mov r1, #000H
mov r0, #0FFH
mov a, r1
jnz fail
 
mov r2, #000H
mov r1, #0FFH
mov a, r2
jnz fail
 
mov r3, #000H
mov r2, #0FFH
mov a, r3
jnz fail
 
mov r4, #000H
mov r3, #0FFH
mov a, r4
jnz fail
 
mov r5, #000H
mov r4, #0FFH
mov a, r5
jnz fail
 
mov r6, #000H
mov r5, #0FFH
mov a, r6
jnz fail
 
mov r7, #000H
mov r6, #0FFH
mov a, r7
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/mov/a_rr/data_num/test.asm
0,0 → 1,50
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:37:27 arniml Exp $
;;
;; Test MOV A, Rr for RB0 with 2*r.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
mov r0, #0FEH
mov r1, #0FDH
mov r2, #0FBH
mov r3, #0F7H
mov r4, #0EFH
mov r5, #0DFH
mov r6, #0BFH
mov r7, #07FH
 
mov a, r0
jz fail
jb0 fail
 
mov a, r1
jb1 fail
 
mov a, r2
jb2 fail
 
mov a, r3
jb3 fail
 
mov a, r4
jb4 fail
 
mov a, r5
jb5 fail
 
mov a, r6
jb6 fail
 
mov a, r7
jb7 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/mov/mov_rr_a/data_00/test.asm
0,0 → 1,78
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:37:39 arniml Exp $
;;
;; Test MOV Rr, A for RB0 with 0x00.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #00H
mov r0, a
mov a, #0FFH
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
 
mov a, r0
jnz fail
 
mov a, #000H
mov r1, a
mov a, #0FFH
mov r0, a
mov a, r1
jnz fail
 
mov a, #000H
mov r2, a
mov a, #0FFH
mov r1, a
mov a, r2
jnz fail
 
mov a, #000H
mov r3, a
mov a, #0FFH
mov r2, a
mov a, r3
jnz fail
 
mov a, #000H
mov r4, a
mov a, #0FFH
mov r3, a
mov a, r4
jnz fail
 
mov a, #000H
mov r5, a
mov a, #0FFH
mov r4, a
mov a, r5
jnz fail
 
mov a, #000H
mov r6, a
mov a, #0FFH
mov r5, a
mov a, r6
jnz fail
 
mov a, #000H
mov r7, a
mov a, #0FFH
mov r6, a
mov a, r7
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/mov/mov_rr_a/data_num/test.asm
0,0 → 1,59
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:37:46 arniml Exp $
;;
;; Test MOV Rr, A for RB0 with 2*r.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
 
mov a, #000H
 
mov a, r0
jz fail
jb0 fail
 
mov a, r1
jb1 fail
 
mov a, r2
jb2 fail
 
mov a, r3
jb3 fail
 
mov a, r4
jb4 fail
 
mov a, r5
jb5 fail
 
mov a, r6
jb6 fail
 
mov a, r7
jb7 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/mov/ind_rr/test.asm
0,0 → 1,185
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test MOV @ Rr for RB0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r0, #0FFH
fill_loop:
mov a, r0
mov @r0, a
djnz r0, fill_loop
 
;; check memory
mov a, r0
jnz fail
mov r0, #0FFH
check_loop1:
mov a, @r1
add a, r0
jnz fail
dec r0
inc r1
mov a, r1
jnz check_loop1
jmp test_2
 
fail: FAIL
 
;;
ALIGN 256
;;
 
test_2: ;; test MOV @ Rr, data
mov r0, #0C0H
mov r1, #0E0H
mov @r0, #000H
mov @r1, #020H
 
inc r0
inc r1
mov @r0, #001H
mov @r1, #021H
inc r0
inc r1
mov @r0, #002H
mov @r1, #022H
inc r0
inc r1
mov @r0, #003H
mov @r1, #023H
inc r0
inc r1
mov @r0, #004H
mov @r1, #024H
inc r0
inc r1
mov @r0, #005H
mov @r1, #025H
inc r0
inc r1
mov @r0, #006H
mov @r1, #026H
inc r0
inc r1
mov @r0, #007H
mov @r1, #027H
inc r0
inc r1
mov @r0, #008H
mov @r1, #028H
inc r0
inc r1
mov @r0, #009H
mov @r1, #029H
inc r0
inc r1
mov @r0, #00AH
mov @r1, #02AH
inc r0
inc r1
mov @r0, #00BH
mov @r1, #02BH
inc r0
inc r1
mov @r0, #00CH
mov @r1, #02CH
inc r0
inc r1
mov @r0, #00DH
mov @r1, #02DH
inc r0
inc r1
mov @r0, #00EH
mov @r1, #02EH
inc r0
inc r1
mov @r0, #00FH
mov @r1, #02FH
;;
inc r0
inc r1
mov @r0, #010H
mov @r1, #030H
inc r0
inc r1
mov @r0, #011H
mov @r1, #031H
inc r0
inc r1
mov @r0, #012H
mov @r1, #032H
inc r0
inc r1
mov @r0, #013H
mov @r1, #033H
inc r0
inc r1
mov @r0, #014H
mov @r1, #034H
inc r0
inc r1
mov @r0, #015H
mov @r1, #035H
inc r0
inc r1
mov @r0, #016H
mov @r1, #036H
inc r0
inc r1
mov @r0, #017H
mov @r1, #037H
inc r0
inc r1
mov @r0, #018H
mov @r1, #038H
inc r0
inc r1
mov @r0, #019H
mov @r1, #039H
inc r0
inc r1
mov @r0, #01AH
mov @r1, #03AH
inc r0
inc r1
mov @r0, #01BH
mov @r1, #03BH
inc r0
inc r1
mov @r0, #01CH
mov @r1, #03CH
inc r0
inc r1
mov @r0, #01DH
mov @r1, #03DH
inc r0
inc r1
mov @r0, #01EH
mov @r1, #03EH
inc r0
inc r1
mov @r0, #01FH
mov @r1, #03FH
 
mov r0, #0FFH
mov r1, #11000001B
check_loop2:
mov a, @r0
add a, r1
jnz fail2
inc r1
dec r0
mov a, #01000000B
add a, r0
jnz check_loop2
 
pass2: PASS
 
fail2: FAIL
/verif/black_box/addc/ind_rr/test.asm
0,0 → 1,99
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-03-26 22:33:30 arniml Exp $
;;
;; Test ADDC A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testADDC MACRO val
jmp goon
ALIGN 040H
goon: inc r0
inc r1
mov a, #val
addc a, @r0
jnz fail
jnc fail
mov a, #val
addc a, @r0
dec a
jnz fail
jnc fail
clr c
;;
mov a, #val
addc a, @r1
jnz fail
jnc fail
mov a, #val
addc a, @r1
dec a
jnz fail
jnc fail
clr c
jmp pass
;;
fail: FAIL
pass:
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
;;
mov r0, #00FH
mov r1, #01FH
 
testADDC 002H
testADDC 003H
testADDC 005H
testADDC 009H
testADDC 011H
testADDC 021H
testADDC 041H
testADDC 081H
 
pass: PASS
/verif/black_box/addc/rr/test.asm
0,0 → 1,98
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ADDC A, Rr with carry, RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testADDC MACRO val,reg
mov a, #val
addc a, reg
jnz fail_p3
jnc fail_p3
mov a, #val
addc a, reg
jz fail_p3
jnc fail_p3
dec a
jnz fail_p3
clr c
jc fail_p3
ENDM
 
ORG 0
 
;; Start of test
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
check: testADDC 002H, r0
testADDC 003H, r1
testADDC 005H, r2
testADDC 009H, r3
testADDC 011H, r4
testADDC 021H, r5
testADDC 041H, r6
testADDC 081H, r7
ret
 
clr: mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
fail_p3:
FAIL
/verif/black_box/addc/a_data/test.asm
0,0 → 1,30
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test ADDC A, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jc fail
mov a, #000H
 
addc a, #055H
jc fail
addc a, #0ABH
jnz fail
jnc fail
 
addc a, #000H
jc fail
addc a, #0FFH
jnz fail
jnc fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/clr/a/test.asm
0,0 → 1,33
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CLR A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
jz fail
clr a
jnz fail
 
inc a
jb0 ok_1
jmp fail
 
ok_1: add a, #0FFH
jnz fail
 
add a, #010H
clr a
dec a
add a, #001H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/clr/c/test.asm
0,0 → 1,29
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CLR C.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jc fail
cpl c
jnc fail
clr c
jc fail
clr c
jc fail
 
mov a, #0FFH
add a, #001H
jnc fail
clr c
jc fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/clr/f0/test.asm
0,0 → 1,23
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CLR F0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jf0 fail
cpl f0
jf0 ok_1
jmp fail
 
ok_1: clr f0
jf0 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/clr/f1/test.asm
0,0 → 1,23
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CLR F1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jf1 fail
cpl f1
jf1 ok_1
jmp fail
 
ok_1: clr f1
jf1 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/dec/a/test.asm
0,0 → 1,32
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test DEC A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #001H
dec a
jnz fail
 
dec a
jb0 ok_0
jmp fail
 
ok_0: inc a
jnz fail
mov a, #10100101B
dec a
add a, #01011101B
dec a
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/dec/rr/test.asm
0,0 → 1,244
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test DECC Rr for RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #000H
mov r0, a
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, #0FFH
dec r0
jz fail_p3
mov a, r0
jz fail_p3
;;
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r1
jz fail_p3
mov a, r1
jz fail_p3
;;
mov a, r0
jz fail_p3
;;
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r2
jz fail_p3
mov a, r2
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
;;
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r3
jz fail_p3
mov a, r3
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
;;
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r4
jz fail_p3
mov a, r4
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
;;
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r5
jz fail_p3
mov a, r5
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
;;
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
 
mov a, #0FFH
dec r6
jz fail_p3
mov a, r6
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
;;
mov a, r7
jnz fail_p3
 
mov a, #0FFH
inc r7
jz fail_p3
mov a, r7
jz fail_p3
;;
mov a, r0
jz fail_p3
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
ret
 
 
fail_p3:
FAIL
/verif/black_box/jc/test.asm
0,0 → 1,20
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test JC instruction.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jc fail
mov a, #0FFH
add a, #001H
jc pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/rc/test.asm
0,0 → 1,107
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test RR(C) A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #080H
 
rr a
jb7 fail
jb6 ok1_1
jmp fail
 
ok1_1: rr a
jb6 fail
jb5 ok1_2
jmp fail
 
ok1_2: rr a
jb5 fail
jb4 ok1_3
jmp fail
 
ok1_3: rr a
jb4 fail
jb3 ok1_4
jmp fail
 
ok1_4: rr a
jb3 fail
jb2 ok1_5
jmp fail
 
ok1_5: rr a
jb2 fail
jb1 ok1_6
jmp fail
 
ok1_6: rr a
jb1 fail
jb0 ok1_7
jmp fail
 
ok1_7: rr a
jb0 fail
jb7 ok2
jmp fail
 
 
ok2: mov a, #07FH
cpl c
 
rrc a
jb7 ok2_1
jmp fail
ok2_1: jb6 fail
 
rrc a
jb6 ok2_2
jmp fail
ok2_2: jb5 fail
 
rrc a
jb5 ok2_3
jmp fail
ok2_3: jb4 fail
 
rrc a
jb4 ok2_4
jmp fail
ok2_4: jb3 fail
 
rrc a
jb3 ok2_5
jmp fail
ok2_5: jb2 fail
 
rrc a
jb2 ok2_6
jmp fail
ok2_6: jb1 fail
 
rrc a
jb1 ok2_7
jmp fail
ok2_7: jb0 fail
jnc fail
 
rrc a
jb0 ok2_8
jmp fail
ok2_8: jc fail
 
rrc a
jc ok2_9
jmp fail
ok2_9: jb7 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/xrl/rr/test.asm
0,0 → 1,157
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test XRL A, Rr for RB0 and RB1
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
 
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, #(1 << 0)
xrl a, r0
cpl a
jnz fail_p3
dec a
xrl a, r0
cpl a
add a, #(~(0FFH - (1 << 0)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 1)
xrl a, r1
cpl a
jnz fail_p3
dec a
xrl a, r1
cpl a
add a, #(~(0FFH - (1 << 1)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 2)
xrl a, r2
cpl a
jnz fail_p3
dec a
xrl a, r2
cpl a
add a, #(~(0FFH - (1 << 2)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 3)
xrl a, r3
cpl a
jnz fail_p3
dec a
xrl a, r3
cpl a
add a, #(~(0FFH - (1 << 3)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 4)
xrl a, r4
cpl a
jnz fail_p3
dec a
xrl a, r4
cpl a
add a, #(~(0FFH - (1 << 4)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 5)
xrl a, r5
cpl a
jnz fail_p3
dec a
xrl a, r5
cpl a
add a, #(~(0FFH - (1 << 5)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 6)
xrl a, r6
cpl a
jnz fail_p3
dec a
xrl a, r6
cpl a
add a, #(~(0FFH - (1 << 6)) + 1) & 0FFH
jnz fail_p3
 
mov a, #(1 << 7)
xrl a, r7
cpl a
jnz fail_p3
dec a
xrl a, r7
cpl a
add a, #(~(0FFH - (1 << 7)) + 1) & 0FFH
jnz fail_p3
 
ret
 
fail_p3:
FAIL
/verif/black_box/xrl/a_data/test.asm
0,0 → 1,32
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test XRL A, data.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
clr a
xrl a, #0FFH
jz fail
xrl a, #0FFH
jnz fail
 
clr a
xrl a, #055H
add a, #0ABH
jnz fail
 
clr a
xrl a, #023H
xrl a, #0A9H
add a, #076H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/xrl/ind_rr/test.asm
0,0 → 1,92
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test XRL A, @ Rr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
testR0R1 MACRO pos
inc r0
inc r1
mov a, #(1 << pos)
cpl a
xrl a, @r0
jnz fail
clr a
xrl a, @r0
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
mov a, #(1 << pos)
cpl a
xrl a, @r1
jnz fail
clr a
xrl a, @r1
add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
jnz fail
ENDM
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
jmp goon
 
ORG 256
;;
goon: mov r0, #00FH
mov r1, #01FH
testR0R1 0
testR0R1 1
testR0R1 2
testR0R1 3
testR0R1 4
testR0R1 5
testR0R1 6
testR0R1 7
 
pass: PASS
 
fail: FAIL
/verif/black_box/rl/test.asm
0,0 → 1,108
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test RL(C) A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #001H
 
rl a
jb0 fail
jb1 ok1_1
jmp fail
 
ok1_1: rl a
jb1 fail
jb2 ok1_2
jmp fail
 
ok1_2: rl a
jb2 fail
jb3 ok1_3
jmp fail
 
ok1_3: rl a
jb3 fail
jb4 ok1_4
jmp fail
 
ok1_4: rl a
jb4 fail
jb5 ok1_5
jmp fail
 
ok1_5: rl a
jb5 fail
jb6 ok1_6
jmp fail
 
ok1_6: rl a
jb6 fail
jb7 ok1_7
jmp fail
 
ok1_7: rl a
jb7 fail
jb0 ok2
jmp fail
 
 
ok2: mov a, #0FEH
cpl c
 
rlc a
jb0 ok2_1
jmp fail
ok2_1: jb1 fail
 
rlc a
jb1 ok2_2
jmp fail
ok2_2: jb2 fail
 
rlc a
jb2 ok2_3
jmp fail
ok2_3: jb3 fail
 
rlc a
jb3 ok2_4
jmp fail
ok2_4: jb4 fail
 
rlc a
jb4 ok2_5
jmp fail
ok2_5: jb5 fail
 
rlc a
jb5 ok2_6
jmp fail
ok2_6: jb6 fail
 
rlc a
jb6 ok2_7
jmp fail
ok2_7: jb7 fail
jnc fail
 
rlc a
jb7 ok2_8
jmp fail
ok2_8: jc fail
 
rlc a
jc ok2_9
jmp fail
ok2_9: jb0 fail
 
 
pass: PASS
 
fail: FAIL
/verif/black_box/movp/test.asm
0,0 → 1,67
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test MOVP A, @ A and MOVP3 A, @ A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
table MACRO data
DB data & 0FFH
ENDM
 
ORG 0
 
;; Start of test
mov r1, #008H
 
loop: mov a, r1
dec a
call fetch_table1
mov r0, a
 
mov a, r1
dec a
call fetch_table3
 
add a, r0
cpl a
jnz fail
 
djnz r1, loop
 
 
pass: PASS
 
fail: FAIL
 
 
ORG 0100H
 
db 0AFH
db 033H
db 0C0H
db 012H
db 055H
db 061H
db 02BH
db 0F4H
fetch_table1:
movp a, @a
ret
fetch_table3:
movp3 a, @a
ret
 
 
ORG 0300H
 
db 050H
db 0CCH
db 03FH
db 0EDH
db 0AAH
db 09EH
db 0D4H
db 00BH
/verif/black_box/jmp/test.asm
0,0 → 1,11
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jmp pass
FAIL
 
pass: PASS
/verif/black_box/add/rr/test.asm
0,0 → 1,106
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test ADD A, Rr without carry, RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
;; fill RB0
call fill
 
;; check RB0
sel rb0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
 
;; check RB1
sel rb1
call check
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
fill: mov a, #0FEH
mov r0, a
mov a, #0FDH
mov r1, a
mov a, #0FBH
mov r2, a
mov a, #0F7H
mov r3, a
mov a, #0EFH
mov r4, a
mov a, #0DFH
mov r5, a
mov a, #0BFH
mov r6, a
mov a, #07FH
mov r7, a
ret
 
 
check: mov a, #002H
add a, r0
jnz fail_p3
 
mov a, #003H
add a, r1
jnz fail_p3
 
mov a, #005H
add a, r2
jnz fail_p3
 
mov a, #009H
add a, r3
jnz fail_p3
 
mov a, #011H
add a, r4
jnz fail_p3
 
mov a, #021H
add a, r5
jnz fail_p3
 
mov a, #041H
add a, r6
jnz fail_p3
 
mov a, #081H
add a, r7
jnz fail_p3
 
ret
 
 
fail_p3:
FAIL
/verif/black_box/add/a_data/test.asm
0,0 → 1,82
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test ADD A, data without carry.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
 
add a, #055H
jz fail
;; exact check for 055H
jb0 ok_1
jmp fail
 
ok_1: jb1 fail
 
jb2 ok_2
jmp fail
 
ok_2: jb3 fail
 
jb4 ok_4
jmp fail
 
ok_4: jb5 fail
 
jb6 ok_6
jmp fail
 
ok_6: jb7 fail
 
add a, #0AAH
jz fail
add a, #001H
jnz fail
 
add a, #011111110B
jb0 fail
 
add a, #011111111B
jb1 fail
jb0 ko_1
jmp fail
 
ko_1: add a, #011111110B
jb2 fail
jb1 ko_2
jmp fail
 
ko_2: add a, #011111100B
jb3 fail
jb2 ko_3
jmp fail
 
ko_3: add a, #011111000B
jb4 fail
jb3 ko_4
jmp fail
 
ko_4: add a, #011110000B
jb5 fail
jb4 ko_5
jmp fail
 
ko_5: add a, #011100000B
jb6 fail
jb5 ko_6
jmp fail
 
ko_6: add a, #011000000B
jb7 fail
jb6 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/add/ind_rr/test.asm
0,0 → 1,129
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test ADD A, @ Rr without carry.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r0, #010H
mov r1, #020H
mov a, #0FEH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FDH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0FBH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0F7H
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0EFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0DFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #0BFH
mov @r0, a
mov @r1, a
inc r0
inc r1
mov a, #07FH
mov @r0, a
mov @r1, a
 
;;
mov r0, #010H
mov r1, #020H
mov a, #002H
add a, @r0
jnz fail
mov a, #002H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #003H
add a, @r0
jnz fail
mov a, #003H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #005H
add a, @r0
jnz fail
mov a, #005H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #009H
add a, @r0
jnz fail
mov a, #009H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #011H
add a, @r0
jnz fail
mov a, #011H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #021H
add a, @r0
jnz fail
mov a, #021H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #041H
add a, @r0
jnz fail
mov a, #041H
add a, @r1
jnz fail
 
inc r0
inc r1
mov a, #081H
add a, @r0
jnz fail
mov a, #081H
add a, @r1
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/tx/t0/ent0_clk/test.asm
0,0 → 1,15
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Execute ENT0 CLK.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
ent0 clk
 
pass: PASS
/verif/black_box/tx/t0/t0/test.asm
0,0 → 1,21
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test J(N)T0 addr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jnt0 fail
anl P1, #0FEH
jt0 fail
orl P1, #001H
jt0 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/tx/t1/test.asm
0,0 → 1,21
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test J(N)T1 addr.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jnt1 fail
anl P1, #0FDH
jt1 fail
orl P1, #002H
jt1 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/jbb/jbb_all_0/test.asm
0,0 → 1,20
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
jb0 fail
jb1 fail
jb2 fail
jb3 fail
jb4 fail
jb5 fail
jb6 fail
jb7 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/jbb/jbb_all_1/test.asm
0,0 → 1,34
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
jb0 ok_0
jmp fail
 
ok_0: jb1 ok_1
jmp fail
 
ok_1: jb2 ok_2
jmp fail
 
ok_2: jb3 ok_3
jmp fail
ok_3: jb4 ok_4
jmp fail
 
ok_4: jb5 ok_5
jmp fail
 
ok_5: jb6 ok_6
jmp fail
 
ok_6: jb7 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/jbb/jbb_55/test.asm
0,0 → 1,36
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test the JBb instruction on 055H.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #055H
jb0 ok_0
jmp fail
 
ok_0: jb1 fail
 
jb2 ok_2
jmp fail
 
ok_2: jb3 fail
 
jb4 ok_4
jmp fail
 
ok_4: jb5 fail
 
jb6 ok_6
jmp fail
 
ok_6: jb7 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/jbb/jbb_aa/test.asm
0,0 → 1,35
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test the JBb instruction on 0AAH.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0AAH
jb0 fail
 
jb1 ok_1
jmp fail
 
ok_1: jb2 fail
 
jb3 ok_3
jmp fail
 
ok_3: jb4 fail
 
jb5 ok_5
jmp fail
 
ok_5: jb6 fail
 
jb7 pass
 
fail: FAIL
 
pass: PASS
/verif/black_box/djnz/test.asm
0,0 → 1,54
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test DJNZ Rr, addr
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov r0, #003H
mov a, #000H
djnz r0, r0_2
jmp fail
 
r0_2: djnz r0, r0_1
jmp fail
r0_1: mov a, #0FFH
djnz r0, fail
 
mov r1, #000H
mov r2, #000H
r1_loop:
mov a, r2
add a, r1
jnz fail
inc r2
djnz r1, r1_loop
 
mov a, r1
jnz fail
 
 
mov a, #002H
mov r3, a
mov r4, a
mov r5, a
djnz r5, ok_r5
jmp fail
ok_r5: djnz r4, ok_r4
jmp fail
ok_r4: djnz r3, ok_r3
jmp fail
ok_r3: djnz r3, fail
djnz r4, fail
djnz r5, fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/jmpp/test.asm
0,0 → 1,490
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test JMPP.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
table MACRO data
DB data & 0FFH
ENDM
 
ORG 0
 
;; Start of test
mov a, #000H
jmp table1
 
fail: FAIL
 
pass: PASS
 
 
;; *******************************************************************
ORG 0100H
;;
table t1_e00
table t1_e01
table t1_e02
table t1_e03
table t1_e04
table t1_e05
table t1_e06
table t1_e07
table t1_e08
table t1_e09
table t1_e0a
table t1_e0b
table t1_e0c
table t1_e0d
table t1_e0e
table t1_e0f
table t1_e10
table t1_e11
table t1_e12
table t1_e13
table t1_e14
table t1_e15
table t1_e16
table t1_e17
table t1_e18
table t1_e19
table t1_e1a
table t1_e1b
table t1_e1c
table t1_e1d
table t1_e1e
table t1_e1f
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
;;
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
table t1_e01
 
jmp fail
table1: jmpp @a
jmp fail
t1_e00: mov a, #007H
jmp table2
;;
t1_e01: jmp fail
jmp fail
;;
t1_e02: mov a, #005H
jmp table2
;;
t1_e03: jmp fail
jmp fail
;;
t1_e04: mov a, #003H
jmp table2
;;
t1_e05: jmp fail
jmp fail
;;
t1_e06: mov a, #001H
jmp table2
;;
t1_e07: jmp fail
jmp fail
;;
t1_e08: jmp fail
jmp fail
;;
t1_e09: jmp fail
jmp fail
;;
t1_e0a: jmp fail
jmp fail
;;
t1_e0b: jmp fail
jmp fail
;;
t1_e0c: jmp fail
jmp fail
;;
t1_e0d: jmp fail
jmp fail
;;
t1_e0e: jmp fail
jmp fail
;;
t1_e0f: jmp fail
jmp fail
;;
t1_e10: mov a, #018H
jmp table2
;;
t1_e11: jmp fail
jmp fail
;;
t1_e12: jmp fail
jmp fail
;;
t1_e13: jmp fail
jmp fail
;;
t1_e14: jmp fail
jmp fail
;;
t1_e15: jmp fail
jmp fail
;;
t1_e16: jmp fail
jmp fail
;;
t1_e17: jmp fail
jmp fail
;;
t1_e18: jmp fail
jmp fail
;;
t1_e19: jmp fail
jmp fail
;;
t1_e1a: jmp fail
jmp fail
;;
t1_e1b: jmp fail
jmp fail
;;
t1_e1c: jmp fail
jmp fail
;;
t1_e1d: jmp fail
jmp fail
;;
t1_e1e: jmp fail
jmp fail
;;
t1_e1f: jmp pass
jmp fail
 
 
;; *******************************************************************
ORG 512
;;
table t2_e00
table t2_e01
table t2_e02
table t2_e03
table t2_e04
table t2_e05
table t2_e06
table t2_e07
table t2_e08
table t2_e09
table t2_e0a
table t2_e0b
table t2_e0c
table t2_e0d
table t2_e0e
table t2_e0f
table t2_e10
table t2_e11
table t2_e12
table t2_e13
table t2_e14
table t2_e15
table t2_e16
table t2_e17
table t2_e18
table t2_e19
table t2_e1a
table t2_e1b
table t2_e1c
table t2_e1d
table t2_e1e
table t2_e1f
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
;;
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
table t2_e01
 
jmp fail
table2: jmpp @a
jmp fail
t2_e00: jmp fail
jmp fail
;;
t2_e01: mov a, #010H
jmp table1
;;
t2_e02: jmp fail
jmp fail
;;
t2_e03: mov a, #006H
jmp table1
;;
t2_e04: jmp fail
jmp fail
;;
t2_e05: mov a, #004H
jmp table1
;;
t2_e06: jmp fail
jmp fail
;;
t2_e07: mov a, #002H
jmp table1
;;
t2_e08: jmp fail
jmp fail
;;
t2_e09: jmp fail
jmp fail
;;
t2_e0a: jmp fail
jmp fail
;;
t2_e0b: jmp fail
jmp fail
;;
t2_e0c: jmp fail
jmp fail
;;
t2_e0d: jmp fail
jmp fail
;;
t2_e0e: jmp fail
jmp fail
;;
t2_e0f: jmp fail
jmp fail
;;
t2_e10: jmp fail
jmp fail
;;
t2_e11: jmp fail
jmp fail
;;
t2_e12: jmp fail
jmp fail
;;
t2_e13: jmp fail
jmp fail
;;
t2_e14: jmp fail
jmp fail
;;
t2_e15: jmp fail
jmp fail
;;
t2_e16: jmp fail
jmp fail
;;
t2_e17: jmp fail
jmp fail
;;
t2_e18: mov a, #01FH
jmp table1
;;
t2_e19: jmp fail
jmp fail
;;
t2_e1a: jmp fail
jmp fail
;;
t2_e1b: jmp fail
jmp fail
;;
t2_e1c: jmp fail
jmp fail
;;
t2_e1d: jmp fail
jmp fail
;;
t2_e1e: jmp fail
jmp fail
;;
t2_e1f: jmp fail
jmp fail
/verif/black_box/in/test.asm
0,0 → 1,29
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test IN A, Pp.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #055H
outl p1, a
mov a, #0AAH
outl p2, a
 
clr a
in a, p1
add a, #0ABH
jnz fail
 
in a, p2
add a, #056H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/inc/a/test.asm
0,0 → 1,34
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test INC A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #000H
inc a
add a, #0FFH
jnz fail
 
inc a
jb0 ok_0
jmp fail
 
ok_0: mov a, #0FFH
inc a
jnz fail
 
mov a, #010100101B
inc a
add a, #001011001B
inc a
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/inc/rr/test.asm
0,0 → 1,243
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test INC Rr for RB0 and RB1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill RB0
call fill
 
;; check RB0
call check
 
;; fill RB1
sel rb1
call fill
sel rb0
 
;; clear RB0
call clr_rb0
 
;; check RB1
sel rb1
call check
 
;; check RB0 for all 0
mov r0, #000H
mov r1, #008H
chk0_loop:
mov a, @r0
jnz fail
inc r0
djnz r1, chk0_loop
 
 
pass: PASS
 
fail: FAIL
 
 
ORG 0300H
fill: mov a, #0FFH
mov r0, a
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
ret
 
clr_rb0:
mov r0, #007H
clr a
clr_loop:
mov @r0, a
djnz r0, clr_loop
ret
 
check: mov a, #000H
inc r0
jnz fail_p3
mov a, r0
jnz fail_p3
;;
mov a, r1
jz fail_p3
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r1
jnz fail_p3
mov a, r1
jnz fail_p3
;;
mov a, r0
jnz fail_p3
;;
mov a, r2
jz fail_p3
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r2
jnz fail_p3
mov a, r2
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
;;
mov a, r3
jz fail_p3
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r3
jnz fail_p3
mov a, r3
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
;;
mov a, r4
jz fail_p3
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r4
jnz fail_p3
mov a, r4
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
;;
mov a, r5
jz fail_p3
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r5
jnz fail_p3
mov a, r5
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
;;
mov a, r6
jz fail_p3
mov a, r7
jz fail_p3
 
mov a, #000H
inc r6
jnz fail_p3
mov a, r6
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
;;
mov a, r7
jz fail_p3
 
mov a, #000H
inc r7
jnz fail_p3
mov a, r7
jnz fail_p3
;;
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
ret
 
fail_p3:
FAIL
/verif/black_box/inc/ind_rr/test.asm
0,0 → 1,345
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:16 arniml Exp $
;;
;; Test INC @ Rr for RB0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
 
mov r0, #001H
mov a, #000H
inc @r0
jnz fail
mov a, r1
jnz fail
;;
mov a, r2
jz fail
mov a, r3
jz fail
mov a, r4
jz fail
mov a, r5
jz fail
mov a, r6
jz fail
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r2
jnz fail
;;
mov a, r1
jnz fail
;;
mov a, r3
jz fail
mov a, r4
jz fail
mov a, r5
jz fail
mov a, r6
jz fail
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r3
jnz fail
;;
mov a, r1
jnz fail
mov a, r2
jnz fail
;;
mov a, r4
jz fail
mov a, r5
jz fail
mov a, r6
jz fail
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r4
jnz fail
;;
mov a, r1
jnz fail
mov a, r2
jnz fail
mov a, r3
jnz fail
;;
mov a, r5
jz fail
mov a, r6
jz fail
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r5
jnz fail
;;
mov a, r1
jnz fail
mov a, r2
jnz fail
mov a, r3
jnz fail
mov a, r4
jnz fail
;;
mov a, r6
jz fail
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r6
jnz fail
;;
mov a, r1
jnz fail
mov a, r2
jnz fail
mov a, r3
jnz fail
mov a, r4
jnz fail
mov a, r5
jnz fail
;;
mov a, r7
jz fail
 
mov a, #000H
inc r0
jnz fail
inc @r0
jnz fail
mov a, r7
jnz fail
;;
mov a, r1
jnz fail
mov a, r2
jnz fail
mov a, r3
jnz fail
mov a, r4
jnz fail
mov a, r5
jnz fail
mov a, r6
jnz fail
 
jmp test_r1
 
fail: FAIL
 
;;
ALIGN 256
;;
 
test_r1:
mov a, #0FFH
mov r0, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
 
mov r1, #000H
mov a, #000H
inc @r1
jnz fail2
mov a, r0
jnz fail2
;;
mov a, r2
jz fail2
mov a, r3
jz fail2
mov a, r4
jz fail2
mov a, r5
jz fail2
mov a, r6
jz fail2
mov a, r7
jz fail2
 
mov a, #000H
inc r1
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r2
jnz fail2
;;
mov a, r0
jnz fail2
;;
mov a, r3
jz fail2
mov a, r4
jz fail2
mov a, r5
jz fail2
mov a, r6
jz fail2
mov a, r7
jz fail2
 
mov a, #000H
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r3
jnz fail2
;;
mov a, r0
jnz fail2
mov a, r2
jnz fail2
;;
mov a, r4
jz fail2
mov a, r5
jz fail2
mov a, r6
jz fail2
mov a, r7
jz fail2
 
mov a, #000H
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r4
jnz fail2
;;
mov a, r0
jnz fail2
mov a, r2
jnz fail2
mov a, r3
jnz fail2
;;
mov a, r5
jz fail2
mov a, r6
jz fail2
mov a, r7
jz fail2
 
mov a, #000H
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r5
jnz fail2
;;
mov a, r0
jnz fail2
mov a, r2
jnz fail2
mov a, r3
jnz fail2
mov a, r4
jnz fail2
;;
mov a, r6
jz fail2
mov a, r7
jz fail2
 
mov a, #000H
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r6
jnz fail2
;;
mov a, r0
jnz fail2
mov a, r2
jnz fail2
mov a, r3
jnz fail2
mov a, r4
jnz fail2
mov a, r5
jnz fail2
;;
mov a, r7
jz fail2
 
mov a, #000H
inc r1
jnz fail2
inc @r1
jnz fail2
mov a, r7
jnz fail2
;;
mov a, r0
jnz fail2
mov a, r2
jnz fail2
mov a, r3
jnz fail2
mov a, r4
jnz fail2
mov a, r5
jnz fail2
mov a, r6
jnz fail2
 
pass: PASS
 
fail2: FAIL
/verif/black_box/jnc/test.asm
0,0 → 1,22
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test JNC instruction.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jnc ok_1
jmp fail
 
ok_1: mov a, #0FFH
add a, #001H
jnc fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/swap/test.asm
0,0 → 1,25
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test SWAP A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #05AH
swap a
add a, #05BH
jnz fail
 
mov a, #0C8H
swap a
add a, #074H
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/cpl/a/test.asm
0,0 → 1,28
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CPL A.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
mov a, #0FFH
cpl a
jnz fail
 
cpl a
inc a
jnz fail
 
mov a, #055H
cpl a
add a, #01010110B
jnz fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/cpl/c/test.asm
0,0 → 1,31
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CPL C.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jc fail
 
cpl c
jnc fail
 
mov a, #0FEH
add a, #001H
jc fail
cpl c
jnc fail
 
add a, #001H
jnc fail
cpl c
jc fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/cpl/f0/test.asm
0,0 → 1,23
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CPL F0.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jf0 fail
cpl f0
jf0 ok_1
jmp fail
 
ok_1: cpl f0
jf0 fail
 
pass: PASS
 
fail: FAIL
/verif/black_box/cpl/f1/test.asm
0,0 → 1,23
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
;;
;; Test CPL F1.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
jf1 fail
cpl f1
jf1 ok_1
jmp fail
 
ok_1: cpl f1
jf1 fail
 
pass: PASS
 
fail: FAIL
/verif/include/Makefile.core
0,0 → 1,20
 
.PHONY: all
all: t48_rom.hex t48_ext_rom.hex
 
$(MODULE).p: $(MODULE).asm
asl -i $(VERIF_DIR)/include -L $(MODULE).asm
 
t48_rom.hex: $(MODULE).p
p2hex -r 0-2047 $(MODULE).p t48_rom.hex
 
t48_ext_rom.hex: $(MODULE).p
p2hex -a -r 2048-4095 $(MODULE).p t48_ext_rom.hex
 
.PHONY: simu
simu: all
cp t48_rom.hex t48_ext_rom.hex $(SIM_DIR)
 
.PHONY: clean
clean:
rm -f *.p *~ *.hex *.lst
/verif/include/Makefile.cell
0,0 → 1,4
 
MODULE=test
 
include $(VERIF_DIR)/include/Makefile.core
/verif/include/cpu.inc
0,0 → 1,2
 
CPU 8048
/verif/include/pass_fail.inc
0,0 → 1,12
 
FAIL MACRO
mov a, #0AAH
mov a, #055H
mov a, #000H
ENDM
 
PASS MACRO
mov a, #0AAH
mov a, #055H
mov a, #001H
ENDM
/verif/gp_sw/toggle/test.asm
0,0 → 1,23
;; *******************************************************************
;; $Id: test.asm,v 1.1 2004-05-02 19:15:27 arniml Exp $
;;
;; Toggle P1[0]
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
mov a, #0FFH
 
loop: outl p1, a
xrl a, #001H
 
mov r1, #000H
wait1:
mov r0, #000H
wait2: djnz r0, wait2
djnz r1, wait1
 
jmp loop
/run_regression.pl
0,0 → 1,136
#!/usr/bin/perl -w
#
# ############################################################################
#
# run_regression.pl
#
# $Id: run_regression.pl,v 1.8 2004-09-12 00:30:53 arniml Exp $
#
# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
#
# All rights reserved
#
# ############################################################################
#
# Purpose:
# ========
#
# Runs regression suite over all testcells found in $VERIF_DIR.
#
# run_regression.pl [-d]
# -d : Perform a dump compare on each test with the i8039 simulator.
#
# The testcells are identified by searching for the .asm file(s).
# Each testcell is built by calling the central Makefile.cell.
# The resulting hex-file is then copied to $SIM_DIR where the VHDL simulator
# is started.
#
 
 
use strict;
 
use Getopt::Std;
 
 
sub print_usage {
print <<EOU;
Runs regression tests in \$VERIF_DIR.
Usage:
run_regression.pl [-d]
-d : Perform a dump compare on each test with the i8039 simulator.
EOU
}
 
 
my %options;
my (@asm_files, $asm_file);
my (%cells, $cell, $cell_dir, $tag);
my $pwd;
my $dump_compare = 0;
my $dump_compare_cell = 0;
 
 
##############################################################################
# Commands to call the different VHDL simulators.
#
# GHDL
my $ghdl_simulator = './tb_behav_c0 --assert-level=error';
my $ghdl_simulator_vcd = $ghdl_simulator.' --vcd=temp.vcd';
#
# Choose simulator:
my $vhdl_simulator = $ghdl_simulator;
my $vhdl_simulator_vcd = $ghdl_simulator_vcd;
#
##############################################################################
 
 
# process command line options
if (!getopts('d', \%options)) {
print_usage();
exit(1);
}
 
if (exists($options{'d'})) {
$dump_compare = 1;
}
 
$pwd = `pwd`;
chomp($pwd);
 
 
@asm_files = `find \$VERIF_DIR/black_box -name '*.asm'`;
push(@asm_files, `find \$VERIF_DIR/white_box -name '*.asm'`);
 
 
foreach $asm_file (@asm_files) {
chomp($asm_file);
# strip off assembler file names
$asm_file =~ s/\/[^\/]+\.asm//;
# strip off verification directory
$asm_file =~ s/$ENV{'VERIF_DIR'}\///;
$cells{$asm_file} = 1;
}
 
while (($cell, $tag) = each(%cells)) {
$cell_dir = "$ENV{'VERIF_DIR'}/$cell";
 
if (chdir($cell_dir)) {
print("Processing $cell\n");
 
$dump_compare_cell = -e 'no_dump_compare' ? 0 : $dump_compare;
 
system('sh', '-c', 'rm -f $SIM_DIR/t48_rom.hex');
system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell clean');
system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell simu clean');
if ($? == 0) {
chdir($ENV{'SIM_DIR'});
system('sh', '-c', 'ls -l t48_rom.hex');
system('sh', '-c', $dump_compare_cell > 0 ? $vhdl_simulator_vcd : $vhdl_simulator);
 
if ($dump_compare_cell) {
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump');
system('sh', '-c',
'vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump');
system('sh', '-c', 'i8039 -f t48_rom.hex -x t48_ext_rom.hex -d > dump');
system('sh', '-c', 'egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump');
system('sh', '-c', 'diff -b -q sim.dump vhdl.dump');
print("Dump Compare: ");
if ($? == 0) {
print("PASS\n");
} else {
print("FAIL\n");
}
system('sh', '-c', 'rm -f dump sim.dump vhdl.dump temp.vcd');
} elsif ($dump_compare) {
print("Dump Compare: Excluded\n");
}
 
} else {
print("Error: Cannot make cell $cell!\n");
}
} else {
print("Error: Cannot change to directory $cell_dir!\n");
}
}
 
chdir($pwd);
run_regression.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: i8039emu/i8039.c =================================================================== --- i8039emu/i8039.c (nonexistent) +++ i8039emu/i8039.c (revision 292) @@ -0,0 +1,841 @@ +/**************************************************************************** + * Intel 8039 Portable Emulator * + * * + * Copyright (C) 1997 by Mirko Buffoni * + * Based on the original work (C) 1997 by Dan Boris, an 8048 emulator * + * You are not allowed to distribute this software commercially * + * Please, notify me, if you make any changes to this file * + * * + * Adapted for the T48 uController project, 2004 by Arnim Laeuger * + * See http://www.opencores.org/projects.cgi/web/t48/overview * + * * + * $Id: i8039.c,v 1.7 2004-07-04 12:06:53 arniml Exp $ + * * + * **** Change Log **** * + * * + * TLP (19-Jun-2001) * + * - Changed Ports 1 and 2 to quasi bidirectional output latched ports * + * - Added the Port 1 & 2 output latch data to the debugger window * + * TLP (02-Jan-2002) * + * - External IRQs no longer go pending (sampled as a level state) * + * - Timer IRQs do not go pending if Timer interrupts are disabled * + * - Timer IRQs made pending, were incorrectly being cleared if the * + * external interrupt was being serviced * + * - External interrupts now take precedence when simultaneous * + * internal and external interrupt requests occur * + * - 'DIS TCNTI' now removes pending timer IRQs * + * - Nested IRQs of any sort are no longer allowed * + * - T_flag was not being set in the right place of execution, which * + * could have lead to it being incorrectly set after being cleared * + * - Counter overflows now also set the T_flag * + * - Added the Timer/Counter register to the debugger window * + * TLP (09-Jan-2002) * + * - Changed Interrupt system to instant servicing * + * - The Timer and Counter can no longer be 'on' simultaneously * + * - Added Save State * + * TLP (15-Feb-2002) * + * - Corrected Positive signal edge sensing (used on the T1 input) * + ****************************************************************************/ + + +#include +#include +#include + +#include "i8039.h" + + +/*** Cycle times for the jump on condition instructions, are unusual. + Condition is tested during the first cycle, so if condition is not + met, second address fetch cycle may not really be taken. For now we + just use the cycle counts as listed in the i8048 user manual. +***/ + +#if 0 +#define ADJUST_CYCLES { inst_cycles -= 1; } /* Possible real cycles setting */ +#else +#define ADJUST_CYCLES { } /* User Manual cycles setting */ +#endif + + + +/* HJB 01/05/99 changed to positive values to use pending_irq as a flag */ +#define I8039_NO_INT 0 /* No Interrupts pending or executing */ +#define I8039_EXTERNAL_INT 1 /* Execute a normal external interrupt */ +#define I8039_TIMCNT_INT 2 /* Execute a Timer/Counter interrupt */ + + +/* Layout of the registers in the debugger */ +static UINT8 i8039_reg_layout[] = { + I8039_PC, I8039_SP, I8039_PSW, I8039_A, I8039_TC, I8039_P1, I8039_P2, -1, + I8039_R0, I8039_R1, I8039_R2, I8039_R3, I8039_R4, I8039_R5, I8039_R6, I8039_R7, 0 +}; + +/* Layout of the debugger windows x,y,w,h */ +static UINT8 i8039_win_layout[] = { + 0, 0,80, 2, /* register window (top rows) */ + 0, 3,24,19, /* disassembler window (left colums) */ + 25, 3,55, 9, /* memory #1 window (right, upper middle) */ + 25,13,55, 9, /* memory #2 window (right, lower middle) */ + 0,23,80, 1, /* command line window (bottom rows) */ +}; + + +static int Ext_IRQ(void); +static int Timer_IRQ(void); + +#define M_RDMEM(A) I8039_RDMEM(A) +#define M_RDOP(A) I8039_RDOP(A) +#define M_RDOP_ARG(A) I8039_RDOP_ARG(A) +#define M_IN(A) I8039_In(A) +#define M_OUT(A,V) I8039_Out(A,V) + +#define port_r(A) I8039_In(I8039_p0 + A) +#define port_w(A,V) I8039_Out(I8039_p0 + A,V) +#define test_r(A) I8039_In(I8039_t0 + A) +#define test_w(A,V) I8039_Out(I8039_t0 + A,V) +#define bus_r() I8039_In(I8039_bus) +#define bus_w(V) I8039_Out(I8039_bus,V) + +#define C_FLAG 0x80 +#define A_FLAG 0x40 +#define F_FLAG 0x20 +#define B_FLAG 0x10 + +typedef struct +{ + PAIR PREVPC; /* previous program counter */ + PAIR PC; /* program counter */ + UINT8 A, SP, PSW; + UINT8 RAM[256]; + UINT8 bus, f1; /* Bus data, and flag1 */ + UINT8 P1, P2; /* Internal Port 1 and 2 latched outputs */ + + UINT8 pending_irq, irq_executing, masterClock, regPtr; + UINT8 t_flag, timer, timerON, countON, xirq_en, tirq_en; + UINT16 A11, A11ff; + UINT8 irq_state, irq_extra_cycles; + int (*irq_callback)(int irqline); +} I8039_Regs; + +static I8039_Regs R; +int i8039_ICount; +int inst_cycles; +static UINT8 Old_T1; + +/* The opcode table now is a combination of cycle counts and function pointers */ +typedef struct { + unsigned cycles; + void (*function) (void); +} s_opcode; + +#define POSITIVE_EDGE_T1 (( (int)(T1-Old_T1) > 0) ? 1 : 0) +#define NEGATIVE_EDGE_T1 (( (int)(Old_T1-T1) > 0) ? 1 : 0) + +#define M_Cy ((R.PSW & C_FLAG) >> 7) +#define M_Cn (!M_Cy) +#define M_Ay ((R.PSW & A_FLAG)) +#define M_An (!M_Ay) +#define M_F0y ((R.PSW & F_FLAG)) +#define M_F0n (!M_F0y) +#define M_By ((R.PSW & B_FLAG)) +#define M_Bn (!M_By) + +#define intRAM R.RAM +#define regPTR R.regPtr + +#define R0 intRAM[regPTR ] +#define R1 intRAM[regPTR+1] +#define R2 intRAM[regPTR+2] +#define R3 intRAM[regPTR+3] +#define R4 intRAM[regPTR+4] +#define R5 intRAM[regPTR+5] +#define R6 intRAM[regPTR+6] +#define R7 intRAM[regPTR+7] + + +INLINE void CLR (UINT8 flag) { R.PSW &= ~flag; } +INLINE void SET (UINT8 flag) { R.PSW |= flag; } + + +/* Get next opcode argument and increment program counter */ +INLINE unsigned M_RDMEM_OPCODE (void) +{ + unsigned retval; + retval=M_RDOP_ARG(R.PC.w.l); + R.PC.w.l++; + return retval; +} + +INLINE void push(UINT8 d) +{ + intRAM[8+R.SP++] = d; + R.SP = R.SP & 0x0f; + R.PSW = R.PSW & 0xf8; + R.PSW = R.PSW | (R.SP >> 1); +} + +INLINE UINT8 pull(void) { + R.SP = (R.SP + 15) & 0x0f; /* if (--R.SP < 0) R.SP = 15; */ + R.PSW = R.PSW & 0xf8; + R.PSW = R.PSW | (R.SP >> 1); + /* regPTR = ((M_By) ? 24 : 0); regPTR should not change */ + return intRAM[8+R.SP]; +} + +INLINE void daa_a(void) +{ + if ((R.A & 0x0f) > 0x09 || (R.PSW & A_FLAG)) + R.A += 0x06; + if ((R.A & 0xf0) > 0x90 || (R.PSW & C_FLAG)) + { + R.A += 0x60; + SET(C_FLAG); + } else CLR(C_FLAG); +} + +INLINE void M_ADD(UINT8 dat) +{ + UINT16 temp; + + CLR(C_FLAG | A_FLAG); + if ((R.A & 0xf) + (dat & 0xf) > 0xf) SET(A_FLAG); + temp = R.A + dat; + if (temp > 0xff) SET(C_FLAG); + R.A = temp & 0xff; +} + +INLINE void M_ADDC(UINT8 dat) +{ + UINT16 temp; + + CLR(A_FLAG); + if ((R.A & 0xf) + (dat & 0xf) + M_Cy > 0xf) SET(A_FLAG); + temp = R.A + dat + M_Cy; + CLR(C_FLAG); + if (temp > 0xff) SET(C_FLAG); + R.A = temp & 0xff; +} + +INLINE void M_CALL(UINT16 addr) +{ + push(R.PC.b.l); + push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); + R.PC.w.l = addr; + +} + +INLINE void M_XCHD(UINT8 addr) +{ + UINT8 dat = R.A & 0x0f; + R.A &= 0xf0; + R.A |= intRAM[addr] & 0x0f; + intRAM[addr] &= 0xf0; + intRAM[addr] |= dat; +} + + +INLINE void M_ILLEGAL(void) +{ + logerror("I8039: PC = %04x, Illegal opcode = %02x\n", R.PC.w.l-1, M_RDMEM(R.PC.w.l-1)); +} + +INLINE void M_UNDEFINED(void) +{ + logerror("I8039: PC = %04x, Unimplemented opcode = %02x\n", R.PC.w.l-1, M_RDMEM(R.PC.w.l-1)); +} + +#define INT_RAM_MASK 0xff + +static void illegal(void) { M_ILLEGAL(); } + +static void add_a_n(void) { M_ADD(M_RDMEM_OPCODE()); } +static void add_a_r0(void) { M_ADD(R0); } +static void add_a_r1(void) { M_ADD(R1); } +static void add_a_r2(void) { M_ADD(R2); } +static void add_a_r3(void) { M_ADD(R3); } +static void add_a_r4(void) { M_ADD(R4); } +static void add_a_r5(void) { M_ADD(R5); } +static void add_a_r6(void) { M_ADD(R6); } +static void add_a_r7(void) { M_ADD(R7); } +static void add_a_xr0(void) { M_ADD(intRAM[R0 & INT_RAM_MASK]); } +static void add_a_xr1(void) { M_ADD(intRAM[R1 & INT_RAM_MASK]); } +static void adc_a_n(void) { M_ADDC(M_RDMEM_OPCODE()); } +static void adc_a_r0(void) { M_ADDC(R0); } +static void adc_a_r1(void) { M_ADDC(R1); } +static void adc_a_r2(void) { M_ADDC(R2); } +static void adc_a_r3(void) { M_ADDC(R3); } +static void adc_a_r4(void) { M_ADDC(R4); } +static void adc_a_r5(void) { M_ADDC(R5); } +static void adc_a_r6(void) { M_ADDC(R6); } +static void adc_a_r7(void) { M_ADDC(R7); } +static void adc_a_xr0(void) { M_ADDC(intRAM[R0 & INT_RAM_MASK]); } +static void adc_a_xr1(void) { M_ADDC(intRAM[R1 & INT_RAM_MASK]); } +static void anl_a_n(void) { R.A &= M_RDMEM_OPCODE(); } +static void anl_a_r0(void) { R.A &= R0; } +static void anl_a_r1(void) { R.A &= R1; } +static void anl_a_r2(void) { R.A &= R2; } +static void anl_a_r3(void) { R.A &= R3; } +static void anl_a_r4(void) { R.A &= R4; } +static void anl_a_r5(void) { R.A &= R5; } +static void anl_a_r6(void) { R.A &= R6; } +static void anl_a_r7(void) { R.A &= R7; } +static void anl_a_xr0(void) { R.A &= intRAM[R0 & INT_RAM_MASK]; } +static void anl_a_xr1(void) { R.A &= intRAM[R1 & INT_RAM_MASK]; } +static void anl_bus_n(void) { bus_w( bus_r() & M_RDMEM_OPCODE() ); } +static void anl_p1_n(void) { R.P1 &= M_RDMEM_OPCODE(); port_w( 1, R.P1 ); } +static void anl_p2_n(void) { R.P2 &= M_RDMEM_OPCODE(); port_w( 2, R.P2 ); } +static void anld_p4_a(void) { port_w( 4, port_r(4) & M_RDMEM_OPCODE() ); } +static void anld_p5_a(void) { port_w( 5, port_r(5) & M_RDMEM_OPCODE() ); } +static void anld_p6_a(void) { port_w( 6, port_r(6) & M_RDMEM_OPCODE() ); } +static void anld_p7_a(void) { port_w( 7, port_r(7) & M_RDMEM_OPCODE() ); } +static void call(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | R.A11); } +static void call_1(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x100 | R.A11); } +static void call_2(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x200 | R.A11); } +static void call_3(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x300 | R.A11); } +static void call_4(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x400 | R.A11); } +static void call_5(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x500 | R.A11); } +static void call_6(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x600 | R.A11); } +static void call_7(void) { UINT8 i=M_RDMEM_OPCODE(); M_CALL(i | 0x700 | R.A11); } +static void clr_a(void) { R.A=0; } +static void clr_c(void) { CLR(C_FLAG); } +static void clr_f0(void) { CLR(F_FLAG); } +static void clr_f1(void) { R.f1 = 0; } +static void cpl_a(void) { R.A ^= 0xff; } +static void cpl_c(void) { R.PSW ^= C_FLAG; } +static void cpl_f0(void) { R.PSW ^= F_FLAG; } +static void cpl_f1(void) { R.f1 ^= 1; } +static void dec_a(void) { R.A--; } +static void dec_r0(void) { R0--; } +static void dec_r1(void) { R1--; } +static void dec_r2(void) { R2--; } +static void dec_r3(void) { R3--; } +static void dec_r4(void) { R4--; } +static void dec_r5(void) { R5--; } +static void dec_r6(void) { R6--; } +static void dec_r7(void) { R7--; } +static void dis_i(void) { R.xirq_en = 0; } +static void dis_tcnti(void) { R.tirq_en = 0; R.pending_irq &= ~I8039_TIMCNT_INT; } +static void djnz_r0(void) { UINT8 i=M_RDMEM_OPCODE(); R0--; if (R0 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r1(void) { UINT8 i=M_RDMEM_OPCODE(); R1--; if (R1 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r2(void) { UINT8 i=M_RDMEM_OPCODE(); R2--; if (R2 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r3(void) { UINT8 i=M_RDMEM_OPCODE(); R3--; if (R3 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r4(void) { UINT8 i=M_RDMEM_OPCODE(); R4--; if (R4 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r5(void) { UINT8 i=M_RDMEM_OPCODE(); R5--; if (R5 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r6(void) { UINT8 i=M_RDMEM_OPCODE(); R6--; if (R6 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void djnz_r7(void) { UINT8 i=M_RDMEM_OPCODE(); R7--; if (R7 != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void en_i(void) { R.xirq_en = 1; if (R.irq_state == I8039_EXTERNAL_INT) { R.irq_extra_cycles += Ext_IRQ(); } } +static void en_tcnti(void) { R.tirq_en = 1; } +static void ento_clk(void) { M_UNDEFINED(); } +static void in_a_p1(void) { R.A = port_r(1) & R.P1; } +static void in_a_p2(void) { R.A = port_r(2) & R.P2; } +static void ins_a_bus(void) { R.A = bus_r(); } +static void inc_a(void) { R.A++; } +static void inc_r0(void) { R0++; } +static void inc_r1(void) { R1++; } +static void inc_r2(void) { R2++; } +static void inc_r3(void) { R3++; } +static void inc_r4(void) { R4++; } +static void inc_r5(void) { R5++; } +static void inc_r6(void) { R6++; } +static void inc_r7(void) { R7++; } +static void inc_xr0(void) { intRAM[R0 & INT_RAM_MASK]++; } +static void inc_xr1(void) { intRAM[R1 & INT_RAM_MASK]++; } + +/* static void jmp(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | R.A11; } + */ + +static void jmp(void) +{ + UINT8 i=M_RDOP(R.PC.w.l); + UINT16 oldpc,newpc; + + oldpc = R.PC.w.l-1; + R.PC.w.l = i | R.A11; + newpc = R.PC.w.l; + if (newpc == oldpc) { if (i8039_ICount > 0) i8039_ICount = 0; } /* speed up busy loop */ + else if (newpc == oldpc-1 && M_RDOP(newpc) == 0x00) /* NOP - Gyruss */ + { if (i8039_ICount > 0) i8039_ICount = 0; } +} + +static void jmp_1(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x100 | R.A11; } +static void jmp_2(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x200 | R.A11; } +static void jmp_3(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x300 | R.A11; } +static void jmp_4(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x400 | R.A11; } +static void jmp_5(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x500 | R.A11; } +static void jmp_6(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x600 | R.A11; } +static void jmp_7(void) { UINT8 i=M_RDOP(R.PC.w.l); R.PC.w.l = i | 0x700 | R.A11; } +static void jmpp_xa(void) { UINT16 addr = (R.PC.w.l & 0xf00) | R.A; R.PC.w.l = (R.PC.w.l & 0xf00) | M_RDMEM(addr); } +static void jb_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x01) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x02) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_2(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x04) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_3(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x08) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_4(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x10) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_5(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x20) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_6(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x40) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jb_7(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A & 0x80) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jf0(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_F0y) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jf1(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.f1) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jnc(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_Cn) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jc(void) { UINT8 i=M_RDMEM_OPCODE(); if (M_Cy) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jni(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.irq_state == I8039_EXTERNAL_INT) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jnt_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (!test_r(0)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jt_0(void) { UINT8 i=M_RDMEM_OPCODE(); if (test_r(0)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jnt_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (!test_r(1)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jt_1(void) { UINT8 i=M_RDMEM_OPCODE(); if (test_r(1)) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jnz(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A != 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jz(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.A == 0) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; } else ADJUST_CYCLES } +static void jtf(void) { UINT8 i=M_RDMEM_OPCODE(); if (R.t_flag) { R.PC.w.l = ((R.PC.w.l-1) & 0xf00) | i; R.t_flag = 0; } else ADJUST_CYCLES } + +static void mov_a_n(void) { R.A = M_RDMEM_OPCODE(); } +static void mov_a_r0(void) { R.A = R0; } +static void mov_a_r1(void) { R.A = R1; } +static void mov_a_r2(void) { R.A = R2; } +static void mov_a_r3(void) { R.A = R3; } +static void mov_a_r4(void) { R.A = R4; } +static void mov_a_r5(void) { R.A = R5; } +static void mov_a_r6(void) { R.A = R6; } +static void mov_a_r7(void) { R.A = R7; } +static void mov_a_psw(void) { R.A = R.PSW | 0x08; } +static void mov_a_xr0(void) { R.A = intRAM[R0 & INT_RAM_MASK]; } +static void mov_a_xr1(void) { R.A = intRAM[R1 & INT_RAM_MASK]; } +static void mov_r0_a(void) { R0 = R.A; } +static void mov_r1_a(void) { R1 = R.A; } +static void mov_r2_a(void) { R2 = R.A; } +static void mov_r3_a(void) { R3 = R.A; } +static void mov_r4_a(void) { R4 = R.A; } +static void mov_r5_a(void) { R5 = R.A; } +static void mov_r6_a(void) { R6 = R.A; } +static void mov_r7_a(void) { R7 = R.A; } +static void mov_psw_a(void) { R.PSW = R.A | 0x08; regPTR = ((M_By) ? 24 : 0); R.SP = (R.PSW & 7) << 1; } +static void mov_r0_n(void) { R0 = M_RDMEM_OPCODE(); } +static void mov_r1_n(void) { R1 = M_RDMEM_OPCODE(); } +static void mov_r2_n(void) { R2 = M_RDMEM_OPCODE(); } +static void mov_r3_n(void) { R3 = M_RDMEM_OPCODE(); } +static void mov_r4_n(void) { R4 = M_RDMEM_OPCODE(); } +static void mov_r5_n(void) { R5 = M_RDMEM_OPCODE(); } +static void mov_r6_n(void) { R6 = M_RDMEM_OPCODE(); } +static void mov_r7_n(void) { R7 = M_RDMEM_OPCODE(); } +static void mov_a_t(void) { R.A = R.timer; } +static void mov_t_a(void) { R.timer = R.A; } +static void mov_xr0_a(void) { intRAM[R0 & INT_RAM_MASK] = R.A; } +static void mov_xr1_a(void) { intRAM[R1 & INT_RAM_MASK] = R.A; } +static void mov_xr0_n(void) { intRAM[R0 & INT_RAM_MASK] = M_RDMEM_OPCODE(); } +static void mov_xr1_n(void) { intRAM[R1 & INT_RAM_MASK] = M_RDMEM_OPCODE(); } +static void movd_a_p4(void) { R.A = port_r(4); } +static void movd_a_p5(void) { R.A = port_r(5); } +static void movd_a_p6(void) { R.A = port_r(6); } +static void movd_a_p7(void) { R.A = port_r(7); } +static void movd_p4_a(void) { port_w(4, R.A); } +static void movd_p5_a(void) { port_w(5, R.A); } +static void movd_p6_a(void) { port_w(6, R.A); } +static void movd_p7_a(void) { port_w(7, R.A); } +static void movp_a_xa(void) { R.A = M_RDMEM((R.PC.w.l & 0x0f00) | R.A); } +static void movp3_a_xa(void) { R.A = M_RDMEM(0x300 | R.A); } +static void movx_a_xr0(void) { R.A = M_IN(R0); } +static void movx_a_xr1(void) { R.A = M_IN(R1); } +static void movx_xr0_a(void) { M_OUT(R0, R.A); } +static void movx_xr1_a(void) { M_OUT(R1, R.A); } +static void nop(void) { } +static void orl_a_n(void) { R.A |= M_RDMEM_OPCODE(); } +static void orl_a_r0(void) { R.A |= R0; } +static void orl_a_r1(void) { R.A |= R1; } +static void orl_a_r2(void) { R.A |= R2; } +static void orl_a_r3(void) { R.A |= R3; } +static void orl_a_r4(void) { R.A |= R4; } +static void orl_a_r5(void) { R.A |= R5; } +static void orl_a_r6(void) { R.A |= R6; } +static void orl_a_r7(void) { R.A |= R7; } +static void orl_a_xr0(void) { R.A |= intRAM[R0 & INT_RAM_MASK]; } +static void orl_a_xr1(void) { R.A |= intRAM[R1 & INT_RAM_MASK]; } +static void orl_bus_n(void) { bus_w( bus_r() | M_RDMEM_OPCODE() ); } +static void orl_p1_n(void) { R.P1 |= M_RDMEM_OPCODE(); port_w(1, R.P1); } +static void orl_p2_n(void) { R.P2 |= M_RDMEM_OPCODE(); port_w(2, R.P2); } +static void orld_p4_a(void) { port_w(4, port_r(4) | R.A ); } +static void orld_p5_a(void) { port_w(5, port_r(5) | R.A ); } +static void orld_p6_a(void) { port_w(6, port_r(6) | R.A ); } +static void orld_p7_a(void) { port_w(7, port_r(7) | R.A ); } +static void outl_bus_a(void) { bus_w(R.A); } +static void outl_p1_a(void) { port_w(1, R.A); R.P1 = R.A; } +static void outl_p2_a(void) { port_w(2, R.A); R.P2 = R.A; } +static void ret(void) { R.PC.w.l = ((pull() & 0x0f) << 8); R.PC.w.l |= pull(); } + +static void retr(void) +{ + UINT8 i=pull(); + R.PC.w.l = ((i & 0x0f) << 8) | pull(); + R.PSW = (R.PSW & 0x0f) | (i & 0xf0); /* Stack is already changed by pull */ + regPTR = ((M_By) ? 24 : 0); + + R.irq_executing = I8039_NO_INT; + + R.A11 = R.A11ff; + + /* Take an interrupt if a request is still being made */ + if (R.irq_state == I8039_EXTERNAL_INT) { + R.irq_extra_cycles += Ext_IRQ(); /* Service External IRQ */ + } + else if (R.pending_irq == I8039_TIMCNT_INT) { + R.irq_extra_cycles += Timer_IRQ(); /* Service pending Timer/Counter IRQ */ + } +} +static void rl_a(void) { UINT8 i=R.A & 0x80; R.A <<= 1; if (i) R.A |= 0x01; else R.A &= 0xfe; } +/* NS990113 */ +static void rlc_a(void) { UINT8 i=M_Cy; if (R.A & 0x80) SET(C_FLAG); else CLR(C_FLAG); R.A <<= 1; if (i) R.A |= 0x01; else R.A &= 0xfe; } +static void rr_a(void) { UINT8 i=R.A & 1; R.A >>= 1; if (i) R.A |= 0x80; else R.A &= 0x7f; } +/* NS990113 */ +static void rrc_a(void) { UINT8 i=M_Cy; if (R.A & 1) SET(C_FLAG); else CLR(C_FLAG); R.A >>= 1; if (i) R.A |= 0x80; else R.A &= 0x7f; } +static void sel_mb0(void) { R.A11 = 0; R.A11ff = 0; } +static void sel_mb1(void) { R.A11ff = 0x800; R.A11 = 0x800; } +static void sel_rb0(void) { CLR(B_FLAG); regPTR = 0; } +static void sel_rb1(void) { SET(B_FLAG); regPTR = 24; } +static void stop_tcnt(void) { R.timerON = R.countON = 0; } +static void strt_cnt(void) { R.countON = 1; R.timerON = 0; Old_T1 = test_r(1); } /* NS990113 */ +static void strt_t(void) { R.timerON = 1; R.countON = 0; R.masterClock = 0; } /* NS990113 */ +static void swap_a(void) { UINT8 i=R.A >> 4; R.A <<= 4; R.A |= i; } +static void xch_a_r0(void) { UINT8 i=R.A; R.A=R0; R0=i; } +static void xch_a_r1(void) { UINT8 i=R.A; R.A=R1; R1=i; } +static void xch_a_r2(void) { UINT8 i=R.A; R.A=R2; R2=i; } +static void xch_a_r3(void) { UINT8 i=R.A; R.A=R3; R3=i; } +static void xch_a_r4(void) { UINT8 i=R.A; R.A=R4; R4=i; } +static void xch_a_r5(void) { UINT8 i=R.A; R.A=R5; R5=i; } +static void xch_a_r6(void) { UINT8 i=R.A; R.A=R6; R6=i; } +static void xch_a_r7(void) { UINT8 i=R.A; R.A=R7; R7=i; } +static void xch_a_xr0(void) { UINT8 i=R.A; R.A=intRAM[R0 & INT_RAM_MASK]; intRAM[R0 & INT_RAM_MASK]=i; } +static void xch_a_xr1(void) { UINT8 i=R.A; R.A=intRAM[R1 & INT_RAM_MASK]; intRAM[R1 & INT_RAM_MASK]=i; } +static void xchd_a_xr0(void) { M_XCHD(R0 & INT_RAM_MASK); } +static void xchd_a_xr1(void) { M_XCHD(R1 & INT_RAM_MASK); } +static void xrl_a_n(void) { R.A ^= M_RDMEM_OPCODE(); } +static void xrl_a_r0(void) { R.A ^= R0; } +static void xrl_a_r1(void) { R.A ^= R1; } +static void xrl_a_r2(void) { R.A ^= R2; } +static void xrl_a_r3(void) { R.A ^= R3; } +static void xrl_a_r4(void) { R.A ^= R4; } +static void xrl_a_r5(void) { R.A ^= R5; } +static void xrl_a_r6(void) { R.A ^= R6; } +static void xrl_a_r7(void) { R.A ^= R7; } +static void xrl_a_xr0(void) { R.A ^= intRAM[R0 & INT_RAM_MASK]; } +static void xrl_a_xr1(void) { R.A ^= intRAM[R1 & INT_RAM_MASK]; } + +static s_opcode opcode_main[256]= +{ + {1, nop },{0, illegal },{2, outl_bus_a },{2, add_a_n },{2, jmp },{1, en_i },{0, illegal },{1, dec_a }, + {2, ins_a_bus },{2, in_a_p1 },{2, in_a_p2 },{0, illegal },{2, movd_a_p4 },{2, movd_a_p5 },{2, movd_a_p6 },{2, movd_a_p7 }, + {1, inc_xr0 },{1, inc_xr1 },{2, jb_0 },{2, adc_a_n },{2, call },{1, dis_i },{2, jtf },{1, inc_a }, + {1, inc_r0 },{1, inc_r1 },{1, inc_r2 },{1, inc_r3 },{1, inc_r4 },{1, inc_r5 },{1, inc_r6 },{1, inc_r7 }, + {1, xch_a_xr0 },{1, xch_a_xr1 },{0, illegal },{2, mov_a_n },{2, jmp_1 },{1, en_tcnti },{2, jnt_0 },{1, clr_a }, + {1, xch_a_r0 },{1, xch_a_r1 },{1, xch_a_r2 },{1, xch_a_r3 },{1, xch_a_r4 },{1, xch_a_r5 },{1, xch_a_r6 },{1, xch_a_r7 }, + {1, xchd_a_xr0 },{1, xchd_a_xr1 },{2, jb_1 },{0, illegal },{2, call_1 },{1, dis_tcnti },{2, jt_0 },{1, cpl_a }, + {0, illegal },{2, outl_p1_a },{2, outl_p2_a },{0, illegal },{2, movd_p4_a },{2, movd_p5_a },{2, movd_p6_a },{2, movd_p7_a }, + {1, orl_a_xr0 },{1, orl_a_xr1 },{1, mov_a_t },{2, orl_a_n },{2, jmp_2 },{1, strt_cnt },{2, jnt_1 },{1, swap_a }, + {1, orl_a_r0 },{1, orl_a_r1 },{1, orl_a_r2 },{1, orl_a_r3 },{1, orl_a_r4 },{1, orl_a_r5 },{1, orl_a_r6 },{1, orl_a_r7 }, + {1, anl_a_xr0 },{1, anl_a_xr1 },{2, jb_2 },{2, anl_a_n },{2, call_2 },{1, strt_t },{2, jt_1 },{1, daa_a }, + {1, anl_a_r0 },{1, anl_a_r1 },{1, anl_a_r2 },{1, anl_a_r3 },{1, anl_a_r4 },{1, anl_a_r5 },{1, anl_a_r6 },{1, anl_a_r7 }, + {1, add_a_xr0 },{1, add_a_xr1 },{1, mov_t_a },{0, illegal },{2, jmp_3 },{1, stop_tcnt },{0, illegal },{1, rrc_a }, + {1, add_a_r0 },{1, add_a_r1 },{1, add_a_r2 },{1, add_a_r3 },{1, add_a_r4 },{1, add_a_r5 },{1, add_a_r6 },{1, add_a_r7 }, + {1, adc_a_xr0 },{1, adc_a_xr1 },{2, jb_3 },{0, illegal },{2, call_3 },{1, ento_clk },{2, jf1 },{1, rr_a }, + {1, adc_a_r0 },{1, adc_a_r1 },{1, adc_a_r2 },{1, adc_a_r3 },{1, adc_a_r4 },{1, adc_a_r5 },{1, adc_a_r6 },{1, adc_a_r7 }, + {2, movx_a_xr0 },{2, movx_a_xr1 },{0, illegal },{2, ret },{2, jmp_4 },{1, clr_f0 },{2, jni },{0, illegal }, + {2, orl_bus_n },{2, orl_p1_n },{2, orl_p2_n },{0, illegal },{2, orld_p4_a },{2, orld_p5_a },{2, orld_p6_a },{2, orld_p7_a }, + {2, movx_xr0_a },{2, movx_xr1_a },{2, jb_4 },{2, retr },{2, call_4 },{1, cpl_f0 },{2, jnz },{1, clr_c }, + {2, anl_bus_n },{2, anl_p1_n },{2, anl_p2_n },{0, illegal },{2, anld_p4_a },{2, anld_p5_a },{2, anld_p6_a },{2, anld_p7_a }, + {1, mov_xr0_a },{1, mov_xr1_a },{0, illegal },{2, movp_a_xa },{2, jmp_5 },{1, clr_f1 },{0, illegal },{1, cpl_c }, + {1, mov_r0_a },{1, mov_r1_a },{1, mov_r2_a },{1, mov_r3_a },{1, mov_r4_a },{1, mov_r5_a },{1, mov_r6_a },{1, mov_r7_a }, + {2, mov_xr0_n },{2, mov_xr1_n },{2, jb_5 },{2, jmpp_xa },{2, call_5 },{1, cpl_f1 },{2, jf0 },{0, illegal }, + {2, mov_r0_n },{2, mov_r1_n },{2, mov_r2_n },{2, mov_r3_n },{2, mov_r4_n },{2, mov_r5_n },{2, mov_r6_n },{2, mov_r7_n }, + {0, illegal },{0, illegal },{0, illegal },{0, illegal },{2, jmp_6 },{1, sel_rb0 },{2, jz },{1, mov_a_psw }, + {1, dec_r0 },{1, dec_r1 },{1, dec_r2 },{1, dec_r3 },{1, dec_r4 },{1, dec_r5 },{1, dec_r6 },{1, dec_r7 }, + {1, xrl_a_xr0 },{1, xrl_a_xr1 },{2, jb_6 },{2, xrl_a_n },{2, call_6 },{1, sel_rb1 },{0, illegal },{1, mov_psw_a }, + {1, xrl_a_r0 },{1, xrl_a_r1 },{1, xrl_a_r2 },{1, xrl_a_r3 },{1, xrl_a_r4 },{1, xrl_a_r5 },{1, xrl_a_r6 },{1, xrl_a_r7 }, + {0, illegal },{0, illegal },{0, illegal },{2, movp3_a_xa },{2, jmp_7 },{1, sel_mb0 },{2, jnc },{1, rl_a }, + {2, djnz_r0 },{2, djnz_r1 },{2, djnz_r2 },{2, djnz_r3 },{2, djnz_r4 },{2, djnz_r5 },{2, djnz_r6 },{2, djnz_r7 }, + {1, mov_a_xr0 },{1, mov_a_xr1 },{2, jb_7 },{0, illegal },{2, call_7 },{1, sel_mb1 },{2, jc },{1, rlc_a }, + {1, mov_a_r0 },{1, mov_a_r1 },{1, mov_a_r2 },{1, mov_a_r3 },{1, mov_a_r4 },{1, mov_a_r5 },{1, mov_a_r6 },{1, mov_a_r7 } +}; + + +/**************************************************************************** + * Reset registers to their initial values + ****************************************************************************/ +void i8039_reset (void *param) +{ + R.PC.w.l = 0; + R.SP = 0; + R.A = 0; + R.PSW = 0x08; /* Start with Carry SET, Bit 4 is always SET */ + memset(R.RAM, 0x0, 128); + R.P1 = 0xff; + R.P2 = 0xff; + R.bus = 0; + R.irq_executing = I8039_NO_INT; + R.pending_irq = I8039_NO_INT; + + R.A11ff = R.A11 = 0; + R.tirq_en = R.xirq_en = 0; + R.timerON = R.countON = 0; + R.timerON = 1; /* Mario Bros. doesn't work without this */ + R.irq_extra_cycles = 0; + R.masterClock = 0; + + /* print dump header */ + printf(" Addr | Instruction | PC Accu SP PSW BUS F1 P1 P2 A11 RAM\n"); + printf(" ------+--------------------+---------------------------------------\n"); +} + + +/**************************************************************************** + * Shut down CPU emulation + ****************************************************************************/ +static void i8039_exit (void) +{ + /* nothing to do ? */ +} + +/**************************************************************************** + * Issue an interrupt if necessary + ****************************************************************************/ +static int Ext_IRQ(void) +{ + int extra_cycles = 0; + + if (R.xirq_en) { + if (R.irq_executing == I8039_NO_INT) { +/* logerror("I8039: EXT INTERRUPT being serviced\n"); */ + R.irq_executing = I8039_EXTERNAL_INT; + push(R.PC.b.l); + push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); + R.PC.w.l = 0x03; + R.A11ff = R.A11; + R.A11 = 0; + + extra_cycles = 2; /* 2 clock cycles used */ + + if (R.timerON) /* NS990113 */ + R.masterClock += extra_cycles; + if (R.irq_callback) (*R.irq_callback)(0); + } + } + + return extra_cycles; +} + +static int Timer_IRQ(void) +{ + int extra_cycles = 0; + + if (R.tirq_en) { + if (R.irq_executing == I8039_NO_INT) { +/* logerror("I8039: TIMER/COUNTER INTERRUPT\n"); */ + R.irq_executing = I8039_TIMCNT_INT; + R.pending_irq &= ~I8039_TIMCNT_INT; + push(R.PC.b.l); + push((R.PC.b.h & 0x0f) | (R.PSW & 0xf0)); + R.PC.w.l = 0x07; + R.A11ff = R.A11; + R.A11 = 0; + + extra_cycles = 2; /* 2 clock cycles used */ + + if (R.timerON) /* NS990113 */ + R.masterClock += extra_cycles; + } + else { + if (R.irq_executing == I8039_EXTERNAL_INT) { + R.pending_irq |= I8039_TIMCNT_INT; + } + } + } + + R.t_flag = 1; + + return extra_cycles; +} + + +static void dump_machine_state(void) +{ + int i; + + printf(" | %04X %02X %02X %02X", (UINT32)R.PC.w.l, (UINT32)R.A, (UINT32)(R.SP >> 1), (UINT32)R.PSW); + printf(" %02X %X %02X %02X", (UINT32)R.bus, (UINT32)R.f1, (UINT32)R.P1, (UINT32)R.P2); + printf(" %X ", (UINT32)(R.A11ff >> 11)); + + for (i = 0; i < 256; i++) + printf(" %02X", R.RAM[i]); + + printf("\n"); +} + + +enum {ACCU_IDLE, ACCU_HAS_AA, ACCU_HAS_55, ACCU_PASS, ACCU_FAIL}; + +/**************************************************************************** + * Execute cycles CPU cycles. Return number of cycles really executed + ****************************************************************************/ +int i8039_execute(int cycles, int dump) +{ + unsigned opcode, T1; + int count, i; + char buffer[64]; + char string[32]; + + static int accu = 0; + static int accu_state = ACCU_IDLE; + + i8039_ICount = (cycles - R.irq_extra_cycles); + R.irq_extra_cycles = 0; + + if ((accu_state == ACCU_PASS) || (accu_state == ACCU_FAIL)) { + printf("End of simulation detected\n"); + + return(accu_state == ACCU_PASS ? 0 : -1); + } + + do + { + R.PREVPC = R.PC; + + + opcode=M_RDOP(R.PC.w.l); + + buffer[0] = '\0'; + Dasm8039(buffer, R.PC.w.l); + sprintf(string, " %04X : %s", R.PC.w.l, buffer); + for (i = strlen(string); i < 26; i++) + string[i] = ' '; + string[i <= 31 ? i : 31] = '\0'; + printf("%s", string); + +/* logerror("I8039: PC = %04x, opcode = %02x\n", R.PC.w.l, opcode); */ + + R.PC.w.l++; + inst_cycles = opcode_main[opcode].cycles; + (*(opcode_main[opcode].function))(); + i8039_ICount -= inst_cycles; /*/ */ + + if (dump == 1) { + /* dump machine state information */ + dump_machine_state(); + } else + printf("\n"); + + /* end-of-simulation check */ + if (accu != R.A) { + accu = R.A; + + switch (accu_state) { + case ACCU_IDLE: + accu_state = accu == 0xaa ? ACCU_HAS_AA : ACCU_IDLE; + break; + + case ACCU_HAS_AA: + accu_state = accu == 0x55 ? ACCU_HAS_55 : ACCU_IDLE; + break; + + case ACCU_HAS_55: + switch (accu) { + case 0x01: + accu_state = ACCU_PASS; + break; + case 0x00: + accu_state = ACCU_FAIL; + break; + default: + accu_state = ACCU_IDLE; + break; + } + break; + + case ACCU_PASS: + case ACCU_FAIL: + break; + + default: + accu_state = ACCU_IDLE; + break; + } + } + + + + + if (R.countON) /* NS990113 */ + { + for ( ; inst_cycles > 0; inst_cycles-- ) + { + T1 = test_r(1); + if (NEGATIVE_EDGE_T1) + { + R.timer++; + if (R.timer == 0) { + count = Timer_IRQ(); /* Handle Counter IRQ */ + i8039_ICount -= count; + } + } + Old_T1 = T1; + } + } + + if (R.timerON) { + R.masterClock += opcode_main[opcode].cycles; + if (R.masterClock >= 32) { /* NS990113 */ + R.masterClock -= 32; + R.timer++; + if (R.timer == 0) { + count = Timer_IRQ(); /* Handle Timer IRQ */ + i8039_ICount -= count; + } + } + } + } while (i8039_ICount > 0 && accu_state != ACCU_PASS && accu_state != ACCU_FAIL); + + i8039_ICount -= R.irq_extra_cycles; + R.irq_extra_cycles = 0; + + return cycles - i8039_ICount; +} + +/**************************************************************************** + * Get all registers in given buffer + ****************************************************************************/ +static void i8039_get_context (void *dst) +{ + if( dst ) + *(I8039_Regs*)dst = R; +} + + +/**************************************************************************** + * Set all registers to given values + ****************************************************************************/ +static void i8039_set_context (void *src) +{ + if( src ) + { + R = *(I8039_Regs*)src; + regPTR = ((M_By) ? 24 : 0); + R.SP = (R.PSW << 1) & 0x0f; + } + /* Handle forced Interrupts throught the Debugger */ + if (R.irq_state != I8039_NO_INT) { + R.irq_extra_cycles += Ext_IRQ(); /* Handle External IRQ */ + } + if (R.timer == 0) { + R.irq_extra_cycles += Timer_IRQ(); /* Handle Timer IRQ */ + } +} + + +/**************************************************************************** + * Set IRQ line state + ****************************************************************************/ +void set_irq_line(int irqline, int state) +{ + if (state != CLEAR_LINE) { + R.irq_state = I8039_EXTERNAL_INT; + R.irq_extra_cycles += Ext_IRQ(); /* Handle External IRQ */ + } + else { + R.irq_state = I8039_NO_INT; + } +} Index: i8039emu/main.c =================================================================== --- i8039emu/main.c (nonexistent) +++ i8039emu/main.c (revision 292) @@ -0,0 +1,128 @@ +/* + * $Id: main.c,v 1.3 2004-07-03 14:37:12 arniml Exp $ + * + * Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) + * + * All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. See also the file COPYING which + * came with this application. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include + +#include "types.h" +#include "memory.h" +#include "i8039.h" + + +void logerror(char *msg, UINT16 address, UINT8 opcode) +{ +} + + +void print_usage(void) { + printf("Usage:\n"); + printf(" i8039 -f [-x ] [-d] [-h]\n"); + printf(" -f : Name of hex file for internal ROM\n"); + printf(" -x : Name of hex file for external ROM (optional)\n"); + printf(" -d : Dump machine state\n"); + printf(" -h : Print this help\n"); +} + + +int main(int argc, char *argv[]) +{ + int do_cycles, real_cycles, total_cycles; + char *hex_file = ""; + char *ext_hex_file = ""; + int c; + int dump = 0; + + /* process options */ + while ((c = getopt(argc, argv, "df:hx:")) != -1) { + switch (c) { + case 'd': + dump = 1; + break; + + case 'f': + hex_file = optarg; + break; + + case 'x': + ext_hex_file = optarg; + break; + + case 'h': + /* fallthrough */ + + default: + print_usage(); + return(0); + break; + } + } + + /* check options */ + if (strlen(hex_file) == 0) { + print_usage(); + return(1); + } + + /* read hex file for internal ROM */ + printf("Reading %s\n", hex_file); + if (!read_hex_file(hex_file, 0)) { + printf("Error reading file!\n"); + return(1); + } + + /* read hex fiel for external ROM */ + if (strlen(ext_hex_file) > 0) { + printf("Reading %s\n", ext_hex_file); + if (!read_hex_file(ext_hex_file, 0x800)) { + printf("Error reading file!\n"); + return(1); + } + } + + printf("Resetting 8039\n"); + i8039_reset(NULL); + + do_cycles = 52; + + total_cycles = 0; + + do { + real_cycles = i8039_execute(do_cycles, dump); + + /* activate interrupt */ + set_irq_line(0, HOLD_LINE); + /* hold interrupt for 3 machine cycles */ + real_cycles += i8039_execute(3, dump); + set_irq_line(0, CLEAR_LINE); + + if (real_cycles > 0) + total_cycles += real_cycles; + } while (real_cycles > 0); + + printf("Emulated %i cycles\n", total_cycles); + printf("Simulation Result: %s\n", real_cycles == 0 ? "PASS" : "FAIL"); + + return(0); +} Index: i8039emu/memory.c =================================================================== --- i8039emu/memory.c (nonexistent) +++ i8039emu/memory.c (revision 292) @@ -0,0 +1,149 @@ +/* + * $Id: memory.c,v 1.3 2004-07-03 14:35:52 arniml Exp $ + * + * Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) + * + * All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. See also the file COPYING which + * came with this application. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include + +#include "memory.h" +#include "i8039.h" + + +static UINT8 code_mem[4096]; + + +static UINT8 port1 = 0xff, port2 = 0xff; + + +UINT8 program_read_byte_8(UINT16 address) +{ + return(code_mem[address]); +} + +UINT8 cpu_readop(UINT16 address) +{ + return(code_mem[address]); +} + +UINT8 cpu_readop_arg(UINT16 address) +{ + return(code_mem[address]); +} + + +UINT8 io_read_byte_8(UINT8 address) +{ + UINT8 data; + + switch (0x100 | address) { + case I8039_p1: + data = port1; + break; + + case I8039_p2: + data = port2; + break; + + case I8039_t0: + /* connect T0 to P1[0] */ + data = port1 & 0x01; + break; + + case I8039_t1: + /* connect T1 to P1[1] */ + data = (port1 & 0x02) >> 1; + break; + + default: + data = 0; + break; + } + + + return(data); +} + + +void io_write_byte_8(UINT8 address, UINT8 data) +{ + switch (0x100 | address) { + case I8039_p1: + port1 = data; + break; + + case I8039_p2: + port2 = data; + break; + + default: + break; + } +} + + +int read_hex_file(char *filename, UINT16 file_offset) +{ + FILE *hex_file; + UINT16 record_len, offset, record_type; + UINT16 byte; + char line[540]; + char *payload, *idx; + int result = 0; + + record_len = offset = record_type = 0; + hex_file = fopen(filename, "r"); + if (hex_file != NULL) { + + while (fgets(line, 539, hex_file)) { + if (sscanf(line, ":%2hx%4hx%2hx", &record_len, &offset, &record_type) == 3) { + /* strip off newline */ + idx = (char *)strchr(line, '\n'); + if (idx != NULL) + *idx = '\0'; + /* extract payload */ + payload = &(line[9]); + /* strip of checksum */ + if (strlen(payload) > 2) + payload[strlen(payload) - 2] = '\0'; + + /* read payload to array */ + if (record_type == 0) { + while (strlen(payload) >= 2) { + if (sscanf(payload, "%2hx", &byte) == 1) + code_mem[file_offset + offset++] = byte; + + payload++; + payload++; + } + } + + } + } + + result = 1; + + fclose(hex_file); + } + + return(result); +} Index: i8039emu/memory.h =================================================================== --- i8039emu/memory.h (nonexistent) +++ i8039emu/memory.h (revision 292) @@ -0,0 +1,26 @@ +/* + * $Id: memory.h,v 1.2 2004-07-03 14:35:52 arniml Exp $ + * + */ + +#ifndef _MEMORY_H_ +#define _MEMORY_H_ + +#include "types.h" + +typedef UINT32 offs_t; + + +UINT8 program_read_byte_8(UINT16); + +UINT8 cpu_readop(UINT16); + +UINT8 cpu_readop_arg(UINT16); + +UINT8 io_read_byte_8(UINT8); + +void io_write_byte_8(UINT8, UINT8); + +int read_hex_file(char *, UINT16); + +#endif Index: i8039emu/i8039.h =================================================================== --- i8039emu/i8039.h (nonexistent) +++ i8039emu/i8039.h (revision 292) @@ -0,0 +1,107 @@ +/************************************************************************** + * Intel 8039 Portable Emulator * + * * + * Copyright (C) 1997 by Mirko Buffoni * + * Based on the original work (C) 1997 by Dan Boris, an 8048 emulator * + * You are not allowed to distribute this software commercially * + * Please, notify me, if you make any changes to this file * + * * + * Adapted for the T48 uController project, 2004 by Arnim Laeuger * + * See http://www.opencores.org/projects.cgi/web/t48/overview * + * * + * $Id: i8039.h,v 1.2 2004-04-15 22:03:53 arniml Exp $ + **************************************************************************/ + +#ifndef _I8039_H +#define _I8039_H + +#ifndef INLINE +#define INLINE static inline +#endif + +#include "types.h" + + +/************************************************************************** + Internal Clock divisor + + External Clock is divided internally by 3 to produce the machine state + generator. This is then divided by 5 for the instruction cycle times. + (Each instruction cycle passes through 5 machine states). +*/ + +#define I8039_CLOCK_DIVIDER (3*5) + + + +enum { I8039_PC=1, I8039_SP, I8039_PSW, I8039_A, I8039_TC, + I8039_P1, I8039_P2, I8039_R0, I8039_R1, I8039_R2, + I8039_R3, I8039_R4, I8039_R5, I8039_R6, I8039_R7 +}; + +/* This handling of special I/O ports should be better for actual MAME + * architecture. (i.e., define access to ports { I8039_p1, I8039_p1, dkong_out_w }) + */ + +#define I8039_p0 0x100 /* Not used */ +#define I8039_p1 0x101 +#define I8039_p2 0x102 +#define I8039_p4 0x104 +#define I8039_p5 0x105 +#define I8039_p6 0x106 +#define I8039_p7 0x107 +#define I8039_t0 0x110 +#define I8039_t1 0x111 +#define I8039_bus 0x120 + + +#include "memory.h" + +/* + * Input a UINT8 from given I/O port + */ +#define I8039_In(Port) ((UINT8)io_read_byte_8((UINT8)Port)) + + +/* + * Output a UINT8 to given I/O port + */ +#define I8039_Out(Port,Value) (io_write_byte_8((UINT8)Port,(UINT8)Value)) + + +/* + * Read a UINT8 from given memory location + */ +#define I8039_RDMEM(A) ((unsigned)program_read_byte_8(A)) + + +/* + * Write a UINT8 to given memory location + */ +#define I8039_WRMEM(A,V) (program_write_byte_8(A,V)) + + +/* + * I8039_RDOP() is identical to I8039_RDMEM() except it is used for reading + * opcodes. In case of system with memory mapped I/O, this function can be + * used to greatly speed up emulation + */ +#define I8039_RDOP(A) ((unsigned)cpu_readop(A)) + + +/* + * I8039_RDOP_ARG() is identical to I8039_RDOP() except it is used for reading + * opcode arguments. This difference can be used to support systems that + * use different encoding mechanisms for opcodes and opcode arguments + */ +#define I8039_RDOP_ARG(A) ((unsigned)cpu_readop_arg(A)) + +int Dasm8039(char *dst, unsigned pc); + +void i8039_reset(void *); +int i8039_execute(int, int); +void set_irq_line(int, int); + +void logerror(char *, UINT16, UINT8); + +#endif /* _I8039_H */ Index: i8039emu/8039dasm.c =================================================================== --- i8039emu/8039dasm.c (nonexistent) +++ i8039emu/8039dasm.c (revision 292) @@ -0,0 +1,289 @@ +/**************************************************************************** + * + * mcs48 disassembler + * + * This file is Copyright 1996 Michael Cuddy, Fen's Ende Sofware. + * Redistribution is allowed in source and binary form as long as both + * forms are distributed together with the file 'README'. This copyright + * notice must also accompany the files. + * + * This software should be considered a small token to all of the + * emulator authors for thier dilligence in preserving our Arcade and + * Computer history. + * + * Michael Cuddy, Fen's Ende Software. + * 11/25/1996 + * + * Adapted by Andrea Mazzoleni for use with MAME + * + ***************************************************************************/ + +#include +#include +#include +#include + +#include "memory.h" + +typedef unsigned char byte; + +#define FMT(a,b) a, b +#define PTRS_PER_FORMAT 2 + +const char *Formats[] = { + FMT("00000011dddddddd", "add a, #%X"), + FMT("01101rrr", "add a, %R"), + FMT("0110000r", "add a, @%R"), + FMT("00010011dddddddd", "adc a, #%X"), + FMT("01111rrr", "adc a, %R"), + FMT("0111000r", "adc a, @%R"), + FMT("01010011dddddddd", "anl a, #%X"), + FMT("01011rrr", "anl a, %R"), + FMT("0101000r", "anl a, @%R"), + FMT("10011000dddddddd", "anl bus, #%X"), + FMT("10011001dddddddd", "anl p1, #%X"), + FMT("10011010dddddddd", "anl p2, #%X"), + FMT("100111pp", "anld %P, a"), + FMT("aaa10100aaaaaaaa", "call %A"), + FMT("00100111", "clr a"), + FMT("10010111", "clr c"), + FMT("10100101", "clr f1"), + FMT("10000101", "clr f0"), + FMT("00110111", "cpl a"), + FMT("10100111", "cpl c"), + FMT("10010101", "cpl f0"), + FMT("10110101", "cpl f1"), + FMT("01010111", "da a"), + FMT("00000111", "dec a"), + FMT("11001rrr", "dec %R"), + FMT("00010101", "dis i"), + FMT("00110101", "dis tcnti"), + FMT("11101rrraaaaaaaa", "djnz %R, %J"), + FMT("00000101", "en i"), + FMT("00100101", "en tcnti"), + FMT("01110101", "ent0 clk"), + FMT("00001001", "in a, p1"), + FMT("00001010", "in a, p2"), + FMT("00010111", "inc a"), + FMT("00011rrr", "inc %R"), + FMT("0001000r", "inc @%R"), + FMT("00001000", "ins a,bus"), + FMT("0001 0110aaaaaaaa", "jtf %J"), + FMT("0010 0110aaaaaaaa", "jnt0 %J"), + FMT("0011 0110aaaaaaaa", "jt0 %J"), + FMT("0100 0110aaaaaaaa", "jnt1 %J"), + FMT("0101 0110aaaaaaaa", "jt1 %J"), + FMT("0111 0110aaaaaaaa", "jf1 %J"), + FMT("1000 0110aaaaaaaa", "jni %J"), + FMT("1001 0110aaaaaaaa", "jnz %J"), + FMT("1011 0110aaaaaaaa", "jf0 %J"), + FMT("1100 0110aaaaaaaa", "jz %J"), + FMT("1110 0110aaaaaaaa", "jnc %J"), + FMT("1111 0110aaaaaaaa", "jc %J"), + FMT("bbb10010aaaaaaaa", "jb%B %J"), + FMT("aaa00100aaaaaaaa", "jmp %A"), + FMT("10110011", "jmpp @a"), + FMT("00100011dddddddd", "mov a, #%X"), + FMT("11111rrr", "mov a, %R"), + FMT("1111000r", "mov a, @%R"), + FMT("11000111", "mov a, psw"), + FMT("10111rrrdddddddd", "mov %R, #%X"), + FMT("10101rrr", "mov %R, a"), + FMT("1010000r", "mov @%R, a"), + FMT("1011000rdddddddd", "mov @%R, #%X"), + FMT("11010111", "mov psw, a"), + FMT("000011pp", "movd a, %P"), + FMT("001111pp", "movd %P, a"), + FMT("01000010", "mov a, t"), + FMT("01100010", "mov t, a"), + FMT("11100011", "movp3 a, @a"), + FMT("10100011", "movp a, @a"), + FMT("1000000r", "movx a, @%R"), + FMT("1001000r", "movx @%R, a"), + FMT("0100 1rrr", "orl a, %R"), + FMT("0100 000r", "orl a, @%R"), + FMT("0100 0011dddddddd", "orl a, #%X"), + FMT("1000 1000dddddddd", "orl bus, #%X"), + FMT("1000 1001dddddddd", "orl p1, #%X"), + FMT("1000 1010dddddddd", "orl p2, #%X"), + FMT("1000 11pp", "orld %P, a"), + FMT("00000010", "outl bus, a"), + FMT("001110pp", "outl %P, a"), + FMT("10000011", "ret"), + FMT("10010011", "retr"), + FMT("11100111", "rl a"), + FMT("11110111", "rlc a"), + FMT("01110111", "rr a"), + FMT("01100111", "rrc a"), + FMT("11100101", "sel mb0"), + FMT("11110101", "sel mb1"), + FMT("11000101", "sel rb0"), + FMT("11010101", "sel rb1"), + FMT("01100101", "stop tcnt"), + FMT("01000101", "strt cnt"), + FMT("01010101", "strt t"), + FMT("01000111", "swap a"), + FMT("00101rrr", "xch a, %R"), + FMT("0010000r", "xch a, @%R"), + FMT("0011000r", "xchd a, @%R"), + FMT("1101 0011dddddddd", "xrl a, #%X"), + FMT("1101 1rrr", "xrl a, %R"), + FMT("1101 000r", "xrl a, @%R"), + FMT("00000000", "nop"), + NULL +}; + +#define MAX_OPS (((sizeof(Formats) / sizeof(Formats[0])) - 1) / PTRS_PER_FORMAT) + +typedef struct opcode { + byte mask; /* instruction mask */ + byte bits; /* constant bits */ + char extcode; /* value that gets extension code */ + const char *parse; /* how to parse bits */ + const char *fmt; /* instruction format */ +} M48Opcode; + +static M48Opcode Op[MAX_OPS+1]; +static int OpInizialized = 0; + +static void InitDasm8039(void) +{ + const char *p, **ops; + byte mask, bits; + int bit; + int i; + + ops = Formats; i = 0; + while (*ops) { + p = *ops; + mask = 0; bits = 0; bit = 7; + while (*p && bit >= 0) { + switch (*p++) { + case '1': mask |= 1<= 0) + { + /* printf("{%c/%d}",*cp,bit); */ + switch(*cp) + { + case 'a': a <<=1; a |= ((code & (1<) { + if (/^(\S+):/) { + chomp($_); + @signals = split(/ +/); + + # remove time information + shift(@signals); + last; + } +} + +# build index +for ($i = 0; $i < scalar(@signals); $i++) { + # strip off hierarchical path + $signals[$i] =~ s/.*\.//; + $index{$signals[$i]} = $i; +} + +$istrobe = 0; +# read vectors +while () { + if (/^\d+> /) { + chop($_); + @vector = split(/ +/); + + # remove time information + shift(@vector); + + # process write operation to RAM + if ($vector[$index{'we_tmp'}] eq '1') { + $ram[hex(hex8($vector[$index{'address_tmp[7:0]'}]))] = hex8($vector[$index{'data_tmp[7:0]'}]); + } + + # find falling instruction strobe + if ($istrobe == 0) { + $istrobe = $vector[0]; + next; + } else { + $istrobe = $vector[0]; + if ($vector[0] == 0) { + # falling edge detected + } else { + next; + } + } + + # process each signal + for ($i = 1; $i < scalar(@vector); $i++) { + $_ = $signals[$i]; + $line = ''; + + SWITCH: { + if (/^program_counter/) { print(hex16($vector[$i]).' '); last; } + if (/^accumulator/) { print(hex8($vector[$i]).' '); last; } + if (/^sp/) { print(hex8($vector[$i]).' '); last; } + if (/^psw/) { print(hex8($vector[$i]).' '); last; } + if (/^bus/) { print(hex8($vector[$i]).' '); last; } + if (/^f1/) { print($vector[$i].' '); last; } + if (/^p1/) { print(hex8($vector[$i]).' '); last; } + if (/^p2/) { print(hex8($vector[$i]).' '); last; } + if (/^mb/) { print($vector[$i].' '); last; } + if (/^we_tmp/) { dump_ram(\@ram); last; } + } + } + print("\n"); + } +}
vec2dump.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vcd2vec.pl =================================================================== --- vcd2vec.pl (nonexistent) +++ vcd2vec.pl (revision 292) @@ -0,0 +1,234 @@ +#!/usr/bin/perl -w +# +# ############################################################################ +# +# vcd2vec.pl +# +# $Id: vcd2vec.pl,v 1.1 2004-04-09 19:16:00 arniml Exp $ +# +# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org) +# +# All rights reserved +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. See also the file COPYING which +# came with this application. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# ############################################################################ +# +# Purpose: +# ======== +# +# Converts a VCD-file to a vector file. +# +# Reads VCD from STDIN and writes the resulting vector stream to STDOUT. +# vcd2vec.pl -s [-i] [-h] +# -s : Name of the file containing the signals for vector output +# -i : Read initial state from VCD (given with $dumpvars) +# -h : Print this help +# + + +use strict; + +use Getopt::Std; + + +my $time_unit = 'ns'; + +sub print_usage { + print < [-i] [-h] + -s : Name of the file containing the signals for vector output + -i : Read initial state from VCD (given with \$dumpvars) + -h : Print this help +EOU +} + +sub print_index { + my $index = shift; + my ($tok, $desc); + + while (($tok, $desc) = each %{$index}) { + print("Token $tok:\n"); + print(" $desc->{'name'}\n"); + print(" $desc->{'pos'}\n"); + } +} + +sub dump_state { + my ($state, $time, $dump_signals) = @_; + my $signal; + + print("${time}>"); + foreach $signal (@{$dump_signals}) { + if (exists($state->{$signal})) { + print(" ".$state->{$signal}); + } else { + print(STDERR "Error: Signal '$signal' not included in VCD!\n"); + } + } + print("\n"); +} + +sub read_scope { + my $scope = shift; + my $index = shift; + my $pos = shift; + my ($token, $base, $extension); + my $ipt; + + print("Processing scope '$scope'\n"); + + while () { + last if (/^\$upscope/); + + last if (/^\$enddefinitions/); + + if (/^\$var +\S+ +\S+ +(\S+) +(\S+) +(([^\$]\S*)|\$end)/) { + $token = $1; + $base = $2; + + $extension = defined($4) ? $4 : ''; + $extension =~ s/[\[\]]//g; + + $index->{$token} = {}; + $ipt = $index->{$token}; + $ipt->{'name'} = "$scope.$base$extension"; + $ipt->{'pos'} = $$pos++; + + print("Appended ".$ipt->{'name'}."\n"); + } + + if (/^\$scope +\S+ +(\S+)/) { + read_scope("$scope.$1", $index, $pos); + } + + if (/^\$timescale/) { + $_ = ; + if (/^\s*1(\S+)/) { + $time_unit = $1; + } + } + } +} + +my %options; +my %index; +my %state; +my ($i, $time, $pos); +my $index; +my $token; +my ($ipt, $val); +my ($tok, $desc); +my $signal; +my $initial_states = 0; +local *SIGNALS_FILE; + +my @dump_signals; + +# process command line options +if (!getopts('s:ih', \%options)) { + print_usage(); + exit(1); +} + +if (exists($options{'h'})) { + print_usage(); + exit(0); +} + +if (exists($options{'i'})) { + $initial_states = 1; +} + +if (exists($options{'s'})) { +} else { + print(STDERR "File with signal names is required!\n"); + print_usage(); + exit(1); +} + + +############################################################################## +# Read signals file +# +if (!open(SIGNALS_FILE, "<$options{'s'}")) { + print(STDERR "Cannot read signals file '$options{'s'}'!\n"); + exit(1); +} + +@dump_signals = ; +close(SIGNALS_FILE); +chomp(@dump_signals); + + +# parse header +$index = {}; +$pos = 0; +read_scope("", $index, \$pos); + + +if ($initial_states) { + # read initial state + while () { last if (/^\$dumpvars/) } + while () { + last if (/^\$end/); + if (/^(.)(\S+)/) { + $val = $1; + $token = $2; + $state{$index->{$token}->{'name'}} = $val; + } + } +} + +$time = '0'; + +print("time:"); +foreach $signal (@dump_signals) { + print(" $signal"); +} +print("\n"); + +# now read all state changes +while () { + if (/^#(\d+)/) { + if ($1 != 0) { + # dump previous state + dump_state(\%state, $time, \@dump_signals); + } + $time = $1; + next; + } else { + if (/^(\S)(\S+)$/) { + $val = $1; + $token = $2; + $state{$index->{$token}->{'name'}} = $val; + } + + if (/^(\S+) (\S+)$/) { + $val = $1; + $token = $2; + $state{$index->{$token}->{'name'}} = $val; + } + } + +} + +# final dump +dump_state(\%state, $time, \@dump_signals); + +0;
vcd2vec.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: init_project.template.sh =================================================================== --- init_project.template.sh (nonexistent) +++ init_project.template.sh (revision 292) @@ -0,0 +1,17 @@ +############################################################################## +# +# Template script to set up all project-specific environemt variables. +# +# Copy this script to init_project.sh and fill in your local information. +# +# This script has to be sourced from the command line! +# Do not run it as a 'usual' program, as this does not set the variables +# in the current shell process. +# +############################################################################## + +export PROJECT_DIR=/t48 +export VERIF_DIR=$PROJECT_DIR/sw/verif +export SIM_DIR=$PROJECT_DIR/sim/rtl_sim + +export PATH=$PATH:$PROJECT_DIR/sw

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