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  • This comparison shows the changes necessary to convert path 
    /t48/tags/rel_1_1/sw/verif/black_box/rb
    from Rev 289 to Rev 292
    ↔ Reverse comparison
  •

Rev 289 → Rev 292

/misc/no_t39
/misc/test.asm
0,0 → 1,142
;; *******************************************************************
;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:18 arniml Exp $
;;
;; Test several operations in conjunction with RB-switching.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
;; Start of test
 
;; fill data memory with 0
clr a
mov r0, a
fill_loop:
mov @r0, a
djnz r0, fill_loop
 
;; set up both register banks with indirect writes
mov r0, #01FH
mov r1, #008H
fill_rb1_loop:
mov a, r0
mov @r0, a
dec r0
djnz r1, fill_rb1_loop
 
mov r0, #007H
fill_rb0_loop:
mov a, r0
mov @r0, a
djnz r0, fill_rb0_loop
mov a, r0
mov @r0, a
 
;; check RB0
call check_rb0
 
;; check RB1
sel rb1
call check_rb1
 
;; check RB0 again
sel rb0
call check_rb0
 
;; check memory between RB0 and RB1 for 0
mov r0, #00EH ; check 14 bytes
mov r1, #00AH ; starting from address A
chk_loop1:
mov a, @r1
jnz fail
inc r1
djnz r0, chk_loop1
 
;; check memory above RB1 for 0
mov r0, #0100H - 0020H ; check 256-32 bytes
mov r1, #020H ; starting from address 20H
chk_loop2:
mov a, @r1
jnz fail
inc r1
djnz r0, chk_loop2
 
;; now use RB1 to indirect address register 0-7
mov r1, #001H ; restore r1
mov r0, #000H ; restore r0, set trap
sel rb1
mov r0, #007H
ind_chk_loop:
mov a, @r0
cpl a
add a, r0
cpl a
jnz fail
djnz r0, ind_chk_loop
 
 
pass: PASS
 
fail: FAIL
 
 
 
ORG 0300H
check_rb0:
mov a, r0
jnz fail_p3
mov a,r1
add a, #0FFH
jnz fail_p3
mov a,r2
add a, #0FEH
jnz fail_p3
mov a,r3
add a, #0FDH
jnz fail_p3
mov a,r4
add a, #0FCH
jnz fail_p3
mov a,r5
add a, #0FBH
jnz fail_p3
mov a,r6
add a, #0FAH
jnz fail_p3
mov a,r7
add a, #0F9H
jnz fail_p3
ret
 
check_rb1:
mov a, r0
add a, #0E8H
jnz fail_p3
mov a,r1
add a, #0E7H
jnz fail_p3
mov a,r2
add a, #0E6H
jnz fail_p3
mov a,r3
add a, #0E5H
jnz fail_p3
mov a,r4
add a, #0E4H
jnz fail_p3
mov a,r5
add a, #0E3H
jnz fail_p3
mov a,r6
add a, #0E2H
jnz fail_p3
mov a,r7
add a, #0E1H
jnz fail_p3
ret
 
fail_p3:
FAIL
/int/no_dump_compare
0,0 → 1,2
Reason why this cell is exluded from dump compare:
Modelling accuracy of interrupts is not sufficient for 1:1 dump compare.
/int/test.asm
0,0 → 1,228
;; *******************************************************************
;; $Id: test.asm,v 1.2 2004-04-15 22:01:51 arniml Exp $
;;
;; Test interrupts in conjunction with RB-switching.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
 
ORG 0
 
jmp start
nop
jmp interrupt
jmp fail
jmp fail
jmp fail
 
 
;; Start of test
start:
;; fill RB0
clr a
call fill
 
;; fill RB1
sel rb1
mov a, #010H
call fill
sel rb0
 
;; set up interrupt
clr f1
;; sync on next interrupt
call sync_on_int
 
mov r0, #000H
en i
loop1: jf1 goon1
djnz r0, loop1
jmp fail
 
goon1:
dis i
clr f1
 
;; check BS implicitely
;; r0 must not be zero
mov a, r0
jz fail
 
;; check RB1
sel rb1
call check_0
 
;; check RB0
sel rb0
call check_rb0
 
pass: PASS
 
fail: FAIL
 
 
ORG 0200H
interrupt:
sel rb1
mov r0, a
 
call check_rb1
 
clr a
mov r1, a
mov r2, a
mov r3, a
mov r4, a
mov r5, a
mov r6, a
mov r7, a
xch a, r0
 
cpl f1
 
retr
 
 
ORG 0300H
 
fill: add a, #0B0H
mov r0, a
inc a
mov r1, a
inc a
mov r2, a
inc a
mov r3, a
inc a
mov r4, a
inc a
mov r5, a
inc a
mov r6, a
inc a
mov r7, a
ret
 
check_0:
mov a, r0
jnz fail_p3
mov a, r1
jnz fail_p3
mov a, r2
jnz fail_p3
mov a, r3
jnz fail_p3
mov a, r4
jnz fail_p3
mov a, r5
jnz fail_p3
mov a, r6
jnz fail_p3
mov a, r7
jnz fail_p3
ret
 
;; synchronize on interrupt
;; use r7 for timeout detection
sync_on_int:
mov a, r7 ; save r7
mov r7, #000H
wait_int1:
jni sync_on_int2
djnz r7, wait_int1
jmp fail_p3
 
sync_on_int2:
mov r7, #000H
wait_int2:
jni still_int
mov r7, a ; restore r7
call clr_int
retr
still_int:
djnz r7, wait_int2
jmp fail_p3
 
clr_int:
;; clear latched interrupt request with RETR!
retr
 
check_rb1:
mov a, #(~0C1H & 0FFH)
add a, r1
cpl a
jnz fail_p3
 
mov a, #(~0C2H & 0FFH)
add a, r2
cpl a
jnz fail_p3
 
mov a, #(~0C3H & 0FFH)
add a, r3
cpl a
jnz fail_p3
 
mov a, #(~0C4H & 0FFH)
add a, r4
cpl a
jnz fail_p3
 
mov a, #(~0C5H & 0FFH)
add a, r5
cpl a
jnz fail_p3
 
mov a, #(~0C6H & 0FFH)
add a, r6
cpl a
jnz fail_p3
 
mov a, #(~0C7H & 0FFH)
add a, r7
cpl a
jnz fail_p3
 
ret
 
check_rb0:
mov a, #(~0B1H & 0FFH)
add a, r1
cpl a
jnz fail_p3
 
mov a, #(~0B2H & 0FFH)
add a, r2
cpl a
jnz fail_p3
 
mov a, #(~0B3H & 0FFH)
add a, r3
cpl a
jnz fail_p3
 
mov a, #(~0B4H & 0FFH)
add a, r4
cpl a
jnz fail_p3
 
mov a, #(~0B5H & 0FFH)
add a, r5
cpl a
jnz fail_p3
 
mov a, #(~0B6H & 0FFH)
add a, r6
cpl a
jnz fail_p3
 
mov a, #(~0B7H & 0FFH)
add a, r7
cpl a
jnz fail_p3
 
ret
 
fail_p3:
FAIL

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