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  • This comparison shows the changes necessary to convert path 
    /t48
    from Rev 318 to Rev 319
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Rev 318 → Rev 319

/trunk/bench/vhdl/upi_stim.vhd
1,6 → 1,7
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity upi_stim is
 
21,6 → 22,8
architecture behav of upi_stim is
 
subtype word_t is std_logic_vector(7 downto 0);
alias dack_n : std_logic is p2_b(7);
alias drq : std_logic is p2_b(6);
alias int_ibf_n : std_logic is p2_b(5);
alias int_obf : std_logic is p2_b(4);
 
32,6 → 35,7
constant test_status41_c : word_t := "00000010";
constant test_status41a_c : word_t := "00000011";
constant test_master_int_c : word_t := "00000100";
constant test_dma_int_c : word_t := "00000101";
 
constant del_seq_c : time := 5 us;
constant del_dat_c : time := 10 us;
39,7 → 43,7
 
variable rdata : std_logic_vector(db_b'range);
 
procedure write_dbbin(data : in std_logic_vector(7 downto 0);
procedure write_dbbin(data : in word_t;
a0 : in std_logic) is
begin
cs_n_o <= '0';
73,6 → 77,38
wait for del_step_c;
end;
 
procedure read_dma is
begin
wait for del_seq_c;
dack_n <= '0';
wait for del_seq_c;
rd_n_o <= '0';
wait for del_dat_c;
rdata := db_b;
rd_n_o <= '1';
wait for del_seq_c;
dack_n <= '1';
wait for del_seq_c;
wait for del_step_c;
end;
 
procedure write_dma(data : in word_t) is
begin
wait for del_seq_c;
dack_n <= '0';
wait for del_seq_c;
wr_n_o <= '0';
wait for del_seq_c;
db_b <= data;
wait for del_dat_c;
wr_n_o <= '1';
wait for del_seq_c;
dack_n <= '1';
wait for del_seq_c;
db_b <= (others => 'Z');
wait for del_step_c;
end;
 
procedure poll_obf is
begin
-- poll for OBF
327,6 → 363,71
write_dbbin(data => test_master_int_c, a0 => '1');
end;
 
---------------------------------------------------------------------------
--
procedure dma_int_test is
begin
-- acknowledge
write_dbbin(data => not test_dma_int_c, a0 => '0');
 
-- test DRQ line low
if drq /= '0' then
fail_o <= true;
end if;
 
-- read 4 bytes with DMA
for byte in 4 downto 1 loop
-- wait for DRQ
wait until rising_edge(drq);
 
-- check status
read_dbbout(a0 => '1');
if rdata /= "00000001" then
fail_o <= true;
end if;
-- check DRQ still active
if drq /= 'H' then
fail_o <= true;
end if;
 
-- finally read data
read_dma;
if unsigned(rdata) /= byte then
fail_o <= true;
end if;
 
-- check status
read_dbbout(a0 => '1');
if rdata /= "00000000" then
fail_o <= true;
end if;
end loop;
--wait;
 
-- write 4 bytes with DMA
for byte in 4 downto 1 loop
-- wait for DRQ
wait until rising_edge(drq);
 
-- check status
read_dbbout(a0 => '1');
if rdata /= "00000000" then
fail_o <= true;
end if;
-- check DRQ still active
if drq /= 'H' then
fail_o <= true;
end if;
 
-- finally write data
write_dma(data => std_logic_vector(to_unsigned(byte, word_t'length)));
end loop;
 
-- send ok to dut
write_dbbin(data => test_dma_int_c, a0 => '1');
 
end;
 
begin
 
fail_o <= false;
335,6 → 436,7
wr_n_o <= '1';
a0_o <= '0';
db_b <= (others => 'Z');
dack_n <= 'H';
 
wait until falling_edge(p1_b(2));
wait for 100 us;
358,6 → 460,9
when test_master_int_c =>
master_int_test;
 
when test_dma_int_c =>
dma_int_test;
 
when others =>
null;
end case;
/trunk/rtl/vhdl/upi41_db_bus.vhd
203,6 → 203,10
int_n_o <= '0';
end if;
 
if dack_s and (read_s or write_s) then
drq_o <= '0';
end if;
 
if en_clk_i then
if write_bus_i then
dbbout_q <= data_i;
226,9 → 230,7
flags_q <= true;
end if;
 
if dack_s then
drq_o <= '0';
elsif dma_q and write_p2_i and data_i(6) = '1' then
if dma_q and write_p2_i and data_i(6) = '1' then
drq_o <= '1';
end if;
end if;
/trunk/sw/verif/black_box/upi41/dma/no_gen
/trunk/sw/verif/black_box/upi41/dma/no_t41
/trunk/sw/verif/black_box/upi41/dma/test.asm
0,0 → 1,84
;; *******************************************************************
;; Test UPI41A DMA.
;; *******************************************************************
 
INCLUDE "cpu.inc"
INCLUDE "pass_fail.inc"
INCLUDE "upi41_opcodes.inc"
 
ORG 0
 
;; Start of test
 
;; test IBF empty
ujnibf ibfempty
jmp fail
 
ibfempty:
;; test OBF empty
ujobf fail
 
;; signal test start
anl P1, #~004H
 
;; request master interrupt test
mov a, #005H
uout dbb, a
 
;; setup DMA
;; read input as data
step1: ujnibf step1
jf1 fail
 
uin a, dbb
xrl a, #~005H
jnz fail
 
uen_dma
 
;; Step 2: Request 4 reads via DMA
mov r7, #004H
read4dma:
mov r0, #020H
dloop2: djnz r0, dloop2
 
mov a, r7
uout dbb, a
 
orl p2, #040H
 
step2: ujobf step2
djnz r7, read4dma
 
;; Step 3: Request 4 writes via DMA
mov r7, #004H
write4dma:
mov r0, #020H
dloop3: djnz r0, dloop3
 
orl p2, #040H
 
step3: ujnibf step3
 
uin a, dbb
xrl a, r7
jnz fail
jf1 fail
 
djnz r7, write4dma
 
 
;; read next input as command
done: ujnibf done
jf1 done_goon
jmp done
done_goon:
 
uin a, dbb
xrl a, #005H
jz pass
 
 
fail: FAIL
 
pass: PASS
/trunk/sw/verif/include/upi41_opcodes.inc
23,3 → 23,7
uen_flags MACRO
db 0F5H
ENDM
 
uen_dma MACRO
db 0E5H
ENDM

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