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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/fv
    from Rev 180 to Rev 182
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Rev 180 → Rev 182

/alu_input.e
1,20 → 1,25
alu_input.e
<'
import alu_components.e;
type alu_input_t: [ENABLED_VALID, DISABLED_VALID, RESET];
type alu_input_t: [ENABLED_VALID, DISABLED_VALID, RESET, ENABLED_RAND, DISABLED_RAND];
type alu_test_type: [REGULAR, RAND];
 
struct alu_input_s {
input_kind : alu_input_t;
test_kind : alu_test_type;
reset_n: bool;
alu_enable: bool;
alu_opcode: valid_opcodes;
alu_a: byte;
 
keep soft input_kind == select {
45: ENABLED_VALID;
45: DISABLED_VALID;
10: RESET;
keep test_kind == RAND;
when REGULAR'test_kind alu_input_s {
keep soft input_kind == select {
45: ENABLED_VALID;
45: DISABLED_VALID;
10: RESET;
};
};
 
when ENABLED_VALID'input_kind alu_input_s {
31,7 → 36,10
 
when RESET'input_kind alu_input_s {
keep reset_n == FALSE; // remember this is active low
//keep alu_enable in [FALSE, TRUE];
keep soft alu_enable == select {
50: FALSE;
50: TRUE;
};
keep alu_a in [0..255];
//keep alu_opcode in [0..255];
};
43,7 → 51,40
cross input_kind, alu_opcode;
//item alu_a;
};
};
 
 
extend alu_input_s {
rand_op : byte;
 
when RAND'test_kind alu_input_s {
keep soft input_kind == select {
45: ENABLED_RAND;
45: DISABLED_RAND;
10: RESET;
};
};
 
when ENABLED_RAND'input_kind alu_input_s {
keep reset_n == TRUE; // remember this is active low
keep alu_enable == TRUE;
keep alu_a in [0..255];
keep rand_op in [0..255];
};
 
when DISABLED_RAND'input_kind alu_input_s {
keep reset_n == TRUE; // remember this is active low
keep alu_enable == TRUE;
keep alu_a in [0..255];
keep rand_op in [0..255];
};
 
event T2_cover_event;
cover T2_cover_event is {
item alu_enable using no_collect=TRUE;
item rand_op using num_of_buckets=256, radix=HEX, no_collect=TRUE;
cross alu_enable, rand_op;
};
};
'>
 
/alu_bfm.e
9,7 → 9,7
 
reset_needed : bool;
keep reset_needed == TRUE;
 
event done;
event main_clk;
 
25,12 → 25,18
reset_needed = FALSE;
};
};
emit data.T1_cover_event;
 
if (data.test_kind == REGULAR) {
emit data.T1_cover_event;
alu_opcode$ = data.rand_op;
}
else {
emit data.T2_cover_event;
alu_opcode$ = data.alu_opcode.as_a(byte);
};
 
reset_n$ = data.reset_n;
alu_enable$ = data.alu_enable;
alu_opcode$ = data.alu_opcode.as_a(byte);
alu_a$ = data.alu_a;
 
agent.chk.store(data);
/alu_chk.e
17,10 → 17,18
last_a : byte;
last_status : byte;
last_result : byte;
rst_counter : byte;
 
keep first_cycle == TRUE;
keep count_cycles == 0;
keep rst_counter == 0;
 
event T3_cover_event;
cover T3_cover_event is {
item rst_counter; // using num_of_buckets=100;
};
 
 
store(input : alu_input_s) is {
count_cycles = count_cycles + 1;
 
52,8 → 60,8
reg_result = 0;
}
else {
//out ("CYCLE ", count_cycles, " COMPARE:");
//print inst;
out ("CYCLE ", count_cycles, " COMPARE:");
print inst;
 
if (count_cycles == 99999) {
out("ENOUGH!");
60,14 → 68,19
stop_run();
};
 
if (inst.input_kind == RESET) {
rst_counter = rst_counter + 1;
}
else {
emit T3_cover_event;
rst_counter = 0;
};
 
case inst.input_kind {
ENABLED_VALID: {
//out("CYCLE ", count_cycles, ": executing and comparing");
execute();
};
DISABLED_VALID: {
//out("CYCLE ", count_cycles, ": just comparing");
};
RESET: {
reg_x = 0;
reg_y = 0;
77,8 → 90,10
return;
};
ENABLED_RAND: {
execute();
};
default: {
dut_error("error at e code");
};
};
276,23 → 291,22
STA_ABY: { reg_result = reg_a; };
STA_IDX: { reg_result = reg_a; };
STA_IDY: { reg_result = reg_a; };
//STX_ZPG: { reg_result = reg_x; };
//STX_ZPY: { reg_result = reg_x; };
//STX_ABS: { reg_result = reg_x; };
//STY_ZPG: { reg_result = reg_y; };
//STY_ZPX: { reg_result = reg_y; };
//STY_ABS: { reg_result = reg_y; };
STX_ZPG: { };
STX_ZPY: { };
STX_ABS: { };
STY_ZPG: { };
STY_ZPX: { };
STY_ABS: { };
 
//TAX_IMP: { exec_transfer(reg_a, reg_x); };
//TAY_IMP: { exec_transfer(reg_a, reg_y); };
//TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
//TXA_IMP: { exec_transfer(reg_x, reg_a); };
//TXS_IMP: { };
//TYA_IMP: { exec_transfer(reg_y, reg_a); };
TAX_IMP: { exec_transfer(reg_a, reg_x); };
TAY_IMP: { exec_transfer(reg_a, reg_y); };
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
TXA_IMP: { exec_transfer(reg_x, reg_a); };
TXS_IMP: { };
TYA_IMP: { exec_transfer(reg_y, reg_a); reg_result = reg_y; }; // A = Y
 
default: {
out(inst.alu_opcode);
dut_error("unknown opcode");
// all the random generated opcodes will fall here
}
};
};
324,9 → 338,10
op1 = -(op1 % 10);
};
 
reg_status[0:0] = 1;
if (op2 >= 10) {
op2 = op2 % 10;
reg_status[0:0] = 1;
}
else if (op2 < 0) {
op2 = op2 + 10;

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