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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/fv
    from Rev 215 to Rev 216
    ↔ Reverse comparison
  •

Rev 215 → Rev 216

/fsm_opcodes.e
45,11 → 45,11
CMP_IDX = 8'hC1,
CMP_IDY = 8'hD1,
CPX_IMM = 8'hE0,
//CPX_ZPG = 8'hE4,
//CPX_ABS = 8'hEC,
CPX_ZPG = 8'hE4,
CPX_ABS = 8'hEC,
CPY_IMM = 8'hC0,
//CPY_ZPG = 8'hC4,
//CPY_ABS = 8'hCC,
CPY_ZPG = 8'hC4,
CPY_ABS = 8'hCC,
DEC_ZPG = 8'hC6,
DEC_ZPX = 8'hD6,
DEC_ABS = 8'hCE,
71,7 → 71,7
INX_IMP = 8'hE8,
INY_IMP = 8'hC8,
JMP_ABS = 8'h4C,
//JMP_IND = 8'h6C,
JMP_IND = 8'h6C,
//JSR_ABS = 8'h20,
LDA_IMM = 8'hA9,
LDA_ZPG = 8'hA5,
135,10 → 135,10
STA_ZPG = 8'h85,
STA_ZPX = 8'h95,
STA_ABS = 8'h8D,
//STA_ABX = 8'h9D,
//STA_ABY = 8'h99,
STA_ABX = 8'h9D,
STA_ABY = 8'h99,
STA_IDX = 8'h81,
//STA_IDY = 8'h91,
STA_IDY = 8'h91,
STX_ZPG = 8'h86,
STX_ZPY = 8'h96,
STX_ABS = 8'h8E,
/fsm_chk.e
16,6 → 16,8
keep soft SP == 0;
!pointer : byte;
keep soft pointer == 0;
!pointer_h : byte;
keep soft pointer_h == 0;
 
!more_cycles : bool;
keep soft more_cycles == FALSE;
174,6 → 176,8
instruction == BIT_ABS ||
instruction == AND_ABS ||
instruction == CMP_ABS ||
instruction == CPX_ABS ||
instruction == CPY_ABS ||
instruction == DEC_ABS ||
instruction == EOR_ABS ||
instruction == INC_ABS ||
198,6 → 202,8
instruction == ADC_ZPG ||
instruction == SBC_ZPG ||
instruction == CMP_ZPG ||
instruction == CPX_ZPG ||
instruction == CPY_ZPG ||
instruction == BIT_ZPG ||
instruction == STA_ZPG ||
instruction == STX_ZPG ||
228,6 → 234,8
instruction == STY_ZPX ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == STA_ABX ||
instruction == STA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
262,13 → 270,14
instruction == CMP_IDX ||
instruction == SBC_IDX ||
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
instruction == ADC_IDY ||
instruction == CMP_IDY ||
instruction == SBC_IDY
instruction == SBC_IDY ||
instruction == JMP_IND
) : {
new_state = CYCLE_3;
pointer = input.data_in;
333,7 → 342,7
};
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
345,11 → 354,19
PCL = input.data_in;
};
(
instruction == JMP_IND
) : {
new_state = CYCLE_4;
pointer_h = input.data_in;
};
(
instruction == ADC_ABS ||
instruction == ASL_ABS ||
instruction == BIT_ABS ||
instruction == AND_ABS ||
instruction == CMP_ABS ||
instruction == CPX_ABS ||
instruction == CPY_ABS ||
instruction == DEC_ABS ||
instruction == EOR_ABS ||
instruction == INC_ABS ||
366,6 → 383,8
instruction == STY_ABS ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == STA_ABX ||
instruction == STA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
407,7 → 426,8
// new_state = CYCLE_5;
//};
(
instruction == RTS_IMP
instruction == RTS_IMP ||
instruction == JMP_IND
) : {
new_state = CYCLE_5;
PCL = input.data_in;
439,6 → 459,8
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX ||
instruction == STA_ABX ||
instruction == STA_ABY ||
(
more_cycles == TRUE &&
(
478,7 → 500,7
};
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
531,11 → 553,11
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX ||
instruction == STA_IDY ||
(
more_cycles == TRUE &&
(
instruction == LDA_IDY ||
--instruction == STA_IDY ||
instruction == ORA_IDY ||
instruction == EOR_IDY ||
instruction == AND_IDY ||
560,6 → 582,12
new_state = CYCLE_6;
PCH = input.data_in;
};
(
instruction == JMP_IND
) : {
new_state = CYCLE_1;
PCH = input.data_in;
};
default : {
new_state = CYCLE_1;
};
636,6 → 664,8
last_instruction == AND_IMM ||
last_instruction == BIT_ABS ||
last_instruction == CMP_ABS ||
last_instruction == CPX_ABS ||
last_instruction == CPY_ABS ||
last_instruction == CMP_IMM ||
last_instruction == CPX_IMM ||
last_instruction == CPY_IMM ||
662,6 → 692,8
last_instruction == ADC_ZPG ||
last_instruction == SBC_ZPG ||
last_instruction == CMP_ZPG ||
last_instruction == CPX_ZPG ||
last_instruction == CPY_ZPG ||
last_instruction == BIT_ZPG ||
last_instruction == LDA_ZPX ||
last_instruction == LDX_ZPY ||
780,6 → 812,8
instructions == BIT_ABS ||
instructions == BRK_IMP ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == CMP_IMM ||
instructions == CPX_IMM ||
instructions == CPY_IMM ||
810,6 → 844,8
instructions == ADC_ZPG ||
instructions == SBC_ZPG ||
instructions == CMP_ZPG ||
instructions == CPX_ZPG ||
instructions == CPY_ZPG ||
instructions == BIT_ZPG ||
instructions == ASL_ZPG ||
instructions == LSR_ZPG ||
837,6 → 873,8
instructions == STA_ZPX ||
instructions == LDA_ABX ||
instructions == LDA_ABY ||
instructions == STA_ABX ||
instructions == STA_ABY ||
instructions == LDX_ABY ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
866,13 → 904,14
instructions == CMP_IDX ||
instructions == SBC_IDX ||
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
instructions == ADC_IDY ||
instructions == CMP_IDY ||
instructions == SBC_IDY
instructions == SBC_IDY ||
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1117,7 → 1156,7
instructions == CMP_IDX ||
instructions == SBC_IDX ||
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1144,6 → 1183,8
instructions == ASL_ABS ||
instructions == BIT_ABS ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == DEC_ABS ||
instructions == EOR_ABS ||
instructions == INC_ABS ||
1218,6 → 1259,25
};
};
(
instructions == STA_ABX ||
instructions == STA_ABY ||
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (addr != PC) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
PC = PC + 1;
};
(
instructions == LDA_ZPG ||
instructions == LDX_ZPG ||
instructions == LDY_ZPG ||
1227,6 → 1287,8
instructions == ADC_ZPG ||
instructions == SBC_ZPG ||
instructions == CMP_ZPG ||
instructions == CPX_ZPG ||
instructions == CPY_ZPG ||
instructions == BIT_ZPG ||
instructions == ASL_ZPG ||
instructions == LSR_ZPG ||
1334,6 → 1396,58
// SP = SP - 1;
//};
(
instructions == STA_ABX
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == STA_ABY
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == LDA_ZPX ||
instructions == LDY_ZPX ||
instructions == EOR_ZPX ||
1439,7 → 1553,7
};
(
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1464,6 → 1578,25
};
};
(
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != pointer) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != pointer_h[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
1501,6 → 1634,8
instructions == ASL_ABS ||
instructions == BIT_ABS ||
instructions == CMP_ABS ||
instructions == CPX_ABS ||
instructions == CPY_ABS ||
instructions == DEC_ABS ||
instructions == EOR_ABS ||
instructions == INC_ABS ||
1690,6 → 1825,37
};
SP = SP - 1;
};
(
instructions == JMP_IND
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (pointer + 1 > 255) {
if (addr[7:0] != pointer + 1 - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != pointer + 1) {
dut_error("ADDR should be equal SP!");
};
};
-- TODO: This is the correct behaviour expected from spec
--if (addr[12:8] != pointer_h[4:0]) {
-- print addr[7:0], pointer;
-- print addr[12:8], pointer_h[4:0];
-- dut_error("ADDR should be equal SP!");
--};
PC[7:0] = PCL;
PC[12:8] = PCH[4:0];
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
1736,10 → 1902,14
dut_error("ADDR is wrong");
};
};
if (addr[12:8] != 0) {
print addr[12:8], PCH[4:0];
dut_error("ADDR is wrong");
};
};
(
instructions == LDA_IDY ||
--instructions == STA_IDY ||
instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1766,6 → 1936,12
dut_error("ADDR is wrong");
};
};
-- TODO: This is the expected behavior (took from spec)
-- addr[12:8] is 0 or 1 acording to PCL + Y > 255
--if (addr[12:8] != PCH[4:0]) {
-- print addr[12:8], PCH[4:0];
-- dut_error("ADDR is wrong");
--};
};
(
instructions == STA_IDX
1791,6 → 1967,64
};
};
(
instructions == STA_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH + 1) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == STA_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH + 1) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR should be equal SP!");
};
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
};
(
instructions == RTI_IMP
) : {
if (alu_opcode != instructions) {
2076,6 → 2310,35
};
};
(
instructions == STA_IDY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong");
};
};
};
(
instructions == STA_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {

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