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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 100 to Rev 101
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  •

Rev 100 → Rev 101

/t6507lp_fsm_tb.v
141,6 → 141,7
fake_mem[47] = 8'h0a;
fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
fake_mem[59] = 8'hff;
fake_mem[60] = 8'hff;
fake_mem[254] = 8'hff;
fake_mem[255] = 8'h11;
fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
166,14 → 167,21
this is probably not an issue */
fake_mem[331] = LDA_IDY;
fake_mem[332] = 8'hfe;
fake_mem[333] = STA_IDY;
fake_mem[334] = 8'h00; // testing IDY mode WRITE TYPE, page not crossed;
fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
fake_mem[334] = 8'h00;
fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
fake_mem[336] = 8'h0e;
fake_mem[337] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
fake_mem[338] = 8'hff;
fake_mem[339] = 8'h00;
//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
//fake_mem[338] = 8'h3b;
//fake_mem[339] = 8'h00;
 
 
 
 
 
 
@(negedge clk) // will wait for next negative edge of the clock (t=20)
reset_n=1'b1;
/t6507lp_fsm.v
122,6 → 122,7
reg read_modify_write;
reg write;
reg jump;
reg jump_indirect;
 
wire [ADDR_SIZE_:0] next_pc;
assign next_pc = pc + 13'b0000000000001;
150,6 → 151,10
{page_crossed, address_plus_index[7:0]} = temp_data + index;
address_plus_index[12:8] = 5'b00000;
end
else if (jump_indirect) begin
address_plus_index[7:0] = temp_addr + 8'h01;
address_plus_index[12:8] = 5'b00000;
end
else begin // indirecty falls here
address_plus_index[7:0] = temp_data + 8'h01;
address_plus_index[12:8] = 5'b00000;
212,11 → 217,12
control <= MEM_READ;
temp_data <= data_in; // the follow-up byte is saved in temp_data
end
else if (absolute || absolute_indexed) begin
else if (absolute || absolute_indexed || jump_indirect) begin
pc <= next_pc;
address <= next_pc;
control <= MEM_READ;
temp_addr <= {{5{1'b0}},data_in};
temp_data <= 8'h00;
end
else if (zero_page) begin
pc <= next_pc;
379,15 → 385,22
data_out <= 8'h00;
end
READ_FROM_POINTER: begin
pc <= pc;
control <= MEM_READ;
if (indirectx) begin
if (jump_indirect) begin
pc[7:0] <= data_in;
control <= MEM_READ;
address <= address_plus_index;
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr <= {{5{1'b0}}, data_in};
else begin
pc <= pc;
control <= MEM_READ;
if (indirectx) begin
address <= address_plus_index;
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr <= {{5{1'b0}}, data_in};
end
end
end
READ_FROM_POINTER_X: begin
397,10 → 410,13
control <= MEM_READ;
end
READ_FROM_POINTER_X1: begin
pc <= pc;
if (indirectx) begin
address <= {data_in[5:0], temp_addr[7:0]};
if (jump_indirect) begin
pc[12:8] <= data_in[4:0];
control <= MEM_READ;
address <= {data_in[4:0], pc[7:0]};
end
else if (indirectx) begin
address <= {data_in[4:0], temp_addr[7:0]};
if (write) begin
control <= MEM_WRITE;
data_out <= alu_result;
476,7 → 492,7
else if (zero_page_indexed) begin
next_state = READ_MEM_CALC_INDEX;
end
else if (absolute) begin // at least the absolute address mode falls here
else if (absolute || jump_indirect) begin // at least the absolute address mode falls here
next_state = FETCH_HIGH;
if (write) begin // this is being done one cycle early but i have checked and the ALU will still work properly
alu_opcode = ir;
498,7 → 514,7
if (indirectx) begin
next_state = READ_FROM_POINTER_X;
end
else begin // indirecty falls here
else begin // indirecty and jump indirect falls here
next_state = READ_FROM_POINTER_X1;
end
end
506,7 → 522,10
next_state = READ_FROM_POINTER_X1;
end
READ_FROM_POINTER_X1: begin
if (indirecty) begin
if (jump_indirect) begin
next_state = FETCH_OP;
end
else if (indirecty) begin
next_state = READ_MEM_FIX_ADDR;
end
else begin
562,7 → 581,10
end
end
FETCH_HIGH: begin
if (jump) begin
if (jump_indirect) begin
next_state = READ_FROM_POINTER;
end
else if (jump) begin
next_state = FETCH_OP;
end
else if (read || read_modify_write) begin
632,10 → 654,9
read_modify_write = 1'b0;
write = 1'b0;
jump = 1'b0;
jump_indirect = 1'b0;
branch = 1'b0;
 
//$write("trying with %h\n", ir);
case (ir)
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
748,7 → 769,7
branch = 1'b0;
end
end
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JSR_ABS, LDA_ABS,
LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
absolute = 1'b1;
end
769,6 → 790,13
indirecty = 1'b1;
index = alu_y;
end
JMP_ABS: begin
absolute = 1'b1;
jump = 1'b1;
end
JMP_IND: begin
jump_indirect = 1'b1;
end
default: begin
$write("state : %b", state);
if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
791,10 → 819,6
read = 1'b1;
end
endcase
if (ir == JMP_ABS || ir == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
jump = 1'b1;
end
end
endmodule
 

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