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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 106 to Rev 107
    ↔ Reverse comparison
  •

Rev 106 → Rev 107

/t6507lp_fsm_tb.v
143,7 → 143,9
fake_mem[59] = 8'hff;
fake_mem[60] = 8'hff;
fake_mem[254] = 8'hff;
fake_mem[255] = 8'h11;
fake_mem[257] = 8'h55; // PCL fetched from here when executing RTS_IMP
fake_mem[258] = 8'h01; // PCH fetched from here when executing RTS_IMP
fake_mem[264] = 8'd340;
fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
fake_mem[316] = 8'hff;
fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
180,8 → 182,11
//fake_mem[339] = 8'h00;
fake_mem[338] = BRK_IMP;
fake_mem[339] = RTI_IMP;
fake_mem[340] = RTS_IMP;
// 341 is skipped due to RTS internal functionality
fake_mem[342] = PHA_IMP;
fake_mem[342] = PHP_IMP;
 
 
 
fake_mem[8190] = 8'h53; // this is the reset vector
/t6507lp_fsm.v
94,6 → 94,7
localparam PULL_STATUS = 5'b10110;
localparam PULL_PCL = 5'b10111;
localparam PULL_PCH = 5'b11000;
localparam INCREMENT_PC = 5'b11001;
 
localparam RESET = 5'b11111;
 
136,6 → 137,7
// regs for the special instructions
reg break;
reg rti;
reg rts;
 
wire [ADDR_SIZE_:0] next_pc;
assign next_pc = pc + 13'b0000000000001;
278,7 → 280,7
control <= MEM_WRITE;
sp <= sp_minus_one;
end
else if (rti) begin
else if (rti || rts) begin
address <= sp;
control <= MEM_READ;
end
513,6 → 515,10
pc[12:8] <= data_in[4:0];
address <= {data_in[4:0], pc[7:0]};
end
INCREMENT_PC: begin
pc <= next_pc;
address <= next_pc;
end
default: begin
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
$finish(0);
595,7 → 601,7
if (break) begin
next_state = PUSH_PCH;
end
else if (rti) begin
else if (rti || rts) begin
next_state = INCREMENT_SP;
end
end
735,7 → 741,12
next_state = FETCH_OP;
end
INCREMENT_SP: begin
next_state = PULL_STATUS;
if (rti) begin
next_state = PULL_STATUS;
end
else begin // rts
next_state = PULL_PCL;
end
end
PULL_STATUS: begin
next_state = PULL_PCL;
747,6 → 758,14
alu_a = temp_data;
end
PULL_PCH: begin
if (rti) begin
next_state = FETCH_OP;
end
else begin // rts
next_state = INCREMENT_PC;
end
end
INCREMENT_PC: begin
next_state = FETCH_OP;
end
default: begin
779,10 → 798,11
 
break = 1'b0;
rti = 1'b0;
rts = 1'b0;
 
case (ir)
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
PLP_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
PLP_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
implied = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
926,6 → 946,9
RTI_IMP: begin
rti = 1'b1;
end
RTS_IMP: begin
rts = 1'b1;
end
default: begin
$write("state : %b", state);
if (reset_n == 1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc

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